1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
5 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
7 * This driver is inspired by:
8 * pinctrl-nomadik.c, please see original file for copyright information
9 * pinctrl-tegra.c, please see original file for copyright information
12 #include <linux/bitmap.h>
13 #include <linux/bug.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
19 #include <linux/irq.h>
20 #include <linux/irqdesc.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/module.h>
24 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/pinctrl/machine.h>
29 #include <linux/pinctrl/pinconf.h>
30 #include <linux/pinctrl/pinctrl.h>
31 #include <linux/pinctrl/pinmux.h>
32 #include <linux/pinctrl/pinconf-generic.h>
33 #include <linux/platform_device.h>
34 #include <linux/seq_file.h>
35 #include <linux/slab.h>
36 #include <linux/spinlock.h>
37 #include <linux/types.h>
38 #include <dt-bindings/pinctrl/bcm2835.h>
40 #define MODULE_NAME "pinctrl-bcm2835"
41 #define BCM2835_NUM_GPIOS 54
42 #define BCM2711_NUM_GPIOS 58
43 #define BCM2835_NUM_BANKS 2
44 #define BCM2835_NUM_IRQS 3
46 /* GPIO register offsets */
47 #define GPFSEL0 0x0 /* Function Select */
48 #define GPSET0 0x1c /* Pin Output Set */
49 #define GPCLR0 0x28 /* Pin Output Clear */
50 #define GPLEV0 0x34 /* Pin Level */
51 #define GPEDS0 0x40 /* Pin Event Detect Status */
52 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
53 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
54 #define GPHEN0 0x64 /* Pin High Detect Enable */
55 #define GPLEN0 0x70 /* Pin Low Detect Enable */
56 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
57 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
58 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
59 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
60 #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
62 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
63 #define FSEL_SHIFT(p) (((p) % 10) * 3)
64 #define GPIO_REG_OFFSET(p) ((p) / 32)
65 #define GPIO_REG_SHIFT(p) ((p) % 32)
67 #define PUD_2711_MASK 0x3
68 #define PUD_2711_REG_OFFSET(p) ((p) / 16)
69 #define PUD_2711_REG_SHIFT(p) (((p) % 16) * 2)
71 /* argument: bcm2835_pinconf_pull */
72 #define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1)
74 #define BCM2711_PULL_NONE 0x0
75 #define BCM2711_PULL_UP 0x1
76 #define BCM2711_PULL_DOWN 0x2
78 struct bcm2835_pinctrl {
83 /* note: locking assumes each bank will have its own unsigned long */
84 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
85 unsigned int irq_type[BCM2711_NUM_GPIOS];
87 struct pinctrl_dev *pctl_dev;
88 struct gpio_chip gpio_chip;
89 struct pinctrl_desc pctl_desc;
90 struct pinctrl_gpio_range gpio_range;
92 raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
95 /* pins are just named GPIO0..GPIO53 */
96 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
97 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
108 BCM2835_GPIO_PIN(10),
109 BCM2835_GPIO_PIN(11),
110 BCM2835_GPIO_PIN(12),
111 BCM2835_GPIO_PIN(13),
112 BCM2835_GPIO_PIN(14),
113 BCM2835_GPIO_PIN(15),
114 BCM2835_GPIO_PIN(16),
115 BCM2835_GPIO_PIN(17),
116 BCM2835_GPIO_PIN(18),
117 BCM2835_GPIO_PIN(19),
118 BCM2835_GPIO_PIN(20),
119 BCM2835_GPIO_PIN(21),
120 BCM2835_GPIO_PIN(22),
121 BCM2835_GPIO_PIN(23),
122 BCM2835_GPIO_PIN(24),
123 BCM2835_GPIO_PIN(25),
124 BCM2835_GPIO_PIN(26),
125 BCM2835_GPIO_PIN(27),
126 BCM2835_GPIO_PIN(28),
127 BCM2835_GPIO_PIN(29),
128 BCM2835_GPIO_PIN(30),
129 BCM2835_GPIO_PIN(31),
130 BCM2835_GPIO_PIN(32),
131 BCM2835_GPIO_PIN(33),
132 BCM2835_GPIO_PIN(34),
133 BCM2835_GPIO_PIN(35),
134 BCM2835_GPIO_PIN(36),
135 BCM2835_GPIO_PIN(37),
136 BCM2835_GPIO_PIN(38),
137 BCM2835_GPIO_PIN(39),
138 BCM2835_GPIO_PIN(40),
139 BCM2835_GPIO_PIN(41),
140 BCM2835_GPIO_PIN(42),
141 BCM2835_GPIO_PIN(43),
142 BCM2835_GPIO_PIN(44),
143 BCM2835_GPIO_PIN(45),
144 BCM2835_GPIO_PIN(46),
145 BCM2835_GPIO_PIN(47),
146 BCM2835_GPIO_PIN(48),
147 BCM2835_GPIO_PIN(49),
148 BCM2835_GPIO_PIN(50),
149 BCM2835_GPIO_PIN(51),
150 BCM2835_GPIO_PIN(52),
151 BCM2835_GPIO_PIN(53),
152 BCM2835_GPIO_PIN(54),
153 BCM2835_GPIO_PIN(55),
154 BCM2835_GPIO_PIN(56),
155 BCM2835_GPIO_PIN(57),
158 /* one pin per group */
159 static const char * const bcm2835_gpio_groups[] = {
221 BCM2835_FSEL_COUNT = 8,
222 BCM2835_FSEL_MASK = 0x7,
225 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
226 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
227 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
228 [BCM2835_FSEL_ALT0] = "alt0",
229 [BCM2835_FSEL_ALT1] = "alt1",
230 [BCM2835_FSEL_ALT2] = "alt2",
231 [BCM2835_FSEL_ALT3] = "alt3",
232 [BCM2835_FSEL_ALT4] = "alt4",
233 [BCM2835_FSEL_ALT5] = "alt5",
236 static const char * const irq_type_names[] = {
237 [IRQ_TYPE_NONE] = "none",
238 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
239 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
240 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
241 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
242 [IRQ_TYPE_LEVEL_LOW] = "level-low",
245 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
247 return readl(pc->base + reg);
250 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
253 writel(val, pc->base + reg);
256 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
259 reg += GPIO_REG_OFFSET(bit) * 4;
260 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
263 /* note NOT a read/modify/write cycle */
264 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
265 unsigned reg, unsigned bit)
267 reg += GPIO_REG_OFFSET(bit) * 4;
268 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
271 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
272 struct bcm2835_pinctrl *pc, unsigned pin)
274 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
275 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
277 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
278 bcm2835_functions[status]);
283 static inline void bcm2835_pinctrl_fsel_set(
284 struct bcm2835_pinctrl *pc, unsigned pin,
285 enum bcm2835_fsel fsel)
287 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
288 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
290 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
291 bcm2835_functions[cur]);
296 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
297 /* always transition through GPIO_IN */
298 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
299 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
301 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
302 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
303 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
306 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
307 val |= fsel << FSEL_SHIFT(pin);
309 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
310 bcm2835_functions[fsel]);
311 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
314 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
316 return pinctrl_gpio_direction_input(chip->base + offset);
319 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
321 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
323 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
326 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
328 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
329 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
331 /* Alternative function doesn't clearly provide a direction */
332 if (fsel > BCM2835_FSEL_GPIO_OUT)
335 if (fsel == BCM2835_FSEL_GPIO_IN)
336 return GPIO_LINE_DIRECTION_IN;
338 return GPIO_LINE_DIRECTION_OUT;
341 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
343 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
345 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
348 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
349 unsigned offset, int value)
351 bcm2835_gpio_set(chip, offset, value);
352 return pinctrl_gpio_direction_output(chip->base + offset);
355 static const struct gpio_chip bcm2835_gpio_chip = {
356 .label = MODULE_NAME,
357 .owner = THIS_MODULE,
358 .request = gpiochip_generic_request,
359 .free = gpiochip_generic_free,
360 .direction_input = bcm2835_gpio_direction_input,
361 .direction_output = bcm2835_gpio_direction_output,
362 .get_direction = bcm2835_gpio_get_direction,
363 .get = bcm2835_gpio_get,
364 .set = bcm2835_gpio_set,
365 .set_config = gpiochip_generic_config,
367 .ngpio = BCM2835_NUM_GPIOS,
371 static const struct gpio_chip bcm2711_gpio_chip = {
372 .label = "pinctrl-bcm2711",
373 .owner = THIS_MODULE,
374 .request = gpiochip_generic_request,
375 .free = gpiochip_generic_free,
376 .direction_input = bcm2835_gpio_direction_input,
377 .direction_output = bcm2835_gpio_direction_output,
378 .get_direction = bcm2835_gpio_get_direction,
379 .get = bcm2835_gpio_get,
380 .set = bcm2835_gpio_set,
381 .set_config = gpiochip_generic_config,
383 .ngpio = BCM2711_NUM_GPIOS,
387 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
388 unsigned int bank, u32 mask)
390 unsigned long events;
394 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
396 events &= pc->enabled_irq_map[bank];
397 for_each_set_bit(offset, &events, 32) {
398 gpio = (32 * bank) + offset;
399 generic_handle_domain_irq(pc->gpio_chip.irq.domain,
404 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
406 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
407 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
408 struct irq_chip *host_chip = irq_desc_get_chip(desc);
409 int irq = irq_desc_get_irq(desc);
413 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
414 if (chip->irq.parents[i] == irq) {
419 /* This should not happen, every IRQ has a bank */
420 BUG_ON(i == BCM2835_NUM_IRQS);
422 chained_irq_enter(host_chip, desc);
425 case 0: /* IRQ0 covers GPIOs 0-27 */
426 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
428 case 1: /* IRQ1 covers GPIOs 28-45 */
429 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
430 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
432 case 2: /* IRQ2 covers GPIOs 46-57 */
433 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
437 chained_irq_exit(host_chip, desc);
440 static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)
445 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
446 unsigned reg, unsigned offset, bool enable)
449 reg += GPIO_REG_OFFSET(offset) * 4;
450 value = bcm2835_gpio_rd(pc, reg);
452 value |= BIT(GPIO_REG_SHIFT(offset));
454 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
455 bcm2835_gpio_wr(pc, reg, value);
458 /* fast path for IRQ handler */
459 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
460 unsigned offset, bool enable)
462 switch (pc->irq_type[offset]) {
463 case IRQ_TYPE_EDGE_RISING:
464 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
467 case IRQ_TYPE_EDGE_FALLING:
468 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
471 case IRQ_TYPE_EDGE_BOTH:
472 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
473 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
476 case IRQ_TYPE_LEVEL_HIGH:
477 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
480 case IRQ_TYPE_LEVEL_LOW:
481 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
486 static void bcm2835_gpio_irq_enable(struct irq_data *data)
488 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
489 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
490 unsigned gpio = irqd_to_hwirq(data);
491 unsigned offset = GPIO_REG_SHIFT(gpio);
492 unsigned bank = GPIO_REG_OFFSET(gpio);
495 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
496 set_bit(offset, &pc->enabled_irq_map[bank]);
497 bcm2835_gpio_irq_config(pc, gpio, true);
498 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
501 static void bcm2835_gpio_irq_disable(struct irq_data *data)
503 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
504 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
505 unsigned gpio = irqd_to_hwirq(data);
506 unsigned offset = GPIO_REG_SHIFT(gpio);
507 unsigned bank = GPIO_REG_OFFSET(gpio);
510 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
511 bcm2835_gpio_irq_config(pc, gpio, false);
512 /* Clear events that were latched prior to clearing event sources */
513 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
514 clear_bit(offset, &pc->enabled_irq_map[bank]);
515 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
518 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
519 unsigned offset, unsigned int type)
523 case IRQ_TYPE_EDGE_RISING:
524 case IRQ_TYPE_EDGE_FALLING:
525 case IRQ_TYPE_EDGE_BOTH:
526 case IRQ_TYPE_LEVEL_HIGH:
527 case IRQ_TYPE_LEVEL_LOW:
528 pc->irq_type[offset] = type;
537 /* slower path for reconfiguring IRQ type */
538 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
539 unsigned offset, unsigned int type)
543 if (pc->irq_type[offset] != type) {
544 bcm2835_gpio_irq_config(pc, offset, false);
545 pc->irq_type[offset] = type;
549 case IRQ_TYPE_EDGE_RISING:
550 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
551 /* RISING already enabled, disable FALLING */
552 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
553 bcm2835_gpio_irq_config(pc, offset, false);
554 pc->irq_type[offset] = type;
555 } else if (pc->irq_type[offset] != type) {
556 bcm2835_gpio_irq_config(pc, offset, false);
557 pc->irq_type[offset] = type;
558 bcm2835_gpio_irq_config(pc, offset, true);
562 case IRQ_TYPE_EDGE_FALLING:
563 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
564 /* FALLING already enabled, disable RISING */
565 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
566 bcm2835_gpio_irq_config(pc, offset, false);
567 pc->irq_type[offset] = type;
568 } else if (pc->irq_type[offset] != type) {
569 bcm2835_gpio_irq_config(pc, offset, false);
570 pc->irq_type[offset] = type;
571 bcm2835_gpio_irq_config(pc, offset, true);
575 case IRQ_TYPE_EDGE_BOTH:
576 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
577 /* RISING already enabled, enable FALLING too */
578 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
579 bcm2835_gpio_irq_config(pc, offset, true);
580 pc->irq_type[offset] = type;
581 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
582 /* FALLING already enabled, enable RISING too */
583 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
584 bcm2835_gpio_irq_config(pc, offset, true);
585 pc->irq_type[offset] = type;
586 } else if (pc->irq_type[offset] != type) {
587 bcm2835_gpio_irq_config(pc, offset, false);
588 pc->irq_type[offset] = type;
589 bcm2835_gpio_irq_config(pc, offset, true);
593 case IRQ_TYPE_LEVEL_HIGH:
594 case IRQ_TYPE_LEVEL_LOW:
595 if (pc->irq_type[offset] != type) {
596 bcm2835_gpio_irq_config(pc, offset, false);
597 pc->irq_type[offset] = type;
598 bcm2835_gpio_irq_config(pc, offset, true);
608 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
610 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
611 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
612 unsigned gpio = irqd_to_hwirq(data);
613 unsigned offset = GPIO_REG_SHIFT(gpio);
614 unsigned bank = GPIO_REG_OFFSET(gpio);
618 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
620 if (test_bit(offset, &pc->enabled_irq_map[bank]))
621 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
623 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
625 if (type & IRQ_TYPE_EDGE_BOTH)
626 irq_set_handler_locked(data, handle_edge_irq);
628 irq_set_handler_locked(data, handle_level_irq);
630 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
635 static void bcm2835_gpio_irq_ack(struct irq_data *data)
637 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
638 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
639 unsigned gpio = irqd_to_hwirq(data);
641 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
644 static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
646 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
647 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
648 unsigned gpio = irqd_to_hwirq(data);
649 unsigned int irqgroup;
657 else if (gpio >= 28 && gpio <= 45)
659 else if (gpio >= 46 && gpio <= 57)
665 ret = enable_irq_wake(pc->wake_irq[irqgroup]);
667 ret = disable_irq_wake(pc->wake_irq[irqgroup]);
672 static struct irq_chip bcm2835_gpio_irq_chip = {
674 .irq_enable = bcm2835_gpio_irq_enable,
675 .irq_disable = bcm2835_gpio_irq_disable,
676 .irq_set_type = bcm2835_gpio_irq_set_type,
677 .irq_ack = bcm2835_gpio_irq_ack,
678 .irq_mask = bcm2835_gpio_irq_disable,
679 .irq_unmask = bcm2835_gpio_irq_enable,
680 .irq_set_wake = bcm2835_gpio_irq_set_wake,
681 .flags = IRQCHIP_MASK_ON_SUSPEND,
684 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
686 return BCM2835_NUM_GPIOS;
689 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
692 return bcm2835_gpio_groups[selector];
695 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
697 const unsigned **pins,
700 *pins = &bcm2835_gpio_pins[selector].number;
706 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
710 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
711 struct gpio_chip *chip = &pc->gpio_chip;
712 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
713 const char *fname = bcm2835_functions[fsel];
714 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
715 int irq = irq_find_mapping(chip->irq.domain, offset);
717 seq_printf(s, "function %s in %s; irq %d (%s)",
718 fname, value ? "hi" : "lo",
719 irq, irq_type_names[pc->irq_type[offset]]);
722 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
723 struct pinctrl_map *maps, unsigned num_maps)
727 for (i = 0; i < num_maps; i++)
728 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
729 kfree(maps[i].data.configs.configs);
734 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
735 struct device_node *np, u32 pin, u32 fnum,
736 struct pinctrl_map **maps)
738 struct pinctrl_map *map = *maps;
740 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
741 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
745 map->type = PIN_MAP_TYPE_MUX_GROUP;
746 map->data.mux.group = bcm2835_gpio_groups[pin];
747 map->data.mux.function = bcm2835_functions[fnum];
753 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
754 struct device_node *np, u32 pin, u32 pull,
755 struct pinctrl_map **maps)
757 struct pinctrl_map *map = *maps;
758 unsigned long *configs;
761 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
765 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
768 configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
770 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
771 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
772 map->data.configs.configs = configs;
773 map->data.configs.num_configs = 1;
779 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
780 struct device_node *np,
781 struct pinctrl_map **map, unsigned int *num_maps)
783 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
784 struct property *pins, *funcs, *pulls;
785 int num_pins, num_funcs, num_pulls, maps_per_pin;
786 struct pinctrl_map *maps, *cur_map;
790 /* Check for generic binding in this node */
791 err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
792 if (err || *num_maps)
795 /* Generic binding did not find anything continue with legacy parse */
796 pins = of_find_property(np, "brcm,pins", NULL);
798 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
802 funcs = of_find_property(np, "brcm,function", NULL);
803 pulls = of_find_property(np, "brcm,pull", NULL);
805 if (!funcs && !pulls) {
807 "%pOF: neither brcm,function nor brcm,pull specified\n",
812 num_pins = pins->length / 4;
813 num_funcs = funcs ? (funcs->length / 4) : 0;
814 num_pulls = pulls ? (pulls->length / 4) : 0;
816 if (num_funcs > 1 && num_funcs != num_pins) {
818 "%pOF: brcm,function must have 1 or %d entries\n",
823 if (num_pulls > 1 && num_pulls != num_pins) {
825 "%pOF: brcm,pull must have 1 or %d entries\n",
835 cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
840 for (i = 0; i < num_pins; i++) {
841 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
844 if (pin >= pc->pctl_desc.npins) {
845 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
852 err = of_property_read_u32_index(np, "brcm,function",
853 (num_funcs > 1) ? i : 0, &func);
856 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
862 err = of_property_read_u32_index(np, "brcm,pull",
863 (num_pulls > 1) ? i : 0, &pull);
866 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
874 *num_maps = num_pins * maps_per_pin;
879 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
883 static const struct pinctrl_ops bcm2835_pctl_ops = {
884 .get_groups_count = bcm2835_pctl_get_groups_count,
885 .get_group_name = bcm2835_pctl_get_group_name,
886 .get_group_pins = bcm2835_pctl_get_group_pins,
887 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
888 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
889 .dt_free_map = bcm2835_pctl_dt_free_map,
892 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
895 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
897 /* disable by setting to GPIO_IN */
898 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
902 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
904 return BCM2835_FSEL_COUNT;
907 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
910 return bcm2835_functions[selector];
913 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
915 const char * const **groups,
916 unsigned * const num_groups)
918 /* every pin can do every function */
919 *groups = bcm2835_gpio_groups;
920 *num_groups = BCM2835_NUM_GPIOS;
925 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
926 unsigned func_selector,
927 unsigned group_selector)
929 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
931 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
936 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
937 struct pinctrl_gpio_range *range,
940 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
942 /* disable by setting to GPIO_IN */
943 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
946 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
947 struct pinctrl_gpio_range *range,
951 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
952 enum bcm2835_fsel fsel = input ?
953 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
955 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
960 static const struct pinmux_ops bcm2835_pmx_ops = {
961 .free = bcm2835_pmx_free,
962 .get_functions_count = bcm2835_pmx_get_functions_count,
963 .get_function_name = bcm2835_pmx_get_function_name,
964 .get_function_groups = bcm2835_pmx_get_function_groups,
965 .set_mux = bcm2835_pmx_set,
966 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
967 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
970 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
971 unsigned pin, unsigned long *config)
973 /* No way to read back config in HW */
977 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
978 unsigned int pin, unsigned int arg)
982 off = GPIO_REG_OFFSET(pin);
983 bit = GPIO_REG_SHIFT(pin);
985 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
987 * BCM2835 datasheet say to wait 150 cycles, but not of what.
988 * But the VideoCore firmware delay for this operation
989 * based nearly on the same amount of VPU cycles and this clock
993 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
995 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
998 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
999 unsigned int pin, unsigned long *configs,
1000 unsigned int num_configs)
1002 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1006 for (i = 0; i < num_configs; i++) {
1007 param = pinconf_to_config_param(configs[i]);
1008 arg = pinconf_to_config_argument(configs[i]);
1011 /* Set legacy brcm,pull */
1012 case BCM2835_PINCONF_PARAM_PULL:
1013 bcm2835_pull_config_set(pc, pin, arg);
1016 /* Set pull generic bindings */
1017 case PIN_CONFIG_BIAS_DISABLE:
1018 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
1021 case PIN_CONFIG_BIAS_PULL_DOWN:
1022 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
1025 case PIN_CONFIG_BIAS_PULL_UP:
1026 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
1029 /* Set output-high or output-low */
1030 case PIN_CONFIG_OUTPUT:
1031 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1037 } /* switch param type */
1038 } /* for each config */
1043 static const struct pinconf_ops bcm2835_pinconf_ops = {
1045 .pin_config_get = bcm2835_pinconf_get,
1046 .pin_config_set = bcm2835_pinconf_set,
1049 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
1050 unsigned int pin, unsigned int arg)
1056 off = PUD_2711_REG_OFFSET(pin);
1057 shifter = PUD_2711_REG_SHIFT(pin);
1059 value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
1060 value &= ~(PUD_2711_MASK << shifter);
1061 value |= (arg << shifter);
1062 bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1065 static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
1066 unsigned int pin, unsigned long *configs,
1067 unsigned int num_configs)
1069 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1073 for (i = 0; i < num_configs; i++) {
1074 param = pinconf_to_config_param(configs[i]);
1075 arg = pinconf_to_config_argument(configs[i]);
1078 /* convert legacy brcm,pull */
1079 case BCM2835_PINCONF_PARAM_PULL:
1080 if (arg == BCM2835_PUD_UP)
1081 arg = BCM2711_PULL_UP;
1082 else if (arg == BCM2835_PUD_DOWN)
1083 arg = BCM2711_PULL_DOWN;
1085 arg = BCM2711_PULL_NONE;
1087 bcm2711_pull_config_set(pc, pin, arg);
1090 /* Set pull generic bindings */
1091 case PIN_CONFIG_BIAS_DISABLE:
1092 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
1094 case PIN_CONFIG_BIAS_PULL_DOWN:
1095 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
1097 case PIN_CONFIG_BIAS_PULL_UP:
1098 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
1101 /* Set output-high or output-low */
1102 case PIN_CONFIG_OUTPUT:
1103 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1109 } /* for each config */
1114 static const struct pinconf_ops bcm2711_pinconf_ops = {
1116 .pin_config_get = bcm2835_pinconf_get,
1117 .pin_config_set = bcm2711_pinconf_set,
1120 static const struct pinctrl_desc bcm2835_pinctrl_desc = {
1121 .name = MODULE_NAME,
1122 .pins = bcm2835_gpio_pins,
1123 .npins = BCM2835_NUM_GPIOS,
1124 .pctlops = &bcm2835_pctl_ops,
1125 .pmxops = &bcm2835_pmx_ops,
1126 .confops = &bcm2835_pinconf_ops,
1127 .owner = THIS_MODULE,
1130 static const struct pinctrl_desc bcm2711_pinctrl_desc = {
1131 .name = "pinctrl-bcm2711",
1132 .pins = bcm2835_gpio_pins,
1133 .npins = BCM2711_NUM_GPIOS,
1134 .pctlops = &bcm2835_pctl_ops,
1135 .pmxops = &bcm2835_pmx_ops,
1136 .confops = &bcm2711_pinconf_ops,
1137 .owner = THIS_MODULE,
1140 static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
1141 .name = MODULE_NAME,
1142 .npins = BCM2835_NUM_GPIOS,
1145 static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
1146 .name = "pinctrl-bcm2711",
1147 .npins = BCM2711_NUM_GPIOS,
1150 struct bcm_plat_data {
1151 const struct gpio_chip *gpio_chip;
1152 const struct pinctrl_desc *pctl_desc;
1153 const struct pinctrl_gpio_range *gpio_range;
1156 static const struct bcm_plat_data bcm2835_plat_data = {
1157 .gpio_chip = &bcm2835_gpio_chip,
1158 .pctl_desc = &bcm2835_pinctrl_desc,
1159 .gpio_range = &bcm2835_pinctrl_gpio_range,
1162 static const struct bcm_plat_data bcm2711_plat_data = {
1163 .gpio_chip = &bcm2711_gpio_chip,
1164 .pctl_desc = &bcm2711_pinctrl_desc,
1165 .gpio_range = &bcm2711_pinctrl_gpio_range,
1168 static const struct of_device_id bcm2835_pinctrl_match[] = {
1170 .compatible = "brcm,bcm2835-gpio",
1171 .data = &bcm2835_plat_data,
1174 .compatible = "brcm,bcm2711-gpio",
1175 .data = &bcm2711_plat_data,
1178 .compatible = "brcm,bcm7211-gpio",
1179 .data = &bcm2711_plat_data,
1184 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
1186 struct device *dev = &pdev->dev;
1187 struct device_node *np = dev->of_node;
1188 const struct bcm_plat_data *pdata;
1189 struct bcm2835_pinctrl *pc;
1190 struct gpio_irq_chip *girq;
1191 struct resource iomem;
1193 const struct of_device_id *match;
1196 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
1197 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
1199 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1203 platform_set_drvdata(pdev, pc);
1206 err = of_address_to_resource(np, 0, &iomem);
1208 dev_err(dev, "could not get IO memory\n");
1212 pc->base = devm_ioremap_resource(dev, &iomem);
1213 if (IS_ERR(pc->base))
1214 return PTR_ERR(pc->base);
1216 match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
1220 pdata = match->data;
1221 is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio");
1223 pc->gpio_chip = *pdata->gpio_chip;
1224 pc->gpio_chip.parent = dev;
1225 pc->gpio_chip.of_node = np;
1227 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1228 unsigned long events;
1231 /* clear event detection flags */
1232 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1233 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1234 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1235 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1236 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1237 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1239 /* clear all the events */
1240 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1241 for_each_set_bit(offset, &events, 32)
1242 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1244 raw_spin_lock_init(&pc->irq_lock[i]);
1247 girq = &pc->gpio_chip.irq;
1248 girq->chip = &bcm2835_gpio_irq_chip;
1249 girq->parent_handler = bcm2835_gpio_irq_handler;
1250 girq->num_parents = BCM2835_NUM_IRQS;
1251 girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1252 sizeof(*girq->parents),
1258 pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1259 sizeof(*pc->wake_irq),
1266 * Use the same handler for all groups: this is necessary
1267 * since we use one gpiochip to cover all lines - the
1268 * irq handler then needs to figure out which group and
1269 * bank that was firing the IRQ and look up the per-group
1272 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1276 girq->parents[i] = irq_of_parse_and_map(np, i);
1278 if (!girq->parents[i]) {
1279 girq->num_parents = i;
1284 /* Skip over the all banks interrupts */
1285 pc->wake_irq[i] = irq_of_parse_and_map(np, i +
1286 BCM2835_NUM_IRQS + 1);
1288 len = strlen(dev_name(pc->dev)) + 16;
1289 name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1293 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1295 /* These are optional interrupts */
1296 err = devm_request_irq(dev, pc->wake_irq[i],
1297 bcm2835_gpio_wake_irq_handler,
1298 IRQF_SHARED, name, pc);
1300 dev_warn(dev, "unable to request wake IRQ %d\n",
1304 girq->default_type = IRQ_TYPE_NONE;
1305 girq->handler = handle_level_irq;
1307 err = gpiochip_add_data(&pc->gpio_chip, pc);
1309 dev_err(dev, "could not add GPIO chip\n");
1313 pc->pctl_desc = *pdata->pctl_desc;
1314 pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
1315 if (IS_ERR(pc->pctl_dev)) {
1316 gpiochip_remove(&pc->gpio_chip);
1317 return PTR_ERR(pc->pctl_dev);
1320 pc->gpio_range = *pdata->gpio_range;
1321 pc->gpio_range.base = pc->gpio_chip.base;
1322 pc->gpio_range.gc = &pc->gpio_chip;
1323 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1328 static struct platform_driver bcm2835_pinctrl_driver = {
1329 .probe = bcm2835_pinctrl_probe,
1331 .name = MODULE_NAME,
1332 .of_match_table = bcm2835_pinctrl_match,
1333 .suppress_bind_attrs = true,
1336 module_platform_driver(bcm2835_pinctrl_driver);
1338 MODULE_AUTHOR("Chris Boot");
1339 MODULE_AUTHOR("Simon Arlott");
1340 MODULE_AUTHOR("Stephen Warren");
1341 MODULE_DESCRIPTION("Broadcom BCM2835/2711 pinctrl and GPIO driver");
1342 MODULE_LICENSE("GPL");