1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Copyright (C) 2019 IBM Corp. */
4 #ifndef ASPEED_PINMUX_H
5 #define ASPEED_PINMUX_H
7 #include <linux/regmap.h>
11 * The ASPEED SoCs provide typically more than 200 pins for GPIO and other
12 * functions. The SoC function enabled on a pin is determined on a priority
13 * basis where a given pin can provide a number of different signal types.
15 * The signal active on a pin is described by both a priority level and
16 * compound logical expressions involving multiple operators, registers and
17 * bits. Some difficulty arises as the pin's function bit masks for each
18 * priority level are frequently not the same (i.e. cannot just flip a bit to
19 * change from a high to low priority signal), or even in the same register.
20 * Further, not all signals can be unmuxed, as some expressions depend on
21 * values in the hardware strapping register (which may be treated as
24 * SoC Multi-function Pin Expression Examples
25 * ------------------------------------------
27 * Here are some sample mux configurations from the AST2400 and AST2500
28 * datasheets to illustrate the corner cases, roughly in order of least to most
29 * corner. The signal priorities are in decending order from P0 (highest).
31 * D6 is a pin with a single function (beside GPIO); a high priority signal
32 * that participates in one function:
34 * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
35 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
36 * D6 GPIOA0 MAC1LINK SCU80[0]=1 GPIOA0
37 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
39 * C5 is a multi-signal pin (high and low priority signals). Here we touch
40 * different registers for the different functions that enable each signal:
42 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
43 * C5 GPIOA4 SCL9 SCU90[22]=1 TIMER5 SCU80[4]=1 GPIOA4
44 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
46 * E19 is a single-signal pin with two functions that influence the active
47 * signal. In this case both bits have the same meaning - enable a dedicated
48 * LPC reset pin. However it's not always the case that the bits in the
49 * OR-relationship have the same meaning.
51 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
52 * E19 GPIOB4 LPCRST# SCU80[12]=1 | Strap[14]=1 GPIOB4
53 * -----+---------+-----------+-----------------------------+-----------+---------------+----------
55 * For example, pin B19 has a low-priority signal that's enabled by two
56 * distinct SoC functions: A specific SIOPBI bit in register SCUA4, and an ACPI
57 * bit in the STRAP register. The ACPI bit configures signals on pins in
58 * addition to B19. Both of the low priority functions as well as the high
59 * priority function must be disabled for GPIOF1 to be used.
61 * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
62 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
63 * B19 GPIOF1 NDCD4 SCU80[25]=1 SIOPBI# SCUA4[12]=1 | Strap[19]=0 GPIOF1
64 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
66 * For pin E18, the SoC ANDs the expected state of three bits to determine the
67 * pin's active signal:
69 * * SCU3C[3]: Enable external SOC reset function
70 * * SCU80[15]: Enable SPICS1# or EXTRST# function pin
71 * * SCU90[31]: Select SPI interface CS# output
73 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
74 * E18 GPIOB7 EXTRST# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=0 SPICS1# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=1 GPIOB7
75 * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
77 * (Bits SCU3C[3] and SCU80[15] appear to only be used in the expressions for
78 * selecting the signals on pin E18)
80 * Pin T5 is a multi-signal pin with a more complex configuration:
82 * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
83 * -----+---------+-----------+------------------------------+-----------+---------------+----------
84 * T5 GPIOL1 VPIDE SCU90[5:4]!=0 & SCU84[17]=1 NDCD1 SCU84[17]=1 GPIOL1
85 * -----+---------+-----------+------------------------------+-----------+---------------+----------
87 * The high priority signal configuration is best thought of in terms of its
88 * exploded form, with reference to the SCU90[5:4] bits:
90 * * SCU90[5:4]=00: disable
91 * * SCU90[5:4]=01: 18 bits (R6/G6/B6) video mode.
92 * * SCU90[5:4]=10: 24 bits (R8/G8/B8) video mode.
93 * * SCU90[5:4]=11: 30 bits (R10/G10/B10) video mode.
97 * -----+---------+-----------+------------------------------+-----------+---------------+----------
98 * T5 GPIOL1 VPIDE (SCU90[5:4]=1 & SCU84[17]=1) NDCD1 SCU84[17]=1 GPIOL1
99 * | (SCU90[5:4]=2 & SCU84[17]=1)
100 * | (SCU90[5:4]=3 & SCU84[17]=1)
101 * -----+---------+-----------+------------------------------+-----------+---------------+----------
103 * For reference the SCU84[17] bit configure the "UART1 NDCD1 or Video VPIDE
104 * function pin", where the signal itself is determined by whether SCU94[5:4]
105 * is disabled or in one of the 18, 24 or 30bit video modes.
107 * Other video-input-related pins require an explicit state in SCU90[5:4], e.g.
110 * -----+---------+-----------+------------------------------+-----------+---------------+----------
111 * W1 GPIOL6 VPIB0 SCU90[5:4]=3 & SCU84[22]=1 TXD1 SCU84[22]=1 GPIOL6
112 * U5 GPIOL7 VPIB1 SCU90[5:4]=3 & SCU84[23]=1 RXD1 SCU84[23]=1 GPIOL7
113 * -----+---------+-----------+------------------------------+-----------+---------------+----------
115 * The examples of T5 and W1 are particularly fertile, as they also demonstrate
116 * that despite operating as part of the video input bus each signal needs to
117 * be enabled individually via it's own SCU84 (in the cases of T5 and W1)
118 * register bit. This is a little crazy if the bus doesn't have optional
119 * signals, but is used to decent effect with some of the UARTs where not all
120 * signals are required. However, this isn't done consistently - UART1 is
121 * enabled on a per-pin basis, and by contrast, all signals for UART6 are
122 * enabled by a single bit.
124 * Further, the high and low priority signals listed in the table above share
125 * a configuration bit. The VPI signals should operate in concert in a single
126 * function, but the UART signals should retain the ability to be configured
127 * independently. This pushes the implementation down the path of tagging a
128 * signal's expressions with the function they participate in, rather than
129 * defining masks affecting multiple signals per function. The latter approach
130 * fails in this instance where applying the configuration for the UART pin of
131 * interest will stomp on the state of other UART signals when disabling the
132 * VPI functions on the current pin.
134 * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
135 * -----+------------+-----------+---------------------------+-----------+---------------+------------
136 * A12 RGMII1TXCK GPIOT0 SCUA0[0]=1 RMII1TXEN Strap[6]=0 RGMII1TXCK
137 * B12 RGMII1TXCTL GPIOT1 SCUA0[1]=1 – Strap[6]=0 RGMII1TXCTL
138 * -----+------------+-----------+---------------------------+-----------+---------------+------------
140 * A12 demonstrates that the "Other" signal isn't always GPIO - in this case
141 * GPIOT0 is a high-priority signal and RGMII1TXCK is Other. Thus, GPIO
142 * should be treated like any other signal type with full function expression
143 * requirements, and not assumed to be the default case. Separately, GPIOT0 and
144 * GPIOT1's signal descriptor bits are distinct, therefore we must iterate all
145 * pins in the function's group to disable the higher-priority signals such
146 * that the signal for the function of interest is correctly enabled.
148 * Finally, three priority levels aren't always enough; the AST2500 brings with
149 * it 18 pins of five priority levels, however the 18 pins only use three of
150 * the five priority levels.
152 * Ultimately the requirement to control pins in the examples above drive the
155 * * Pins provide signals according to functions activated in the mux
158 * * Pins provide up to five signal types in a priority order
160 * * For priorities levels defined on a pin, each priority provides one signal
162 * * Enabling lower priority signals requires higher priority signals be
165 * * A function represents a set of signals; functions are distinct if their
166 * sets of signals are not equal
168 * * Signals participate in one or more functions
170 * * A function is described by an expression of one or more signal
171 * descriptors, which compare bit values in a register
173 * * A signal expression is the smallest set of signal descriptors whose
174 * comparisons must evaluate 'true' for a signal to be enabled on a pin.
176 * * A signal participating in a function is active on a pin if evaluating all
177 * signal descriptors in the pin's signal expression for the function yields
180 * * A signal at a given priority on a given pin is active if any of the
181 * functions in which the signal participates are active, and no higher
182 * priority signal on the pin is active
184 * * GPIO is configured per-pin
188 * * To disable a signal, any function(s) activating the signal must be
191 * * Each pin must know the signal expressions of functions in which it
192 * participates, for the purpose of enabling the Other function. This is done
193 * by deactivating all functions that activate higher priority signals on the
196 * As a concrete example:
198 * * T5 provides three signals types: VPIDE, NDCD1 and GPIO
200 * * The VPIDE signal participates in 3 functions: VPI18, VPI24 and VPI30
202 * * The NDCD1 signal participates in just its own NDCD1 function
204 * * VPIDE is high priority, NDCD1 is low priority, and GPIOL1 is the least
207 * * The prerequisit for activating the NDCD1 signal is that the VPI18, VPI24
208 * and VPI30 functions all be disabled
210 * * Similarly, all of VPI18, VPI24, VPI30 and NDCD1 functions must be disabled
216 * If pinctrl allows us to allocate a pin we can configure a function without
217 * concern for the function of already allocated pins, if pin groups are
218 * created with respect to the SoC functions in which they participate. This is
219 * intuitive, but it did not feel obvious from the bit/pin relationships.
221 * Conversely, failing to allocate all pins in a group indicates some bits (as
222 * well as pins) required for the group's configuration will already be in use,
223 * likely in a way that's inconsistent with the requirements of the failed
229 * Beyond the documentation below the various structures and helper macros that
230 * allow the implementation to hang together are defined. The macros are fairly
231 * dense, so below we walk through some raw examples of the configuration
232 * tables in an effort to clarify the concepts.
234 * The complexity of configuring the mux combined with the scale of the pins
235 * and functions was a concern, so the table design along with the macro jungle
236 * is an attempt to address it. The rough principles of the approach are:
238 * 1. Use a data-driven solution rather than embedding state into code
239 * 2. Minimise editing to the specifics of the given mux configuration
240 * 3. Detect as many errors as possible at compile time
242 * Addressing point 3 leads to naming of symbols in terms of the four
243 * properties associated with a given mux configuration: The pin, the signal,
244 * the group and the function. In this way copy/paste errors cause duplicate
245 * symbols to be defined, which prevents successful compilation. Failing to
246 * properly parent the tables leads to unused symbol warnings, and use of
247 * designated initialisers and additional warnings ensures that there are
248 * no override errors in the pin, group and function arrays.
250 * Addressing point 2 drives the development of the macro jungle, as it
251 * centralises the definition noise at the cost of taking some time to
254 * Here's a complete, concrete "pre-processed" example of the table structures
255 * used to describe the D6 ball from the examples above:
258 * static const struct aspeed_sig_desc sig_descs_MAC1LINK_MAC1LINK[] = {
260 * .ip = ASPEED_IP_SCU,
268 * static const struct aspeed_sig_expr sig_expr_MAC1LINK_MAC1LINK = {
269 * .signal = "MAC1LINK",
270 * .function = "MAC1LINK",
271 * .ndescs = ARRAY_SIZE(sig_descs_MAC1LINK_MAC1LINK),
272 * .descs = &(sig_descs_MAC1LINK_MAC1LINK)[0],
275 * static const struct aspeed_sig_expr *sig_exprs_MAC1LINK_MAC1LINK[] = {
276 * &sig_expr_MAC1LINK_MAC1LINK,
280 * static const struct aspeed_sig_desc sig_descs_GPIOA0_GPIOA0[] = { };
282 * static const struct aspeed_sig_expr sig_expr_GPIOA0_GPIOA0 = {
283 * .signal = "GPIOA0",
284 * .function = "GPIOA0",
285 * .ndescs = ARRAY_SIZE(sig_descs_GPIOA0_GPIOA0),
286 * .descs = &(sig_descs_GPIOA0_GPIOA0)[0],
289 * static const struct aspeed_sig_expr *sig_exprs_GPIOA0_GPIOA0[] = {
290 * &sig_expr_GPIOA0_GPIOA0,
294 * static const struct aspeed_sig_expr **pin_exprs_0[] = {
295 * sig_exprs_MAC1LINK_MAC1LINK,
296 * sig_exprs_GPIOA0_GPIOA0,
300 * static const struct aspeed_pin_desc pin_0 = { "0", (&pin_exprs_0[0]) };
301 * static const int group_pins_MAC1LINK[] = { 0 };
302 * static const char *func_groups_MAC1LINK[] = { "MAC1LINK" };
304 * static struct pinctrl_pin_desc aspeed_g4_pins[] = {
305 * [0] = { .number = 0, .name = "D6", .drv_data = &pin_0 },
308 * static const struct aspeed_pin_group aspeed_g4_groups[] = {
310 * .name = "MAC1LINK",
311 * .pins = &(group_pins_MAC1LINK)[0],
312 * .npins = ARRAY_SIZE(group_pins_MAC1LINK),
316 * static const struct aspeed_pin_function aspeed_g4_functions[] = {
318 * .name = "MAC1LINK",
319 * .groups = &func_groups_MAC1LINK[0],
320 * .ngroups = ARRAY_SIZE(func_groups_MAC1LINK),
325 * At the end of the day much of the above code is compressed into the
326 * following two lines:
330 * SSSF_PIN_DECL(D6, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
333 * The two examples below show just the differences from the example above.
335 * Ball E18 demonstrates a function, EXTRST, that requires multiple descriptors
336 * be set for it to be muxed:
339 * static const struct aspeed_sig_desc sig_descs_EXTRST_EXTRST[] = {
341 * .ip = ASPEED_IP_SCU,
348 * .ip = ASPEED_IP_SCU,
355 * .ip = ASPEED_IP_SCU,
363 * static const struct aspeed_sig_expr sig_expr_EXTRST_EXTRST = {
364 * .signal = "EXTRST",
365 * .function = "EXTRST",
366 * .ndescs = ARRAY_SIZE(sig_descs_EXTRST_EXTRST),
367 * .descs = &(sig_descs_EXTRST_EXTRST)[0],
372 * For ball E19, we have multiple functions enabling a single signal, LPCRST#.
373 * The data structures look like:
375 * static const struct aspeed_sig_desc sig_descs_LPCRST_LPCRST[] = {
377 * .ip = ASPEED_IP_SCU,
385 * static const struct aspeed_sig_expr sig_expr_LPCRST_LPCRST = {
386 * .signal = "LPCRST",
387 * .function = "LPCRST",
388 * .ndescs = ARRAY_SIZE(sig_descs_LPCRST_LPCRST),
389 * .descs = &(sig_descs_LPCRST_LPCRST)[0],
392 * static const struct aspeed_sig_desc sig_descs_LPCRST_LPCRSTS[] = {
394 * .ip = ASPEED_IP_SCU,
402 * static const struct aspeed_sig_expr sig_expr_LPCRST_LPCRSTS = {
403 * .signal = "LPCRST",
404 * .function = "LPCRSTS",
405 * .ndescs = ARRAY_SIZE(sig_descs_LPCRST_LPCRSTS),
406 * .descs = &(sig_descs_LPCRST_LPCRSTS)[0],
409 * static const struct aspeed_sig_expr *sig_exprs_LPCRST_LPCRST[] = {
410 * &sig_expr_LPCRST_LPCRST,
411 * &sig_expr_LPCRST_LPCRSTS,
417 * Both expressions listed in the sig_exprs_LPCRST_LPCRST array need to be set
418 * to disabled for the associated GPIO to be muxed.
422 #define ASPEED_IP_SCU 0
423 #define ASPEED_IP_GFX 1
424 #define ASPEED_IP_LPC 2
425 #define ASPEED_NR_PINMUX_IPS 3
428 * A signal descriptor, which describes the register, bits and the
429 * enable/disable values that should be compared or written.
431 * @ip: The IP block identifier, used as an index into the regmap array in
432 * struct aspeed_pinctrl_data
433 * @reg: The register offset with respect to the base address of the IP block
434 * @mask: The mask to apply to the register. The lowest set bit of the mask is
435 * used to derive the shift value.
436 * @enable: The value that enables the function. Value should be in the LSBs,
437 * not at the position of the mask.
438 * @disable: The value that disables the function. Value should be in the
439 * LSBs, not at the position of the mask.
441 struct aspeed_sig_desc {
450 * Describes a signal expression. The expression is evaluated by ANDing the
451 * evaluation of the descriptors.
453 * @signal: The signal name for the priority level on the pin. If the signal
454 * type is GPIO, then the signal name must begin with the string
455 * "GPIO", e.g. GPIOA0, GPIOT4 etc.
456 * @function: The name of the function the signal participates in for the
457 * associated expression
458 * @ndescs: The number of signal descriptors in the expression
459 * @descs: Pointer to an array of signal descriptors that comprise the
460 * function expression
462 struct aspeed_sig_expr {
464 const char *function;
466 const struct aspeed_sig_desc *descs;
470 * A struct capturing the list of expressions enabling signals at each priority
471 * for a given pin. The signal configuration for a priority level is evaluated
472 * by ORing the evaluation of the signal expressions in the respective
475 * @name: A name for the pin
476 * @prios: A pointer to an array of expression list pointers
479 struct aspeed_pin_desc {
481 const struct aspeed_sig_expr ***prios;
486 #define SIG_DESC_IP_BIT(ip, reg, idx, val) \
487 { ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) }
490 * Short-hand macro for describing an SCU descriptor enabled by the state of
491 * one bit. The disable value is derived.
493 * @reg: The signal's associated register, offset from base
494 * @idx: The signal's bit index in the register
495 * @val: The value (0 or 1) that enables the function
497 #define SIG_DESC_BIT(reg, idx, val) \
498 SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val)
500 #define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1)
503 * A further short-hand macro expanding to an SCU descriptor enabled by a set
506 * @reg: The register, offset from base
507 * @idx: The bit index in the register
509 #define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
511 #define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func
512 #define SIG_DESC_LIST_DECL(sig, func, ...) \
513 static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, func)[] = \
516 #define SIG_EXPR_SYM(sig, func) sig_expr_ ## sig ## _ ## func
517 #define SIG_EXPR_DECL_(sig, func) \
518 static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, func) = \
522 .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, func)), \
523 .descs = &(SIG_DESC_LIST_SYM(sig, func))[0], \
527 * Declare a signal expression.
529 * @sig: A macro symbol name for the signal (is subjected to stringification
531 * @func: The function in which the signal is participating
532 * @...: Signal descriptors that define the signal expression
534 * For example, the following declares the ROMD8 signal for the ROM16 function:
536 * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
538 * And with multiple signal descriptors:
540 * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
541 * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
543 #define SIG_EXPR_DECL(sig, func, ...) \
544 SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
545 SIG_EXPR_DECL_(sig, func)
548 * Declare a pointer to a signal expression
550 * @sig: The macro symbol name for the signal (subjected to token pasting)
551 * @func: The macro symbol name for the function (subjected to token pasting)
553 #define SIG_EXPR_PTR(sig, func) (&SIG_EXPR_SYM(sig, func))
555 #define SIG_EXPR_LIST_SYM(sig) sig_exprs_ ## sig
558 * Declare a signal expression list for reference in a struct aspeed_pin_prio.
560 * @sig: A macro symbol name for the signal (is subjected to token pasting)
561 * @...: Signal expression structure pointers (use SIG_EXPR_PTR())
563 * For example, the 16-bit ROM bus can be enabled by one of two possible signal
566 * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
567 * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
568 * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
569 * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
570 * SIG_EXPR_PTR(ROMD8, ROM16S));
572 #define SIG_EXPR_LIST_DECL(sig, ...) \
573 static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig)[] = \
574 { __VA_ARGS__, NULL }
577 * A short-hand macro for declaring a function expression and an expression
578 * list with a single function.
580 * @func: A macro symbol name for the function (is subjected to token pasting)
581 * @...: Function descriptors that define the function expression
583 * For example, signal NCTS6 participates in its own function with one group:
585 * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
587 #define SIG_EXPR_LIST_DECL_SINGLE(sig, func, ...) \
588 SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
589 SIG_EXPR_DECL_(sig, func); \
590 SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, func))
592 #define SIG_EXPR_LIST_DECL_DUAL(sig, f0, f1) \
593 SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, f0), SIG_EXPR_PTR(sig, f1))
595 #define SIG_EXPR_LIST_PTR(sig) (&SIG_EXPR_LIST_SYM(sig)[0])
597 #define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin
598 #define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0])
599 #define PIN_SYM(pin) pin_ ## pin
601 #define MS_PIN_DECL_(pin, ...) \
602 static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \
603 { __VA_ARGS__, NULL }; \
604 static const struct aspeed_pin_desc PIN_SYM(pin) = \
605 { #pin, PIN_EXPRS_PTR(pin) }
608 * Declare a multi-signal pin
610 * @pin: The pin number
611 * @other: Macro name for "other" functionality (subjected to stringification)
612 * @high: Macro name for the highest priority signal functions
613 * @low: Macro name for the low signal functions
618 * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
619 * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
620 * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
621 * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
622 * SIG_EXPR_PTR(ROMD8, ROM16S));
623 * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
624 * MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6);
626 #define MS_PIN_DECL(pin, other, high, low) \
627 SIG_EXPR_LIST_DECL_SINGLE(other, other); \
629 SIG_EXPR_LIST_PTR(high), \
630 SIG_EXPR_LIST_PTR(low), \
631 SIG_EXPR_LIST_PTR(other))
633 #define PIN_GROUP_SYM(func) pins_ ## func
634 #define FUNC_GROUP_SYM(func) groups_ ## func
635 #define FUNC_GROUP_DECL(func, ...) \
636 static const int PIN_GROUP_SYM(func)[] = { __VA_ARGS__ }; \
637 static const char *FUNC_GROUP_SYM(func)[] = { #func }
640 * Declare a single signal pin
642 * @pin: The pin number
643 * @other: Macro name for "other" functionality (subjected to stringification)
644 * @sig: Macro name for the signal (subjected to stringification)
649 * SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
650 * SS_PIN_DECL(E3, GPIOK0, SCL5);
652 #define SS_PIN_DECL(pin, other, sig) \
653 SIG_EXPR_LIST_DECL_SINGLE(other, other); \
654 MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other))
657 * Single signal, single function pin declaration
659 * @pin: The pin number
660 * @other: Macro name for "other" functionality (subjected to stringification)
661 * @sig: Macro name for the signal (subjected to stringification)
662 * @...: Signal descriptors that define the function expression
666 * SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
668 #define SSSF_PIN_DECL(pin, other, sig, ...) \
669 SIG_EXPR_LIST_DECL_SINGLE(sig, sig, __VA_ARGS__); \
670 SIG_EXPR_LIST_DECL_SINGLE(other, other); \
671 MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)); \
672 FUNC_GROUP_DECL(sig, pin)
674 #define GPIO_PIN_DECL(pin, gpio) \
675 SIG_EXPR_LIST_DECL_SINGLE(gpio, gpio); \
676 MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio))
678 struct aspeed_pin_group {
680 const unsigned int *pins;
681 const unsigned int npins;
684 #define ASPEED_PINCTRL_GROUP(name_) { \
686 .pins = &(PIN_GROUP_SYM(name_))[0], \
687 .npins = ARRAY_SIZE(PIN_GROUP_SYM(name_)), \
690 struct aspeed_pin_function {
692 const char *const *groups;
693 unsigned int ngroups;
696 #define ASPEED_PINCTRL_FUNC(name_, ...) { \
698 .groups = &FUNC_GROUP_SYM(name_)[0], \
699 .ngroups = ARRAY_SIZE(FUNC_GROUP_SYM(name_)), \
702 struct aspeed_pinmux_data;
704 struct aspeed_pinmux_ops {
705 int (*set)(struct aspeed_pinmux_data *ctx,
706 const struct aspeed_sig_expr *expr, bool enabled);
709 struct aspeed_pinmux_data {
711 struct regmap *maps[ASPEED_NR_PINMUX_IPS];
713 const struct aspeed_pinmux_ops *ops;
715 const struct aspeed_pin_group *groups;
716 const unsigned int ngroups;
718 const struct aspeed_pin_function *functions;
719 const unsigned int nfunctions;
722 int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, bool enabled,
725 int aspeed_sig_expr_eval(const struct aspeed_pinmux_data *ctx,
726 const struct aspeed_sig_expr *expr,
729 static inline int aspeed_sig_expr_set(struct aspeed_pinmux_data *ctx,
730 const struct aspeed_sig_expr *expr,
733 return ctx->ops->set(ctx, expr, enabled);
736 #endif /* ASPEED_PINMUX_H */