Merge tag 'for-5.8/dm-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/devic...
[linux-2.6-microblaze.git] / drivers / pinctrl / actions / pinctrl-owl.h
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * OWL SoC's Pinctrl definitions
4  *
5  * Copyright (c) 2014 Actions Semi Inc.
6  * Author: David Liu <liuwei@actions-semi.com>
7  *
8  * Copyright (c) 2018 Linaro Ltd.
9  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10  */
11
12 #ifndef __PINCTRL_OWL_H__
13 #define __PINCTRL_OWL_H__
14
15 #define OWL_PINCONF_SLEW_SLOW 0
16 #define OWL_PINCONF_SLEW_FAST 1
17
18 #define MUX_PG(group_name, reg, shift, width)                           \
19         {                                                               \
20                 .name = #group_name,                                    \
21                 .pads = group_name##_pads,                              \
22                 .npads = ARRAY_SIZE(group_name##_pads),                 \
23                 .funcs = group_name##_funcs,                            \
24                 .nfuncs = ARRAY_SIZE(group_name##_funcs),               \
25                 .mfpctl_reg  = MFCTL##reg,                              \
26                 .mfpctl_shift = shift,                                  \
27                 .mfpctl_width = width,                                  \
28                 .drv_reg = -1,                                          \
29                 .drv_shift = -1,                                        \
30                 .drv_width = -1,                                        \
31                 .sr_reg = -1,                                           \
32                 .sr_shift = -1,                                         \
33                 .sr_width = -1,                                         \
34         }
35
36 #define DRV_PG(group_name, reg, shift, width)                           \
37         {                                                               \
38                 .name = #group_name,                                    \
39                 .pads = group_name##_pads,                              \
40                 .npads = ARRAY_SIZE(group_name##_pads),                 \
41                 .mfpctl_reg  = -1,                                      \
42                 .mfpctl_shift = -1,                                     \
43                 .mfpctl_width = -1,                                     \
44                 .drv_reg = PAD_DRV##reg,                                \
45                 .drv_shift = shift,                                     \
46                 .drv_width = width,                                     \
47                 .sr_reg = -1,                                           \
48                 .sr_shift = -1,                                         \
49                 .sr_width = -1,                                         \
50         }
51
52 #define SR_PG(group_name, reg, shift, width)                            \
53         {                                                               \
54                 .name = #group_name,                                    \
55                 .pads = group_name##_pads,                              \
56                 .npads = ARRAY_SIZE(group_name##_pads),                 \
57                 .mfpctl_reg  = -1,                                      \
58                 .mfpctl_shift = -1,                                     \
59                 .mfpctl_width = -1,                                     \
60                 .drv_reg = -1,                                          \
61                 .drv_shift = -1,                                        \
62                 .drv_width = -1,                                        \
63                 .sr_reg = PAD_SR##reg,                                  \
64                 .sr_shift = shift,                                      \
65                 .sr_width = width,                                      \
66         }
67
68 #define FUNCTION(fname)                                 \
69         {                                               \
70                 .name = #fname,                         \
71                 .groups = fname##_groups,               \
72                 .ngroups = ARRAY_SIZE(fname##_groups),  \
73         }
74
75 /* PAD PULL UP/DOWN CONFIGURES */
76 #define PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)      \
77         {                                               \
78                 .reg = PAD_PULLCTL##pull_reg,           \
79                 .shift = pull_sft,                      \
80                 .width = pull_wdt,                      \
81         }
82
83 #define PAD_PULLCTL_CONF(pad_name, pull_reg, pull_sft, pull_wdt)        \
84         struct owl_pullctl pad_name##_pullctl_conf                      \
85                 = PULLCTL_CONF(pull_reg, pull_sft, pull_wdt)
86
87 #define ST_CONF(st_reg, st_sft, st_wdt)                 \
88         {                                               \
89                 .reg = PAD_ST##st_reg,                  \
90                 .shift = st_sft,                        \
91                 .width = st_wdt,                        \
92         }
93
94 #define PAD_ST_CONF(pad_name, st_reg, st_sft, st_wdt)   \
95         struct owl_st pad_name##_st_conf                \
96                 = ST_CONF(st_reg, st_sft, st_wdt)
97
98 #define PAD_INFO(name)                                  \
99         {                                               \
100                 .pad = name,                            \
101                 .pullctl = NULL,                        \
102                 .st = NULL,                             \
103         }
104
105 #define PAD_INFO_ST(name)                               \
106         {                                               \
107                 .pad = name,                            \
108                 .pullctl = NULL,                        \
109                 .st = &name##_st_conf,                  \
110         }
111
112 #define PAD_INFO_PULLCTL(name)                          \
113         {                                               \
114                 .pad = name,                            \
115                 .pullctl = &name##_pullctl_conf,        \
116                 .st = NULL,                             \
117         }
118
119 #define PAD_INFO_PULLCTL_ST(name)                       \
120         {                                               \
121                 .pad = name,                            \
122                 .pullctl = &name##_pullctl_conf,        \
123                 .st = &name##_st_conf,                  \
124         }
125
126 #define OWL_GPIO_PORT_A         0
127 #define OWL_GPIO_PORT_B         1
128 #define OWL_GPIO_PORT_C         2
129 #define OWL_GPIO_PORT_D         3
130 #define OWL_GPIO_PORT_E         4
131 #define OWL_GPIO_PORT_F         5
132
133 #define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, _intc_ctl,\
134                         _intc_pd, _intc_msk, _intc_type, _share)        \
135         [OWL_GPIO_PORT_##port] = {                              \
136                 .offset = base,                                 \
137                 .pins = count,                                  \
138                 .outen = _outen,                                \
139                 .inen = _inen,                                  \
140                 .dat = _dat,                                    \
141                 .intc_ctl = _intc_ctl,                          \
142                 .intc_pd = _intc_pd,                            \
143                 .intc_msk = _intc_msk,                          \
144                 .intc_type = _intc_type,                        \
145                 .shared_ctl_offset = _share,                    \
146         }
147
148 enum owl_pinconf_drv {
149         OWL_PINCONF_DRV_2MA,
150         OWL_PINCONF_DRV_4MA,
151         OWL_PINCONF_DRV_8MA,
152         OWL_PINCONF_DRV_12MA,
153 };
154
155 /* GPIO CTRL Bit Definition */
156 #define OWL_GPIO_CTLR_PENDING           0
157 #define OWL_GPIO_CTLR_ENABLE            1
158 #define OWL_GPIO_CTLR_SAMPLE_CLK_24M    2
159
160 /* GPIO TYPE Bit Definition */
161 #define OWL_GPIO_INT_LEVEL_HIGH         0
162 #define OWL_GPIO_INT_LEVEL_LOW          1
163 #define OWL_GPIO_INT_EDGE_RISING        2
164 #define OWL_GPIO_INT_EDGE_FALLING       3
165 #define OWL_GPIO_INT_MASK               3
166
167 /**
168  * struct owl_pullctl - Actions pad pull control register
169  * @reg: offset to the pull control register
170  * @shift: shift value of the register
171  * @width: width of the register
172  */
173 struct owl_pullctl {
174         int reg;
175         unsigned int shift;
176         unsigned int width;
177 };
178
179 /**
180  * struct owl_st - Actions pad schmitt trigger enable register
181  * @reg: offset to the schmitt trigger enable register
182  * @shift: shift value of the register
183  * @width: width of the register
184  */
185 struct owl_st {
186         int reg;
187         unsigned int shift;
188         unsigned int width;
189 };
190
191 /**
192  * struct owl_pingroup - Actions pingroup definition
193  * @name: name of the  pin group
194  * @pads: list of pins assigned to this pingroup
195  * @npads: size of @pads array
196  * @funcs: list of pinmux functions for this pingroup
197  * @nfuncs: size of @funcs array
198  * @mfpctl_reg: multiplexing control register offset
199  * @mfpctl_shift: multiplexing control register bit mask
200  * @mfpctl_width: multiplexing control register width
201  * @drv_reg: drive control register offset
202  * @drv_shift: drive control register bit mask
203  * @drv_width: driver control register width
204  * @sr_reg: slew rate control register offset
205  * @sr_shift: slew rate control register bit mask
206  * @sr_width: slew rate control register width
207  */
208 struct owl_pingroup {
209         const char *name;
210         unsigned int *pads;
211         unsigned int npads;
212         unsigned int *funcs;
213         unsigned int nfuncs;
214
215         int mfpctl_reg;
216         unsigned int mfpctl_shift;
217         unsigned int mfpctl_width;
218
219         int drv_reg;
220         unsigned int drv_shift;
221         unsigned int drv_width;
222
223         int sr_reg;
224         unsigned int sr_shift;
225         unsigned int sr_width;
226 };
227
228 /**
229  * struct owl_padinfo - Actions pinctrl pad info
230  * @pad: pad name of the SoC
231  * @pullctl: pull control register info
232  * @st: schmitt trigger register info
233  */
234 struct owl_padinfo {
235         int pad;
236         struct owl_pullctl *pullctl;
237         struct owl_st *st;
238 };
239
240 /**
241  * struct owl_pinmux_func - Actions pinctrl mux functions
242  * @name: name of the pinmux function.
243  * @groups: array of pin groups that may select this function.
244  * @ngroups: number of entries in @groups.
245  */
246 struct owl_pinmux_func {
247         const char *name;
248         const char * const *groups;
249         unsigned int ngroups;
250 };
251
252 /**
253  * struct owl_gpio_port - Actions GPIO port info
254  * @offset: offset of the GPIO port.
255  * @pins: number of pins belongs to the GPIO port.
256  * @outen: offset of the output enable register.
257  * @inen: offset of the input enable register.
258  * @dat: offset of the data register.
259  * @intc_ctl: offset of the interrupt control register.
260  * @intc_pd: offset of the interrupt pending register.
261  * @intc_msk: offset of the interrupt mask register.
262  * @intc_type: offset of the interrupt type register.
263  */
264 struct owl_gpio_port {
265         unsigned int offset;
266         unsigned int pins;
267         unsigned int outen;
268         unsigned int inen;
269         unsigned int dat;
270         unsigned int intc_ctl;
271         unsigned int intc_pd;
272         unsigned int intc_msk;
273         unsigned int intc_type;
274         u8 shared_ctl_offset;
275 };
276
277 /**
278  * struct owl_pinctrl_soc_data - Actions pin controller driver configuration
279  * @pins: array describing all pins of the pin controller.
280  * @npins: number of entries in @pins.
281  * @functions: array describing all mux functions of this SoC.
282  * @nfunction: number of entries in @functions.
283  * @groups: array describing all pin groups of this SoC.
284  * @ngroups: number of entries in @groups.
285  * @padinfo: array describing the pad info of this SoC.
286  * @ngpios: number of pingroups the driver should expose as GPIOs.
287  * @ports: array describing all GPIO ports of this SoC.
288  * @nports: number of GPIO ports in this SoC.
289  */
290 struct owl_pinctrl_soc_data {
291         const struct pinctrl_pin_desc *pins;
292         unsigned int npins;
293         const struct owl_pinmux_func *functions;
294         unsigned int nfunctions;
295         const struct owl_pingroup *groups;
296         unsigned int ngroups;
297         const struct owl_padinfo *padinfo;
298         unsigned int ngpios;
299         const struct owl_gpio_port *ports;
300         unsigned int nports;
301         int (*padctl_val2arg)(const struct owl_padinfo *padinfo,
302                                 unsigned int param,
303                                 u32 *arg);
304         int (*padctl_arg2val)(const struct owl_padinfo *info,
305                                 unsigned int param,
306                                 u32 *arg);
307 };
308
309 int owl_pinctrl_probe(struct platform_device *pdev,
310                 struct owl_pinctrl_soc_data *soc_data);
311
312 #endif /* __PINCTRL_OWL_H__ */