1 // SPDX-License-Identifier: GPL-2.0+
3 * OWL SoC's Pinctrl driver
5 * Copyright (c) 2014 Actions Semi Inc.
6 * Author: David Liu <liuwei@actions-semi.com>
8 * Copyright (c) 2018 Linaro Ltd.
9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
12 #include <linux/clk.h>
13 #include <linux/err.h>
14 #include <linux/gpio/driver.h>
16 #include <linux/irq.h>
17 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/pinctrl/machine.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
29 #include "../pinctrl-utils.h"
30 #include "pinctrl-owl.h"
33 * struct owl_pinctrl - pinctrl state of the device
35 * @pctrldev: pinctrl handle
37 * @lock: spinlock to protect registers
39 * @soc: reference to soc_data
40 * @base: pinctrl register base address
41 * @irq_chip: IRQ chip information
42 * @num_irq: number of possible interrupts
43 * @irq: interrupt numbers
47 struct pinctrl_dev *pctrldev;
48 struct gpio_chip chip;
51 const struct owl_pinctrl_soc_data *soc;
53 struct irq_chip irq_chip;
58 static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
62 reg_val = readl_relaxed(base);
64 reg_val = (reg_val & ~mask) | (val & mask);
66 writel_relaxed(reg_val, base);
69 static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg,
74 tmp = readl_relaxed(pctrl->base + reg);
75 mask = (1 << width) - 1;
77 return (tmp >> bit) & mask;
80 static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg,
85 mask = (1 << width) - 1;
88 owl_update_bits(pctrl->base + reg, mask, (arg << bit));
91 static int owl_get_groups_count(struct pinctrl_dev *pctrldev)
93 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
95 return pctrl->soc->ngroups;
98 static const char *owl_get_group_name(struct pinctrl_dev *pctrldev,
101 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
103 return pctrl->soc->groups[group].name;
106 static int owl_get_group_pins(struct pinctrl_dev *pctrldev,
108 const unsigned int **pins,
109 unsigned int *num_pins)
111 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
113 *pins = pctrl->soc->groups[group].pads;
114 *num_pins = pctrl->soc->groups[group].npads;
119 static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev,
123 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
125 seq_printf(s, "%s", dev_name(pctrl->dev));
128 static const struct pinctrl_ops owl_pinctrl_ops = {
129 .get_groups_count = owl_get_groups_count,
130 .get_group_name = owl_get_group_name,
131 .get_group_pins = owl_get_group_pins,
132 .pin_dbg_show = owl_pin_dbg_show,
133 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
134 .dt_free_map = pinctrl_utils_free_map,
137 static int owl_get_funcs_count(struct pinctrl_dev *pctrldev)
139 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
141 return pctrl->soc->nfunctions;
144 static const char *owl_get_func_name(struct pinctrl_dev *pctrldev,
145 unsigned int function)
147 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
149 return pctrl->soc->functions[function].name;
152 static int owl_get_func_groups(struct pinctrl_dev *pctrldev,
153 unsigned int function,
154 const char * const **groups,
155 unsigned int * const num_groups)
157 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
159 *groups = pctrl->soc->functions[function].groups;
160 *num_groups = pctrl->soc->functions[function].ngroups;
165 static inline int get_group_mfp_mask_val(const struct owl_pingroup *g,
174 for (id = 0; id < g->nfuncs; id++) {
175 if (g->funcs[id] == function)
178 if (WARN_ON(id == g->nfuncs))
181 option_num = (1 << g->mfpctl_width);
185 option_mask = option_num - 1;
186 *mask = (option_mask << g->mfpctl_shift);
187 *val = (id << g->mfpctl_shift);
192 static int owl_set_mux(struct pinctrl_dev *pctrldev,
193 unsigned int function,
196 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
197 const struct owl_pingroup *g;
201 g = &pctrl->soc->groups[group];
203 if (get_group_mfp_mask_val(g, function, &mask, &val))
206 raw_spin_lock_irqsave(&pctrl->lock, flags);
208 owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val);
210 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
215 static const struct pinmux_ops owl_pinmux_ops = {
216 .get_functions_count = owl_get_funcs_count,
217 .get_function_name = owl_get_func_name,
218 .get_function_groups = owl_get_func_groups,
219 .set_mux = owl_set_mux,
222 static int owl_pad_pinconf_reg(const struct owl_padinfo *info,
229 case PIN_CONFIG_BIAS_BUS_HOLD:
230 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
231 case PIN_CONFIG_BIAS_PULL_DOWN:
232 case PIN_CONFIG_BIAS_PULL_UP:
235 *reg = info->pullctl->reg;
236 *bit = info->pullctl->shift;
237 *width = info->pullctl->width;
239 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
242 *reg = info->st->reg;
243 *bit = info->st->shift;
244 *width = info->st->width;
253 static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
255 unsigned long *config)
258 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
259 const struct owl_padinfo *info;
260 unsigned int param = pinconf_to_config_param(*config);
261 u32 reg, bit, width, arg;
263 info = &pctrl->soc->padinfo[pin];
265 ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width);
269 arg = owl_read_field(pctrl, reg, bit, width);
271 if (!pctrl->soc->padctl_val2arg)
274 ret = pctrl->soc->padctl_val2arg(info, param, &arg);
278 *config = pinconf_to_config_packed(param, arg);
283 static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
285 unsigned long *configs,
286 unsigned int num_configs)
288 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
289 const struct owl_padinfo *info;
292 u32 reg, bit, width, arg;
295 info = &pctrl->soc->padinfo[pin];
297 for (i = 0; i < num_configs; i++) {
298 param = pinconf_to_config_param(configs[i]);
299 arg = pinconf_to_config_argument(configs[i]);
301 ret = owl_pad_pinconf_reg(info, param, ®, &bit, &width);
305 if (!pctrl->soc->padctl_arg2val)
308 ret = pctrl->soc->padctl_arg2val(info, param, &arg);
312 raw_spin_lock_irqsave(&pctrl->lock, flags);
314 owl_write_field(pctrl, reg, arg, bit, width);
316 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
322 static int owl_group_pinconf_reg(const struct owl_pingroup *g,
329 case PIN_CONFIG_DRIVE_STRENGTH:
334 *width = g->drv_width;
336 case PIN_CONFIG_SLEW_RATE:
341 *width = g->sr_width;
350 static int owl_group_pinconf_arg2val(const struct owl_pingroup *g,
355 case PIN_CONFIG_DRIVE_STRENGTH:
358 *arg = OWL_PINCONF_DRV_2MA;
361 *arg = OWL_PINCONF_DRV_4MA;
364 *arg = OWL_PINCONF_DRV_8MA;
367 *arg = OWL_PINCONF_DRV_12MA;
373 case PIN_CONFIG_SLEW_RATE:
375 *arg = OWL_PINCONF_SLEW_FAST;
377 *arg = OWL_PINCONF_SLEW_SLOW;
386 static int owl_group_pinconf_val2arg(const struct owl_pingroup *g,
391 case PIN_CONFIG_DRIVE_STRENGTH:
393 case OWL_PINCONF_DRV_2MA:
396 case OWL_PINCONF_DRV_4MA:
399 case OWL_PINCONF_DRV_8MA:
402 case OWL_PINCONF_DRV_12MA:
409 case PIN_CONFIG_SLEW_RATE:
422 static int owl_group_config_get(struct pinctrl_dev *pctrldev,
424 unsigned long *config)
426 const struct owl_pingroup *g;
427 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
428 unsigned int param = pinconf_to_config_param(*config);
429 u32 reg, bit, width, arg;
432 g = &pctrl->soc->groups[group];
434 ret = owl_group_pinconf_reg(g, param, ®, &bit, &width);
438 arg = owl_read_field(pctrl, reg, bit, width);
440 ret = owl_group_pinconf_val2arg(g, param, &arg);
444 *config = pinconf_to_config_packed(param, arg);
450 static int owl_group_config_set(struct pinctrl_dev *pctrldev,
452 unsigned long *configs,
453 unsigned int num_configs)
455 const struct owl_pingroup *g;
456 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
459 u32 reg, bit, width, arg;
462 g = &pctrl->soc->groups[group];
464 for (i = 0; i < num_configs; i++) {
465 param = pinconf_to_config_param(configs[i]);
466 arg = pinconf_to_config_argument(configs[i]);
468 ret = owl_group_pinconf_reg(g, param, ®, &bit, &width);
472 ret = owl_group_pinconf_arg2val(g, param, &arg);
476 /* Update register */
477 raw_spin_lock_irqsave(&pctrl->lock, flags);
479 owl_write_field(pctrl, reg, arg, bit, width);
481 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
487 static const struct pinconf_ops owl_pinconf_ops = {
489 .pin_config_get = owl_pin_config_get,
490 .pin_config_set = owl_pin_config_set,
491 .pin_config_group_get = owl_group_config_get,
492 .pin_config_group_set = owl_group_config_set,
495 static struct pinctrl_desc owl_pinctrl_desc = {
496 .pctlops = &owl_pinctrl_ops,
497 .pmxops = &owl_pinmux_ops,
498 .confops = &owl_pinconf_ops,
499 .owner = THIS_MODULE,
502 static const struct owl_gpio_port *
503 owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin)
505 unsigned int start = 0, i;
507 for (i = 0; i < pctrl->soc->nports; i++) {
508 const struct owl_gpio_port *port = &pctrl->soc->ports[i];
510 if (*pin >= start && *pin < start + port->pins) {
521 static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag)
525 val = readl_relaxed(base);
532 writel_relaxed(val, base);
535 static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset)
537 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
538 const struct owl_gpio_port *port;
539 void __iomem *gpio_base;
542 port = owl_gpio_get_port(pctrl, &offset);
543 if (WARN_ON(port == NULL))
546 gpio_base = pctrl->base + port->offset;
549 * GPIOs have higher priority over other modules, so either setting
550 * them as OUT or IN is sufficient
552 raw_spin_lock_irqsave(&pctrl->lock, flags);
553 owl_gpio_update_reg(gpio_base + port->outen, offset, true);
554 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
559 static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset)
561 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
562 const struct owl_gpio_port *port;
563 void __iomem *gpio_base;
566 port = owl_gpio_get_port(pctrl, &offset);
567 if (WARN_ON(port == NULL))
570 gpio_base = pctrl->base + port->offset;
572 raw_spin_lock_irqsave(&pctrl->lock, flags);
573 /* disable gpio output */
574 owl_gpio_update_reg(gpio_base + port->outen, offset, false);
576 /* disable gpio input */
577 owl_gpio_update_reg(gpio_base + port->inen, offset, false);
578 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
581 static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset)
583 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
584 const struct owl_gpio_port *port;
585 void __iomem *gpio_base;
589 port = owl_gpio_get_port(pctrl, &offset);
590 if (WARN_ON(port == NULL))
593 gpio_base = pctrl->base + port->offset;
595 raw_spin_lock_irqsave(&pctrl->lock, flags);
596 val = readl_relaxed(gpio_base + port->dat);
597 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
599 return !!(val & BIT(offset));
602 static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
604 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
605 const struct owl_gpio_port *port;
606 void __iomem *gpio_base;
609 port = owl_gpio_get_port(pctrl, &offset);
610 if (WARN_ON(port == NULL))
613 gpio_base = pctrl->base + port->offset;
615 raw_spin_lock_irqsave(&pctrl->lock, flags);
616 owl_gpio_update_reg(gpio_base + port->dat, offset, value);
617 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
620 static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
622 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
623 const struct owl_gpio_port *port;
624 void __iomem *gpio_base;
627 port = owl_gpio_get_port(pctrl, &offset);
628 if (WARN_ON(port == NULL))
631 gpio_base = pctrl->base + port->offset;
633 raw_spin_lock_irqsave(&pctrl->lock, flags);
634 owl_gpio_update_reg(gpio_base + port->outen, offset, false);
635 owl_gpio_update_reg(gpio_base + port->inen, offset, true);
636 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
641 static int owl_gpio_direction_output(struct gpio_chip *chip,
642 unsigned int offset, int value)
644 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
645 const struct owl_gpio_port *port;
646 void __iomem *gpio_base;
649 port = owl_gpio_get_port(pctrl, &offset);
650 if (WARN_ON(port == NULL))
653 gpio_base = pctrl->base + port->offset;
655 raw_spin_lock_irqsave(&pctrl->lock, flags);
656 owl_gpio_update_reg(gpio_base + port->inen, offset, false);
657 owl_gpio_update_reg(gpio_base + port->outen, offset, true);
658 owl_gpio_update_reg(gpio_base + port->dat, offset, value);
659 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
664 static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type)
666 const struct owl_gpio_port *port;
667 void __iomem *gpio_base;
669 unsigned int offset, value, irq_type = 0;
672 case IRQ_TYPE_EDGE_BOTH:
674 * Since the hardware doesn't support interrupts on both edges,
675 * emulate it in the software by setting the single edge
676 * interrupt and switching to the opposite edge while ACKing
679 if (owl_gpio_get(&pctrl->chip, gpio))
680 irq_type = OWL_GPIO_INT_EDGE_FALLING;
682 irq_type = OWL_GPIO_INT_EDGE_RISING;
685 case IRQ_TYPE_EDGE_RISING:
686 irq_type = OWL_GPIO_INT_EDGE_RISING;
689 case IRQ_TYPE_EDGE_FALLING:
690 irq_type = OWL_GPIO_INT_EDGE_FALLING;
693 case IRQ_TYPE_LEVEL_HIGH:
694 irq_type = OWL_GPIO_INT_LEVEL_HIGH;
697 case IRQ_TYPE_LEVEL_LOW:
698 irq_type = OWL_GPIO_INT_LEVEL_LOW;
705 port = owl_gpio_get_port(pctrl, &gpio);
706 if (WARN_ON(port == NULL))
709 gpio_base = pctrl->base + port->offset;
711 raw_spin_lock_irqsave(&pctrl->lock, flags);
713 offset = (gpio < 16) ? 4 : 0;
714 value = readl_relaxed(gpio_base + port->intc_type + offset);
715 value &= ~(OWL_GPIO_INT_MASK << ((gpio % 16) * 2));
716 value |= irq_type << ((gpio % 16) * 2);
717 writel_relaxed(value, gpio_base + port->intc_type + offset);
719 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
722 static void owl_gpio_irq_mask(struct irq_data *data)
724 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
725 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
726 const struct owl_gpio_port *port;
727 void __iomem *gpio_base;
729 unsigned int gpio = data->hwirq;
732 port = owl_gpio_get_port(pctrl, &gpio);
733 if (WARN_ON(port == NULL))
736 gpio_base = pctrl->base + port->offset;
738 raw_spin_lock_irqsave(&pctrl->lock, flags);
740 owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, false);
742 /* disable port interrupt if no interrupt pending bit is active */
743 val = readl_relaxed(gpio_base + port->intc_msk);
745 owl_gpio_update_reg(gpio_base + port->intc_ctl,
746 OWL_GPIO_CTLR_ENABLE + port->shared_ctl_offset * 5, false);
748 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
751 static void owl_gpio_irq_unmask(struct irq_data *data)
753 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
754 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
755 const struct owl_gpio_port *port;
756 void __iomem *gpio_base;
758 unsigned int gpio = data->hwirq;
761 port = owl_gpio_get_port(pctrl, &gpio);
762 if (WARN_ON(port == NULL))
765 gpio_base = pctrl->base + port->offset;
766 raw_spin_lock_irqsave(&pctrl->lock, flags);
768 /* enable port interrupt */
769 value = readl_relaxed(gpio_base + port->intc_ctl);
770 value |= ((BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M))
771 << port->shared_ctl_offset * 5);
772 writel_relaxed(value, gpio_base + port->intc_ctl);
774 /* enable GPIO interrupt */
775 owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, true);
777 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
780 static void owl_gpio_irq_ack(struct irq_data *data)
782 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
783 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
784 const struct owl_gpio_port *port;
785 void __iomem *gpio_base;
787 unsigned int gpio = data->hwirq;
790 * Switch the interrupt edge to the opposite edge of the interrupt
791 * which got triggered for the case of emulating both edges
793 if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) {
794 if (owl_gpio_get(gc, gpio))
795 irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_FALLING);
797 irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_RISING);
800 port = owl_gpio_get_port(pctrl, &gpio);
801 if (WARN_ON(port == NULL))
804 gpio_base = pctrl->base + port->offset;
806 raw_spin_lock_irqsave(&pctrl->lock, flags);
808 owl_gpio_update_reg(gpio_base + port->intc_ctl,
809 OWL_GPIO_CTLR_PENDING + port->shared_ctl_offset * 5, true);
811 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
814 static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type)
816 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
817 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
819 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
820 irq_set_handler_locked(data, handle_level_irq);
822 irq_set_handler_locked(data, handle_edge_irq);
824 irq_set_type(pctrl, data->hwirq, type);
829 static void owl_gpio_irq_handler(struct irq_desc *desc)
831 struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc);
832 struct irq_chip *chip = irq_desc_get_chip(desc);
833 struct irq_domain *domain = pctrl->chip.irq.domain;
834 unsigned int parent = irq_desc_get_irq(desc);
835 const struct owl_gpio_port *port;
837 unsigned int pin, irq, offset = 0, i;
838 unsigned long pending_irq;
840 chained_irq_enter(chip, desc);
842 for (i = 0; i < pctrl->soc->nports; i++) {
843 port = &pctrl->soc->ports[i];
844 base = pctrl->base + port->offset;
846 /* skip ports that are not associated with this irq */
847 if (parent != pctrl->irq[i])
850 pending_irq = readl_relaxed(base + port->intc_pd);
852 for_each_set_bit(pin, &pending_irq, port->pins) {
853 irq = irq_find_mapping(domain, offset + pin);
854 generic_handle_irq(irq);
856 /* clear pending interrupt */
857 owl_gpio_update_reg(base + port->intc_pd, pin, true);
861 offset += port->pins;
864 chained_irq_exit(chip, desc);
867 static int owl_gpio_init(struct owl_pinctrl *pctrl)
869 struct gpio_chip *chip;
870 struct gpio_irq_chip *gpio_irq;
871 int ret, i, j, offset;
875 chip->ngpio = pctrl->soc->ngpios;
876 chip->label = dev_name(pctrl->dev);
877 chip->parent = pctrl->dev;
878 chip->owner = THIS_MODULE;
879 chip->of_node = pctrl->dev->of_node;
881 pctrl->irq_chip.name = chip->of_node->name;
882 pctrl->irq_chip.irq_ack = owl_gpio_irq_ack;
883 pctrl->irq_chip.irq_mask = owl_gpio_irq_mask;
884 pctrl->irq_chip.irq_unmask = owl_gpio_irq_unmask;
885 pctrl->irq_chip.irq_set_type = owl_gpio_irq_set_type;
887 gpio_irq = &chip->irq;
888 gpio_irq->chip = &pctrl->irq_chip;
889 gpio_irq->handler = handle_simple_irq;
890 gpio_irq->default_type = IRQ_TYPE_NONE;
891 gpio_irq->parent_handler = owl_gpio_irq_handler;
892 gpio_irq->parent_handler_data = pctrl;
893 gpio_irq->num_parents = pctrl->num_irq;
894 gpio_irq->parents = pctrl->irq;
896 gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio,
897 sizeof(*gpio_irq->map), GFP_KERNEL);
901 for (i = 0, offset = 0; i < pctrl->soc->nports; i++) {
902 const struct owl_gpio_port *port = &pctrl->soc->ports[i];
904 for (j = 0; j < port->pins; j++)
905 gpio_irq->map[offset + j] = gpio_irq->parents[i];
907 offset += port->pins;
910 ret = gpiochip_add_data(&pctrl->chip, pctrl);
912 dev_err(pctrl->dev, "failed to register gpiochip\n");
919 int owl_pinctrl_probe(struct platform_device *pdev,
920 struct owl_pinctrl_soc_data *soc_data)
922 struct owl_pinctrl *pctrl;
925 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
929 pctrl->base = devm_platform_ioremap_resource(pdev, 0);
930 if (IS_ERR(pctrl->base))
931 return PTR_ERR(pctrl->base);
933 /* enable GPIO/MFP clock */
934 pctrl->clk = devm_clk_get(&pdev->dev, NULL);
935 if (IS_ERR(pctrl->clk)) {
936 dev_err(&pdev->dev, "no clock defined\n");
937 return PTR_ERR(pctrl->clk);
940 ret = clk_prepare_enable(pctrl->clk);
942 dev_err(&pdev->dev, "clk enable failed\n");
946 raw_spin_lock_init(&pctrl->lock);
948 owl_pinctrl_desc.name = dev_name(&pdev->dev);
949 owl_pinctrl_desc.pins = soc_data->pins;
950 owl_pinctrl_desc.npins = soc_data->npins;
952 pctrl->chip.direction_input = owl_gpio_direction_input;
953 pctrl->chip.direction_output = owl_gpio_direction_output;
954 pctrl->chip.get = owl_gpio_get;
955 pctrl->chip.set = owl_gpio_set;
956 pctrl->chip.request = owl_gpio_request;
957 pctrl->chip.free = owl_gpio_free;
959 pctrl->soc = soc_data;
960 pctrl->dev = &pdev->dev;
962 pctrl->pctrldev = devm_pinctrl_register(&pdev->dev,
963 &owl_pinctrl_desc, pctrl);
964 if (IS_ERR(pctrl->pctrldev)) {
965 dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n");
966 ret = PTR_ERR(pctrl->pctrldev);
970 ret = platform_irq_count(pdev);
974 pctrl->num_irq = ret;
976 pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq,
977 sizeof(*pctrl->irq), GFP_KERNEL);
983 for (i = 0; i < pctrl->num_irq ; i++) {
984 ret = platform_get_irq(pdev, i);
990 ret = owl_gpio_init(pctrl);
994 platform_set_drvdata(pdev, pctrl);
999 clk_disable_unprepare(pctrl->clk);