drivers/phy/tegra/xusb-tegra210.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
   4  * Copyright (C) 2015 Google, Inc.
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/clk/tegra.h>
   9 #include <linux/delay.h>
  10 #include <linux/io.h>
  11 #include <linux/mailbox_client.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/phy/phy.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/regmap.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/reset.h>
  20 #include <linux/slab.h>
  21
  22 #include <soc/tegra/fuse.h>
  23
  24 #include "xusb.h"
  25
  26 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) \
  27                                         ((x) ? (11 + ((x) - 1) * 6) : 0)
  28 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f
  29 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT 7
  30 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf
  31
  32 #define FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT 0
  33 #define FUSE_USB_CALIB_EXT_RPD_CTRL_MASK 0x1f
  34
  35 #define XUSB_PADCTL_USB2_PAD_MUX 0x004
  36 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT 16
  37 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK 0x3
  38 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB 0x1
  39 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT 18
  40 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK 0x3
  41 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB 0x1
  42
  43 #define XUSB_PADCTL_USB2_PORT_CAP 0x008
  44 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(x) (0x0 << ((x) * 4))
  45 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4))
  46 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(x) (0x2 << ((x) * 4))
  47 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(x) (0x3 << ((x) * 4))
  48 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4))
  49
  50 #define XUSB_PADCTL_SS_PORT_MAP 0x014
  51 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
  52 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_SHIFT(x) ((x) * 5)
  53 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 5))
  54 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 5))
  55 #define XUSB_PADCTL_SS_PORT_MAP_PORT_DISABLED 0x7
  56
  57 #define XUSB_PADCTL_ELPG_PROGRAM_0 0x20
  58 #define   USB2_PORT_WAKE_INTERRUPT_ENABLE(x)      BIT((x))
  59 #define   USB2_PORT_WAKEUP_EVENT(x)               BIT((x) + 7)
  60 #define   SS_PORT_WAKE_INTERRUPT_ENABLE(x)        BIT((x) + 14)
  61 #define   SS_PORT_WAKEUP_EVENT(x)                 BIT((x) + 21)
  62 #define   USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28)
  63 #define   USB2_HSIC_PORT_WAKEUP_EVENT(x)          BIT((x) + 30)
  64 #define   ALL_WAKE_EVENTS ( \
  65                 USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
  66                 USB2_PORT_WAKEUP_EVENT(2) | USB2_PORT_WAKEUP_EVENT(3) | \
  67                 SS_PORT_WAKEUP_EVENT(0) | SS_PORT_WAKEUP_EVENT(1) | \
  68                 SS_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(3) | \
  69                 USB2_HSIC_PORT_WAKEUP_EVENT(0))
  70
  71 #define XUSB_PADCTL_ELPG_PROGRAM1 0x024
  72 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
  73 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
  74 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29)
  75 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
  76 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(x) \
  77                                                         (1 << (1 + (x) * 3))
  78 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(x) (1 << ((x) * 3))
  79
  80 #define XUSB_PADCTL_USB3_PAD_MUX 0x028
  81 #define XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x)))
  82 #define XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(x) (1 << (8 + (x)))
  83
  84 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(x) (0x080 + (x) * 0x40)
  85 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIP (1 << 18)
  86 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIN (1 << 22)
  87
  88 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x084 + (x) * 0x40)
  89 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT 7
  90 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK 0x3
  91 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL 0x1
  92 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18 (1 << 6)
  93
  94 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x088 + (x) * 0x40)
  95 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI (1 << 29)
  96 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 (1 << 27)
  97 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD (1 << 26)
  98 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT 0
  99 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK 0x3f
 100
 101 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x08c + (x) * 0x40)
 102 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT 26
 103 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK 0x1f
 104 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT 3
 105 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK 0xf
 106 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
 107 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD (1 << 1)
 108 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD (1 << 0)
 109 #define   RPD_CTRL(x)                      (((x) & 0x1f) << 26)
 110 #define   RPD_CTRL_VALUE(x)                (((x) >> 26) & 0x1f)
 111
 112 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
 113 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD (1 << 11)
 114 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT 3
 115 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK 0x7
 116 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL 0x7
 117 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT 0
 118 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK 0x7
 119 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL 0x2
 120
 121 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
 122 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK (1 << 26)
 123 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT 19
 124 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK 0x7f
 125 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL 0x0a
 126 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT 12
 127 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK 0x7f
 128 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL 0x1e
 129 #define   TCTRL_VALUE(x)                (((x) & 0x3f) >> 0)
 130 #define   PCTRL_VALUE(x)                (((x) >> 6) & 0x3f)
 131
 132 #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
 133 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE (1 << 18)
 134 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 (1 << 17)
 135 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 (1 << 16)
 136 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE (1 << 15)
 137 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 (1 << 14)
 138 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 (1 << 13)
 139 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE (1 << 9)
 140 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 (1 << 8)
 141 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 (1 << 7)
 142 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE (1 << 6)
 143 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 (1 << 5)
 144 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4)
 145 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE (1 << 3)
 146 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 (1 << 2)
 147 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 (1 << 1)
 148
 149 #define XUSB_PADCTL_HSIC_PADX_CTL1(x) (0x304 + (x) * 0x20)
 150 #define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT 0
 151 #define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK 0xf
 152
 153 #define XUSB_PADCTL_HSIC_PADX_CTL2(x) (0x308 + (x) * 0x20)
 154 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT 8
 155 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK 0xf
 156 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT 0
 157 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK 0xff
 158
 159 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL 0x340
 160 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK (1 << 19)
 161 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT 12
 162 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK 0x7f
 163 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL 0x0a
 164 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT 5
 165 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK 0x7f
 166 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL 0x1e
 167
 168 #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL 0x344
 169
 170 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
 171 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT 20
 172 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK 0xff
 173 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL 0x19
 174 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL 0x1e
 175 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT 16
 176 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK 0x3
 177 #define XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS (1 << 15)
 178 #define XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD (1 << 4)
 179 #define XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE (1 << 3)
 180 #define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT 1
 181 #define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK 0x3
 182 #define XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ (1 << 0)
 183
 184 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
 185 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT 4
 186 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK 0xffffff
 187 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL 0x136
 188 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD (1 << 2)
 189 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE (1 << 1)
 190 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN (1 << 0)
 191
 192 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
 193 #define XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN (1 << 19)
 194 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN (1 << 15)
 195 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT 12
 196 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK 0x3
 197 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL 0x2
 198 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL 0x0
 199 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN (1 << 8)
 200 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT 4
 201 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK 0xf
 202
 203 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
 204 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT 16
 205 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK 0xff
 206 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL 0x2a
 207
 208 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
 209 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE (1 << 31)
 210 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD (1 << 15)
 211 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN (1 << 13)
 212 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN (1 << 12)
 213
 214 #define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(x) (0x460 + (x) * 0x40)
 215 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT 20
 216 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK 0x3
 217 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL 0x1
 218 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN BIT(18)
 219 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD BIT(13)
 220
 221 #define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(x) (0x464 + (x) * 0x40)
 222 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ BIT(0)
 223 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD BIT(1)
 224 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_MASK GENMASK(5, 4)
 225 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_VAL GENMASK(5, 4)
 226 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_PWR_OVRD BIT(24)
 227 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ BIT(8)
 228 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD BIT(9)
 229 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_MASK GENMASK(13, 12)
 230 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL GENMASK(13, 12)
 231 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_PWR_OVRD BIT(25)
 232
 233 #define XUSB_PADCTL_UPHY_PLL_S0_CTL1 0x860
 234
 235 #define XUSB_PADCTL_UPHY_PLL_S0_CTL2 0x864
 236
 237 #define XUSB_PADCTL_UPHY_PLL_S0_CTL4 0x86c
 238
 239 #define XUSB_PADCTL_UPHY_PLL_S0_CTL5 0x870
 240
 241 #define XUSB_PADCTL_UPHY_PLL_S0_CTL8 0x87c
 242
 243 #define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1 0x960
 244 #define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL2 0x964
 245
 246 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(x) (0xa60 + (x) * 0x40)
 247 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT 16
 248 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK 0x3
 249 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL 0x2
 250
 251 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(x) (0xa64 + (x) * 0x40)
 252 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT 0
 253 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK 0xffff
 254 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL 0x00fc
 255
 256 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(x) (0xa68 + (x) * 0x40)
 257 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL 0xc0077f1f
 258
 259 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(x) (0xa6c + (x) * 0x40)
 260 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT 16
 261 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK 0xffff
 262 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL 0x01c7
 263
 264 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(x) (0xa74 + (x) * 0x40)
 265 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL 0xfcf01368
 266
 267 #define XUSB_PADCTL_USB2_VBUS_ID 0xc60
 268 #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON (1 << 14)
 269 #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT 18
 270 #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK 0xf
 271 #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING 8
 272 #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_GROUNDED 0
 273
 274 /* USB2 SLEEPWALK registers */
 275 #define UTMIP(_port, _offset1, _offset2) \
 276                 (((_port) <= 2) ? (_offset1) : (_offset2))
 277
 278 #define PMC_UTMIP_UHSIC_SLEEP_CFG(x)    UTMIP(x, 0x1fc, 0x4d0)
 279 #define   UTMIP_MASTER_ENABLE(x)                UTMIP(x, BIT(8 * (x)), BIT(0))
 280 #define   UTMIP_FSLS_USE_PMC(x)                 UTMIP(x, BIT(8 * (x) + 1), \
 281                                                         BIT(1))
 282 #define   UTMIP_PCTRL_USE_PMC(x)                UTMIP(x, BIT(8 * (x) + 2), \
 283                                                         BIT(2))
 284 #define   UTMIP_TCTRL_USE_PMC(x)                UTMIP(x, BIT(8 * (x) + 3), \
 285                                                         BIT(3))
 286 #define   UTMIP_WAKE_VAL(_port, _value)         (((_value) & 0xf) << \
 287                                         (UTMIP(_port, 8 * (_port) + 4, 4)))
 288 #define   UTMIP_WAKE_VAL_NONE(_port)            UTMIP_WAKE_VAL(_port, 12)
 289 #define   UTMIP_WAKE_VAL_ANY(_port)             UTMIP_WAKE_VAL(_port, 15)
 290
 291 #define PMC_UTMIP_UHSIC_SLEEP_CFG1      (0x4d0)
 292 #define   UTMIP_RPU_SWITC_LOW_USE_PMC_PX(x)     BIT((x) + 8)
 293 #define   UTMIP_RPD_CTRL_USE_PMC_PX(x)          BIT((x) + 16)
 294
 295 #define PMC_UTMIP_MASTER_CONFIG         (0x274)
 296 #define   UTMIP_PWR(x)                          UTMIP(x, BIT(x), BIT(4))
 297 #define   UHSIC_PWR                             BIT(3)
 298
 299 #define PMC_USB_DEBOUNCE_DEL            (0xec)
 300 #define   DEBOUNCE_VAL(x)                       (((x) & 0xffff) << 0)
 301 #define   UTMIP_LINE_DEB_CNT(x)                 (((x) & 0xf) << 16)
 302 #define   UHSIC_LINE_DEB_CNT(x)                 (((x) & 0xf) << 20)
 303
 304 #define PMC_UTMIP_UHSIC_FAKE(x)         UTMIP(x, 0x218, 0x294)
 305 #define   UTMIP_FAKE_USBOP_VAL(x)               UTMIP(x, BIT(4 * (x)), BIT(8))
 306 #define   UTMIP_FAKE_USBON_VAL(x)               UTMIP(x, BIT(4 * (x) + 1), \
 307                                                         BIT(9))
 308 #define   UTMIP_FAKE_USBOP_EN(x)                UTMIP(x, BIT(4 * (x) + 2), \
 309                                                         BIT(10))
 310 #define   UTMIP_FAKE_USBON_EN(x)                UTMIP(x, BIT(4 * (x) + 3), \
 311                                                         BIT(11))
 312
 313 #define PMC_UTMIP_UHSIC_SLEEPWALK_CFG(x)        UTMIP(x, 0x200, 0x288)
 314 #define   UTMIP_LINEVAL_WALK_EN(x)              UTMIP(x, BIT(8 * (x) + 7), \
 315                                                         BIT(15))
 316
 317 #define PMC_USB_AO                      (0xf0)
 318 #define   USBOP_VAL_PD(x)                       UTMIP(x, BIT(4 * (x)), BIT(20))
 319 #define   USBON_VAL_PD(x)                       UTMIP(x, BIT(4 * (x) + 1), \
 320                                                         BIT(21))
 321 #define   STROBE_VAL_PD                         BIT(12)
 322 #define   DATA0_VAL_PD                          BIT(13)
 323 #define   DATA1_VAL_PD                          BIT(24)
 324
 325 #define PMC_UTMIP_UHSIC_SAVED_STATE(x)  UTMIP(x, 0x1f0, 0x280)
 326 #define   SPEED(_port, _value)                  (((_value) & 0x3) << \
 327                                                 (UTMIP(_port, 8 * (_port), 8)))
 328 #define   UTMI_HS(_port)                        SPEED(_port, 0)
 329 #define   UTMI_FS(_port)                        SPEED(_port, 1)
 330 #define   UTMI_LS(_port)                        SPEED(_port, 2)
 331 #define   UTMI_RST(_port)                       SPEED(_port, 3)
 332
 333 #define PMC_UTMIP_UHSIC_TRIGGERS                (0x1ec)
 334 #define   UTMIP_CLR_WALK_PTR(x)                 UTMIP(x, BIT(x), BIT(16))
 335 #define   UTMIP_CAP_CFG(x)                      UTMIP(x, BIT((x) + 4), BIT(17))
 336 #define   UTMIP_CLR_WAKE_ALARM(x)               UTMIP(x, BIT((x) + 12), \
 337                                                         BIT(19))
 338 #define   UHSIC_CLR_WALK_PTR                    BIT(3)
 339 #define   UHSIC_CLR_WAKE_ALARM                  BIT(15)
 340
 341 #define PMC_UTMIP_SLEEPWALK_PX(x)       UTMIP(x, 0x204 + (4 * (x)), \
 342                                                         0x4e0)
 343 /* phase A */
 344 #define   UTMIP_USBOP_RPD_A                     BIT(0)
 345 #define   UTMIP_USBON_RPD_A                     BIT(1)
 346 #define   UTMIP_AP_A                            BIT(4)
 347 #define   UTMIP_AN_A                            BIT(5)
 348 #define   UTMIP_HIGHZ_A                         BIT(6)
 349 /* phase B */
 350 #define   UTMIP_USBOP_RPD_B                     BIT(8)
 351 #define   UTMIP_USBON_RPD_B                     BIT(9)
 352 #define   UTMIP_AP_B                            BIT(12)
 353 #define   UTMIP_AN_B                            BIT(13)
 354 #define   UTMIP_HIGHZ_B                         BIT(14)
 355 /* phase C */
 356 #define   UTMIP_USBOP_RPD_C                     BIT(16)
 357 #define   UTMIP_USBON_RPD_C                     BIT(17)
 358 #define   UTMIP_AP_C                            BIT(20)
 359 #define   UTMIP_AN_C                            BIT(21)
 360 #define   UTMIP_HIGHZ_C                         BIT(22)
 361 /* phase D */
 362 #define   UTMIP_USBOP_RPD_D                     BIT(24)
 363 #define   UTMIP_USBON_RPD_D                     BIT(25)
 364 #define   UTMIP_AP_D                            BIT(28)
 365 #define   UTMIP_AN_D                            BIT(29)
 366 #define   UTMIP_HIGHZ_D                         BIT(30)
 367
 368 #define PMC_UTMIP_UHSIC_LINE_WAKEUP     (0x26c)
 369 #define   UTMIP_LINE_WAKEUP_EN(x)               UTMIP(x, BIT(x), BIT(4))
 370 #define   UHSIC_LINE_WAKEUP_EN                  BIT(3)
 371
 372 #define PMC_UTMIP_TERM_PAD_CFG          (0x1f8)
 373 #define   PCTRL_VAL(x)                          (((x) & 0x3f) << 1)
 374 #define   TCTRL_VAL(x)                          (((x) & 0x3f) << 7)
 375
 376 #define PMC_UTMIP_PAD_CFGX(x)           (0x4c0 + (4 * (x)))
 377 #define   RPD_CTRL_PX(x)                        (((x) & 0x1f) << 22)
 378
 379 #define PMC_UHSIC_SLEEP_CFG     PMC_UTMIP_UHSIC_SLEEP_CFG(0)
 380 #define   UHSIC_MASTER_ENABLE                   BIT(24)
 381 #define   UHSIC_WAKE_VAL(_value)                (((_value) & 0xf) << 28)
 382 #define   UHSIC_WAKE_VAL_SD10                   UHSIC_WAKE_VAL(2)
 383 #define   UHSIC_WAKE_VAL_NONE                   UHSIC_WAKE_VAL(12)
 384
 385 #define PMC_UHSIC_FAKE                  PMC_UTMIP_UHSIC_FAKE(0)
 386 #define   UHSIC_FAKE_STROBE_VAL                 BIT(12)
 387 #define   UHSIC_FAKE_DATA_VAL                   BIT(13)
 388 #define   UHSIC_FAKE_STROBE_EN                  BIT(14)
 389 #define   UHSIC_FAKE_DATA_EN                    BIT(15)
 390
 391 #define PMC_UHSIC_SAVED_STATE           PMC_UTMIP_UHSIC_SAVED_STATE(0)
 392 #define   UHSIC_MODE(_value)                    (((_value) & 0x1) << 24)
 393 #define   UHSIC_HS                              UHSIC_MODE(0)
 394 #define   UHSIC_RST                             UHSIC_MODE(1)
 395
 396 #define PMC_UHSIC_SLEEPWALK_CFG         PMC_UTMIP_UHSIC_SLEEPWALK_CFG(0)
 397 #define   UHSIC_WAKE_WALK_EN                    BIT(30)
 398 #define   UHSIC_LINEVAL_WALK_EN                 BIT(31)
 399
 400 #define PMC_UHSIC_SLEEPWALK_P0          (0x210)
 401 #define   UHSIC_DATA0_RPD_A                     BIT(1)
 402 #define   UHSIC_DATA0_RPU_B                     BIT(11)
 403 #define   UHSIC_DATA0_RPU_C                     BIT(19)
 404 #define   UHSIC_DATA0_RPU_D                     BIT(27)
 405 #define   UHSIC_STROBE_RPU_A                    BIT(2)
 406 #define   UHSIC_STROBE_RPD_B                    BIT(8)
 407 #define   UHSIC_STROBE_RPD_C                    BIT(16)
 408 #define   UHSIC_STROBE_RPD_D                    BIT(24)
 409
 410 struct tegra210_xusb_fuse_calibration {
 411         u32 hs_curr_level[4];
 412         u32 hs_term_range_adj;
 413         u32 rpd_ctrl;
 414 };
 415
 416 struct tegra210_xusb_padctl_context {
 417         u32 usb2_pad_mux;
 418         u32 usb2_port_cap;
 419         u32 ss_port_map;
 420         u32 usb3_pad_mux;
 421 };
 422
 423 struct tegra210_xusb_padctl {
 424         struct tegra_xusb_padctl base;
 425         struct regmap *regmap;
 426
 427         struct tegra210_xusb_fuse_calibration fuse;
 428         struct tegra210_xusb_padctl_context context;
 429 };
 430
 431 static inline struct tegra210_xusb_padctl *
 432 to_tegra210_xusb_padctl(struct tegra_xusb_padctl *padctl)
 433 {
 434         return container_of(padctl, struct tegra210_xusb_padctl, base);
 435 }
 436
 437 static const struct tegra_xusb_lane_map tegra210_usb3_map[] = {
 438         { 0, "pcie", 6 },
 439         { 1, "pcie", 5 },
 440         { 2, "pcie", 0 },
 441         { 2, "pcie", 3 },
 442         { 3, "pcie", 4 },
 443         { 3, "sata", 0 },
 444         { 0, NULL,   0 }
 445 };
 446
 447 static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane)
 448 {
 449         const struct tegra_xusb_lane_map *map;
 450
 451         for (map = tegra210_usb3_map; map->type; map++) {
 452                 if (map->index == lane->index &&
 453                     strcmp(map->type, lane->pad->soc->name) == 0) {
 454                         dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n",
 455                                 lane->pad->soc->lanes[lane->index].name, map->port);
 456                         return map->port;
 457                 }
 458         }
 459
 460         return -EINVAL;
 461 }
 462
 463 /* must be called under padctl->lock */
 464 static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
 465 {
 466         struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie);
 467         unsigned long timeout;
 468         u32 value;
 469         unsigned int i;
 470         int err;
 471
 472         if (pcie->enable)
 473                 return 0;
 474
 475         err = clk_prepare_enable(pcie->pll);
 476         if (err < 0)
 477                 return err;
 478
 479         if (tegra210_plle_hw_sequence_is_enabled())
 480                 goto skip_pll_init;
 481
 482         err = reset_control_deassert(pcie->rst);
 483         if (err < 0)
 484                 goto disable;
 485
 486         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 487         value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK <<
 488                    XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT);
 489         value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL <<
 490                  XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT;
 491         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 492
 493         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
 494         value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK <<
 495                    XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT);
 496         value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL <<
 497                  XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT;
 498         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
 499
 500         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 501         value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
 502         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 503
 504         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 505         value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
 506         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 507
 508         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 509         value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
 510         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 511
 512         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
 513         value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK <<
 514                     XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) |
 515                    (XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK <<
 516                     XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT));
 517         value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL <<
 518                   XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) |
 519                  XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN;
 520         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
 521
 522         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 523         value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK <<
 524                     XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT) |
 525                    (XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK <<
 526                     XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT));
 527         value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL <<
 528                  XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT;
 529         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 530
 531         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 532         value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ;
 533         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 534
 535         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 536         value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK <<
 537                    XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT);
 538         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 539
 540         usleep_range(10, 20);
 541
 542         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
 543         value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN;
 544         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
 545
 546         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 547         value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
 548         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 549
 550         timeout = jiffies + msecs_to_jiffies(100);
 551
 552         while (time_before(jiffies, timeout)) {
 553                 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 554                 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)
 555                         break;
 556
 557                 usleep_range(10, 20);
 558         }
 559
 560         if (time_after_eq(jiffies, timeout)) {
 561                 err = -ETIMEDOUT;
 562                 goto reset;
 563         }
 564
 565         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 566         value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
 567         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 568
 569         timeout = jiffies + msecs_to_jiffies(100);
 570
 571         while (time_before(jiffies, timeout)) {
 572                 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 573                 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE))
 574                         break;
 575
 576                 usleep_range(10, 20);
 577         }
 578
 579         if (time_after_eq(jiffies, timeout)) {
 580                 err = -ETIMEDOUT;
 581                 goto reset;
 582         }
 583
 584         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 585         value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE;
 586         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 587
 588         timeout = jiffies + msecs_to_jiffies(100);
 589
 590         while (time_before(jiffies, timeout)) {
 591                 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 592                 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS)
 593                         break;
 594
 595                 usleep_range(10, 20);
 596         }
 597
 598         if (time_after_eq(jiffies, timeout)) {
 599                 err = -ETIMEDOUT;
 600                 goto reset;
 601         }
 602
 603         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 604         value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN |
 605                  XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
 606         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 607
 608         timeout = jiffies + msecs_to_jiffies(100);
 609
 610         while (time_before(jiffies, timeout)) {
 611                 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 612                 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)
 613                         break;
 614
 615                 usleep_range(10, 20);
 616         }
 617
 618         if (time_after_eq(jiffies, timeout)) {
 619                 err = -ETIMEDOUT;
 620                 goto reset;
 621         }
 622
 623         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 624         value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN;
 625         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 626
 627         timeout = jiffies + msecs_to_jiffies(100);
 628
 629         while (time_before(jiffies, timeout)) {
 630                 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 631                 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE))
 632                         break;
 633
 634                 usleep_range(10, 20);
 635         }
 636
 637         if (time_after_eq(jiffies, timeout)) {
 638                 err = -ETIMEDOUT;
 639                 goto reset;
 640         }
 641
 642         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 643         value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
 644         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 645
 646         tegra210_xusb_pll_hw_control_enable();
 647
 648         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 649         value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
 650         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 651
 652         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 653         value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
 654         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 655
 656         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 657         value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
 658         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 659
 660         usleep_range(10, 20);
 661
 662         tegra210_xusb_pll_hw_sequence_start();
 663
 664 skip_pll_init:
 665         pcie->enable = true;
 666
 667         for (i = 0; i < padctl->pcie->soc->num_lanes; i++) {
 668                 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
 669                 value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(i);
 670                 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
 671         }
 672
 673         return 0;
 674
 675 reset:
 676         reset_control_assert(pcie->rst);
 677 disable:
 678         clk_disable_unprepare(pcie->pll);
 679         return err;
 680 }
 681
 682 static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl *padctl)
 683 {
 684         struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie);
 685         u32 value;
 686         unsigned int i;
 687
 688         if (WARN_ON(!pcie->enable))
 689                 return;
 690
 691         pcie->enable = false;
 692
 693         for (i = 0; i < padctl->pcie->soc->num_lanes; i++) {
 694                 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
 695                 value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(i);
 696                 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
 697         }
 698
 699         clk_disable_unprepare(pcie->pll);
 700 }
 701
 702 /* must be called under padctl->lock */
 703 static int tegra210_sata_uphy_enable(struct tegra_xusb_padctl *padctl)
 704 {
 705         struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata);
 706         struct tegra_xusb_lane *lane = tegra_xusb_find_lane(padctl, "sata", 0);
 707         unsigned long timeout;
 708         u32 value;
 709         unsigned int i;
 710         int err;
 711         bool usb;
 712
 713         if (sata->enable)
 714                 return 0;
 715
 716         if (IS_ERR(lane))
 717                 return 0;
 718
 719         if (tegra210_plle_hw_sequence_is_enabled())
 720                 goto skip_pll_init;
 721
 722         usb = tegra_xusb_lane_check(lane, "usb3-ss");
 723
 724         err = clk_prepare_enable(sata->pll);
 725         if (err < 0)
 726                 return err;
 727
 728         err = reset_control_deassert(sata->rst);
 729         if (err < 0)
 730                 goto disable;
 731
 732         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 733         value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK <<
 734                    XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT);
 735         value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL <<
 736                  XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT;
 737         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 738
 739         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL5);
 740         value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK <<
 741                    XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT);
 742         value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL <<
 743                  XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT;
 744         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL5);
 745
 746         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 747         value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
 748         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 749
 750         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 751         value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
 752         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 753
 754         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 755         value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
 756         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 757
 758         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
 759         value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK <<
 760                     XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) |
 761                    (XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK <<
 762                     XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT));
 763         value |= XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN;
 764
 765         if (usb)
 766                 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL <<
 767                           XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT);
 768         else
 769                 value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL <<
 770                           XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT);
 771
 772         value &= ~XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN;
 773         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
 774
 775         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 776         value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK <<
 777                     XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT) |
 778                    (XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK <<
 779                     XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT));
 780
 781         if (usb)
 782                 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL <<
 783                          XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT;
 784         else
 785                 value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL <<
 786                          XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT;
 787
 788         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 789
 790         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 791         value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ;
 792         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 793
 794         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 795         value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK <<
 796                    XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT);
 797         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 798
 799         usleep_range(10, 20);
 800
 801         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
 802         value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN;
 803         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
 804
 805         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 806         value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
 807         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 808
 809         timeout = jiffies + msecs_to_jiffies(100);
 810
 811         while (time_before(jiffies, timeout)) {
 812                 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 813                 if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)
 814                         break;
 815
 816                 usleep_range(10, 20);
 817         }
 818
 819         if (time_after_eq(jiffies, timeout)) {
 820                 err = -ETIMEDOUT;
 821                 goto reset;
 822         }
 823
 824         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 825         value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
 826         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 827
 828         timeout = jiffies + msecs_to_jiffies(100);
 829
 830         while (time_before(jiffies, timeout)) {
 831                 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 832                 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE))
 833                         break;
 834
 835                 usleep_range(10, 20);
 836         }
 837
 838         if (time_after_eq(jiffies, timeout)) {
 839                 err = -ETIMEDOUT;
 840                 goto reset;
 841         }
 842
 843         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 844         value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE;
 845         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 846
 847         timeout = jiffies + msecs_to_jiffies(100);
 848
 849         while (time_before(jiffies, timeout)) {
 850                 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 851                 if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS)
 852                         break;
 853
 854                 usleep_range(10, 20);
 855         }
 856
 857         if (time_after_eq(jiffies, timeout)) {
 858                 err = -ETIMEDOUT;
 859                 goto reset;
 860         }
 861
 862         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 863         value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN |
 864                  XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
 865         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 866
 867         timeout = jiffies + msecs_to_jiffies(100);
 868
 869         while (time_before(jiffies, timeout)) {
 870                 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 871                 if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)
 872                         break;
 873
 874                 usleep_range(10, 20);
 875         }
 876
 877         if (time_after_eq(jiffies, timeout)) {
 878                 err = -ETIMEDOUT;
 879                 goto reset;
 880         }
 881
 882         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 883         value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN;
 884         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 885
 886         timeout = jiffies + msecs_to_jiffies(100);
 887
 888         while (time_before(jiffies, timeout)) {
 889                 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 890                 if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE))
 891                         break;
 892
 893                 usleep_range(10, 20);
 894         }
 895
 896         if (time_after_eq(jiffies, timeout)) {
 897                 err = -ETIMEDOUT;
 898                 goto reset;
 899         }
 900
 901         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 902         value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
 903         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 904
 905         tegra210_sata_pll_hw_control_enable();
 906
 907         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 908         value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
 909         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 910
 911         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 912         value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
 913         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 914
 915         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 916         value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
 917         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 918
 919         usleep_range(10, 20);
 920
 921         tegra210_sata_pll_hw_sequence_start();
 922
 923 skip_pll_init:
 924         sata->enable = true;
 925
 926         for (i = 0; i < padctl->sata->soc->num_lanes; i++) {
 927                 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
 928                 value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(i);
 929                 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
 930         }
 931
 932         return 0;
 933
 934 reset:
 935         reset_control_assert(sata->rst);
 936 disable:
 937         clk_disable_unprepare(sata->pll);
 938         return err;
 939 }
 940
 941 static void tegra210_sata_uphy_disable(struct tegra_xusb_padctl *padctl)
 942 {
 943         struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata);
 944         u32 value;
 945         unsigned int i;
 946
 947         if (WARN_ON(!sata->enable))
 948                 return;
 949
 950         sata->enable = false;
 951
 952         for (i = 0; i < padctl->sata->soc->num_lanes; i++) {
 953                 value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
 954                 value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(i);
 955                 padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
 956         }
 957
 958         clk_disable_unprepare(sata->pll);
 959 }
 960
 961 static void tegra210_aux_mux_lp0_clamp_disable(struct tegra_xusb_padctl *padctl)
 962 {
 963         u32 value;
 964
 965         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
 966         value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
 967         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
 968
 969         usleep_range(100, 200);
 970
 971         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
 972         value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;
 973         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
 974
 975         usleep_range(100, 200);
 976
 977         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
 978         value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
 979         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
 980 }
 981
 982 static void tegra210_aux_mux_lp0_clamp_enable(struct tegra_xusb_padctl *padctl)
 983 {
 984         u32 value;
 985
 986         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
 987         value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
 988         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
 989
 990         usleep_range(100, 200);
 991
 992         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
 993         value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;
 994         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
 995
 996         usleep_range(100, 200);
 997
 998         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
 999         value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
1000         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1001 }
1002
1003 static int tegra210_uphy_init(struct tegra_xusb_padctl *padctl)
1004 {
1005         if (padctl->pcie)
1006                 tegra210_pex_uphy_enable(padctl);
1007
1008         if (padctl->sata)
1009                 tegra210_sata_uphy_enable(padctl);
1010
1011         if (!tegra210_plle_hw_sequence_is_enabled())
1012                 tegra210_plle_hw_sequence_start();
1013         else
1014                 dev_dbg(padctl->dev, "PLLE is already in HW control\n");
1015
1016         tegra210_aux_mux_lp0_clamp_disable(padctl);
1017
1018         return 0;
1019 }
1020
1021 static void __maybe_unused
1022 tegra210_uphy_deinit(struct tegra_xusb_padctl *padctl)
1023 {
1024         tegra210_aux_mux_lp0_clamp_enable(padctl);
1025
1026         if (padctl->sata)
1027                 tegra210_sata_uphy_disable(padctl);
1028
1029         if (padctl->pcie)
1030                 tegra210_pex_uphy_disable(padctl);
1031 }
1032
1033 static int tegra210_hsic_set_idle(struct tegra_xusb_padctl *padctl,
1034                                   unsigned int index, bool idle)
1035 {
1036         u32 value;
1037
1038         value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1039
1040         value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 |
1041                    XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 |
1042                    XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE);
1043
1044         if (idle)
1045                 value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |
1046                          XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 |
1047                          XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE;
1048         else
1049                 value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |
1050                            XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 |
1051                            XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE);
1052
1053         padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1054
1055         return 0;
1056 }
1057
1058 static int tegra210_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
1059                                               enum usb_device_speed speed)
1060 {
1061         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1062         int port = tegra210_usb3_lane_map(lane);
1063         struct device *dev = padctl->dev;
1064         u32 value;
1065
1066         if (port < 0) {
1067                 dev_err(dev, "invalid usb3 port number\n");
1068                 return -EINVAL;
1069         }
1070
1071         mutex_lock(&padctl->lock);
1072
1073         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1074         value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(port);
1075         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1076
1077         usleep_range(100, 200);
1078
1079         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1080         value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(port);
1081         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1082
1083         usleep_range(250, 350);
1084
1085         mutex_unlock(&padctl->lock);
1086
1087         return 0;
1088 }
1089
1090 static int tegra210_usb3_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
1091 {
1092         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1093         int port = tegra210_usb3_lane_map(lane);
1094         struct device *dev = padctl->dev;
1095         u32 value;
1096
1097         if (port < 0) {
1098                 dev_err(dev, "invalid usb3 port number\n");
1099                 return -EINVAL;
1100         }
1101
1102         mutex_lock(&padctl->lock);
1103
1104         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1105         value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(port);
1106         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1107
1108         usleep_range(100, 200);
1109
1110         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1111         value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(port);
1112         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1113
1114         mutex_unlock(&padctl->lock);
1115
1116         return 0;
1117 }
1118
1119 static int tegra210_usb3_enable_phy_wake(struct tegra_xusb_lane *lane)
1120 {
1121         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1122         int port = tegra210_usb3_lane_map(lane);
1123         struct device *dev = padctl->dev;
1124         u32 value;
1125
1126         if (port < 0) {
1127                 dev_err(dev, "invalid usb3 port number\n");
1128                 return -EINVAL;
1129         }
1130
1131         mutex_lock(&padctl->lock);
1132
1133         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1134         value &= ~ALL_WAKE_EVENTS;
1135         value |= SS_PORT_WAKEUP_EVENT(port);
1136         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1137
1138         usleep_range(10, 20);
1139
1140         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1141         value &= ~ALL_WAKE_EVENTS;
1142         value |= SS_PORT_WAKE_INTERRUPT_ENABLE(port);
1143         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1144
1145         mutex_unlock(&padctl->lock);
1146
1147         return 0;
1148 }
1149
1150 static int tegra210_usb3_disable_phy_wake(struct tegra_xusb_lane *lane)
1151 {
1152         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1153         int port = tegra210_usb3_lane_map(lane);
1154         struct device *dev = padctl->dev;
1155         u32 value;
1156
1157         if (port < 0) {
1158                 dev_err(dev, "invalid usb3 port number\n");
1159                 return -EINVAL;
1160         }
1161
1162         mutex_lock(&padctl->lock);
1163
1164         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1165         value &= ~ALL_WAKE_EVENTS;
1166         value &= ~SS_PORT_WAKE_INTERRUPT_ENABLE(port);
1167         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1168
1169         usleep_range(10, 20);
1170
1171         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1172         value &= ~ALL_WAKE_EVENTS;
1173         value |= SS_PORT_WAKEUP_EVENT(port);
1174         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1175
1176         mutex_unlock(&padctl->lock);
1177
1178         return 0;
1179 }
1180
1181 static bool tegra210_usb3_phy_remote_wake_detected(struct tegra_xusb_lane *lane)
1182 {
1183         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1184         int index = tegra210_usb3_lane_map(lane);
1185         u32 value;
1186
1187         if (index < 0)
1188                 return false;
1189
1190         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1191         if ((value & SS_PORT_WAKE_INTERRUPT_ENABLE(index)) && (value & SS_PORT_WAKEUP_EVENT(index)))
1192                 return true;
1193
1194         return false;
1195 }
1196
1197 static int tegra210_utmi_enable_phy_wake(struct tegra_xusb_lane *lane)
1198 {
1199         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1200         unsigned int index = lane->index;
1201         u32 value;
1202
1203         mutex_lock(&padctl->lock);
1204
1205         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1206         value &= ~ALL_WAKE_EVENTS;
1207         value |= USB2_PORT_WAKEUP_EVENT(index);
1208         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1209
1210         usleep_range(10, 20);
1211
1212         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1213         value &= ~ALL_WAKE_EVENTS;
1214         value |= USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
1215         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1216
1217         mutex_unlock(&padctl->lock);
1218
1219         return 0;
1220 }
1221
1222 static int tegra210_utmi_disable_phy_wake(struct tegra_xusb_lane *lane)
1223 {
1224         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1225         unsigned int index = lane->index;
1226         u32 value;
1227
1228         mutex_lock(&padctl->lock);
1229
1230         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1231         value &= ~ALL_WAKE_EVENTS;
1232         value &= ~USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
1233         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1234
1235         usleep_range(10, 20);
1236
1237         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1238         value &= ~ALL_WAKE_EVENTS;
1239         value |= USB2_PORT_WAKEUP_EVENT(index);
1240         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1241
1242         mutex_unlock(&padctl->lock);
1243
1244         return 0;
1245 }
1246
1247 static bool tegra210_utmi_phy_remote_wake_detected(struct tegra_xusb_lane *lane)
1248 {
1249         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1250         unsigned int index = lane->index;
1251         u32 value;
1252
1253         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1254         if ((value & USB2_PORT_WAKE_INTERRUPT_ENABLE(index)) &&
1255             (value & USB2_PORT_WAKEUP_EVENT(index)))
1256                 return true;
1257
1258         return false;
1259 }
1260
1261 static int tegra210_hsic_enable_phy_wake(struct tegra_xusb_lane *lane)
1262 {
1263         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1264         unsigned int index = lane->index;
1265         u32 value;
1266
1267         mutex_lock(&padctl->lock);
1268
1269         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1270         value &= ~ALL_WAKE_EVENTS;
1271         value |= USB2_HSIC_PORT_WAKEUP_EVENT(index);
1272         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1273
1274         usleep_range(10, 20);
1275
1276         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1277         value &= ~ALL_WAKE_EVENTS;
1278         value |= USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(index);
1279         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1280
1281         mutex_unlock(&padctl->lock);
1282
1283         return 0;
1284 }
1285
1286 static int tegra210_hsic_disable_phy_wake(struct tegra_xusb_lane *lane)
1287 {
1288         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1289         unsigned int index = lane->index;
1290         u32 value;
1291
1292         mutex_lock(&padctl->lock);
1293
1294         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1295         value &= ~ALL_WAKE_EVENTS;
1296         value &= ~USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(index);
1297         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1298
1299         usleep_range(10, 20);
1300
1301         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1302         value &= ~ALL_WAKE_EVENTS;
1303         value |= USB2_HSIC_PORT_WAKEUP_EVENT(index);
1304         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_0);
1305
1306         mutex_unlock(&padctl->lock);
1307
1308         return 0;
1309 }
1310
1311 static bool tegra210_hsic_phy_remote_wake_detected(struct tegra_xusb_lane *lane)
1312 {
1313         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1314         unsigned int index = lane->index;
1315         u32 value;
1316
1317         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_0);
1318         if ((value & USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(index)) &&
1319             (value & USB2_HSIC_PORT_WAKEUP_EVENT(index)))
1320                 return true;
1321
1322         return false;
1323 }
1324
1325 #define padctl_pmc_readl(_priv, _offset)                                                \
1326 ({                                                                                      \
1327         u32 value;                                                                      \
1328         WARN(regmap_read(_priv->regmap, _offset, &value), "read %s failed\n", #_offset);\
1329         value;                                                                          \
1330 })
1331
1332 #define padctl_pmc_writel(_priv, _value, _offset)                                       \
1333         WARN(regmap_write(_priv->regmap, _offset, _value), "write %s failed\n", #_offset)
1334
1335 static int tegra210_pmc_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
1336                                                   enum usb_device_speed speed)
1337 {
1338         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1339         struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
1340         unsigned int port = lane->index;
1341         u32 value, tctrl, pctrl, rpd_ctrl;
1342
1343         if (!priv->regmap)
1344                 return -EOPNOTSUPP;
1345
1346         if (speed > USB_SPEED_HIGH)
1347                 return -EINVAL;
1348
1349         value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1350         tctrl = TCTRL_VALUE(value);
1351         pctrl = PCTRL_VALUE(value);
1352
1353         value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(port));
1354         rpd_ctrl = RPD_CTRL_VALUE(value);
1355
1356         /* ensure sleepwalk logic is disabled */
1357         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1358         value &= ~UTMIP_MASTER_ENABLE(port);
1359         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1360
1361         /* ensure sleepwalk logics are in low power mode */
1362         value = padctl_pmc_readl(priv, PMC_UTMIP_MASTER_CONFIG);
1363         value |= UTMIP_PWR(port);
1364         padctl_pmc_writel(priv, value, PMC_UTMIP_MASTER_CONFIG);
1365
1366         /* set debounce time */
1367         value = padctl_pmc_readl(priv, PMC_USB_DEBOUNCE_DEL);
1368         value &= ~UTMIP_LINE_DEB_CNT(~0);
1369         value |= UTMIP_LINE_DEB_CNT(0x1);
1370         padctl_pmc_writel(priv, value, PMC_USB_DEBOUNCE_DEL);
1371
1372         /* ensure fake events of sleepwalk logic are desiabled */
1373         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_FAKE(port));
1374         value &= ~(UTMIP_FAKE_USBOP_VAL(port) | UTMIP_FAKE_USBON_VAL(port) |
1375                    UTMIP_FAKE_USBOP_EN(port) | UTMIP_FAKE_USBON_EN(port));
1376         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_FAKE(port));
1377
1378         /* ensure wake events of sleepwalk logic are not latched */
1379         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1380         value &= ~UTMIP_LINE_WAKEUP_EN(port);
1381         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1382
1383         /* disable wake event triggers of sleepwalk logic */
1384         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1385         value &= ~UTMIP_WAKE_VAL(port, ~0);
1386         value |= UTMIP_WAKE_VAL_NONE(port);
1387         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1388
1389         /* power down the line state detectors of the pad */
1390         value = padctl_pmc_readl(priv, PMC_USB_AO);
1391         value |= (USBOP_VAL_PD(port) | USBON_VAL_PD(port));
1392         padctl_pmc_writel(priv, value, PMC_USB_AO);
1393
1394         /* save state per speed */
1395         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SAVED_STATE(port));
1396         value &= ~SPEED(port, ~0);
1397
1398         switch (speed) {
1399         case USB_SPEED_HIGH:
1400                 value |= UTMI_HS(port);
1401                 break;
1402
1403         case USB_SPEED_FULL:
1404                 value |= UTMI_FS(port);
1405                 break;
1406
1407         case USB_SPEED_LOW:
1408                 value |= UTMI_LS(port);
1409                 break;
1410
1411         default:
1412                 value |= UTMI_RST(port);
1413                 break;
1414         }
1415
1416         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SAVED_STATE(port));
1417
1418         /* enable the trigger of the sleepwalk logic */
1419         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEPWALK_CFG(port));
1420         value |= UTMIP_LINEVAL_WALK_EN(port);
1421         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEPWALK_CFG(port));
1422
1423         /*
1424          * Reset the walk pointer and clear the alarm of the sleepwalk logic,
1425          * as well as capture the configuration of the USB2.0 pad.
1426          */
1427         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS);
1428         value |= UTMIP_CLR_WALK_PTR(port) | UTMIP_CLR_WAKE_ALARM(port) | UTMIP_CAP_CFG(port);
1429         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS);
1430
1431         /* program electrical parameters read from XUSB PADCTL */
1432         value = padctl_pmc_readl(priv, PMC_UTMIP_TERM_PAD_CFG);
1433         value &= ~(TCTRL_VAL(~0) | PCTRL_VAL(~0));
1434         value |= (TCTRL_VAL(tctrl) | PCTRL_VAL(pctrl));
1435         padctl_pmc_writel(priv, value, PMC_UTMIP_TERM_PAD_CFG);
1436
1437         value = padctl_pmc_readl(priv, PMC_UTMIP_PAD_CFGX(port));
1438         value &= ~RPD_CTRL_PX(~0);
1439         value |= RPD_CTRL_PX(rpd_ctrl);
1440         padctl_pmc_writel(priv, value, PMC_UTMIP_PAD_CFGX(port));
1441
1442         /*
1443          * Set up the pull-ups and pull-downs of the signals during the four
1444          * stages of sleepwalk. If a device is connected, program sleepwalk
1445          * logic to maintain a J and keep driving K upon seeing remote wake.
1446          */
1447         value = padctl_pmc_readl(priv, PMC_UTMIP_SLEEPWALK_PX(port));
1448         value = UTMIP_USBOP_RPD_A | UTMIP_USBOP_RPD_B | UTMIP_USBOP_RPD_C | UTMIP_USBOP_RPD_D;
1449         value |= UTMIP_USBON_RPD_A | UTMIP_USBON_RPD_B | UTMIP_USBON_RPD_C | UTMIP_USBON_RPD_D;
1450
1451         switch (speed) {
1452         case USB_SPEED_HIGH:
1453         case USB_SPEED_FULL:
1454                 /* J state: D+/D- = high/low, K state: D+/D- = low/high */
1455                 value |= UTMIP_HIGHZ_A;
1456                 value |= UTMIP_AP_A;
1457                 value |= UTMIP_AN_B | UTMIP_AN_C | UTMIP_AN_D;
1458                 break;
1459
1460         case USB_SPEED_LOW:
1461                 /* J state: D+/D- = low/high, K state: D+/D- = high/low */
1462                 value |= UTMIP_HIGHZ_A;
1463                 value |= UTMIP_AN_A;
1464                 value |= UTMIP_AP_B | UTMIP_AP_C | UTMIP_AP_D;
1465                 break;
1466
1467         default:
1468                 value |= UTMIP_HIGHZ_A | UTMIP_HIGHZ_B | UTMIP_HIGHZ_C | UTMIP_HIGHZ_D;
1469                 break;
1470         }
1471
1472         padctl_pmc_writel(priv, value, PMC_UTMIP_SLEEPWALK_PX(port));
1473
1474         /* power up the line state detectors of the pad */
1475         value = padctl_pmc_readl(priv, PMC_USB_AO);
1476         value &= ~(USBOP_VAL_PD(port) | USBON_VAL_PD(port));
1477         padctl_pmc_writel(priv, value, PMC_USB_AO);
1478
1479         usleep_range(50, 100);
1480
1481         /* switch the electric control of the USB2.0 pad to PMC */
1482         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1483         value |= UTMIP_FSLS_USE_PMC(port) | UTMIP_PCTRL_USE_PMC(port) | UTMIP_TCTRL_USE_PMC(port);
1484         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1485
1486         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG1);
1487         value |= UTMIP_RPD_CTRL_USE_PMC_PX(port) | UTMIP_RPU_SWITC_LOW_USE_PMC_PX(port);
1488         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG1);
1489
1490         /* set the wake signaling trigger events */
1491         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1492         value &= ~UTMIP_WAKE_VAL(port, ~0);
1493         value |= UTMIP_WAKE_VAL_ANY(port);
1494         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1495
1496         /* enable the wake detection */
1497         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1498         value |= UTMIP_MASTER_ENABLE(port);
1499         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1500
1501         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1502         value |= UTMIP_LINE_WAKEUP_EN(port);
1503         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1504
1505         return 0;
1506 }
1507
1508 static int tegra210_pmc_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
1509 {
1510         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1511         struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
1512         unsigned int port = lane->index;
1513         u32 value;
1514
1515         if (!priv->regmap)
1516                 return -EOPNOTSUPP;
1517
1518         /* disable the wake detection */
1519         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1520         value &= ~UTMIP_MASTER_ENABLE(port);
1521         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1522
1523         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1524         value &= ~UTMIP_LINE_WAKEUP_EN(port);
1525         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1526
1527         /* switch the electric control of the USB2.0 pad to XUSB or USB2 */
1528         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1529         value &= ~(UTMIP_FSLS_USE_PMC(port) | UTMIP_PCTRL_USE_PMC(port) |
1530                    UTMIP_TCTRL_USE_PMC(port));
1531         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1532
1533         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG1);
1534         value &= ~(UTMIP_RPD_CTRL_USE_PMC_PX(port) | UTMIP_RPU_SWITC_LOW_USE_PMC_PX(port));
1535         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG1);
1536
1537         /* disable wake event triggers of sleepwalk logic */
1538         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1539         value &= ~UTMIP_WAKE_VAL(port, ~0);
1540         value |= UTMIP_WAKE_VAL_NONE(port);
1541         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_SLEEP_CFG(port));
1542
1543         /* power down the line state detectors of the port */
1544         value = padctl_pmc_readl(priv, PMC_USB_AO);
1545         value |= (USBOP_VAL_PD(port) | USBON_VAL_PD(port));
1546         padctl_pmc_writel(priv, value, PMC_USB_AO);
1547
1548         /* clear alarm of the sleepwalk logic */
1549         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS);
1550         value |= UTMIP_CLR_WAKE_ALARM(port);
1551         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS);
1552
1553         return 0;
1554 }
1555
1556 static int tegra210_pmc_hsic_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
1557                                                   enum usb_device_speed speed)
1558 {
1559         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1560         struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
1561         u32 value;
1562
1563         if (!priv->regmap)
1564                 return -EOPNOTSUPP;
1565
1566         /* ensure sleepwalk logic is disabled */
1567         value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
1568         value &= ~UHSIC_MASTER_ENABLE;
1569         padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
1570
1571         /* ensure sleepwalk logics are in low power mode */
1572         value = padctl_pmc_readl(priv, PMC_UTMIP_MASTER_CONFIG);
1573         value |= UHSIC_PWR;
1574         padctl_pmc_writel(priv, value, PMC_UTMIP_MASTER_CONFIG);
1575
1576         /* set debounce time */
1577         value = padctl_pmc_readl(priv, PMC_USB_DEBOUNCE_DEL);
1578         value &= ~UHSIC_LINE_DEB_CNT(~0);
1579         value |= UHSIC_LINE_DEB_CNT(0x1);
1580         padctl_pmc_writel(priv, value, PMC_USB_DEBOUNCE_DEL);
1581
1582         /* ensure fake events of sleepwalk logic are desiabled */
1583         value = padctl_pmc_readl(priv, PMC_UHSIC_FAKE);
1584         value &= ~(UHSIC_FAKE_STROBE_VAL | UHSIC_FAKE_DATA_VAL |
1585                    UHSIC_FAKE_STROBE_EN | UHSIC_FAKE_DATA_EN);
1586         padctl_pmc_writel(priv, value, PMC_UHSIC_FAKE);
1587
1588         /* ensure wake events of sleepwalk logic are not latched */
1589         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1590         value &= ~UHSIC_LINE_WAKEUP_EN;
1591         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1592
1593         /* disable wake event triggers of sleepwalk logic */
1594         value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
1595         value &= ~UHSIC_WAKE_VAL(~0);
1596         value |= UHSIC_WAKE_VAL_NONE;
1597         padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
1598
1599         /* power down the line state detectors of the port */
1600         value = padctl_pmc_readl(priv, PMC_USB_AO);
1601         value |= STROBE_VAL_PD | DATA0_VAL_PD | DATA1_VAL_PD;
1602         padctl_pmc_writel(priv, value, PMC_USB_AO);
1603
1604         /* save state, HSIC always comes up as HS */
1605         value = padctl_pmc_readl(priv, PMC_UHSIC_SAVED_STATE);
1606         value &= ~UHSIC_MODE(~0);
1607         value |= UHSIC_HS;
1608         padctl_pmc_writel(priv, value, PMC_UHSIC_SAVED_STATE);
1609
1610         /* enable the trigger of the sleepwalk logic */
1611         value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEPWALK_CFG);
1612         value |= UHSIC_WAKE_WALK_EN | UHSIC_LINEVAL_WALK_EN;
1613         padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEPWALK_CFG);
1614
1615         /*
1616          * Reset the walk pointer and clear the alarm of the sleepwalk logic,
1617          * as well as capture the configuration of the USB2.0 port.
1618          */
1619         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS);
1620         value |= UHSIC_CLR_WALK_PTR | UHSIC_CLR_WAKE_ALARM;
1621         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS);
1622
1623         /*
1624          * Set up the pull-ups and pull-downs of the signals during the four
1625          * stages of sleepwalk. Maintain a HSIC IDLE and keep driving HSIC
1626          * RESUME upon remote wake.
1627          */
1628         value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEPWALK_P0);
1629         value = UHSIC_DATA0_RPD_A | UHSIC_DATA0_RPU_B | UHSIC_DATA0_RPU_C | UHSIC_DATA0_RPU_D |
1630                 UHSIC_STROBE_RPU_A | UHSIC_STROBE_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_STROBE_RPD_D;
1631         padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEPWALK_P0);
1632
1633         /* power up the line state detectors of the port */
1634         value = padctl_pmc_readl(priv, PMC_USB_AO);
1635         value &= ~(STROBE_VAL_PD | DATA0_VAL_PD | DATA1_VAL_PD);
1636         padctl_pmc_writel(priv, value, PMC_USB_AO);
1637
1638         usleep_range(50, 100);
1639
1640         /* set the wake signaling trigger events */
1641         value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
1642         value &= ~UHSIC_WAKE_VAL(~0);
1643         value |= UHSIC_WAKE_VAL_SD10;
1644         padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
1645
1646         /* enable the wake detection */
1647         value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
1648         value |= UHSIC_MASTER_ENABLE;
1649         padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
1650
1651         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1652         value |= UHSIC_LINE_WAKEUP_EN;
1653         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1654
1655         return 0;
1656 }
1657
1658 static int tegra210_pmc_hsic_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
1659 {
1660         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1661         struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
1662         u32 value;
1663
1664         if (!priv->regmap)
1665                 return -EOPNOTSUPP;
1666
1667         /* disable the wake detection */
1668         value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
1669         value &= ~UHSIC_MASTER_ENABLE;
1670         padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
1671
1672         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1673         value &= ~UHSIC_LINE_WAKEUP_EN;
1674         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_LINE_WAKEUP);
1675
1676         /* disable wake event triggers of sleepwalk logic */
1677         value = padctl_pmc_readl(priv, PMC_UHSIC_SLEEP_CFG);
1678         value &= ~UHSIC_WAKE_VAL(~0);
1679         value |= UHSIC_WAKE_VAL_NONE;
1680         padctl_pmc_writel(priv, value, PMC_UHSIC_SLEEP_CFG);
1681
1682         /* power down the line state detectors of the port */
1683         value = padctl_pmc_readl(priv, PMC_USB_AO);
1684         value |= STROBE_VAL_PD | DATA0_VAL_PD | DATA1_VAL_PD;
1685         padctl_pmc_writel(priv, value, PMC_USB_AO);
1686
1687         /* clear alarm of the sleepwalk logic */
1688         value = padctl_pmc_readl(priv, PMC_UTMIP_UHSIC_TRIGGERS);
1689         value |= UHSIC_CLR_WAKE_ALARM;
1690         padctl_pmc_writel(priv, value, PMC_UTMIP_UHSIC_TRIGGERS);
1691
1692         return 0;
1693 }
1694
1695 static int tegra210_usb3_set_lfps_detect(struct tegra_xusb_padctl *padctl,
1696                                          unsigned int index, bool enable)
1697 {
1698         struct tegra_xusb_port *port;
1699         struct tegra_xusb_lane *lane;
1700         u32 value, offset;
1701
1702         port = tegra_xusb_find_port(padctl, "usb3", index);
1703         if (!port)
1704                 return -ENODEV;
1705
1706         lane = port->lane;
1707
1708         if (lane->pad == padctl->pcie)
1709                 offset = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(lane->index);
1710         else
1711                 offset = XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1;
1712
1713         value = padctl_readl(padctl, offset);
1714
1715         value &= ~((XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK <<
1716                     XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT) |
1717                    XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN |
1718                    XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD);
1719
1720         if (!enable) {
1721                 value |= (XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL <<
1722                           XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT) |
1723                          XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN |
1724                          XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD;
1725         }
1726
1727         padctl_writel(padctl, value, offset);
1728
1729         return 0;
1730 }
1731
1732 #define TEGRA210_LANE(_name, _offset, _shift, _mask, _type)             \
1733         {                                                               \
1734                 .name = _name,                                          \
1735                 .offset = _offset,                                      \
1736                 .shift = _shift,                                        \
1737                 .mask = _mask,                                          \
1738                 .num_funcs = ARRAY_SIZE(tegra210_##_type##_functions),  \
1739                 .funcs = tegra210_##_type##_functions,                  \
1740         }
1741
1742 static const char *tegra210_usb2_functions[] = {
1743         "snps",
1744         "xusb",
1745         "uart"
1746 };
1747
1748 static const struct tegra_xusb_lane_soc tegra210_usb2_lanes[] = {
1749         TEGRA210_LANE("usb2-0", 0x004,  0, 0x3, usb2),
1750         TEGRA210_LANE("usb2-1", 0x004,  2, 0x3, usb2),
1751         TEGRA210_LANE("usb2-2", 0x004,  4, 0x3, usb2),
1752         TEGRA210_LANE("usb2-3", 0x004,  6, 0x3, usb2),
1753 };
1754
1755 static struct tegra_xusb_lane *
1756 tegra210_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
1757                          unsigned int index)
1758 {
1759         struct tegra_xusb_usb2_lane *usb2;
1760         int err;
1761
1762         usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
1763         if (!usb2)
1764                 return ERR_PTR(-ENOMEM);
1765
1766         INIT_LIST_HEAD(&usb2->base.list);
1767         usb2->base.soc = &pad->soc->lanes[index];
1768         usb2->base.index = index;
1769         usb2->base.pad = pad;
1770         usb2->base.np = np;
1771
1772         err = tegra_xusb_lane_parse_dt(&usb2->base, np);
1773         if (err < 0) {
1774                 kfree(usb2);
1775                 return ERR_PTR(err);
1776         }
1777
1778         return &usb2->base;
1779 }
1780
1781 static void tegra210_usb2_lane_remove(struct tegra_xusb_lane *lane)
1782 {
1783         struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
1784
1785         kfree(usb2);
1786 }
1787
1788 static const struct tegra_xusb_lane_ops tegra210_usb2_lane_ops = {
1789         .probe = tegra210_usb2_lane_probe,
1790         .remove = tegra210_usb2_lane_remove,
1791         .enable_phy_sleepwalk = tegra210_pmc_utmi_enable_phy_sleepwalk,
1792         .disable_phy_sleepwalk = tegra210_pmc_utmi_disable_phy_sleepwalk,
1793         .enable_phy_wake = tegra210_utmi_enable_phy_wake,
1794         .disable_phy_wake = tegra210_utmi_disable_phy_wake,
1795         .remote_wake_detected = tegra210_utmi_phy_remote_wake_detected,
1796 };
1797
1798 static int tegra210_usb2_phy_init(struct phy *phy)
1799 {
1800         struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1801         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1802         u32 value;
1803
1804         value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
1805         value &= ~(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK <<
1806                    XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT);
1807         value |= XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB <<
1808                  XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT;
1809         padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
1810
1811         return 0;
1812 }
1813
1814 static int tegra210_usb2_phy_exit(struct phy *phy)
1815 {
1816         return 0;
1817 }
1818
1819 static int tegra210_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
1820                                               bool status)
1821 {
1822         u32 value;
1823
1824         dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
1825
1826         value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID);
1827
1828         if (status) {
1829                 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON;
1830                 value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK <<
1831                            XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT);
1832                 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING <<
1833                          XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT;
1834         } else {
1835                 value &= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON;
1836         }
1837
1838         padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID);
1839
1840         return 0;
1841 }
1842
1843 static int tegra210_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
1844                                             bool status)
1845 {
1846         u32 value;
1847
1848         dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");
1849
1850         value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID);
1851
1852         if (status) {
1853                 if (value & XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON) {
1854                         value &= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON;
1855                         padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID);
1856                         usleep_range(1000, 2000);
1857
1858                         value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID);
1859                 }
1860
1861                 value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK <<
1862                            XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT);
1863                 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_GROUNDED <<
1864                          XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT;
1865         } else {
1866                 value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK <<
1867                            XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT);
1868                 value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING <<
1869                          XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT;
1870         }
1871
1872         padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID);
1873
1874         return 0;
1875 }
1876
1877 static int tegra210_usb2_phy_set_mode(struct phy *phy, enum phy_mode mode,
1878                                       int submode)
1879 {
1880         struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1881         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1882         struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
1883                                                                 lane->index);
1884         int err = 0;
1885
1886         mutex_lock(&padctl->lock);
1887
1888         dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);
1889
1890         if (mode == PHY_MODE_USB_OTG) {
1891                 if (submode == USB_ROLE_HOST) {
1892                         tegra210_xusb_padctl_id_override(padctl, true);
1893
1894                         err = regulator_enable(port->supply);
1895                 } else if (submode == USB_ROLE_DEVICE) {
1896                         tegra210_xusb_padctl_vbus_override(padctl, true);
1897                 } else if (submode == USB_ROLE_NONE) {
1898                         /*
1899                          * When port is peripheral only or role transitions to
1900                          * USB_ROLE_NONE from USB_ROLE_DEVICE, regulator is not
1901                          * be enabled.
1902                          */
1903                         if (regulator_is_enabled(port->supply))
1904                                 regulator_disable(port->supply);
1905
1906                         tegra210_xusb_padctl_id_override(padctl, false);
1907                         tegra210_xusb_padctl_vbus_override(padctl, false);
1908                 }
1909         }
1910
1911         mutex_unlock(&padctl->lock);
1912
1913         return err;
1914 }
1915
1916 static int tegra210_usb2_phy_power_on(struct phy *phy)
1917 {
1918         struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1919         struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
1920         struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);
1921         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1922         struct tegra210_xusb_padctl *priv;
1923         struct tegra_xusb_usb2_port *port;
1924         unsigned int index = lane->index;
1925         u32 value;
1926         int err;
1927
1928         port = tegra_xusb_find_usb2_port(padctl, index);
1929         if (!port) {
1930                 dev_err(&phy->dev, "no port found for USB2 lane %u\n", index);
1931                 return -ENODEV;
1932         }
1933
1934         priv = to_tegra210_xusb_padctl(padctl);
1935
1936         if (port->usb3_port_fake != -1) {
1937                 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
1938                 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(
1939                                         port->usb3_port_fake);
1940                 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(
1941                                         port->usb3_port_fake, index);
1942                 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
1943
1944                 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1945                 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(
1946                                         port->usb3_port_fake);
1947                 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1948
1949                 usleep_range(100, 200);
1950
1951                 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1952                 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(
1953                                         port->usb3_port_fake);
1954                 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1955
1956                 usleep_range(100, 200);
1957
1958                 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1959                 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(
1960                                         port->usb3_port_fake);
1961                 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1962         }
1963
1964         value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1965         value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK <<
1966                     XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT) |
1967                    (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK <<
1968                     XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT));
1969         value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL <<
1970                   XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT);
1971
1972         if (tegra_sku_info.revision < TEGRA_REVISION_A02)
1973                 value |=
1974                         (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL <<
1975                         XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT);
1976
1977         padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1978
1979         value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
1980         value &= ~XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(index);
1981         if (port->mode == USB_DR_MODE_UNKNOWN)
1982                 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(index);
1983         else if (port->mode == USB_DR_MODE_PERIPHERAL)
1984                 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(index);
1985         else if (port->mode == USB_DR_MODE_HOST)
1986                 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index);
1987         else if (port->mode == USB_DR_MODE_OTG)
1988                 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(index);
1989         padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
1990
1991         value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
1992         value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK <<
1993                     XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT) |
1994                    XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD |
1995                    XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 |
1996                    XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI);
1997         value |= (priv->fuse.hs_curr_level[index] +
1998                   usb2->hs_curr_level_offset) <<
1999                  XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT;
2000         padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
2001
2002         value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
2003         value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK <<
2004                     XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT) |
2005                    (XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK <<
2006                     XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT) |
2007                    XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR |
2008                    XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD |
2009                    XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD);
2010         value |= (priv->fuse.hs_term_range_adj <<
2011                   XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT) |
2012                  (priv->fuse.rpd_ctrl <<
2013                   XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT);
2014         padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
2015
2016         value = padctl_readl(padctl,
2017                              XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
2018         value &= ~(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK <<
2019                    XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT);
2020         if (port->mode == USB_DR_MODE_HOST)
2021                 value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18;
2022         else
2023                 value |=
2024                       XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL <<
2025                       XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT;
2026         padctl_writel(padctl, value,
2027                       XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
2028
2029         if (port->supply && port->mode == USB_DR_MODE_HOST) {
2030                 err = regulator_enable(port->supply);
2031                 if (err)
2032                         return err;
2033         }
2034
2035         mutex_lock(&padctl->lock);
2036
2037         if (pad->enable > 0) {
2038                 pad->enable++;
2039                 mutex_unlock(&padctl->lock);
2040                 return 0;
2041         }
2042
2043         err = clk_prepare_enable(pad->clk);
2044         if (err)
2045                 goto disable_regulator;
2046
2047         value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
2048         value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK <<
2049                     XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) |
2050                    (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK <<
2051                     XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT));
2052         value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL <<
2053                   XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) |
2054                  (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL <<
2055                   XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT);
2056         padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
2057
2058         value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
2059         value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;
2060         padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
2061
2062         udelay(1);
2063
2064         value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
2065         value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK;
2066         padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
2067
2068         udelay(50);
2069
2070         clk_disable_unprepare(pad->clk);
2071
2072         pad->enable++;
2073         mutex_unlock(&padctl->lock);
2074
2075         return 0;
2076
2077 disable_regulator:
2078         regulator_disable(port->supply);
2079         mutex_unlock(&padctl->lock);
2080         return err;
2081 }
2082
2083 static int tegra210_usb2_phy_power_off(struct phy *phy)
2084 {
2085         struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
2086         struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);
2087         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2088         struct tegra_xusb_usb2_port *port;
2089         u32 value;
2090
2091         port = tegra_xusb_find_usb2_port(padctl, lane->index);
2092         if (!port) {
2093                 dev_err(&phy->dev, "no port found for USB2 lane %u\n",
2094                         lane->index);
2095                 return -ENODEV;
2096         }
2097
2098         mutex_lock(&padctl->lock);
2099
2100         if (port->usb3_port_fake != -1) {
2101                 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2102                 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(
2103                                         port->usb3_port_fake);
2104                 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2105
2106                 usleep_range(100, 200);
2107
2108                 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2109                 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(
2110                                         port->usb3_port_fake);
2111                 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2112
2113                 usleep_range(250, 350);
2114
2115                 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2116                 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(
2117                                         port->usb3_port_fake);
2118                 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2119
2120                 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
2121                 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(port->usb3_port_fake,
2122                                         XUSB_PADCTL_SS_PORT_MAP_PORT_DISABLED);
2123                 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
2124         }
2125
2126         if (WARN_ON(pad->enable == 0))
2127                 goto out;
2128
2129         if (--pad->enable > 0)
2130                 goto out;
2131
2132         value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
2133         value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;
2134         padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
2135
2136 out:
2137         regulator_disable(port->supply);
2138         mutex_unlock(&padctl->lock);
2139         return 0;
2140 }
2141
2142 static const struct phy_ops tegra210_usb2_phy_ops = {
2143         .init = tegra210_usb2_phy_init,
2144         .exit = tegra210_usb2_phy_exit,
2145         .power_on = tegra210_usb2_phy_power_on,
2146         .power_off = tegra210_usb2_phy_power_off,
2147         .set_mode = tegra210_usb2_phy_set_mode,
2148         .owner = THIS_MODULE,
2149 };
2150
2151 static struct tegra_xusb_pad *
2152 tegra210_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
2153                         const struct tegra_xusb_pad_soc *soc,
2154                         struct device_node *np)
2155 {
2156         struct tegra_xusb_usb2_pad *usb2;
2157         struct tegra_xusb_pad *pad;
2158         int err;
2159
2160         usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
2161         if (!usb2)
2162                 return ERR_PTR(-ENOMEM);
2163
2164         pad = &usb2->base;
2165         pad->ops = &tegra210_usb2_lane_ops;
2166         pad->soc = soc;
2167
2168         err = tegra_xusb_pad_init(pad, padctl, np);
2169         if (err < 0) {
2170                 kfree(usb2);
2171                 goto out;
2172         }
2173
2174         usb2->clk = devm_clk_get(&pad->dev, "trk");
2175         if (IS_ERR(usb2->clk)) {
2176                 err = PTR_ERR(usb2->clk);
2177                 dev_err(&pad->dev, "failed to get trk clock: %d\n", err);
2178                 goto unregister;
2179         }
2180
2181         err = tegra_xusb_pad_register(pad, &tegra210_usb2_phy_ops);
2182         if (err < 0)
2183                 goto unregister;
2184
2185         dev_set_drvdata(&pad->dev, pad);
2186
2187         return pad;
2188
2189 unregister:
2190         device_unregister(&pad->dev);
2191 out:
2192         return ERR_PTR(err);
2193 }
2194
2195 static void tegra210_usb2_pad_remove(struct tegra_xusb_pad *pad)
2196 {
2197         struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
2198
2199         kfree(usb2);
2200 }
2201
2202 static const struct tegra_xusb_pad_ops tegra210_usb2_ops = {
2203         .probe = tegra210_usb2_pad_probe,
2204         .remove = tegra210_usb2_pad_remove,
2205 };
2206
2207 static const struct tegra_xusb_pad_soc tegra210_usb2_pad = {
2208         .name = "usb2",
2209         .num_lanes = ARRAY_SIZE(tegra210_usb2_lanes),
2210         .lanes = tegra210_usb2_lanes,
2211         .ops = &tegra210_usb2_ops,
2212 };
2213
2214 static const char *tegra210_hsic_functions[] = {
2215         "snps",
2216         "xusb",
2217 };
2218
2219 static const struct tegra_xusb_lane_soc tegra210_hsic_lanes[] = {
2220         TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, hsic),
2221 };
2222
2223 static struct tegra_xusb_lane *
2224 tegra210_hsic_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
2225                          unsigned int index)
2226 {
2227         struct tegra_xusb_hsic_lane *hsic;
2228         int err;
2229
2230         hsic = kzalloc(sizeof(*hsic), GFP_KERNEL);
2231         if (!hsic)
2232                 return ERR_PTR(-ENOMEM);
2233
2234         INIT_LIST_HEAD(&hsic->base.list);
2235         hsic->base.soc = &pad->soc->lanes[index];
2236         hsic->base.index = index;
2237         hsic->base.pad = pad;
2238         hsic->base.np = np;
2239
2240         err = tegra_xusb_lane_parse_dt(&hsic->base, np);
2241         if (err < 0) {
2242                 kfree(hsic);
2243                 return ERR_PTR(err);
2244         }
2245
2246         return &hsic->base;
2247 }
2248
2249 static void tegra210_hsic_lane_remove(struct tegra_xusb_lane *lane)
2250 {
2251         struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane);
2252
2253         kfree(hsic);
2254 }
2255
2256 static const struct tegra_xusb_lane_ops tegra210_hsic_lane_ops = {
2257         .probe = tegra210_hsic_lane_probe,
2258         .remove = tegra210_hsic_lane_remove,
2259         .enable_phy_sleepwalk = tegra210_pmc_hsic_enable_phy_sleepwalk,
2260         .disable_phy_sleepwalk = tegra210_pmc_hsic_disable_phy_sleepwalk,
2261         .enable_phy_wake = tegra210_hsic_enable_phy_wake,
2262         .disable_phy_wake = tegra210_hsic_disable_phy_wake,
2263         .remote_wake_detected = tegra210_hsic_phy_remote_wake_detected,
2264 };
2265
2266 static int tegra210_hsic_phy_init(struct phy *phy)
2267 {
2268         struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
2269         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2270         u32 value;
2271
2272         value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
2273         value &= ~(XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK <<
2274                    XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT);
2275         value |= XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB <<
2276                  XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT;
2277         padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
2278
2279         return 0;
2280 }
2281
2282 static int tegra210_hsic_phy_exit(struct phy *phy)
2283 {
2284         return 0;
2285 }
2286
2287 static int tegra210_hsic_phy_power_on(struct phy *phy)
2288 {
2289         struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
2290         struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane);
2291         struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad);
2292         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2293         unsigned int index = lane->index;
2294         u32 value;
2295         int err;
2296
2297         err = regulator_enable(pad->supply);
2298         if (err)
2299                 return err;
2300
2301         padctl_writel(padctl, hsic->strobe_trim,
2302                       XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL);
2303
2304         value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index));
2305         value &= ~(XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK <<
2306                    XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT);
2307         value |= (hsic->tx_rtune_p <<
2308                   XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT);
2309         padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
2310
2311         value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index));
2312         value &= ~((XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK <<
2313                     XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT) |
2314                    (XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK <<
2315                     XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT));
2316         value |= (hsic->rx_strobe_trim <<
2317                   XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT) |
2318                  (hsic->rx_data_trim <<
2319                   XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT);
2320         padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index));
2321
2322         value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
2323         value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 |
2324                    XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 |
2325                    XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE |
2326                    XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 |
2327                    XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 |
2328                    XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE |
2329                    XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 |
2330                    XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 |
2331                    XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE |
2332                    XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 |
2333                    XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 |
2334                    XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE);
2335         value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |
2336                  XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 |
2337                  XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE;
2338         padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));
2339
2340         err = clk_prepare_enable(pad->clk);
2341         if (err)
2342                 goto disable;
2343
2344         value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
2345         value &= ~((XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK <<
2346                     XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT) |
2347                    (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK <<
2348                     XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT));
2349         value |= (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL <<
2350                   XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT) |
2351                  (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL <<
2352                   XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT);
2353         padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
2354
2355         udelay(1);
2356
2357         value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
2358         value &= ~XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK;
2359         padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
2360
2361         udelay(50);
2362
2363         clk_disable_unprepare(pad->clk);
2364
2365         return 0;
2366
2367 disable:
2368         regulator_disable(pad->supply);
2369         return err;
2370 }
2371
2372 static int tegra210_hsic_phy_power_off(struct phy *phy)
2373 {
2374         struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
2375         struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad);
2376         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2377         unsigned int index = lane->index;
2378         u32 value;
2379
2380         value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
2381         value |= XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 |
2382                  XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 |
2383                  XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE |
2384                  XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 |
2385                  XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 |
2386                  XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE |
2387                  XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 |
2388                  XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 |
2389                  XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE;
2390         padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
2391
2392         regulator_disable(pad->supply);
2393
2394         return 0;
2395 }
2396
2397 static const struct phy_ops tegra210_hsic_phy_ops = {
2398         .init = tegra210_hsic_phy_init,
2399         .exit = tegra210_hsic_phy_exit,
2400         .power_on = tegra210_hsic_phy_power_on,
2401         .power_off = tegra210_hsic_phy_power_off,
2402         .owner = THIS_MODULE,
2403 };
2404
2405 static struct tegra_xusb_pad *
2406 tegra210_hsic_pad_probe(struct tegra_xusb_padctl *padctl,
2407                         const struct tegra_xusb_pad_soc *soc,
2408                         struct device_node *np)
2409 {
2410         struct tegra_xusb_hsic_pad *hsic;
2411         struct tegra_xusb_pad *pad;
2412         int err;
2413
2414         hsic = kzalloc(sizeof(*hsic), GFP_KERNEL);
2415         if (!hsic)
2416                 return ERR_PTR(-ENOMEM);
2417
2418         pad = &hsic->base;
2419         pad->ops = &tegra210_hsic_lane_ops;
2420         pad->soc = soc;
2421
2422         err = tegra_xusb_pad_init(pad, padctl, np);
2423         if (err < 0) {
2424                 kfree(hsic);
2425                 goto out;
2426         }
2427
2428         hsic->clk = devm_clk_get(&pad->dev, "trk");
2429         if (IS_ERR(hsic->clk)) {
2430                 err = PTR_ERR(hsic->clk);
2431                 dev_err(&pad->dev, "failed to get trk clock: %d\n", err);
2432                 goto unregister;
2433         }
2434
2435         err = tegra_xusb_pad_register(pad, &tegra210_hsic_phy_ops);
2436         if (err < 0)
2437                 goto unregister;
2438
2439         dev_set_drvdata(&pad->dev, pad);
2440
2441         return pad;
2442
2443 unregister:
2444         device_unregister(&pad->dev);
2445 out:
2446         return ERR_PTR(err);
2447 }
2448
2449 static void tegra210_hsic_pad_remove(struct tegra_xusb_pad *pad)
2450 {
2451         struct tegra_xusb_hsic_pad *hsic = to_hsic_pad(pad);
2452
2453         kfree(hsic);
2454 }
2455
2456 static const struct tegra_xusb_pad_ops tegra210_hsic_ops = {
2457         .probe = tegra210_hsic_pad_probe,
2458         .remove = tegra210_hsic_pad_remove,
2459 };
2460
2461 static const struct tegra_xusb_pad_soc tegra210_hsic_pad = {
2462         .name = "hsic",
2463         .num_lanes = ARRAY_SIZE(tegra210_hsic_lanes),
2464         .lanes = tegra210_hsic_lanes,
2465         .ops = &tegra210_hsic_ops,
2466 };
2467
2468 static void tegra210_uphy_lane_iddq_enable(struct tegra_xusb_lane *lane)
2469 {
2470         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2471         u32 value;
2472
2473         value = padctl_readl(padctl, lane->soc->regs.misc_ctl2);
2474         value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD;
2475         value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD;
2476         value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_PWR_OVRD;
2477         value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_PWR_OVRD;
2478         value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ;
2479         value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_MASK;
2480         value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_VAL;
2481         value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ;
2482         value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_MASK;
2483         value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL;
2484         padctl_writel(padctl, value, lane->soc->regs.misc_ctl2);
2485 }
2486
2487 static void tegra210_uphy_lane_iddq_disable(struct tegra_xusb_lane *lane)
2488 {
2489         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2490         u32 value;
2491
2492         value = padctl_readl(padctl, lane->soc->regs.misc_ctl2);
2493         value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ_OVRD;
2494         value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ_OVRD;
2495         value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_PWR_OVRD;
2496         value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_PWR_OVRD;
2497         value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_IDDQ;
2498         value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_MASK;
2499         value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_TX_SLEEP_VAL;
2500         value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_IDDQ;
2501         value &= ~XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_MASK;
2502         value |= XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL;
2503         padctl_writel(padctl, value, lane->soc->regs.misc_ctl2);
2504 }
2505
2506 #define TEGRA210_UPHY_LANE(_name, _offset, _shift, _mask, _type, _misc) \
2507         {                                                               \
2508                 .name = _name,                                          \
2509                 .offset = _offset,                                      \
2510                 .shift = _shift,                                        \
2511                 .mask = _mask,                                          \
2512                 .num_funcs = ARRAY_SIZE(tegra210_##_type##_functions),  \
2513                 .funcs = tegra210_##_type##_functions,                  \
2514                 .regs.misc_ctl2 = _misc,                                \
2515         }
2516
2517 static const char *tegra210_pcie_functions[] = {
2518         "pcie-x1",
2519         "usb3-ss",
2520         "sata",
2521         "pcie-x4",
2522 };
2523
2524 static const struct tegra_xusb_lane_soc tegra210_pcie_lanes[] = {
2525         TEGRA210_UPHY_LANE("pcie-0", 0x028, 12, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(0)),
2526         TEGRA210_UPHY_LANE("pcie-1", 0x028, 14, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(1)),
2527         TEGRA210_UPHY_LANE("pcie-2", 0x028, 16, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(2)),
2528         TEGRA210_UPHY_LANE("pcie-3", 0x028, 18, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(3)),
2529         TEGRA210_UPHY_LANE("pcie-4", 0x028, 20, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(4)),
2530         TEGRA210_UPHY_LANE("pcie-5", 0x028, 22, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(5)),
2531         TEGRA210_UPHY_LANE("pcie-6", 0x028, 24, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(6)),
2532 };
2533
2534 static struct tegra_xusb_usb3_port *
2535 tegra210_lane_to_usb3_port(struct tegra_xusb_lane *lane)
2536 {
2537         int port;
2538
2539         if (!lane || !lane->pad || !lane->pad->padctl)
2540                 return NULL;
2541
2542         port = tegra210_usb3_lane_map(lane);
2543         if (port < 0)
2544                 return NULL;
2545
2546         return tegra_xusb_find_usb3_port(lane->pad->padctl, port);
2547 }
2548
2549 static int tegra210_usb3_phy_power_on(struct phy *phy)
2550 {
2551         struct device *dev = &phy->dev;
2552         struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
2553         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2554         struct tegra_xusb_usb3_port *usb3 = tegra210_lane_to_usb3_port(lane);
2555         unsigned int index;
2556         u32 value;
2557
2558         if (!usb3) {
2559                 dev_err(dev, "no USB3 port found for lane %u\n", lane->index);
2560                 return -ENODEV;
2561         }
2562
2563         index = usb3->base.index;
2564
2565         value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
2566
2567         if (!usb3->internal)
2568                 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
2569         else
2570                 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
2571
2572         value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);
2573         value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port);
2574         padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
2575
2576         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
2577         value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK <<
2578                    XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT);
2579         value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL <<
2580                  XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT;
2581         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
2582
2583         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
2584         value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK <<
2585                    XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT);
2586         value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL <<
2587                  XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT;
2588         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
2589
2590         padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL,
2591                       XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(index));
2592
2593         value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
2594         value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK <<
2595                    XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT);
2596         value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL <<
2597                  XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT;
2598         padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
2599
2600         padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL,
2601                       XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(index));
2602
2603         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2604         value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);
2605         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2606
2607         usleep_range(100, 200);
2608
2609         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2610         value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);
2611         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2612
2613         usleep_range(100, 200);
2614
2615         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2616         value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);
2617         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2618
2619         return 0;
2620 }
2621
2622 static int tegra210_usb3_phy_power_off(struct phy *phy)
2623 {
2624         struct device *dev = &phy->dev;
2625         struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
2626         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2627         struct tegra_xusb_usb3_port *usb3 = tegra210_lane_to_usb3_port(lane);
2628         unsigned int index;
2629         u32 value;
2630
2631         if (!usb3) {
2632                 dev_err(dev, "no USB3 port found for lane %u\n", lane->index);
2633                 return -ENODEV;
2634         }
2635
2636         index = usb3->base.index;
2637
2638         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2639         value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);
2640         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2641
2642         usleep_range(100, 200);
2643
2644         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2645         value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);
2646         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2647
2648         usleep_range(250, 350);
2649
2650         value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2651         value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);
2652         padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2653
2654         return 0;
2655 }
2656 static struct tegra_xusb_lane *
2657 tegra210_pcie_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
2658                          unsigned int index)
2659 {
2660         struct tegra_xusb_pcie_lane *pcie;
2661         int err;
2662
2663         pcie = kzalloc(sizeof(*pcie), GFP_KERNEL);
2664         if (!pcie)
2665                 return ERR_PTR(-ENOMEM);
2666
2667         INIT_LIST_HEAD(&pcie->base.list);
2668         pcie->base.soc = &pad->soc->lanes[index];
2669         pcie->base.index = index;
2670         pcie->base.pad = pad;
2671         pcie->base.np = np;
2672
2673         err = tegra_xusb_lane_parse_dt(&pcie->base, np);
2674         if (err < 0) {
2675                 kfree(pcie);
2676                 return ERR_PTR(err);
2677         }
2678
2679         return &pcie->base;
2680 }
2681
2682 static void tegra210_pcie_lane_remove(struct tegra_xusb_lane *lane)
2683 {
2684         struct tegra_xusb_pcie_lane *pcie = to_pcie_lane(lane);
2685
2686         kfree(pcie);
2687 }
2688
2689 static const struct tegra_xusb_lane_ops tegra210_pcie_lane_ops = {
2690         .probe = tegra210_pcie_lane_probe,
2691         .remove = tegra210_pcie_lane_remove,
2692         .iddq_enable = tegra210_uphy_lane_iddq_enable,
2693         .iddq_disable = tegra210_uphy_lane_iddq_disable,
2694         .enable_phy_sleepwalk = tegra210_usb3_enable_phy_sleepwalk,
2695         .disable_phy_sleepwalk = tegra210_usb3_disable_phy_sleepwalk,
2696         .enable_phy_wake = tegra210_usb3_enable_phy_wake,
2697         .disable_phy_wake = tegra210_usb3_disable_phy_wake,
2698         .remote_wake_detected = tegra210_usb3_phy_remote_wake_detected,
2699 };
2700
2701 static int tegra210_pcie_phy_init(struct phy *phy)
2702 {
2703         struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
2704         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2705
2706         mutex_lock(&padctl->lock);
2707
2708         tegra210_uphy_init(padctl);
2709
2710         mutex_unlock(&padctl->lock);
2711
2712         return 0;
2713 }
2714
2715 static int tegra210_pcie_phy_power_on(struct phy *phy)
2716 {
2717         struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
2718         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2719         int err = 0;
2720
2721         mutex_lock(&padctl->lock);
2722
2723         if (tegra_xusb_lane_check(lane, "usb3-ss"))
2724                 err = tegra210_usb3_phy_power_on(phy);
2725
2726         mutex_unlock(&padctl->lock);
2727         return err;
2728 }
2729
2730 static int tegra210_pcie_phy_power_off(struct phy *phy)
2731 {
2732         struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
2733         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2734         int err = 0;
2735
2736         mutex_lock(&padctl->lock);
2737
2738         if (tegra_xusb_lane_check(lane, "usb3-ss"))
2739                 err = tegra210_usb3_phy_power_off(phy);
2740
2741         mutex_unlock(&padctl->lock);
2742         return err;
2743 }
2744
2745 static const struct phy_ops tegra210_pcie_phy_ops = {
2746         .init = tegra210_pcie_phy_init,
2747         .power_on = tegra210_pcie_phy_power_on,
2748         .power_off = tegra210_pcie_phy_power_off,
2749         .owner = THIS_MODULE,
2750 };
2751
2752 static struct tegra_xusb_pad *
2753 tegra210_pcie_pad_probe(struct tegra_xusb_padctl *padctl,
2754                         const struct tegra_xusb_pad_soc *soc,
2755                         struct device_node *np)
2756 {
2757         struct tegra_xusb_pcie_pad *pcie;
2758         struct tegra_xusb_pad *pad;
2759         int err;
2760
2761         pcie = kzalloc(sizeof(*pcie), GFP_KERNEL);
2762         if (!pcie)
2763                 return ERR_PTR(-ENOMEM);
2764
2765         pad = &pcie->base;
2766         pad->ops = &tegra210_pcie_lane_ops;
2767         pad->soc = soc;
2768
2769         err = tegra_xusb_pad_init(pad, padctl, np);
2770         if (err < 0) {
2771                 kfree(pcie);
2772                 goto out;
2773         }
2774
2775         pcie->pll = devm_clk_get(&pad->dev, "pll");
2776         if (IS_ERR(pcie->pll)) {
2777                 err = PTR_ERR(pcie->pll);
2778                 dev_err(&pad->dev, "failed to get PLL: %d\n", err);
2779                 goto unregister;
2780         }
2781
2782         pcie->rst = devm_reset_control_get(&pad->dev, "phy");
2783         if (IS_ERR(pcie->rst)) {
2784                 err = PTR_ERR(pcie->rst);
2785                 dev_err(&pad->dev, "failed to get PCIe pad reset: %d\n", err);
2786                 goto unregister;
2787         }
2788
2789         err = tegra_xusb_pad_register(pad, &tegra210_pcie_phy_ops);
2790         if (err < 0)
2791                 goto unregister;
2792
2793         dev_set_drvdata(&pad->dev, pad);
2794
2795         return pad;
2796
2797 unregister:
2798         device_unregister(&pad->dev);
2799 out:
2800         return ERR_PTR(err);
2801 }
2802
2803 static void tegra210_pcie_pad_remove(struct tegra_xusb_pad *pad)
2804 {
2805         struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(pad);
2806
2807         kfree(pcie);
2808 }
2809
2810 static const struct tegra_xusb_pad_ops tegra210_pcie_ops = {
2811         .probe = tegra210_pcie_pad_probe,
2812         .remove = tegra210_pcie_pad_remove,
2813 };
2814
2815 static const struct tegra_xusb_pad_soc tegra210_pcie_pad = {
2816         .name = "pcie",
2817         .num_lanes = ARRAY_SIZE(tegra210_pcie_lanes),
2818         .lanes = tegra210_pcie_lanes,
2819         .ops = &tegra210_pcie_ops,
2820 };
2821
2822 static const struct tegra_xusb_lane_soc tegra210_sata_lanes[] = {
2823         TEGRA210_UPHY_LANE("sata-0", 0x028, 30, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL2),
2824 };
2825
2826 static struct tegra_xusb_lane *
2827 tegra210_sata_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
2828                          unsigned int index)
2829 {
2830         struct tegra_xusb_sata_lane *sata;
2831         int err;
2832
2833         sata = kzalloc(sizeof(*sata), GFP_KERNEL);
2834         if (!sata)
2835                 return ERR_PTR(-ENOMEM);
2836
2837         INIT_LIST_HEAD(&sata->base.list);
2838         sata->base.soc = &pad->soc->lanes[index];
2839         sata->base.index = index;
2840         sata->base.pad = pad;
2841         sata->base.np = np;
2842
2843         err = tegra_xusb_lane_parse_dt(&sata->base, np);
2844         if (err < 0) {
2845                 kfree(sata);
2846                 return ERR_PTR(err);
2847         }
2848
2849         return &sata->base;
2850 }
2851
2852 static void tegra210_sata_lane_remove(struct tegra_xusb_lane *lane)
2853 {
2854         struct tegra_xusb_sata_lane *sata = to_sata_lane(lane);
2855
2856         kfree(sata);
2857 }
2858
2859 static const struct tegra_xusb_lane_ops tegra210_sata_lane_ops = {
2860         .probe = tegra210_sata_lane_probe,
2861         .remove = tegra210_sata_lane_remove,
2862         .iddq_enable = tegra210_uphy_lane_iddq_enable,
2863         .iddq_disable = tegra210_uphy_lane_iddq_disable,
2864         .enable_phy_sleepwalk = tegra210_usb3_enable_phy_sleepwalk,
2865         .disable_phy_sleepwalk = tegra210_usb3_disable_phy_sleepwalk,
2866         .enable_phy_wake = tegra210_usb3_enable_phy_wake,
2867         .disable_phy_wake = tegra210_usb3_disable_phy_wake,
2868         .remote_wake_detected = tegra210_usb3_phy_remote_wake_detected,
2869 };
2870
2871 static int tegra210_sata_phy_init(struct phy *phy)
2872 {
2873         struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
2874         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2875
2876         mutex_lock(&padctl->lock);
2877
2878         tegra210_uphy_init(padctl);
2879
2880         mutex_unlock(&padctl->lock);
2881         return 0;
2882 }
2883
2884 static int tegra210_sata_phy_power_on(struct phy *phy)
2885 {
2886         struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
2887         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2888         int err = 0;
2889
2890         mutex_lock(&padctl->lock);
2891
2892         if (tegra_xusb_lane_check(lane, "usb3-ss"))
2893                 err = tegra210_usb3_phy_power_on(phy);
2894
2895         mutex_unlock(&padctl->lock);
2896         return err;
2897 }
2898
2899 static int tegra210_sata_phy_power_off(struct phy *phy)
2900 {
2901         struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
2902         struct tegra_xusb_padctl *padctl = lane->pad->padctl;
2903         int err = 0;
2904
2905         mutex_lock(&padctl->lock);
2906
2907         if (tegra_xusb_lane_check(lane, "usb3-ss"))
2908                 err = tegra210_usb3_phy_power_off(phy);
2909
2910         mutex_unlock(&padctl->lock);
2911         return err;
2912 }
2913
2914 static const struct phy_ops tegra210_sata_phy_ops = {
2915         .init = tegra210_sata_phy_init,
2916         .power_on = tegra210_sata_phy_power_on,
2917         .power_off = tegra210_sata_phy_power_off,
2918         .owner = THIS_MODULE,
2919 };
2920
2921 static struct tegra_xusb_pad *
2922 tegra210_sata_pad_probe(struct tegra_xusb_padctl *padctl,
2923                         const struct tegra_xusb_pad_soc *soc,
2924                         struct device_node *np)
2925 {
2926         struct tegra_xusb_sata_pad *sata;
2927         struct tegra_xusb_pad *pad;
2928         int err;
2929
2930         sata = kzalloc(sizeof(*sata), GFP_KERNEL);
2931         if (!sata)
2932                 return ERR_PTR(-ENOMEM);
2933
2934         pad = &sata->base;
2935         pad->ops = &tegra210_sata_lane_ops;
2936         pad->soc = soc;
2937
2938         err = tegra_xusb_pad_init(pad, padctl, np);
2939         if (err < 0) {
2940                 kfree(sata);
2941                 goto out;
2942         }
2943
2944         sata->rst = devm_reset_control_get(&pad->dev, "phy");
2945         if (IS_ERR(sata->rst)) {
2946                 err = PTR_ERR(sata->rst);
2947                 dev_err(&pad->dev, "failed to get SATA pad reset: %d\n", err);
2948                 goto unregister;
2949         }
2950
2951         err = tegra_xusb_pad_register(pad, &tegra210_sata_phy_ops);
2952         if (err < 0)
2953                 goto unregister;
2954
2955         dev_set_drvdata(&pad->dev, pad);
2956
2957         return pad;
2958
2959 unregister:
2960         device_unregister(&pad->dev);
2961 out:
2962         return ERR_PTR(err);
2963 }
2964
2965 static void tegra210_sata_pad_remove(struct tegra_xusb_pad *pad)
2966 {
2967         struct tegra_xusb_sata_pad *sata = to_sata_pad(pad);
2968
2969         kfree(sata);
2970 }
2971
2972 static const struct tegra_xusb_pad_ops tegra210_sata_ops = {
2973         .probe = tegra210_sata_pad_probe,
2974         .remove = tegra210_sata_pad_remove,
2975 };
2976
2977 static const struct tegra_xusb_pad_soc tegra210_sata_pad = {
2978         .name = "sata",
2979         .num_lanes = ARRAY_SIZE(tegra210_sata_lanes),
2980         .lanes = tegra210_sata_lanes,
2981         .ops = &tegra210_sata_ops,
2982 };
2983
2984 static const struct tegra_xusb_pad_soc * const tegra210_pads[] = {
2985         &tegra210_usb2_pad,
2986         &tegra210_hsic_pad,
2987         &tegra210_pcie_pad,
2988         &tegra210_sata_pad,
2989 };
2990
2991 static int tegra210_usb2_port_enable(struct tegra_xusb_port *port)
2992 {
2993         return 0;
2994 }
2995
2996 static void tegra210_usb2_port_disable(struct tegra_xusb_port *port)
2997 {
2998 }
2999
3000 static struct tegra_xusb_lane *
3001 tegra210_usb2_port_map(struct tegra_xusb_port *port)
3002 {
3003         return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
3004 }
3005
3006 static const struct tegra_xusb_port_ops tegra210_usb2_port_ops = {
3007         .release = tegra_xusb_usb2_port_release,
3008         .remove = tegra_xusb_usb2_port_remove,
3009         .enable = tegra210_usb2_port_enable,
3010         .disable = tegra210_usb2_port_disable,
3011         .map = tegra210_usb2_port_map,
3012 };
3013
3014 static int tegra210_hsic_port_enable(struct tegra_xusb_port *port)
3015 {
3016         return 0;
3017 }
3018
3019 static void tegra210_hsic_port_disable(struct tegra_xusb_port *port)
3020 {
3021 }
3022
3023 static struct tegra_xusb_lane *
3024 tegra210_hsic_port_map(struct tegra_xusb_port *port)
3025 {
3026         return tegra_xusb_find_lane(port->padctl, "hsic", port->index);
3027 }
3028
3029 static const struct tegra_xusb_port_ops tegra210_hsic_port_ops = {
3030         .release = tegra_xusb_hsic_port_release,
3031         .enable = tegra210_hsic_port_enable,
3032         .disable = tegra210_hsic_port_disable,
3033         .map = tegra210_hsic_port_map,
3034 };
3035
3036 static int tegra210_usb3_port_enable(struct tegra_xusb_port *port)
3037 {
3038         return 0;
3039 }
3040
3041 static void tegra210_usb3_port_disable(struct tegra_xusb_port *port)
3042 {
3043 }
3044
3045 static struct tegra_xusb_lane *
3046 tegra210_usb3_port_map(struct tegra_xusb_port *port)
3047 {
3048         return tegra_xusb_port_find_lane(port, tegra210_usb3_map, "usb3-ss");
3049 }
3050
3051 static const struct tegra_xusb_port_ops tegra210_usb3_port_ops = {
3052         .release = tegra_xusb_usb3_port_release,
3053         .remove = tegra_xusb_usb3_port_remove,
3054         .enable = tegra210_usb3_port_enable,
3055         .disable = tegra210_usb3_port_disable,
3056         .map = tegra210_usb3_port_map,
3057 };
3058
3059 static int tegra210_utmi_port_reset(struct phy *phy)
3060 {
3061         struct tegra_xusb_padctl *padctl;
3062         struct tegra_xusb_lane *lane;
3063         u32 value;
3064
3065         lane = phy_get_drvdata(phy);
3066         padctl = lane->pad->padctl;
3067
3068         value = padctl_readl(padctl,
3069                      XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(lane->index));
3070
3071         if ((value & XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIP) ||
3072             (value & XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIN)) {
3073                 tegra210_xusb_padctl_vbus_override(padctl, false);
3074                 tegra210_xusb_padctl_vbus_override(padctl, true);
3075                 return 1;
3076         }
3077
3078         return 0;
3079 }
3080
3081 static int
3082 tegra210_xusb_read_fuse_calibration(struct tegra210_xusb_fuse_calibration *fuse)
3083 {
3084         unsigned int i;
3085         u32 value;
3086         int err;
3087
3088         err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
3089         if (err < 0)
3090                 return err;
3091
3092         for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) {
3093                 fuse->hs_curr_level[i] =
3094                         (value >> FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(i)) &
3095                         FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK;
3096         }
3097
3098         fuse->hs_term_range_adj =
3099                 (value >> FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT) &
3100                 FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK;
3101
3102         err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
3103         if (err < 0)
3104                 return err;
3105
3106         fuse->rpd_ctrl =
3107                 (value >> FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT) &
3108                 FUSE_USB_CALIB_EXT_RPD_CTRL_MASK;
3109
3110         return 0;
3111 }
3112
3113 static struct tegra_xusb_padctl *
3114 tegra210_xusb_padctl_probe(struct device *dev,
3115                            const struct tegra_xusb_padctl_soc *soc)
3116 {
3117         struct tegra210_xusb_padctl *padctl;
3118         struct platform_device *pdev;
3119         struct device_node *np;
3120         int err;
3121
3122         padctl = devm_kzalloc(dev, sizeof(*padctl), GFP_KERNEL);
3123         if (!padctl)
3124                 return ERR_PTR(-ENOMEM);
3125
3126         padctl->base.dev = dev;
3127         padctl->base.soc = soc;
3128
3129         err = tegra210_xusb_read_fuse_calibration(&padctl->fuse);
3130         if (err < 0)
3131                 return ERR_PTR(err);
3132
3133         np = of_parse_phandle(dev->of_node, "nvidia,pmc", 0);
3134         if (!np) {
3135                 dev_warn(dev, "nvidia,pmc property is missing\n");
3136                 goto out;
3137         }
3138
3139         pdev = of_find_device_by_node(np);
3140         if (!pdev) {
3141                 dev_warn(dev, "PMC device is not available\n");
3142                 goto out;
3143         }
3144
3145         if (!platform_get_drvdata(pdev))
3146                 return ERR_PTR(-EPROBE_DEFER);
3147
3148         padctl->regmap = dev_get_regmap(&pdev->dev, "usb_sleepwalk");
3149         if (!padctl->regmap)
3150                 dev_info(dev, "failed to find PMC regmap\n");
3151
3152 out:
3153         return &padctl->base;
3154 }
3155
3156 static void tegra210_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
3157 {
3158 }
3159
3160 static void tegra210_xusb_padctl_save(struct tegra_xusb_padctl *padctl)
3161 {
3162         struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
3163
3164         priv->context.usb2_pad_mux =
3165                 padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
3166         priv->context.usb2_port_cap =
3167                 padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
3168         priv->context.ss_port_map =
3169                 padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
3170         priv->context.usb3_pad_mux =
3171                 padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
3172 }
3173
3174 static void tegra210_xusb_padctl_restore(struct tegra_xusb_padctl *padctl)
3175 {
3176         struct tegra210_xusb_padctl *priv = to_tegra210_xusb_padctl(padctl);
3177         struct tegra_xusb_lane *lane;
3178
3179         padctl_writel(padctl, priv->context.usb2_pad_mux,
3180                 XUSB_PADCTL_USB2_PAD_MUX);
3181         padctl_writel(padctl, priv->context.usb2_port_cap,
3182                 XUSB_PADCTL_USB2_PORT_CAP);
3183         padctl_writel(padctl, priv->context.ss_port_map,
3184                 XUSB_PADCTL_SS_PORT_MAP);
3185
3186         list_for_each_entry(lane, &padctl->lanes, list) {
3187                 if (lane->pad->ops->iddq_enable)
3188                         tegra210_uphy_lane_iddq_enable(lane);
3189         }
3190
3191         padctl_writel(padctl, priv->context.usb3_pad_mux,
3192                 XUSB_PADCTL_USB3_PAD_MUX);
3193
3194         list_for_each_entry(lane, &padctl->lanes, list) {
3195                 if (lane->pad->ops->iddq_disable)
3196                         tegra210_uphy_lane_iddq_disable(lane);
3197         }
3198 }
3199
3200 static int tegra210_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl *padctl)
3201 {
3202         mutex_lock(&padctl->lock);
3203
3204         tegra210_uphy_deinit(padctl);
3205
3206         tegra210_xusb_padctl_save(padctl);
3207
3208         mutex_unlock(&padctl->lock);
3209         return 0;
3210 }
3211
3212 static int tegra210_xusb_padctl_resume_noirq(struct tegra_xusb_padctl *padctl)
3213 {
3214         mutex_lock(&padctl->lock);
3215
3216         tegra210_xusb_padctl_restore(padctl);
3217
3218         tegra210_uphy_init(padctl);
3219
3220         mutex_unlock(&padctl->lock);
3221         return 0;
3222 }
3223
3224 static const struct tegra_xusb_padctl_ops tegra210_xusb_padctl_ops = {
3225         .probe = tegra210_xusb_padctl_probe,
3226         .remove = tegra210_xusb_padctl_remove,
3227         .suspend_noirq = tegra210_xusb_padctl_suspend_noirq,
3228         .resume_noirq = tegra210_xusb_padctl_resume_noirq,
3229         .usb3_set_lfps_detect = tegra210_usb3_set_lfps_detect,
3230         .hsic_set_idle = tegra210_hsic_set_idle,
3231         .vbus_override = tegra210_xusb_padctl_vbus_override,
3232         .utmi_port_reset = tegra210_utmi_port_reset,
3233 };
3234
3235 static const char * const tegra210_xusb_padctl_supply_names[] = {
3236         "avdd-pll-utmip",
3237         "avdd-pll-uerefe",
3238         "dvdd-pex-pll",
3239         "hvdd-pex-pll-e",
3240 };
3241
3242 const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc = {
3243         .num_pads = ARRAY_SIZE(tegra210_pads),
3244         .pads = tegra210_pads,
3245         .ports = {
3246                 .usb2 = {
3247                         .ops = &tegra210_usb2_port_ops,
3248                         .count = 4,
3249                 },
3250                 .hsic = {
3251                         .ops = &tegra210_hsic_port_ops,
3252                         .count = 1,
3253                 },
3254                 .usb3 = {
3255                         .ops = &tegra210_usb3_port_ops,
3256                         .count = 4,
3257                 },
3258         },
3259         .ops = &tegra210_xusb_padctl_ops,
3260         .supply_names = tegra210_xusb_padctl_supply_names,
3261         .num_supplies = ARRAY_SIZE(tegra210_xusb_padctl_supply_names),
3262         .need_fake_usb3_port = true,
3263 };
3264 EXPORT_SYMBOL_GPL(tegra210_xusb_padctl_soc);
3265
3266 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
3267 MODULE_DESCRIPTION("NVIDIA Tegra 210 XUSB Pad Controller driver");
3268 MODULE_LICENSE("GPL v2");