1 // SPDX-License-Identifier: GPL-2.0
3 * STMicroelectronics STM32 USB PHY Controller driver
5 * Copyright (C) 2018 STMicroelectronics
6 * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
8 #include <linux/bitfield.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of_platform.h>
16 #include <linux/phy/phy.h>
17 #include <linux/reset.h>
19 #define STM32_USBPHYC_PLL 0x0
20 #define STM32_USBPHYC_MISC 0x8
21 #define STM32_USBPHYC_MONITOR(X) (0x108 + ((X) * 0x100))
22 #define STM32_USBPHYC_VERSION 0x3F4
24 /* STM32_USBPHYC_PLL bit fields */
25 #define PLLNDIV GENMASK(6, 0)
26 #define PLLFRACIN GENMASK(25, 10)
28 #define PLLSTRB BIT(27)
29 #define PLLSTRBYP BIT(28)
30 #define PLLFRACCTL BIT(29)
31 #define PLLDITHEN0 BIT(30)
32 #define PLLDITHEN1 BIT(31)
34 /* STM32_USBPHYC_MISC bit fields */
35 #define SWITHOST BIT(0)
37 /* STM32_USBPHYC_MONITOR bit fields */
38 #define STM32_USBPHYC_MON_OUT GENMASK(3, 0)
39 #define STM32_USBPHYC_MON_SEL GENMASK(8, 4)
40 #define STM32_USBPHYC_MON_SEL_LOCKP 0x1F
41 #define STM32_USBPHYC_MON_OUT_LOCKP BIT(3)
43 /* STM32_USBPHYC_VERSION bit fields */
44 #define MINREV GENMASK(3, 0)
45 #define MAJREV GENMASK(7, 4)
47 #define PLL_FVCO_MHZ 2880
48 #define PLL_INFF_MIN_RATE_HZ 19200000
49 #define PLL_INFF_MAX_RATE_HZ 38400000
50 #define HZ_PER_MHZ 1000000L
57 struct stm32_usbphyc_phy {
59 struct stm32_usbphyc *usbphyc;
64 struct stm32_usbphyc {
68 struct reset_control *rst;
69 struct stm32_usbphyc_phy **phys;
71 struct regulator *vdda1v1;
72 struct regulator *vdda1v8;
74 struct clk_hw clk48_hw;
78 static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
80 writel_relaxed(readl_relaxed(reg) | bits, reg);
83 static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
85 writel_relaxed(readl_relaxed(reg) & ~bits, reg);
88 static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc)
92 ret = regulator_enable(usbphyc->vdda1v1);
96 ret = regulator_enable(usbphyc->vdda1v8);
103 regulator_disable(usbphyc->vdda1v1);
108 static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc)
112 ret = regulator_disable(usbphyc->vdda1v8);
116 ret = regulator_disable(usbphyc->vdda1v1);
123 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
124 struct pll_params *pll_params)
126 unsigned long long fvco, ndiv, frac;
129 * | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1
132 * | NDIV = integer part of input bits to set the LDF
133 * |_FRACT = fractional part of input bits to set the LDF
134 * => PLLNDIV = integer part of (FVCO / (INFF*2))
135 * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
136 * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
138 fvco = (unsigned long long)PLL_FVCO_MHZ * HZ_PER_MHZ;
141 do_div(ndiv, (clk_rate * 2));
142 pll_params->ndiv = (u8)ndiv;
144 frac = fvco * (1 << 16);
145 do_div(frac, (clk_rate * 2));
146 frac = frac - (ndiv * (1 << 16));
147 pll_params->frac = (u16)frac;
150 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
152 struct pll_params pll_params;
153 u32 clk_rate = clk_get_rate(usbphyc->clk);
157 if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
158 (clk_rate > PLL_INFF_MAX_RATE_HZ)) {
159 dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
164 stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
165 ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
166 frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
168 usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
171 usbphyc_pll |= PLLFRACCTL | frac;
173 writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
175 dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
176 clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
177 FIELD_GET(PLLFRACIN, usbphyc_pll));
182 static int __stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
184 void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
187 stm32_usbphyc_clr_bits(pll_reg, PLLEN);
189 /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
190 if (readl_relaxed_poll_timeout(pll_reg, pllen, !(pllen & PLLEN), 5, 50))
191 dev_err(usbphyc->dev, "PLL not reset\n");
193 return stm32_usbphyc_regulators_disable(usbphyc);
196 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
198 /* Check if a phy port is still active or clk48 in use */
199 if (atomic_dec_return(&usbphyc->n_pll_cons) > 0)
202 return __stm32_usbphyc_pll_disable(usbphyc);
205 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
207 void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
208 bool pllen = readl_relaxed(pll_reg) & PLLEN;
212 * Check if a phy port or clk48 prepare has configured the pll
213 * and ensure the PLL is enabled
215 if (atomic_inc_return(&usbphyc->n_pll_cons) > 1 && pllen)
220 * PLL shouldn't be enabled without known consumer,
221 * disable it and reinit n_pll_cons
223 dev_warn(usbphyc->dev, "PLL enabled without known consumers\n");
225 ret = __stm32_usbphyc_pll_disable(usbphyc);
230 ret = stm32_usbphyc_regulators_enable(usbphyc);
234 ret = stm32_usbphyc_pll_init(usbphyc);
238 stm32_usbphyc_set_bits(pll_reg, PLLEN);
243 stm32_usbphyc_regulators_disable(usbphyc);
246 atomic_dec(&usbphyc->n_pll_cons);
251 static int stm32_usbphyc_phy_init(struct phy *phy)
253 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
254 struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
255 u32 reg_mon = STM32_USBPHYC_MONITOR(usbphyc_phy->index);
256 u32 monsel = FIELD_PREP(STM32_USBPHYC_MON_SEL,
257 STM32_USBPHYC_MON_SEL_LOCKP);
261 ret = stm32_usbphyc_pll_enable(usbphyc);
265 /* Check that PLL Lock input to PHY is High */
266 writel_relaxed(monsel, usbphyc->base + reg_mon);
267 ret = readl_relaxed_poll_timeout(usbphyc->base + reg_mon, monout,
268 (monout & STM32_USBPHYC_MON_OUT_LOCKP),
271 dev_err(usbphyc->dev, "PLL Lock input to PHY is Low (val=%x)\n",
272 (u32)(monout & STM32_USBPHYC_MON_OUT));
276 usbphyc_phy->active = true;
281 return stm32_usbphyc_pll_disable(usbphyc);
284 static int stm32_usbphyc_phy_exit(struct phy *phy)
286 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
287 struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
289 usbphyc_phy->active = false;
291 return stm32_usbphyc_pll_disable(usbphyc);
294 static const struct phy_ops stm32_usbphyc_phy_ops = {
295 .init = stm32_usbphyc_phy_init,
296 .exit = stm32_usbphyc_phy_exit,
297 .owner = THIS_MODULE,
300 static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
302 struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
304 return stm32_usbphyc_pll_enable(usbphyc);
307 static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
309 struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
311 stm32_usbphyc_pll_disable(usbphyc);
314 static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
319 static const struct clk_ops usbphyc_clk48_ops = {
320 .prepare = stm32_usbphyc_clk48_prepare,
321 .unprepare = stm32_usbphyc_clk48_unprepare,
322 .recalc_rate = stm32_usbphyc_clk48_recalc_rate,
325 static void stm32_usbphyc_clk48_unregister(void *data)
327 struct stm32_usbphyc *usbphyc = data;
329 of_clk_del_provider(usbphyc->dev->of_node);
330 clk_hw_unregister(&usbphyc->clk48_hw);
333 static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
335 struct device_node *node = usbphyc->dev->of_node;
336 struct clk_init_data init = { };
339 init.name = "ck_usbo_48m";
340 init.ops = &usbphyc_clk48_ops;
342 usbphyc->clk48_hw.init = &init;
344 ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
348 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &usbphyc->clk48_hw);
350 clk_hw_unregister(&usbphyc->clk48_hw);
355 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
359 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC,
362 stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
364 usbphyc->switch_setup = utmi_switch;
367 static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
368 struct of_phandle_args *args)
370 struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
371 struct stm32_usbphyc_phy *usbphyc_phy = NULL;
372 struct device_node *phynode = args->np;
375 for (port = 0; port < usbphyc->nphys; port++) {
376 if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
377 usbphyc_phy = usbphyc->phys[port];
382 dev_err(dev, "failed to find phy\n");
383 return ERR_PTR(-EINVAL);
386 if (((usbphyc_phy->index == 0) && (args->args_count != 0)) ||
387 ((usbphyc_phy->index == 1) && (args->args_count != 1))) {
388 dev_err(dev, "invalid number of cells for phy port%d\n",
390 return ERR_PTR(-EINVAL);
393 /* Configure the UTMI switch for PHY port#2 */
394 if (usbphyc_phy->index == 1) {
395 if (usbphyc->switch_setup < 0) {
396 stm32_usbphyc_switch_setup(usbphyc, args->args[0]);
398 if (args->args[0] != usbphyc->switch_setup) {
399 dev_err(dev, "phy port1 already used\n");
400 return ERR_PTR(-EBUSY);
405 return usbphyc_phy->phy;
408 static int stm32_usbphyc_probe(struct platform_device *pdev)
410 struct stm32_usbphyc *usbphyc;
411 struct device *dev = &pdev->dev;
412 struct device_node *child, *np = dev->of_node;
413 struct phy_provider *phy_provider;
417 usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
421 dev_set_drvdata(dev, usbphyc);
423 usbphyc->base = devm_platform_ioremap_resource(pdev, 0);
424 if (IS_ERR(usbphyc->base))
425 return PTR_ERR(usbphyc->base);
427 usbphyc->clk = devm_clk_get(dev, NULL);
428 if (IS_ERR(usbphyc->clk))
429 return dev_err_probe(dev, PTR_ERR(usbphyc->clk), "clk get_failed\n");
431 ret = clk_prepare_enable(usbphyc->clk);
433 dev_err(dev, "clk enable failed: %d\n", ret);
437 usbphyc->rst = devm_reset_control_get(dev, NULL);
438 if (!IS_ERR(usbphyc->rst)) {
439 reset_control_assert(usbphyc->rst);
441 reset_control_deassert(usbphyc->rst);
443 ret = PTR_ERR(usbphyc->rst);
444 if (ret == -EPROBE_DEFER)
447 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
451 * Wait for minimum width of powerdown pulse (ENABLE = Low):
452 * we have to ensure the PLL is disabled before phys initialization.
454 if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,
455 pllen, !(pllen & PLLEN), 5, 50)) {
456 dev_warn(usbphyc->dev, "PLL not reset\n");
461 usbphyc->switch_setup = -EINVAL;
462 usbphyc->nphys = of_get_child_count(np);
463 usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys,
464 sizeof(*usbphyc->phys), GFP_KERNEL);
465 if (!usbphyc->phys) {
470 usbphyc->vdda1v1 = devm_regulator_get(dev, "vdda1v1");
471 if (IS_ERR(usbphyc->vdda1v1)) {
472 ret = PTR_ERR(usbphyc->vdda1v1);
473 if (ret != -EPROBE_DEFER)
474 dev_err(dev, "failed to get vdda1v1 supply: %d\n", ret);
478 usbphyc->vdda1v8 = devm_regulator_get(dev, "vdda1v8");
479 if (IS_ERR(usbphyc->vdda1v8)) {
480 ret = PTR_ERR(usbphyc->vdda1v8);
481 if (ret != -EPROBE_DEFER)
482 dev_err(dev, "failed to get vdda1v8 supply: %d\n", ret);
486 for_each_child_of_node(np, child) {
487 struct stm32_usbphyc_phy *usbphyc_phy;
491 phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
494 if (ret != -EPROBE_DEFER)
495 dev_err(dev, "failed to create phy%d: %d\n",
500 usbphyc_phy = devm_kzalloc(dev, sizeof(*usbphyc_phy),
507 ret = of_property_read_u32(child, "reg", &index);
508 if (ret || index > usbphyc->nphys) {
509 dev_err(&phy->dev, "invalid reg property: %d\n", ret);
513 usbphyc->phys[port] = usbphyc_phy;
514 phy_set_bus_width(phy, 8);
515 phy_set_drvdata(phy, usbphyc_phy);
517 usbphyc->phys[port]->phy = phy;
518 usbphyc->phys[port]->usbphyc = usbphyc;
519 usbphyc->phys[port]->index = index;
520 usbphyc->phys[port]->active = false;
525 phy_provider = devm_of_phy_provider_register(dev,
526 stm32_usbphyc_of_xlate);
527 if (IS_ERR(phy_provider)) {
528 ret = PTR_ERR(phy_provider);
529 dev_err(dev, "failed to register phy provider: %d\n", ret);
533 ret = stm32_usbphyc_clk48_register(usbphyc);
535 dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret);
539 version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
540 dev_info(dev, "registered rev:%lu.%lu\n",
541 FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
548 clk_disable_unprepare(usbphyc->clk);
553 static int stm32_usbphyc_remove(struct platform_device *pdev)
555 struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
558 /* Ensure PHYs are not active, to allow PLL disabling */
559 for (port = 0; port < usbphyc->nphys; port++)
560 if (usbphyc->phys[port]->active)
561 stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
563 stm32_usbphyc_clk48_unregister(usbphyc);
565 clk_disable_unprepare(usbphyc->clk);
570 static const struct of_device_id stm32_usbphyc_of_match[] = {
571 { .compatible = "st,stm32mp1-usbphyc", },
574 MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);
576 static struct platform_driver stm32_usbphyc_driver = {
577 .probe = stm32_usbphyc_probe,
578 .remove = stm32_usbphyc_remove,
580 .of_match_table = stm32_usbphyc_of_match,
581 .name = "stm32-usbphyc",
584 module_platform_driver(stm32_usbphyc_driver);
586 MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver");
587 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
588 MODULE_LICENSE("GPL v2");