1 // SPDX-License-Identifier: GPL-2.0
3 * STMicroelectronics STM32 USB PHY Controller driver
5 * Copyright (C) 2018 STMicroelectronics
6 * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
8 #include <linux/bitfield.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of_platform.h>
16 #include <linux/phy/phy.h>
17 #include <linux/reset.h>
19 #define STM32_USBPHYC_PLL 0x0
20 #define STM32_USBPHYC_MISC 0x8
21 #define STM32_USBPHYC_MONITOR(X) (0x108 + ((X) * 0x100))
22 #define STM32_USBPHYC_VERSION 0x3F4
24 /* STM32_USBPHYC_PLL bit fields */
25 #define PLLNDIV GENMASK(6, 0)
26 #define PLLFRACIN GENMASK(25, 10)
28 #define PLLSTRB BIT(27)
29 #define PLLSTRBYP BIT(28)
30 #define PLLFRACCTL BIT(29)
31 #define PLLDITHEN0 BIT(30)
32 #define PLLDITHEN1 BIT(31)
34 /* STM32_USBPHYC_MISC bit fields */
35 #define SWITHOST BIT(0)
37 /* STM32_USBPHYC_MONITOR bit fields */
38 #define STM32_USBPHYC_MON_OUT GENMASK(3, 0)
39 #define STM32_USBPHYC_MON_SEL GENMASK(8, 4)
40 #define STM32_USBPHYC_MON_SEL_LOCKP 0x1F
41 #define STM32_USBPHYC_MON_OUT_LOCKP BIT(3)
43 /* STM32_USBPHYC_VERSION bit fields */
44 #define MINREV GENMASK(3, 0)
45 #define MAJREV GENMASK(7, 4)
47 #define PLL_FVCO_MHZ 2880
48 #define PLL_INFF_MIN_RATE_HZ 19200000
49 #define PLL_INFF_MAX_RATE_HZ 38400000
50 #define HZ_PER_MHZ 1000000L
57 struct stm32_usbphyc_phy {
59 struct stm32_usbphyc *usbphyc;
60 struct regulator *vbus;
65 struct stm32_usbphyc {
69 struct reset_control *rst;
70 struct stm32_usbphyc_phy **phys;
72 struct regulator *vdda1v1;
73 struct regulator *vdda1v8;
75 struct clk_hw clk48_hw;
79 static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
81 writel_relaxed(readl_relaxed(reg) | bits, reg);
84 static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
86 writel_relaxed(readl_relaxed(reg) & ~bits, reg);
89 static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc)
93 ret = regulator_enable(usbphyc->vdda1v1);
97 ret = regulator_enable(usbphyc->vdda1v8);
104 regulator_disable(usbphyc->vdda1v1);
109 static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc)
113 ret = regulator_disable(usbphyc->vdda1v8);
117 ret = regulator_disable(usbphyc->vdda1v1);
124 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
125 struct pll_params *pll_params)
127 unsigned long long fvco, ndiv, frac;
130 * | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1
133 * | NDIV = integer part of input bits to set the LDF
134 * |_FRACT = fractional part of input bits to set the LDF
135 * => PLLNDIV = integer part of (FVCO / (INFF*2))
136 * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
137 * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
139 fvco = (unsigned long long)PLL_FVCO_MHZ * HZ_PER_MHZ;
142 do_div(ndiv, (clk_rate * 2));
143 pll_params->ndiv = (u8)ndiv;
145 frac = fvco * (1 << 16);
146 do_div(frac, (clk_rate * 2));
147 frac = frac - (ndiv * (1 << 16));
148 pll_params->frac = (u16)frac;
151 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
153 struct pll_params pll_params;
154 u32 clk_rate = clk_get_rate(usbphyc->clk);
158 if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
159 (clk_rate > PLL_INFF_MAX_RATE_HZ)) {
160 dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
165 stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
166 ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
167 frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
169 usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
172 usbphyc_pll |= PLLFRACCTL | frac;
174 writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
176 dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
177 clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
178 FIELD_GET(PLLFRACIN, usbphyc_pll));
183 static int __stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
185 void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
188 stm32_usbphyc_clr_bits(pll_reg, PLLEN);
190 /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
191 if (readl_relaxed_poll_timeout(pll_reg, pllen, !(pllen & PLLEN), 5, 50))
192 dev_err(usbphyc->dev, "PLL not reset\n");
194 return stm32_usbphyc_regulators_disable(usbphyc);
197 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
199 /* Check if a phy port is still active or clk48 in use */
200 if (atomic_dec_return(&usbphyc->n_pll_cons) > 0)
203 return __stm32_usbphyc_pll_disable(usbphyc);
206 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
208 void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
209 bool pllen = readl_relaxed(pll_reg) & PLLEN;
213 * Check if a phy port or clk48 prepare has configured the pll
214 * and ensure the PLL is enabled
216 if (atomic_inc_return(&usbphyc->n_pll_cons) > 1 && pllen)
221 * PLL shouldn't be enabled without known consumer,
222 * disable it and reinit n_pll_cons
224 dev_warn(usbphyc->dev, "PLL enabled without known consumers\n");
226 ret = __stm32_usbphyc_pll_disable(usbphyc);
231 ret = stm32_usbphyc_regulators_enable(usbphyc);
235 ret = stm32_usbphyc_pll_init(usbphyc);
239 stm32_usbphyc_set_bits(pll_reg, PLLEN);
244 stm32_usbphyc_regulators_disable(usbphyc);
247 atomic_dec(&usbphyc->n_pll_cons);
252 static int stm32_usbphyc_phy_init(struct phy *phy)
254 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
255 struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
256 u32 reg_mon = STM32_USBPHYC_MONITOR(usbphyc_phy->index);
257 u32 monsel = FIELD_PREP(STM32_USBPHYC_MON_SEL,
258 STM32_USBPHYC_MON_SEL_LOCKP);
262 ret = stm32_usbphyc_pll_enable(usbphyc);
266 /* Check that PLL Lock input to PHY is High */
267 writel_relaxed(monsel, usbphyc->base + reg_mon);
268 ret = readl_relaxed_poll_timeout(usbphyc->base + reg_mon, monout,
269 (monout & STM32_USBPHYC_MON_OUT_LOCKP),
272 dev_err(usbphyc->dev, "PLL Lock input to PHY is Low (val=%x)\n",
273 (u32)(monout & STM32_USBPHYC_MON_OUT));
277 usbphyc_phy->active = true;
282 return stm32_usbphyc_pll_disable(usbphyc);
285 static int stm32_usbphyc_phy_exit(struct phy *phy)
287 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
288 struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
290 usbphyc_phy->active = false;
292 return stm32_usbphyc_pll_disable(usbphyc);
295 static int stm32_usbphyc_phy_power_on(struct phy *phy)
297 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
299 if (usbphyc_phy->vbus)
300 return regulator_enable(usbphyc_phy->vbus);
305 static int stm32_usbphyc_phy_power_off(struct phy *phy)
307 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
309 if (usbphyc_phy->vbus)
310 return regulator_disable(usbphyc_phy->vbus);
315 static const struct phy_ops stm32_usbphyc_phy_ops = {
316 .init = stm32_usbphyc_phy_init,
317 .exit = stm32_usbphyc_phy_exit,
318 .power_on = stm32_usbphyc_phy_power_on,
319 .power_off = stm32_usbphyc_phy_power_off,
320 .owner = THIS_MODULE,
323 static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
325 struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
327 return stm32_usbphyc_pll_enable(usbphyc);
330 static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
332 struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
334 stm32_usbphyc_pll_disable(usbphyc);
337 static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
342 static const struct clk_ops usbphyc_clk48_ops = {
343 .prepare = stm32_usbphyc_clk48_prepare,
344 .unprepare = stm32_usbphyc_clk48_unprepare,
345 .recalc_rate = stm32_usbphyc_clk48_recalc_rate,
348 static void stm32_usbphyc_clk48_unregister(void *data)
350 struct stm32_usbphyc *usbphyc = data;
352 of_clk_del_provider(usbphyc->dev->of_node);
353 clk_hw_unregister(&usbphyc->clk48_hw);
356 static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
358 struct device_node *node = usbphyc->dev->of_node;
359 struct clk_init_data init = { };
362 init.name = "ck_usbo_48m";
363 init.ops = &usbphyc_clk48_ops;
365 usbphyc->clk48_hw.init = &init;
367 ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
371 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &usbphyc->clk48_hw);
373 clk_hw_unregister(&usbphyc->clk48_hw);
378 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
382 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC,
385 stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
387 usbphyc->switch_setup = utmi_switch;
390 static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
391 struct of_phandle_args *args)
393 struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
394 struct stm32_usbphyc_phy *usbphyc_phy = NULL;
395 struct device_node *phynode = args->np;
398 for (port = 0; port < usbphyc->nphys; port++) {
399 if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
400 usbphyc_phy = usbphyc->phys[port];
405 dev_err(dev, "failed to find phy\n");
406 return ERR_PTR(-EINVAL);
409 if (((usbphyc_phy->index == 0) && (args->args_count != 0)) ||
410 ((usbphyc_phy->index == 1) && (args->args_count != 1))) {
411 dev_err(dev, "invalid number of cells for phy port%d\n",
413 return ERR_PTR(-EINVAL);
416 /* Configure the UTMI switch for PHY port#2 */
417 if (usbphyc_phy->index == 1) {
418 if (usbphyc->switch_setup < 0) {
419 stm32_usbphyc_switch_setup(usbphyc, args->args[0]);
421 if (args->args[0] != usbphyc->switch_setup) {
422 dev_err(dev, "phy port1 already used\n");
423 return ERR_PTR(-EBUSY);
428 return usbphyc_phy->phy;
431 static int stm32_usbphyc_probe(struct platform_device *pdev)
433 struct stm32_usbphyc *usbphyc;
434 struct device *dev = &pdev->dev;
435 struct device_node *child, *np = dev->of_node;
436 struct phy_provider *phy_provider;
440 usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
444 dev_set_drvdata(dev, usbphyc);
446 usbphyc->base = devm_platform_ioremap_resource(pdev, 0);
447 if (IS_ERR(usbphyc->base))
448 return PTR_ERR(usbphyc->base);
450 usbphyc->clk = devm_clk_get(dev, NULL);
451 if (IS_ERR(usbphyc->clk))
452 return dev_err_probe(dev, PTR_ERR(usbphyc->clk), "clk get_failed\n");
454 ret = clk_prepare_enable(usbphyc->clk);
456 dev_err(dev, "clk enable failed: %d\n", ret);
460 usbphyc->rst = devm_reset_control_get(dev, NULL);
461 if (!IS_ERR(usbphyc->rst)) {
462 reset_control_assert(usbphyc->rst);
464 reset_control_deassert(usbphyc->rst);
466 ret = PTR_ERR(usbphyc->rst);
467 if (ret == -EPROBE_DEFER)
470 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
474 * Wait for minimum width of powerdown pulse (ENABLE = Low):
475 * we have to ensure the PLL is disabled before phys initialization.
477 if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,
478 pllen, !(pllen & PLLEN), 5, 50)) {
479 dev_warn(usbphyc->dev, "PLL not reset\n");
484 usbphyc->switch_setup = -EINVAL;
485 usbphyc->nphys = of_get_child_count(np);
486 usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys,
487 sizeof(*usbphyc->phys), GFP_KERNEL);
488 if (!usbphyc->phys) {
493 usbphyc->vdda1v1 = devm_regulator_get(dev, "vdda1v1");
494 if (IS_ERR(usbphyc->vdda1v1)) {
495 ret = PTR_ERR(usbphyc->vdda1v1);
496 if (ret != -EPROBE_DEFER)
497 dev_err(dev, "failed to get vdda1v1 supply: %d\n", ret);
501 usbphyc->vdda1v8 = devm_regulator_get(dev, "vdda1v8");
502 if (IS_ERR(usbphyc->vdda1v8)) {
503 ret = PTR_ERR(usbphyc->vdda1v8);
504 if (ret != -EPROBE_DEFER)
505 dev_err(dev, "failed to get vdda1v8 supply: %d\n", ret);
509 for_each_child_of_node(np, child) {
510 struct stm32_usbphyc_phy *usbphyc_phy;
514 phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
517 if (ret != -EPROBE_DEFER)
518 dev_err(dev, "failed to create phy%d: %d\n",
523 usbphyc_phy = devm_kzalloc(dev, sizeof(*usbphyc_phy),
530 ret = of_property_read_u32(child, "reg", &index);
531 if (ret || index > usbphyc->nphys) {
532 dev_err(&phy->dev, "invalid reg property: %d\n", ret);
536 usbphyc->phys[port] = usbphyc_phy;
537 phy_set_bus_width(phy, 8);
538 phy_set_drvdata(phy, usbphyc_phy);
540 usbphyc->phys[port]->phy = phy;
541 usbphyc->phys[port]->usbphyc = usbphyc;
542 usbphyc->phys[port]->index = index;
543 usbphyc->phys[port]->active = false;
545 usbphyc->phys[port]->vbus = devm_regulator_get_optional(&phy->dev, "vbus");
546 if (IS_ERR(usbphyc->phys[port]->vbus)) {
547 ret = PTR_ERR(usbphyc->phys[port]->vbus);
548 if (ret == -EPROBE_DEFER)
550 usbphyc->phys[port]->vbus = NULL;
556 phy_provider = devm_of_phy_provider_register(dev,
557 stm32_usbphyc_of_xlate);
558 if (IS_ERR(phy_provider)) {
559 ret = PTR_ERR(phy_provider);
560 dev_err(dev, "failed to register phy provider: %d\n", ret);
564 ret = stm32_usbphyc_clk48_register(usbphyc);
566 dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret);
570 version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
571 dev_info(dev, "registered rev:%lu.%lu\n",
572 FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
579 clk_disable_unprepare(usbphyc->clk);
584 static int stm32_usbphyc_remove(struct platform_device *pdev)
586 struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
589 /* Ensure PHYs are not active, to allow PLL disabling */
590 for (port = 0; port < usbphyc->nphys; port++)
591 if (usbphyc->phys[port]->active)
592 stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
594 stm32_usbphyc_clk48_unregister(usbphyc);
596 clk_disable_unprepare(usbphyc->clk);
601 static const struct of_device_id stm32_usbphyc_of_match[] = {
602 { .compatible = "st,stm32mp1-usbphyc", },
605 MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);
607 static struct platform_driver stm32_usbphyc_driver = {
608 .probe = stm32_usbphyc_probe,
609 .remove = stm32_usbphyc_remove,
611 .of_match_table = stm32_usbphyc_of_match,
612 .name = "stm32-usbphyc",
615 module_platform_driver(stm32_usbphyc_driver);
617 MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver");
618 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
619 MODULE_LICENSE("GPL v2");