ubifs: Fix memory leak from c->sup_node
[linux-2.6-microblaze.git] / drivers / phy / qualcomm / phy-qcom-ufs-qmp-14nm.h
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
4  */
5
6 #ifndef UFS_QCOM_PHY_QMP_14NM_H_
7 #define UFS_QCOM_PHY_QMP_14NM_H_
8
9 #include "phy-qcom-ufs-i.h"
10
11 /* QCOM UFS PHY control registers */
12 #define COM_OFF(x)      (0x000 + x)
13 #define PHY_OFF(x)      (0xC00 + x)
14 #define TX_OFF(n, x)    (0x400 + (0x400 * n) + x)
15 #define RX_OFF(n, x)    (0x600 + (0x400 * n) + x)
16
17 /* UFS PHY QSERDES COM registers */
18 #define QSERDES_COM_BG_TIMER                    COM_OFF(0x0C)
19 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN         COM_OFF(0x34)
20 #define QSERDES_COM_SYS_CLK_CTRL                COM_OFF(0x3C)
21 #define QSERDES_COM_LOCK_CMP1_MODE0             COM_OFF(0x4C)
22 #define QSERDES_COM_LOCK_CMP2_MODE0             COM_OFF(0x50)
23 #define QSERDES_COM_LOCK_CMP3_MODE0             COM_OFF(0x54)
24 #define QSERDES_COM_LOCK_CMP1_MODE1             COM_OFF(0x58)
25 #define QSERDES_COM_LOCK_CMP2_MODE1             COM_OFF(0x5C)
26 #define QSERDES_COM_LOCK_CMP3_MODE1             COM_OFF(0x60)
27 #define QSERDES_COM_CP_CTRL_MODE0               COM_OFF(0x78)
28 #define QSERDES_COM_CP_CTRL_MODE1               COM_OFF(0x7C)
29 #define QSERDES_COM_PLL_RCTRL_MODE0             COM_OFF(0x84)
30 #define QSERDES_COM_PLL_RCTRL_MODE1             COM_OFF(0x88)
31 #define QSERDES_COM_PLL_CCTRL_MODE0             COM_OFF(0x90)
32 #define QSERDES_COM_PLL_CCTRL_MODE1             COM_OFF(0x94)
33 #define QSERDES_COM_SYSCLK_EN_SEL               COM_OFF(0xAC)
34 #define QSERDES_COM_RESETSM_CNTRL               COM_OFF(0xB4)
35 #define QSERDES_COM_LOCK_CMP_EN                 COM_OFF(0xC8)
36 #define QSERDES_COM_LOCK_CMP_CFG                COM_OFF(0xCC)
37 #define QSERDES_COM_DEC_START_MODE0             COM_OFF(0xD0)
38 #define QSERDES_COM_DEC_START_MODE1             COM_OFF(0xD4)
39 #define QSERDES_COM_DIV_FRAC_START1_MODE0       COM_OFF(0xDC)
40 #define QSERDES_COM_DIV_FRAC_START2_MODE0       COM_OFF(0xE0)
41 #define QSERDES_COM_DIV_FRAC_START3_MODE0       COM_OFF(0xE4)
42 #define QSERDES_COM_DIV_FRAC_START1_MODE1       COM_OFF(0xE8)
43 #define QSERDES_COM_DIV_FRAC_START2_MODE1       COM_OFF(0xEC)
44 #define QSERDES_COM_DIV_FRAC_START3_MODE1       COM_OFF(0xF0)
45 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0       COM_OFF(0x108)
46 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0       COM_OFF(0x10C)
47 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1       COM_OFF(0x110)
48 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1       COM_OFF(0x114)
49 #define QSERDES_COM_VCO_TUNE_CTRL               COM_OFF(0x124)
50 #define QSERDES_COM_VCO_TUNE_MAP                COM_OFF(0x128)
51 #define QSERDES_COM_VCO_TUNE1_MODE0             COM_OFF(0x12C)
52 #define QSERDES_COM_VCO_TUNE2_MODE0             COM_OFF(0x130)
53 #define QSERDES_COM_VCO_TUNE1_MODE1             COM_OFF(0x134)
54 #define QSERDES_COM_VCO_TUNE2_MODE1             COM_OFF(0x138)
55 #define QSERDES_COM_VCO_TUNE_TIMER1             COM_OFF(0x144)
56 #define QSERDES_COM_VCO_TUNE_TIMER2             COM_OFF(0x148)
57 #define QSERDES_COM_CLK_SELECT                  COM_OFF(0x174)
58 #define QSERDES_COM_HSCLK_SEL                   COM_OFF(0x178)
59 #define QSERDES_COM_CORECLK_DIV                 COM_OFF(0x184)
60 #define QSERDES_COM_CORE_CLK_EN                 COM_OFF(0x18C)
61 #define QSERDES_COM_CMN_CONFIG                  COM_OFF(0x194)
62 #define QSERDES_COM_SVS_MODE_CLK_SEL            COM_OFF(0x19C)
63 #define QSERDES_COM_CORECLK_DIV_MODE1           COM_OFF(0x1BC)
64
65 /* UFS PHY registers */
66 #define UFS_PHY_PHY_START                       PHY_OFF(0x00)
67 #define UFS_PHY_POWER_DOWN_CONTROL              PHY_OFF(0x04)
68 #define UFS_PHY_PCS_READY_STATUS                PHY_OFF(0x168)
69
70 /* UFS PHY TX registers */
71 #define QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN       TX_OFF(0, 0x68)
72 #define QSERDES_TX_LANE_MODE                            TX_OFF(0, 0x94)
73
74 /* UFS PHY RX registers */
75 #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN        RX_OFF(0, 0x40)
76 #define QSERDES_RX_RX_TERM_BW                   RX_OFF(0, 0x90)
77 #define QSERDES_RX_RX_EQ_GAIN1_LSB              RX_OFF(0, 0xC4)
78 #define QSERDES_RX_RX_EQ_GAIN1_MSB              RX_OFF(0, 0xC8)
79 #define QSERDES_RX_RX_EQ_GAIN2_LSB              RX_OFF(0, 0xCC)
80 #define QSERDES_RX_RX_EQ_GAIN2_MSB              RX_OFF(0, 0xD0)
81 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2        RX_OFF(0, 0xD8)
82 #define QSERDES_RX_SIGDET_CNTRL                 RX_OFF(0, 0x114)
83 #define QSERDES_RX_SIGDET_LVL                   RX_OFF(0, 0x118)
84 #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL        RX_OFF(0, 0x11C)
85 #define QSERDES_RX_RX_INTERFACE_MODE            RX_OFF(0, 0x12C)
86
87 /*
88  * This structure represents the 14nm specific phy.
89  * common_cfg MUST remain the first field in this structure
90  * in case extra fields are added. This way, when calling
91  * get_ufs_qcom_phy() of generic phy, we can extract the
92  * common phy structure (struct ufs_qcom_phy) out of it
93  * regardless of the relevant specific phy.
94  */
95 struct ufs_qcom_phy_qmp_14nm {
96         struct ufs_qcom_phy common_cfg;
97 };
98
99 static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = {
100         UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
101         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x0e),
102         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
103         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30),
104         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x06),
105         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
106         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0a),
107         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x05),
108         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV, 0x0a),
109         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
110         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
111         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
112         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20),
113         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00),
114         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_CFG, 0x00),
115         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
116         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
117         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x14),
118         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
119         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
120         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
121         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
122         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
123         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
124         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
125         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
126         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
127         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
128         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
129         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
130         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
131         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
132         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
133         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
134         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
135         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
136         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
137         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
138         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
139         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
140         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
141         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
142         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
143         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
144         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
145         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
146         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
147
148         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN, 0x45),
149         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE, 0x02),
150
151         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_LVL, 0x24),
152         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL, 0x02),
153         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
154         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
155         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
156         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_BW, 0x5B),
157         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
158         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
159         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
160         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0F),
161         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
162 };
163
164 static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
165         UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x54),
166 };
167
168 #endif