drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c

   1 /*
   2  * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include "phy-qcom-ufs-qmp-14nm.h"
  16
  17 #define UFS_PHY_NAME "ufs_phy_qmp_14nm"
  18 #define UFS_PHY_VDDA_PHY_UV     (925000)
  19
  20 static
  21 int ufs_qcom_phy_qmp_14nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
  22                                         bool is_rate_B)
  23 {
  24         int tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A);
  25         int tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
  26         int err;
  27
  28         err = ufs_qcom_phy_calibrate(ufs_qcom_phy, phy_cal_table_rate_A,
  29                 tbl_size_A, phy_cal_table_rate_B, tbl_size_B, is_rate_B);
  30
  31         if (err)
  32                 dev_err(ufs_qcom_phy->dev,
  33                         "%s: ufs_qcom_phy_calibrate() failed %d\n",
  34                         __func__, err);
  35         return err;
  36 }
  37
  38 static
  39 void ufs_qcom_phy_qmp_14nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
  40 {
  41         phy_common->quirks =
  42                 UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
  43 }
  44
  45 static int ufs_qcom_phy_qmp_14nm_init(struct phy *generic_phy)
  46 {
  47         struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
  48         bool is_rate_B = false;
  49         int ret;
  50
  51         ret = ufs_qcom_phy_get_reset(phy_common);
  52         if (ret)
  53                 return ret;
  54
  55         ret = reset_control_assert(phy_common->ufs_reset);
  56         if (ret)
  57                 return ret;
  58
  59         if (phy_common->mode == PHY_MODE_UFS_HS_B)
  60                 is_rate_B = true;
  61
  62         ret = ufs_qcom_phy_qmp_14nm_phy_calibrate(phy_common, is_rate_B);
  63         if (!ret)
  64                 /* phy calibrated, but yet to be started */
  65                 phy_common->is_started = false;
  66
  67         return ret;
  68 }
  69
  70 static int ufs_qcom_phy_qmp_14nm_exit(struct phy *generic_phy)
  71 {
  72         return 0;
  73 }
  74
  75 static
  76 int ufs_qcom_phy_qmp_14nm_set_mode(struct phy *generic_phy,
  77                                    enum phy_mode mode, int submode)
  78 {
  79         struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
  80
  81         phy_common->mode = PHY_MODE_INVALID;
  82
  83         if (mode > 0)
  84                 phy_common->mode = mode;
  85
  86         return 0;
  87 }
  88
  89 static
  90 void ufs_qcom_phy_qmp_14nm_power_control(struct ufs_qcom_phy *phy, bool val)
  91 {
  92         writel_relaxed(val ? 0x1 : 0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
  93         /*
  94          * Before any transactions involving PHY, ensure PHY knows
  95          * that it's analog rail is powered ON (or OFF).
  96          */
  97         mb();
  98 }
  99
 100 static inline
 101 void ufs_qcom_phy_qmp_14nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
 102 {
 103         /*
 104          * 14nm PHY does not have TX_LANE_ENABLE register.
 105          * Implement this function so as not to propagate error to caller.
 106          */
 107 }
 108
 109 static inline void ufs_qcom_phy_qmp_14nm_start_serdes(struct ufs_qcom_phy *phy)
 110 {
 111         u32 tmp;
 112
 113         tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
 114         tmp &= ~MASK_SERDES_START;
 115         tmp |= (1 << OFFSET_SERDES_START);
 116         writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
 117         /* Ensure register value is committed */
 118         mb();
 119 }
 120
 121 static int ufs_qcom_phy_qmp_14nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
 122 {
 123         int err = 0;
 124         u32 val;
 125
 126         err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
 127                 val, (val & MASK_PCS_READY), 10, 1000000);
 128         if (err)
 129                 dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
 130                         __func__, err);
 131         return err;
 132 }
 133
 134 static const struct phy_ops ufs_qcom_phy_qmp_14nm_phy_ops = {
 135         .init           = ufs_qcom_phy_qmp_14nm_init,
 136         .exit           = ufs_qcom_phy_qmp_14nm_exit,
 137         .power_on       = ufs_qcom_phy_power_on,
 138         .power_off      = ufs_qcom_phy_power_off,
 139         .set_mode       = ufs_qcom_phy_qmp_14nm_set_mode,
 140         .owner          = THIS_MODULE,
 141 };
 142
 143 static struct ufs_qcom_phy_specific_ops phy_14nm_ops = {
 144         .start_serdes           = ufs_qcom_phy_qmp_14nm_start_serdes,
 145         .is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_14nm_is_pcs_ready,
 146         .set_tx_lane_enable     = ufs_qcom_phy_qmp_14nm_set_tx_lane_enable,
 147         .power_control          = ufs_qcom_phy_qmp_14nm_power_control,
 148 };
 149
 150 static int ufs_qcom_phy_qmp_14nm_probe(struct platform_device *pdev)
 151 {
 152         struct device *dev = &pdev->dev;
 153         struct phy *generic_phy;
 154         struct ufs_qcom_phy_qmp_14nm *phy;
 155         struct ufs_qcom_phy *phy_common;
 156         int err = 0;
 157
 158         phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
 159         if (!phy) {
 160                 err = -ENOMEM;
 161                 goto out;
 162         }
 163         phy_common = &phy->common_cfg;
 164
 165         generic_phy = ufs_qcom_phy_generic_probe(pdev, phy_common,
 166                                 &ufs_qcom_phy_qmp_14nm_phy_ops, &phy_14nm_ops);
 167
 168         if (!generic_phy) {
 169                 err = -EIO;
 170                 goto out;
 171         }
 172
 173         err = ufs_qcom_phy_init_clks(phy_common);
 174         if (err)
 175                 goto out;
 176
 177         err = ufs_qcom_phy_init_vregulators(phy_common);
 178         if (err)
 179                 goto out;
 180
 181         phy_common->vdda_phy.max_uV = UFS_PHY_VDDA_PHY_UV;
 182         phy_common->vdda_phy.min_uV = UFS_PHY_VDDA_PHY_UV;
 183
 184         ufs_qcom_phy_qmp_14nm_advertise_quirks(phy_common);
 185
 186         phy_set_drvdata(generic_phy, phy);
 187
 188         strlcpy(phy_common->name, UFS_PHY_NAME, sizeof(phy_common->name));
 189
 190 out:
 191         return err;
 192 }
 193
 194 static const struct of_device_id ufs_qcom_phy_qmp_14nm_of_match[] = {
 195         {.compatible = "qcom,ufs-phy-qmp-14nm"},
 196         {.compatible = "qcom,msm8996-ufs-phy-qmp-14nm"},
 197         {},
 198 };
 199 MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_14nm_of_match);
 200
 201 static struct platform_driver ufs_qcom_phy_qmp_14nm_driver = {
 202         .probe = ufs_qcom_phy_qmp_14nm_probe,
 203         .driver = {
 204                 .of_match_table = ufs_qcom_phy_qmp_14nm_of_match,
 205                 .name = "ufs_qcom_phy_qmp_14nm",
 206         },
 207 };
 208
 209 module_platform_driver(ufs_qcom_phy_qmp_14nm_driver);
 210
 211 MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 14nm");
 212 MODULE_LICENSE("GPL v2");