drivers/phy/qualcomm/phy-qcom-qusb2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/delay.h>
   8 #include <linux/err.h>
   9 #include <linux/io.h>
  10 #include <linux/kernel.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/module.h>
  13 #include <linux/nvmem-consumer.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regmap.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/reset.h>
  21 #include <linux/slab.h>
  22
  23 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  24
  25 #define QUSB2PHY_PLL                    0x0
  26 #define QUSB2PHY_PLL_TEST               0x04
  27 #define CLK_REF_SEL                     BIT(7)
  28
  29 #define QUSB2PHY_PLL_TUNE               0x08
  30 #define QUSB2PHY_PLL_USER_CTL1          0x0c
  31 #define QUSB2PHY_PLL_USER_CTL2          0x10
  32 #define QUSB2PHY_PLL_AUTOPGM_CTL1       0x1c
  33 #define QUSB2PHY_PLL_PWR_CTRL           0x18
  34
  35 /* QUSB2PHY_PLL_STATUS register bits */
  36 #define PLL_LOCKED                      BIT(5)
  37
  38 /* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */
  39 #define CORE_READY_STATUS               BIT(0)
  40
  41 /* QUSB2PHY_PORT_POWERDOWN register bits */
  42 #define CLAMP_N_EN                      BIT(5)
  43 #define FREEZIO_N                       BIT(1)
  44 #define POWER_DOWN                      BIT(0)
  45
  46 /* QUSB2PHY_PWR_CTRL1 register bits */
  47 #define PWR_CTRL1_VREF_SUPPLY_TRIM      BIT(5)
  48 #define PWR_CTRL1_CLAMP_N_EN            BIT(1)
  49
  50 #define QUSB2PHY_REFCLK_ENABLE          BIT(0)
  51
  52 #define PHY_CLK_SCHEME_SEL              BIT(0)
  53
  54 /* QUSB2PHY_INTR_CTRL register bits */
  55 #define DMSE_INTR_HIGH_SEL                      BIT(4)
  56 #define DPSE_INTR_HIGH_SEL                      BIT(3)
  57 #define CHG_DET_INTR_EN                         BIT(2)
  58 #define DMSE_INTR_EN                            BIT(1)
  59 #define DPSE_INTR_EN                            BIT(0)
  60
  61 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */
  62 #define CORE_PLL_EN_FROM_RESET                  BIT(4)
  63 #define CORE_RESET                              BIT(5)
  64 #define CORE_RESET_MUX                          BIT(6)
  65
  66 /* QUSB2PHY_IMP_CTRL1 register bits */
  67 #define IMP_RES_OFFSET_MASK                     GENMASK(5, 0)
  68 #define IMP_RES_OFFSET_SHIFT                    0x0
  69
  70 /* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */
  71 #define BIAS_CTRL2_RES_OFFSET_MASK              GENMASK(5, 0)
  72 #define BIAS_CTRL2_RES_OFFSET_SHIFT             0x0
  73
  74 /* QUSB2PHY_CHG_CONTROL_2 register bits */
  75 #define CHG_CTRL2_OFFSET_MASK                   GENMASK(5, 4)
  76 #define CHG_CTRL2_OFFSET_SHIFT                  0x4
  77
  78 /* QUSB2PHY_PORT_TUNE1 register bits */
  79 #define HSTX_TRIM_MASK                          GENMASK(7, 4)
  80 #define HSTX_TRIM_SHIFT                         0x4
  81 #define PREEMPH_WIDTH_HALF_BIT                  BIT(2)
  82 #define PREEMPHASIS_EN_MASK                     GENMASK(1, 0)
  83 #define PREEMPHASIS_EN_SHIFT                    0x0
  84
  85 /* QUSB2PHY_PORT_TUNE2 register bits */
  86 #define HSDISC_TRIM_MASK                        GENMASK(1, 0)
  87 #define HSDISC_TRIM_SHIFT                       0x0
  88
  89 #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO        0x04
  90 #define QUSB2PHY_PLL_CLOCK_INVERTERS            0x18c
  91 #define QUSB2PHY_PLL_CMODE                      0x2c
  92 #define QUSB2PHY_PLL_LOCK_DELAY                 0x184
  93 #define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO         0xb4
  94 #define QUSB2PHY_PLL_BIAS_CONTROL_1             0x194
  95 #define QUSB2PHY_PLL_BIAS_CONTROL_2             0x198
  96 #define QUSB2PHY_PWR_CTRL2                      0x214
  97 #define QUSB2PHY_IMP_CTRL1                      0x220
  98 #define QUSB2PHY_IMP_CTRL2                      0x224
  99 #define QUSB2PHY_CHG_CTRL2                      0x23c
 100
 101 struct qusb2_phy_init_tbl {
 102         unsigned int offset;
 103         unsigned int val;
 104         /*
 105          * register part of layout ?
 106          * if yes, then offset gives index in the reg-layout
 107          */
 108         int in_layout;
 109 };
 110
 111 #define QUSB2_PHY_INIT_CFG(o, v) \
 112         {                       \
 113                 .offset = o,    \
 114                 .val = v,       \
 115         }
 116
 117 #define QUSB2_PHY_INIT_CFG_L(o, v) \
 118         {                       \
 119                 .offset = o,    \
 120                 .val = v,       \
 121                 .in_layout = 1, \
 122         }
 123
 124 /* set of registers with offsets different per-PHY */
 125 enum qusb2phy_reg_layout {
 126         QUSB2PHY_PLL_CORE_INPUT_OVERRIDE,
 127         QUSB2PHY_PLL_STATUS,
 128         QUSB2PHY_PORT_TUNE1,
 129         QUSB2PHY_PORT_TUNE2,
 130         QUSB2PHY_PORT_TUNE3,
 131         QUSB2PHY_PORT_TUNE4,
 132         QUSB2PHY_PORT_TUNE5,
 133         QUSB2PHY_PORT_TEST1,
 134         QUSB2PHY_PORT_TEST2,
 135         QUSB2PHY_PORT_POWERDOWN,
 136         QUSB2PHY_INTR_CTRL,
 137 };
 138
 139 static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = {
 140         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14),
 141         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xF8),
 142         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xB3),
 143         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
 144         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xC0),
 145         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
 146         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
 147         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
 148         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00),
 149         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
 150         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
 151         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80),
 152         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F),
 153 };
 154
 155 static const unsigned int ipq6018_regs_layout[] = {
 156         [QUSB2PHY_PLL_STATUS]              = 0x38,
 157         [QUSB2PHY_PORT_TUNE1]              = 0x80,
 158         [QUSB2PHY_PORT_TUNE2]              = 0x84,
 159         [QUSB2PHY_PORT_TUNE3]              = 0x88,
 160         [QUSB2PHY_PORT_TUNE4]              = 0x8C,
 161         [QUSB2PHY_PORT_TUNE5]              = 0x90,
 162         [QUSB2PHY_PORT_TEST1]              = 0x98,
 163         [QUSB2PHY_PORT_TEST2]              = 0x9C,
 164         [QUSB2PHY_PORT_POWERDOWN]          = 0xB4,
 165         [QUSB2PHY_INTR_CTRL]               = 0xBC,
 166 };
 167
 168 static const unsigned int msm8996_regs_layout[] = {
 169         [QUSB2PHY_PLL_STATUS]           = 0x38,
 170         [QUSB2PHY_PORT_TUNE1]           = 0x80,
 171         [QUSB2PHY_PORT_TUNE2]           = 0x84,
 172         [QUSB2PHY_PORT_TUNE3]           = 0x88,
 173         [QUSB2PHY_PORT_TUNE4]           = 0x8c,
 174         [QUSB2PHY_PORT_TUNE5]           = 0x90,
 175         [QUSB2PHY_PORT_TEST1]           = 0xb8,
 176         [QUSB2PHY_PORT_TEST2]           = 0x9c,
 177         [QUSB2PHY_PORT_POWERDOWN]       = 0xb4,
 178         [QUSB2PHY_INTR_CTRL]            = 0xbc,
 179 };
 180
 181 static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
 182         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
 183         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
 184         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
 185         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
 186
 187         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
 188         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
 189         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
 190
 191         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
 192
 193         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
 194         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
 195 };
 196
 197 static const unsigned int msm8998_regs_layout[] = {
 198         [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
 199         [QUSB2PHY_PLL_STATUS]              = 0x1a0,
 200         [QUSB2PHY_PORT_TUNE1]              = 0x23c,
 201         [QUSB2PHY_PORT_TUNE2]              = 0x240,
 202         [QUSB2PHY_PORT_TUNE3]              = 0x244,
 203         [QUSB2PHY_PORT_TUNE4]              = 0x248,
 204         [QUSB2PHY_PORT_TEST1]              = 0x24c,
 205         [QUSB2PHY_PORT_TEST2]              = 0x250,
 206         [QUSB2PHY_PORT_POWERDOWN]          = 0x210,
 207         [QUSB2PHY_INTR_CTRL]               = 0x22c,
 208 };
 209
 210 static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = {
 211         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x13),
 212         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
 213         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
 214         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
 215
 216         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xa5),
 217         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x09),
 218
 219         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
 220 };
 221
 222 static const struct qusb2_phy_init_tbl sm6115_init_tbl[] = {
 223         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
 224         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x53),
 225         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x81),
 226         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x17),
 227
 228         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
 229         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
 230         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
 231
 232         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
 233
 234         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
 235         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
 236 };
 237
 238 static const unsigned int qusb2_v2_regs_layout[] = {
 239         [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
 240         [QUSB2PHY_PLL_STATUS]           = 0x1a0,
 241         [QUSB2PHY_PORT_TUNE1]           = 0x240,
 242         [QUSB2PHY_PORT_TUNE2]           = 0x244,
 243         [QUSB2PHY_PORT_TUNE3]           = 0x248,
 244         [QUSB2PHY_PORT_TUNE4]           = 0x24c,
 245         [QUSB2PHY_PORT_TUNE5]           = 0x250,
 246         [QUSB2PHY_PORT_TEST1]           = 0x254,
 247         [QUSB2PHY_PORT_TEST2]           = 0x258,
 248         [QUSB2PHY_PORT_POWERDOWN]       = 0x210,
 249         [QUSB2PHY_INTR_CTRL]            = 0x230,
 250 };
 251
 252 static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
 253         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
 254         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
 255         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
 256         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
 257         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
 258         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40),
 259         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20),
 260         QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21),
 261         QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0),
 262         QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58),
 263
 264         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30),
 265         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29),
 266         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca),
 267         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04),
 268         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03),
 269
 270         QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0),
 271 };
 272
 273 struct qusb2_phy_cfg {
 274         const struct qusb2_phy_init_tbl *tbl;
 275         /* number of entries in the table */
 276         unsigned int tbl_num;
 277         /* offset to PHY_CLK_SCHEME register in TCSR map */
 278         unsigned int clk_scheme_offset;
 279
 280         /* array of registers with different offsets */
 281         const unsigned int *regs;
 282         unsigned int mask_core_ready;
 283         unsigned int disable_ctrl;
 284         unsigned int autoresume_en;
 285
 286         /* true if PHY has PLL_TEST register to select clk_scheme */
 287         bool has_pll_test;
 288
 289         /* true if TUNE1 register must be updated by fused value, else TUNE2 */
 290         bool update_tune1_with_efuse;
 291
 292         /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
 293         bool has_pll_override;
 294
 295         /* true if PHY default clk scheme is single-ended */
 296         bool se_clk_scheme_default;
 297 };
 298
 299 static const struct qusb2_phy_cfg msm8996_phy_cfg = {
 300         .tbl            = msm8996_init_tbl,
 301         .tbl_num        = ARRAY_SIZE(msm8996_init_tbl),
 302         .regs           = msm8996_regs_layout,
 303
 304         .has_pll_test   = true,
 305         .se_clk_scheme_default = true,
 306         .disable_ctrl   = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
 307         .mask_core_ready = PLL_LOCKED,
 308         .autoresume_en   = BIT(3),
 309 };
 310
 311 static const struct qusb2_phy_cfg msm8998_phy_cfg = {
 312         .tbl            = msm8998_init_tbl,
 313         .tbl_num        = ARRAY_SIZE(msm8998_init_tbl),
 314         .regs           = msm8998_regs_layout,
 315
 316         .disable_ctrl   = POWER_DOWN,
 317         .mask_core_ready = CORE_READY_STATUS,
 318         .has_pll_override = true,
 319         .se_clk_scheme_default = true,
 320         .autoresume_en   = BIT(0),
 321         .update_tune1_with_efuse = true,
 322 };
 323
 324 static const struct qusb2_phy_cfg ipq6018_phy_cfg = {
 325         .tbl            = ipq6018_init_tbl,
 326         .tbl_num        = ARRAY_SIZE(ipq6018_init_tbl),
 327         .regs           = ipq6018_regs_layout,
 328
 329         .disable_ctrl   = POWER_DOWN,
 330         .mask_core_ready = PLL_LOCKED,
 331         /* autoresume not used */
 332         .autoresume_en   = BIT(0),
 333 };
 334
 335 static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
 336         .tbl            = qusb2_v2_init_tbl,
 337         .tbl_num        = ARRAY_SIZE(qusb2_v2_init_tbl),
 338         .regs           = qusb2_v2_regs_layout,
 339
 340         .disable_ctrl   = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN |
 341                            POWER_DOWN),
 342         .mask_core_ready = CORE_READY_STATUS,
 343         .has_pll_override = true,
 344         .se_clk_scheme_default = true,
 345         .autoresume_en    = BIT(0),
 346         .update_tune1_with_efuse = true,
 347 };
 348
 349 static const struct qusb2_phy_cfg sdm660_phy_cfg = {
 350         .tbl            = msm8996_init_tbl,
 351         .tbl_num        = ARRAY_SIZE(msm8996_init_tbl),
 352         .regs           = msm8996_regs_layout,
 353
 354         .has_pll_test   = true,
 355         .se_clk_scheme_default = false,
 356         .disable_ctrl   = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
 357         .mask_core_ready = PLL_LOCKED,
 358         .autoresume_en   = BIT(3),
 359 };
 360
 361 static const struct qusb2_phy_cfg sm6115_phy_cfg = {
 362         .tbl            = sm6115_init_tbl,
 363         .tbl_num        = ARRAY_SIZE(sm6115_init_tbl),
 364         .regs           = msm8996_regs_layout,
 365
 366         .has_pll_test   = true,
 367         .se_clk_scheme_default = true,
 368         .disable_ctrl   = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
 369         .mask_core_ready = PLL_LOCKED,
 370         .autoresume_en   = BIT(3),
 371 };
 372
 373 static const char * const qusb2_phy_vreg_names[] = {
 374         "vdda-pll", "vdda-phy-dpdm",
 375 };
 376
 377 #define QUSB2_NUM_VREGS         ARRAY_SIZE(qusb2_phy_vreg_names)
 378
 379 /* struct override_param - structure holding qusb2 v2 phy overriding param
 380  * set override true if the  device tree property exists and read and assign
 381  * to value
 382  */
 383 struct override_param {
 384         bool override;
 385         u8 value;
 386 };
 387
 388 /*struct override_params - structure holding qusb2 v2 phy overriding params
 389  * @imp_res_offset: rescode offset to be updated in IMP_CTRL1 register
 390  * @hstx_trim: HSTX_TRIM to be updated in TUNE1 register
 391  * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register
 392  * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
 393  * @bias_ctrl: bias ctrl to be updated in BIAS_CONTROL_2 register
 394  * @charge_ctrl: charge ctrl to be updated in CHG_CTRL2 register
 395  * @hsdisc_trim: disconnect threshold to be updated in TUNE2 register
 396  */
 397 struct override_params {
 398         struct override_param imp_res_offset;
 399         struct override_param hstx_trim;
 400         struct override_param preemphasis;
 401         struct override_param preemphasis_width;
 402         struct override_param bias_ctrl;
 403         struct override_param charge_ctrl;
 404         struct override_param hsdisc_trim;
 405 };
 406
 407 /**
 408  * struct qusb2_phy - structure holding qusb2 phy attributes
 409  *
 410  * @phy: generic phy
 411  * @base: iomapped memory space for qubs2 phy
 412  *
 413  * @cfg_ahb_clk: AHB2PHY interface clock
 414  * @ref_clk: phy reference clock
 415  * @iface_clk: phy interface clock
 416  * @phy_reset: phy reset control
 417  * @vregs: regulator supplies bulk data
 418  *
 419  * @tcsr: TCSR syscon register map
 420  * @cell: nvmem cell containing phy tuning value
 421  *
 422  * @overrides: pointer to structure for all overriding tuning params
 423  *
 424  * @cfg: phy config data
 425  * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
 426  * @phy_initialized: indicate if PHY has been initialized
 427  * @mode: current PHY mode
 428  */
 429 struct qusb2_phy {
 430         struct phy *phy;
 431         void __iomem *base;
 432
 433         struct clk *cfg_ahb_clk;
 434         struct clk *ref_clk;
 435         struct clk *iface_clk;
 436         struct reset_control *phy_reset;
 437         struct regulator_bulk_data vregs[QUSB2_NUM_VREGS];
 438
 439         struct regmap *tcsr;
 440         struct nvmem_cell *cell;
 441
 442         struct override_params overrides;
 443
 444         const struct qusb2_phy_cfg *cfg;
 445         bool has_se_clk_scheme;
 446         bool phy_initialized;
 447         enum phy_mode mode;
 448 };
 449
 450 static inline void qusb2_write_mask(void __iomem *base, u32 offset,
 451                                     u32 val, u32 mask)
 452 {
 453         u32 reg;
 454
 455         reg = readl(base + offset);
 456         reg &= ~mask;
 457         reg |= val & mask;
 458         writel(reg, base + offset);
 459
 460         /* Ensure above write is completed */
 461         readl(base + offset);
 462 }
 463
 464 static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val)
 465 {
 466         u32 reg;
 467
 468         reg = readl(base + offset);
 469         reg |= val;
 470         writel(reg, base + offset);
 471
 472         /* Ensure above write is completed */
 473         readl(base + offset);
 474 }
 475
 476 static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val)
 477 {
 478         u32 reg;
 479
 480         reg = readl(base + offset);
 481         reg &= ~val;
 482         writel(reg, base + offset);
 483
 484         /* Ensure above write is completed */
 485         readl(base + offset);
 486 }
 487
 488 static inline
 489 void qcom_qusb2_phy_configure(void __iomem *base,
 490                               const unsigned int *regs,
 491                               const struct qusb2_phy_init_tbl tbl[], int num)
 492 {
 493         int i;
 494
 495         for (i = 0; i < num; i++) {
 496                 if (tbl[i].in_layout)
 497                         writel(tbl[i].val, base + regs[tbl[i].offset]);
 498                 else
 499                         writel(tbl[i].val, base + tbl[i].offset);
 500         }
 501 }
 502
 503 /*
 504  * Update board specific PHY tuning override values if specified from
 505  * device tree.
 506  */
 507 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)
 508 {
 509         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 510         struct override_params *or = &qphy->overrides;
 511
 512         if (or->imp_res_offset.override)
 513                 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,
 514                 or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT,
 515                              IMP_RES_OFFSET_MASK);
 516
 517         if (or->bias_ctrl.override)
 518                 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2,
 519                 or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT,
 520                            BIAS_CTRL2_RES_OFFSET_MASK);
 521
 522         if (or->charge_ctrl.override)
 523                 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2,
 524                 or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT,
 525                              CHG_CTRL2_OFFSET_MASK);
 526
 527         if (or->hstx_trim.override)
 528                 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
 529                 or->hstx_trim.value << HSTX_TRIM_SHIFT,
 530                                  HSTX_TRIM_MASK);
 531
 532         if (or->preemphasis.override)
 533                 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
 534                 or->preemphasis.value << PREEMPHASIS_EN_SHIFT,
 535                                 PREEMPHASIS_EN_MASK);
 536
 537         if (or->preemphasis_width.override) {
 538                 if (or->preemphasis_width.value ==
 539                     QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT)
 540                         qusb2_setbits(qphy->base,
 541                                       cfg->regs[QUSB2PHY_PORT_TUNE1],
 542                                       PREEMPH_WIDTH_HALF_BIT);
 543                 else
 544                         qusb2_clrbits(qphy->base,
 545                                       cfg->regs[QUSB2PHY_PORT_TUNE1],
 546                                       PREEMPH_WIDTH_HALF_BIT);
 547         }
 548
 549         if (or->hsdisc_trim.override)
 550                 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
 551                 or->hsdisc_trim.value << HSDISC_TRIM_SHIFT,
 552                                  HSDISC_TRIM_MASK);
 553 }
 554
 555 /*
 556  * Fetches HS Tx tuning value from nvmem and sets the
 557  * QUSB2PHY_PORT_TUNE1/2 register.
 558  * For error case, skip setting the value and use the default value.
 559  */
 560 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
 561 {
 562         struct device *dev = &qphy->phy->dev;
 563         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 564         u8 *val;
 565
 566         /* efuse register is optional */
 567         if (!qphy->cell)
 568                 return;
 569
 570         /*
 571          * Read efuse register having TUNE2/1 parameter's high nibble.
 572          * If efuse register shows value as 0x0 (indicating value is not
 573          * fused), or if we fail to find a valid efuse register setting,
 574          * then use default value for high nibble that we have already
 575          * set while configuring the phy.
 576          */
 577         val = nvmem_cell_read(qphy->cell, NULL);
 578         if (IS_ERR(val) || !val[0]) {
 579                 dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
 580                 return;
 581         }
 582
 583         /* Fused TUNE1/2 value is the higher nibble only */
 584         if (cfg->update_tune1_with_efuse)
 585                 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
 586                                  val[0] << HSTX_TRIM_SHIFT,
 587                                  HSTX_TRIM_MASK);
 588         else
 589                 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
 590                                  val[0] << HSTX_TRIM_SHIFT,
 591                                  HSTX_TRIM_MASK);
 592 }
 593
 594 static int qusb2_phy_set_mode(struct phy *phy,
 595                               enum phy_mode mode, int submode)
 596 {
 597         struct qusb2_phy *qphy = phy_get_drvdata(phy);
 598
 599         qphy->mode = mode;
 600
 601         return 0;
 602 }
 603
 604 static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
 605 {
 606         struct qusb2_phy *qphy = dev_get_drvdata(dev);
 607         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 608         u32 intr_mask;
 609
 610         dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);
 611
 612         if (!qphy->phy_initialized) {
 613                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
 614                 return 0;
 615         }
 616
 617         /*
 618          * Enable DP/DM interrupts to detect line state changes based on current
 619          * speed. In other words, enable the triggers _opposite_ of what the
 620          * current D+/D- levels are e.g. if currently D+ high, D- low
 621          * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high
 622          */
 623         intr_mask = DPSE_INTR_EN | DMSE_INTR_EN;
 624         switch (qphy->mode) {
 625         case PHY_MODE_USB_HOST_HS:
 626         case PHY_MODE_USB_HOST_FS:
 627         case PHY_MODE_USB_DEVICE_HS:
 628         case PHY_MODE_USB_DEVICE_FS:
 629                 intr_mask |= DMSE_INTR_HIGH_SEL;
 630                 break;
 631         case PHY_MODE_USB_HOST_LS:
 632         case PHY_MODE_USB_DEVICE_LS:
 633                 intr_mask |= DPSE_INTR_HIGH_SEL;
 634                 break;
 635         default:
 636                 /* No device connected, enable both DP/DM high interrupt */
 637                 intr_mask |= DMSE_INTR_HIGH_SEL;
 638                 intr_mask |= DPSE_INTR_HIGH_SEL;
 639                 break;
 640         }
 641
 642         writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
 643
 644         /* hold core PLL into reset */
 645         if (cfg->has_pll_override) {
 646                 qusb2_setbits(qphy->base,
 647                               cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
 648                               CORE_PLL_EN_FROM_RESET | CORE_RESET |
 649                               CORE_RESET_MUX);
 650         }
 651
 652         /* enable phy auto-resume only if device is connected on bus */
 653         if (qphy->mode != PHY_MODE_INVALID) {
 654                 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
 655                               cfg->autoresume_en);
 656                 /* Autoresume bit has to be toggled in order to enable it */
 657                 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
 658                               cfg->autoresume_en);
 659         }
 660
 661         if (!qphy->has_se_clk_scheme)
 662                 clk_disable_unprepare(qphy->ref_clk);
 663
 664         clk_disable_unprepare(qphy->cfg_ahb_clk);
 665         clk_disable_unprepare(qphy->iface_clk);
 666
 667         return 0;
 668 }
 669
 670 static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev)
 671 {
 672         struct qusb2_phy *qphy = dev_get_drvdata(dev);
 673         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 674         int ret;
 675
 676         dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);
 677
 678         if (!qphy->phy_initialized) {
 679                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
 680                 return 0;
 681         }
 682
 683         ret = clk_prepare_enable(qphy->iface_clk);
 684         if (ret) {
 685                 dev_err(dev, "failed to enable iface_clk, %d\n", ret);
 686                 return ret;
 687         }
 688
 689         ret = clk_prepare_enable(qphy->cfg_ahb_clk);
 690         if (ret) {
 691                 dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret);
 692                 goto disable_iface_clk;
 693         }
 694
 695         if (!qphy->has_se_clk_scheme) {
 696                 ret = clk_prepare_enable(qphy->ref_clk);
 697                 if (ret) {
 698                         dev_err(dev, "failed to enable ref clk, %d\n", ret);
 699                         goto disable_ahb_clk;
 700                 }
 701         }
 702
 703         writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
 704
 705         /* bring core PLL out of reset */
 706         if (cfg->has_pll_override) {
 707                 qusb2_clrbits(qphy->base,
 708                               cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
 709                               CORE_RESET | CORE_RESET_MUX);
 710         }
 711
 712         return 0;
 713
 714 disable_ahb_clk:
 715         clk_disable_unprepare(qphy->cfg_ahb_clk);
 716 disable_iface_clk:
 717         clk_disable_unprepare(qphy->iface_clk);
 718
 719         return ret;
 720 }
 721
 722 static int qusb2_phy_init(struct phy *phy)
 723 {
 724         struct qusb2_phy *qphy = phy_get_drvdata(phy);
 725         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 726         unsigned int val = 0;
 727         unsigned int clk_scheme;
 728         int ret;
 729
 730         dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__);
 731
 732         /* turn on regulator supplies */
 733         ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
 734         if (ret)
 735                 return ret;
 736
 737         ret = clk_prepare_enable(qphy->iface_clk);
 738         if (ret) {
 739                 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret);
 740                 goto poweroff_phy;
 741         }
 742
 743         /* enable ahb interface clock to program phy */
 744         ret = clk_prepare_enable(qphy->cfg_ahb_clk);
 745         if (ret) {
 746                 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
 747                 goto disable_iface_clk;
 748         }
 749
 750         /* Perform phy reset */
 751         ret = reset_control_assert(qphy->phy_reset);
 752         if (ret) {
 753                 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
 754                 goto disable_ahb_clk;
 755         }
 756
 757         /* 100 us delay to keep PHY in reset mode */
 758         usleep_range(100, 150);
 759
 760         ret = reset_control_deassert(qphy->phy_reset);
 761         if (ret) {
 762                 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
 763                 goto disable_ahb_clk;
 764         }
 765
 766         /* Disable the PHY */
 767         qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
 768                       qphy->cfg->disable_ctrl);
 769
 770         if (cfg->has_pll_test) {
 771                 /* save reset value to override reference clock scheme later */
 772                 val = readl(qphy->base + QUSB2PHY_PLL_TEST);
 773         }
 774
 775         qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,
 776                                  cfg->tbl_num);
 777
 778         /* Override board specific PHY tuning values */
 779         qusb2_phy_override_phy_params(qphy);
 780
 781         /* Set efuse value for tuning the PHY */
 782         qusb2_phy_set_tune2_param(qphy);
 783
 784         /* Enable the PHY */
 785         qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
 786                       POWER_DOWN);
 787
 788         /* Required to get phy pll lock successfully */
 789         usleep_range(150, 160);
 790
 791         /*
 792          * Not all the SoCs have got a readable TCSR_PHY_CLK_SCHEME
 793          * register in the TCSR so, if there's none, use the default
 794          * value hardcoded in the configuration.
 795          */
 796         qphy->has_se_clk_scheme = cfg->se_clk_scheme_default;
 797
 798         /*
 799          * read TCSR_PHY_CLK_SCHEME register to check if single-ended
 800          * clock scheme is selected. If yes, then disable differential
 801          * ref_clk and use single-ended clock, otherwise use differential
 802          * ref_clk only.
 803          */
 804         if (qphy->tcsr) {
 805                 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,
 806                                   &clk_scheme);
 807                 if (ret) {
 808                         dev_err(&phy->dev, "failed to read clk scheme reg\n");
 809                         goto assert_phy_reset;
 810                 }
 811
 812                 /* is it a differential clock scheme ? */
 813                 if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) {
 814                         dev_vdbg(&phy->dev, "%s(): select differential clk\n",
 815                                  __func__);
 816                         qphy->has_se_clk_scheme = false;
 817                 } else {
 818                         dev_vdbg(&phy->dev, "%s(): select single-ended clk\n",
 819                                  __func__);
 820                 }
 821         }
 822
 823         if (!qphy->has_se_clk_scheme) {
 824                 ret = clk_prepare_enable(qphy->ref_clk);
 825                 if (ret) {
 826                         dev_err(&phy->dev, "failed to enable ref clk, %d\n",
 827                                 ret);
 828                         goto assert_phy_reset;
 829                 }
 830         }
 831
 832         if (cfg->has_pll_test) {
 833                 if (!qphy->has_se_clk_scheme)
 834                         val &= ~CLK_REF_SEL;
 835                 else
 836                         val |= CLK_REF_SEL;
 837
 838                 writel(val, qphy->base + QUSB2PHY_PLL_TEST);
 839
 840                 /* ensure above write is through */
 841                 readl(qphy->base + QUSB2PHY_PLL_TEST);
 842         }
 843
 844         /* Required to get phy pll lock successfully */
 845         usleep_range(100, 110);
 846
 847         val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);
 848         if (!(val & cfg->mask_core_ready)) {
 849                 dev_err(&phy->dev,
 850                         "QUSB2PHY pll lock failed: status reg = %x\n", val);
 851                 ret = -EBUSY;
 852                 goto disable_ref_clk;
 853         }
 854         qphy->phy_initialized = true;
 855
 856         return 0;
 857
 858 disable_ref_clk:
 859         if (!qphy->has_se_clk_scheme)
 860                 clk_disable_unprepare(qphy->ref_clk);
 861 assert_phy_reset:
 862         reset_control_assert(qphy->phy_reset);
 863 disable_ahb_clk:
 864         clk_disable_unprepare(qphy->cfg_ahb_clk);
 865 disable_iface_clk:
 866         clk_disable_unprepare(qphy->iface_clk);
 867 poweroff_phy:
 868         regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
 869
 870         return ret;
 871 }
 872
 873 static int qusb2_phy_exit(struct phy *phy)
 874 {
 875         struct qusb2_phy *qphy = phy_get_drvdata(phy);
 876
 877         /* Disable the PHY */
 878         qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],
 879                       qphy->cfg->disable_ctrl);
 880
 881         if (!qphy->has_se_clk_scheme)
 882                 clk_disable_unprepare(qphy->ref_clk);
 883
 884         reset_control_assert(qphy->phy_reset);
 885
 886         clk_disable_unprepare(qphy->cfg_ahb_clk);
 887         clk_disable_unprepare(qphy->iface_clk);
 888
 889         regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
 890
 891         qphy->phy_initialized = false;
 892
 893         return 0;
 894 }
 895
 896 static const struct phy_ops qusb2_phy_gen_ops = {
 897         .init           = qusb2_phy_init,
 898         .exit           = qusb2_phy_exit,
 899         .set_mode       = qusb2_phy_set_mode,
 900         .owner          = THIS_MODULE,
 901 };
 902
 903 static const struct of_device_id qusb2_phy_of_match_table[] = {
 904         {
 905                 .compatible     = "qcom,ipq6018-qusb2-phy",
 906                 .data           = &ipq6018_phy_cfg,
 907         }, {
 908                 .compatible     = "qcom,ipq8074-qusb2-phy",
 909                 .data           = &msm8996_phy_cfg,
 910         }, {
 911                 .compatible     = "qcom,msm8996-qusb2-phy",
 912                 .data           = &msm8996_phy_cfg,
 913         }, {
 914                 .compatible     = "qcom,msm8998-qusb2-phy",
 915                 .data           = &msm8998_phy_cfg,
 916         }, {
 917                 .compatible     = "qcom,sdm660-qusb2-phy",
 918                 .data           = &sdm660_phy_cfg,
 919         }, {
 920                 .compatible     = "qcom,sm4250-qusb2-phy",
 921                 .data           = &sm6115_phy_cfg,
 922         }, {
 923                 .compatible     = "qcom,sm6115-qusb2-phy",
 924                 .data           = &sm6115_phy_cfg,
 925         }, {
 926                 /*
 927                  * Deprecated. Only here to support legacy device
 928                  * trees that didn't include "qcom,qusb2-v2-phy"
 929                  */
 930                 .compatible     = "qcom,sdm845-qusb2-phy",
 931                 .data           = &qusb2_v2_phy_cfg,
 932         }, {
 933                 .compatible     = "qcom,qusb2-v2-phy",
 934                 .data           = &qusb2_v2_phy_cfg,
 935         },
 936         { },
 937 };
 938 MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table);
 939
 940 static const struct dev_pm_ops qusb2_phy_pm_ops = {
 941         SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend,
 942                            qusb2_phy_runtime_resume, NULL)
 943 };
 944
 945 static int qusb2_phy_probe(struct platform_device *pdev)
 946 {
 947         struct device *dev = &pdev->dev;
 948         struct qusb2_phy *qphy;
 949         struct phy_provider *phy_provider;
 950         struct phy *generic_phy;
 951         int ret, i;
 952         int num;
 953         u32 value;
 954         struct override_params *or;
 955
 956         qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
 957         if (!qphy)
 958                 return -ENOMEM;
 959         or = &qphy->overrides;
 960
 961         qphy->base = devm_platform_ioremap_resource(pdev, 0);
 962         if (IS_ERR(qphy->base))
 963                 return PTR_ERR(qphy->base);
 964
 965         qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
 966         if (IS_ERR(qphy->cfg_ahb_clk)) {
 967                 ret = PTR_ERR(qphy->cfg_ahb_clk);
 968                 if (ret != -EPROBE_DEFER)
 969                         dev_err(dev, "failed to get cfg ahb clk, %d\n", ret);
 970                 return ret;
 971         }
 972
 973         qphy->ref_clk = devm_clk_get(dev, "ref");
 974         if (IS_ERR(qphy->ref_clk)) {
 975                 ret = PTR_ERR(qphy->ref_clk);
 976                 if (ret != -EPROBE_DEFER)
 977                         dev_err(dev, "failed to get ref clk, %d\n", ret);
 978                 return ret;
 979         }
 980
 981         qphy->iface_clk = devm_clk_get_optional(dev, "iface");
 982         if (IS_ERR(qphy->iface_clk))
 983                 return PTR_ERR(qphy->iface_clk);
 984
 985         qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);
 986         if (IS_ERR(qphy->phy_reset)) {
 987                 dev_err(dev, "failed to get phy core reset\n");
 988                 return PTR_ERR(qphy->phy_reset);
 989         }
 990
 991         num = ARRAY_SIZE(qphy->vregs);
 992         for (i = 0; i < num; i++)
 993                 qphy->vregs[i].supply = qusb2_phy_vreg_names[i];
 994
 995         ret = devm_regulator_bulk_get(dev, num, qphy->vregs);
 996         if (ret) {
 997                 if (ret != -EPROBE_DEFER)
 998                         dev_err(dev, "failed to get regulator supplies: %d\n",
 999                                 ret);
1000                 return ret;
1001         }
1002
1003         /* Get the specific init parameters of QMP phy */
1004         qphy->cfg = of_device_get_match_data(dev);
1005
1006         qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,
1007                                                         "qcom,tcsr-syscon");
1008         if (IS_ERR(qphy->tcsr)) {
1009                 dev_dbg(dev, "failed to lookup TCSR regmap\n");
1010                 qphy->tcsr = NULL;
1011         }
1012
1013         qphy->cell = devm_nvmem_cell_get(dev, NULL);
1014         if (IS_ERR(qphy->cell)) {
1015                 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)
1016                         return -EPROBE_DEFER;
1017                 qphy->cell = NULL;
1018                 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n");
1019         }
1020
1021         if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value",
1022                                   &value)) {
1023                 or->imp_res_offset.value = (u8)value;
1024                 or->imp_res_offset.override = true;
1025         }
1026
1027         if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value",
1028                                   &value)) {
1029                 or->bias_ctrl.value = (u8)value;
1030                 or->bias_ctrl.override = true;
1031         }
1032
1033         if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value",
1034                                   &value)) {
1035                 or->charge_ctrl.value = (u8)value;
1036                 or->charge_ctrl.override = true;
1037         }
1038
1039         if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value",
1040                                   &value)) {
1041                 or->hstx_trim.value = (u8)value;
1042                 or->hstx_trim.override = true;
1043         }
1044
1045         if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level",
1046                                      &value)) {
1047                 or->preemphasis.value = (u8)value;
1048                 or->preemphasis.override = true;
1049         }
1050
1051         if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width",
1052                                      &value)) {
1053                 or->preemphasis_width.value = (u8)value;
1054                 or->preemphasis_width.override = true;
1055         }
1056
1057         if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value",
1058                                   &value)) {
1059                 or->hsdisc_trim.value = (u8)value;
1060                 or->hsdisc_trim.override = true;
1061         }
1062
1063         pm_runtime_set_active(dev);
1064         pm_runtime_enable(dev);
1065         /*
1066          * Prevent runtime pm from being ON by default. Users can enable
1067          * it using power/control in sysfs.
1068          */
1069         pm_runtime_forbid(dev);
1070
1071         generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops);
1072         if (IS_ERR(generic_phy)) {
1073                 ret = PTR_ERR(generic_phy);
1074                 dev_err(dev, "failed to create phy, %d\n", ret);
1075                 pm_runtime_disable(dev);
1076                 return ret;
1077         }
1078         qphy->phy = generic_phy;
1079
1080         dev_set_drvdata(dev, qphy);
1081         phy_set_drvdata(generic_phy, qphy);
1082
1083         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1084         if (!IS_ERR(phy_provider))
1085                 dev_info(dev, "Registered Qcom-QUSB2 phy\n");
1086         else
1087                 pm_runtime_disable(dev);
1088
1089         return PTR_ERR_OR_ZERO(phy_provider);
1090 }
1091
1092 static struct platform_driver qusb2_phy_driver = {
1093         .probe          = qusb2_phy_probe,
1094         .driver = {
1095                 .name   = "qcom-qusb2-phy",
1096                 .pm     = &qusb2_phy_pm_ops,
1097                 .of_match_table = qusb2_phy_of_match_table,
1098         },
1099 };
1100
1101 module_platform_driver(qusb2_phy_driver);
1102
1103 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
1104 MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver");
1105 MODULE_LICENSE("GPL v2");