drivers/phy/qualcomm/phy-qcom-qusb2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/delay.h>
   8 #include <linux/err.h>
   9 #include <linux/io.h>
  10 #include <linux/kernel.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/module.h>
  13 #include <linux/nvmem-consumer.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regmap.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/reset.h>
  21 #include <linux/slab.h>
  22
  23 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  24
  25 #define QUSB2PHY_PLL_TEST               0x04
  26 #define CLK_REF_SEL                     BIT(7)
  27
  28 #define QUSB2PHY_PLL_TUNE               0x08
  29 #define QUSB2PHY_PLL_USER_CTL1          0x0c
  30 #define QUSB2PHY_PLL_USER_CTL2          0x10
  31 #define QUSB2PHY_PLL_AUTOPGM_CTL1       0x1c
  32 #define QUSB2PHY_PLL_PWR_CTRL           0x18
  33
  34 /* QUSB2PHY_PLL_STATUS register bits */
  35 #define PLL_LOCKED                      BIT(5)
  36
  37 /* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */
  38 #define CORE_READY_STATUS               BIT(0)
  39
  40 /* QUSB2PHY_PORT_POWERDOWN register bits */
  41 #define CLAMP_N_EN                      BIT(5)
  42 #define FREEZIO_N                       BIT(1)
  43 #define POWER_DOWN                      BIT(0)
  44
  45 /* QUSB2PHY_PWR_CTRL1 register bits */
  46 #define PWR_CTRL1_VREF_SUPPLY_TRIM      BIT(5)
  47 #define PWR_CTRL1_CLAMP_N_EN            BIT(1)
  48
  49 #define QUSB2PHY_REFCLK_ENABLE          BIT(0)
  50
  51 #define PHY_CLK_SCHEME_SEL              BIT(0)
  52
  53 /* QUSB2PHY_INTR_CTRL register bits */
  54 #define DMSE_INTR_HIGH_SEL                      BIT(4)
  55 #define DPSE_INTR_HIGH_SEL                      BIT(3)
  56 #define CHG_DET_INTR_EN                         BIT(2)
  57 #define DMSE_INTR_EN                            BIT(1)
  58 #define DPSE_INTR_EN                            BIT(0)
  59
  60 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */
  61 #define CORE_PLL_EN_FROM_RESET                  BIT(4)
  62 #define CORE_RESET                              BIT(5)
  63 #define CORE_RESET_MUX                          BIT(6)
  64
  65 /* QUSB2PHY_IMP_CTRL1 register bits */
  66 #define IMP_RES_OFFSET_MASK                     GENMASK(5, 0)
  67 #define IMP_RES_OFFSET_SHIFT                    0x0
  68
  69 /* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */
  70 #define BIAS_CTRL2_RES_OFFSET_MASK              GENMASK(5, 0)
  71 #define BIAS_CTRL2_RES_OFFSET_SHIFT             0x0
  72
  73 /* QUSB2PHY_CHG_CONTROL_2 register bits */
  74 #define CHG_CTRL2_OFFSET_MASK                   GENMASK(5, 4)
  75 #define CHG_CTRL2_OFFSET_SHIFT                  0x4
  76
  77 /* QUSB2PHY_PORT_TUNE1 register bits */
  78 #define HSTX_TRIM_MASK                          GENMASK(7, 4)
  79 #define HSTX_TRIM_SHIFT                         0x4
  80 #define PREEMPH_WIDTH_HALF_BIT                  BIT(2)
  81 #define PREEMPHASIS_EN_MASK                     GENMASK(1, 0)
  82 #define PREEMPHASIS_EN_SHIFT                    0x0
  83
  84 /* QUSB2PHY_PORT_TUNE2 register bits */
  85 #define HSDISC_TRIM_MASK                        GENMASK(1, 0)
  86 #define HSDISC_TRIM_SHIFT                       0x0
  87
  88 #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO        0x04
  89 #define QUSB2PHY_PLL_CLOCK_INVERTERS            0x18c
  90 #define QUSB2PHY_PLL_CMODE                      0x2c
  91 #define QUSB2PHY_PLL_LOCK_DELAY                 0x184
  92 #define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO         0xb4
  93 #define QUSB2PHY_PLL_BIAS_CONTROL_1             0x194
  94 #define QUSB2PHY_PLL_BIAS_CONTROL_2             0x198
  95 #define QUSB2PHY_PWR_CTRL2                      0x214
  96 #define QUSB2PHY_IMP_CTRL1                      0x220
  97 #define QUSB2PHY_IMP_CTRL2                      0x224
  98 #define QUSB2PHY_CHG_CTRL2                      0x23c
  99
 100 struct qusb2_phy_init_tbl {
 101         unsigned int offset;
 102         unsigned int val;
 103         /*
 104          * register part of layout ?
 105          * if yes, then offset gives index in the reg-layout
 106          */
 107         int in_layout;
 108 };
 109
 110 #define QUSB2_PHY_INIT_CFG(o, v) \
 111         {                       \
 112                 .offset = o,    \
 113                 .val = v,       \
 114         }
 115
 116 #define QUSB2_PHY_INIT_CFG_L(o, v) \
 117         {                       \
 118                 .offset = o,    \
 119                 .val = v,       \
 120                 .in_layout = 1, \
 121         }
 122
 123 /* set of registers with offsets different per-PHY */
 124 enum qusb2phy_reg_layout {
 125         QUSB2PHY_PLL_CORE_INPUT_OVERRIDE,
 126         QUSB2PHY_PLL_STATUS,
 127         QUSB2PHY_PORT_TUNE1,
 128         QUSB2PHY_PORT_TUNE2,
 129         QUSB2PHY_PORT_TUNE3,
 130         QUSB2PHY_PORT_TUNE4,
 131         QUSB2PHY_PORT_TUNE5,
 132         QUSB2PHY_PORT_TEST1,
 133         QUSB2PHY_PORT_TEST2,
 134         QUSB2PHY_PORT_POWERDOWN,
 135         QUSB2PHY_INTR_CTRL,
 136 };
 137
 138 static const unsigned int msm8996_regs_layout[] = {
 139         [QUSB2PHY_PLL_STATUS]           = 0x38,
 140         [QUSB2PHY_PORT_TUNE1]           = 0x80,
 141         [QUSB2PHY_PORT_TUNE2]           = 0x84,
 142         [QUSB2PHY_PORT_TUNE3]           = 0x88,
 143         [QUSB2PHY_PORT_TUNE4]           = 0x8c,
 144         [QUSB2PHY_PORT_TUNE5]           = 0x90,
 145         [QUSB2PHY_PORT_TEST1]           = 0xb8,
 146         [QUSB2PHY_PORT_TEST2]           = 0x9c,
 147         [QUSB2PHY_PORT_POWERDOWN]       = 0xb4,
 148         [QUSB2PHY_INTR_CTRL]            = 0xbc,
 149 };
 150
 151 static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
 152         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
 153         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
 154         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
 155         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
 156
 157         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
 158         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
 159         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
 160
 161         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
 162
 163         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
 164         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
 165 };
 166
 167 static const unsigned int msm8998_regs_layout[] = {
 168         [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
 169         [QUSB2PHY_PLL_STATUS]              = 0x1a0,
 170         [QUSB2PHY_PORT_TUNE1]              = 0x23c,
 171         [QUSB2PHY_PORT_TUNE2]              = 0x240,
 172         [QUSB2PHY_PORT_TUNE3]              = 0x244,
 173         [QUSB2PHY_PORT_TUNE4]              = 0x248,
 174         [QUSB2PHY_PORT_TEST1]              = 0x24c,
 175         [QUSB2PHY_PORT_TEST2]              = 0x250,
 176         [QUSB2PHY_PORT_POWERDOWN]          = 0x210,
 177         [QUSB2PHY_INTR_CTRL]               = 0x22c,
 178 };
 179
 180 static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = {
 181         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x13),
 182         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
 183         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
 184         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
 185
 186         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xa5),
 187         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x09),
 188
 189         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
 190 };
 191
 192 static const unsigned int qusb2_v2_regs_layout[] = {
 193         [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
 194         [QUSB2PHY_PLL_STATUS]           = 0x1a0,
 195         [QUSB2PHY_PORT_TUNE1]           = 0x240,
 196         [QUSB2PHY_PORT_TUNE2]           = 0x244,
 197         [QUSB2PHY_PORT_TUNE3]           = 0x248,
 198         [QUSB2PHY_PORT_TUNE4]           = 0x24c,
 199         [QUSB2PHY_PORT_TUNE5]           = 0x250,
 200         [QUSB2PHY_PORT_TEST1]           = 0x254,
 201         [QUSB2PHY_PORT_TEST2]           = 0x258,
 202         [QUSB2PHY_PORT_POWERDOWN]       = 0x210,
 203         [QUSB2PHY_INTR_CTRL]            = 0x230,
 204 };
 205
 206 static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
 207         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
 208         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
 209         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
 210         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
 211         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
 212         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40),
 213         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20),
 214         QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21),
 215         QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0),
 216         QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58),
 217
 218         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30),
 219         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29),
 220         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca),
 221         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04),
 222         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03),
 223
 224         QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0),
 225 };
 226
 227 struct qusb2_phy_cfg {
 228         const struct qusb2_phy_init_tbl *tbl;
 229         /* number of entries in the table */
 230         unsigned int tbl_num;
 231         /* offset to PHY_CLK_SCHEME register in TCSR map */
 232         unsigned int clk_scheme_offset;
 233
 234         /* array of registers with different offsets */
 235         const unsigned int *regs;
 236         unsigned int mask_core_ready;
 237         unsigned int disable_ctrl;
 238         unsigned int autoresume_en;
 239
 240         /* true if PHY has PLL_TEST register to select clk_scheme */
 241         bool has_pll_test;
 242
 243         /* true if TUNE1 register must be updated by fused value, else TUNE2 */
 244         bool update_tune1_with_efuse;
 245
 246         /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
 247         bool has_pll_override;
 248 };
 249
 250 static const struct qusb2_phy_cfg msm8996_phy_cfg = {
 251         .tbl            = msm8996_init_tbl,
 252         .tbl_num        = ARRAY_SIZE(msm8996_init_tbl),
 253         .regs           = msm8996_regs_layout,
 254
 255         .has_pll_test   = true,
 256         .disable_ctrl   = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
 257         .mask_core_ready = PLL_LOCKED,
 258         .autoresume_en   = BIT(3),
 259 };
 260
 261 static const struct qusb2_phy_cfg msm8998_phy_cfg = {
 262         .tbl            = msm8998_init_tbl,
 263         .tbl_num        = ARRAY_SIZE(msm8998_init_tbl),
 264         .regs           = msm8998_regs_layout,
 265
 266         .disable_ctrl   = POWER_DOWN,
 267         .mask_core_ready = CORE_READY_STATUS,
 268         .has_pll_override = true,
 269         .autoresume_en   = BIT(0),
 270         .update_tune1_with_efuse = true,
 271 };
 272
 273 static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
 274         .tbl            = qusb2_v2_init_tbl,
 275         .tbl_num        = ARRAY_SIZE(qusb2_v2_init_tbl),
 276         .regs           = qusb2_v2_regs_layout,
 277
 278         .disable_ctrl   = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN |
 279                            POWER_DOWN),
 280         .mask_core_ready = CORE_READY_STATUS,
 281         .has_pll_override = true,
 282         .autoresume_en    = BIT(0),
 283         .update_tune1_with_efuse = true,
 284 };
 285
 286 static const char * const qusb2_phy_vreg_names[] = {
 287         "vdda-pll", "vdda-phy-dpdm",
 288 };
 289
 290 #define QUSB2_NUM_VREGS         ARRAY_SIZE(qusb2_phy_vreg_names)
 291
 292 /* struct override_param - structure holding qusb2 v2 phy overriding param
 293  * set override true if the  device tree property exists and read and assign
 294  * to value
 295  */
 296 struct override_param {
 297         bool override;
 298         u8 value;
 299 };
 300
 301 /*struct override_params - structure holding qusb2 v2 phy overriding params
 302  * @imp_res_offset: rescode offset to be updated in IMP_CTRL1 register
 303  * @hstx_trim: HSTX_TRIM to be updated in TUNE1 register
 304  * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register
 305  * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
 306  * @bias_ctrl: bias ctrl to be updated in BIAS_CONTROL_2 register
 307  * @charge_ctrl: charge ctrl to be updated in CHG_CTRL2 register
 308  * @hsdisc_trim: disconnect threshold to be updated in TUNE2 register
 309  */
 310 struct override_params {
 311         struct override_param imp_res_offset;
 312         struct override_param hstx_trim;
 313         struct override_param preemphasis;
 314         struct override_param preemphasis_width;
 315         struct override_param bias_ctrl;
 316         struct override_param charge_ctrl;
 317         struct override_param hsdisc_trim;
 318 };
 319
 320 /**
 321  * struct qusb2_phy - structure holding qusb2 phy attributes
 322  *
 323  * @phy: generic phy
 324  * @base: iomapped memory space for qubs2 phy
 325  *
 326  * @cfg_ahb_clk: AHB2PHY interface clock
 327  * @ref_clk: phy reference clock
 328  * @iface_clk: phy interface clock
 329  * @phy_reset: phy reset control
 330  * @vregs: regulator supplies bulk data
 331  *
 332  * @tcsr: TCSR syscon register map
 333  * @cell: nvmem cell containing phy tuning value
 334  *
 335  * @overrides: pointer to structure for all overriding tuning params
 336  *
 337  * @cfg: phy config data
 338  * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
 339  * @phy_initialized: indicate if PHY has been initialized
 340  * @mode: current PHY mode
 341  */
 342 struct qusb2_phy {
 343         struct phy *phy;
 344         void __iomem *base;
 345
 346         struct clk *cfg_ahb_clk;
 347         struct clk *ref_clk;
 348         struct clk *iface_clk;
 349         struct reset_control *phy_reset;
 350         struct regulator_bulk_data vregs[QUSB2_NUM_VREGS];
 351
 352         struct regmap *tcsr;
 353         struct nvmem_cell *cell;
 354
 355         struct override_params overrides;
 356
 357         const struct qusb2_phy_cfg *cfg;
 358         bool has_se_clk_scheme;
 359         bool phy_initialized;
 360         enum phy_mode mode;
 361 };
 362
 363 static inline void qusb2_write_mask(void __iomem *base, u32 offset,
 364                                     u32 val, u32 mask)
 365 {
 366         u32 reg;
 367
 368         reg = readl(base + offset);
 369         reg &= ~mask;
 370         reg |= val & mask;
 371         writel(reg, base + offset);
 372
 373         /* Ensure above write is completed */
 374         readl(base + offset);
 375 }
 376
 377 static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val)
 378 {
 379         u32 reg;
 380
 381         reg = readl(base + offset);
 382         reg |= val;
 383         writel(reg, base + offset);
 384
 385         /* Ensure above write is completed */
 386         readl(base + offset);
 387 }
 388
 389 static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val)
 390 {
 391         u32 reg;
 392
 393         reg = readl(base + offset);
 394         reg &= ~val;
 395         writel(reg, base + offset);
 396
 397         /* Ensure above write is completed */
 398         readl(base + offset);
 399 }
 400
 401 static inline
 402 void qcom_qusb2_phy_configure(void __iomem *base,
 403                               const unsigned int *regs,
 404                               const struct qusb2_phy_init_tbl tbl[], int num)
 405 {
 406         int i;
 407
 408         for (i = 0; i < num; i++) {
 409                 if (tbl[i].in_layout)
 410                         writel(tbl[i].val, base + regs[tbl[i].offset]);
 411                 else
 412                         writel(tbl[i].val, base + tbl[i].offset);
 413         }
 414 }
 415
 416 /*
 417  * Update board specific PHY tuning override values if specified from
 418  * device tree.
 419  */
 420 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)
 421 {
 422         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 423         struct override_params *or = &qphy->overrides;
 424
 425         if (or->imp_res_offset.override)
 426                 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,
 427                 or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT,
 428                              IMP_RES_OFFSET_MASK);
 429
 430         if (or->bias_ctrl.override)
 431                 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2,
 432                 or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT,
 433                            BIAS_CTRL2_RES_OFFSET_MASK);
 434
 435         if (or->charge_ctrl.override)
 436                 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2,
 437                 or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT,
 438                              CHG_CTRL2_OFFSET_MASK);
 439
 440         if (or->hstx_trim.override)
 441                 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
 442                 or->hstx_trim.value << HSTX_TRIM_SHIFT,
 443                                  HSTX_TRIM_MASK);
 444
 445         if (or->preemphasis.override)
 446                 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
 447                 or->preemphasis.value << PREEMPHASIS_EN_SHIFT,
 448                                 PREEMPHASIS_EN_MASK);
 449
 450         if (or->preemphasis_width.override) {
 451                 if (or->preemphasis_width.value ==
 452                     QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT)
 453                         qusb2_setbits(qphy->base,
 454                                       cfg->regs[QUSB2PHY_PORT_TUNE1],
 455                                       PREEMPH_WIDTH_HALF_BIT);
 456                 else
 457                         qusb2_clrbits(qphy->base,
 458                                       cfg->regs[QUSB2PHY_PORT_TUNE1],
 459                                       PREEMPH_WIDTH_HALF_BIT);
 460         }
 461
 462         if (or->hsdisc_trim.override)
 463                 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
 464                 or->hsdisc_trim.value << HSDISC_TRIM_SHIFT,
 465                                  HSDISC_TRIM_MASK);
 466 }
 467
 468 /*
 469  * Fetches HS Tx tuning value from nvmem and sets the
 470  * QUSB2PHY_PORT_TUNE1/2 register.
 471  * For error case, skip setting the value and use the default value.
 472  */
 473 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
 474 {
 475         struct device *dev = &qphy->phy->dev;
 476         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 477         u8 *val;
 478
 479         /* efuse register is optional */
 480         if (!qphy->cell)
 481                 return;
 482
 483         /*
 484          * Read efuse register having TUNE2/1 parameter's high nibble.
 485          * If efuse register shows value as 0x0 (indicating value is not
 486          * fused), or if we fail to find a valid efuse register setting,
 487          * then use default value for high nibble that we have already
 488          * set while configuring the phy.
 489          */
 490         val = nvmem_cell_read(qphy->cell, NULL);
 491         if (IS_ERR(val) || !val[0]) {
 492                 dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
 493                 return;
 494         }
 495
 496         /* Fused TUNE1/2 value is the higher nibble only */
 497         if (cfg->update_tune1_with_efuse)
 498                 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
 499                                  val[0] << HSTX_TRIM_SHIFT,
 500                                  HSTX_TRIM_MASK);
 501         else
 502                 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
 503                                  val[0] << HSTX_TRIM_SHIFT,
 504                                  HSTX_TRIM_MASK);
 505 }
 506
 507 static int qusb2_phy_set_mode(struct phy *phy,
 508                               enum phy_mode mode, int submode)
 509 {
 510         struct qusb2_phy *qphy = phy_get_drvdata(phy);
 511
 512         qphy->mode = mode;
 513
 514         return 0;
 515 }
 516
 517 static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
 518 {
 519         struct qusb2_phy *qphy = dev_get_drvdata(dev);
 520         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 521         u32 intr_mask;
 522
 523         dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);
 524
 525         if (!qphy->phy_initialized) {
 526                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
 527                 return 0;
 528         }
 529
 530         /*
 531          * Enable DP/DM interrupts to detect line state changes based on current
 532          * speed. In other words, enable the triggers _opposite_ of what the
 533          * current D+/D- levels are e.g. if currently D+ high, D- low
 534          * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high
 535          */
 536         intr_mask = DPSE_INTR_EN | DMSE_INTR_EN;
 537         switch (qphy->mode) {
 538         case PHY_MODE_USB_HOST_HS:
 539         case PHY_MODE_USB_HOST_FS:
 540         case PHY_MODE_USB_DEVICE_HS:
 541         case PHY_MODE_USB_DEVICE_FS:
 542                 intr_mask |= DMSE_INTR_HIGH_SEL;
 543                 break;
 544         case PHY_MODE_USB_HOST_LS:
 545         case PHY_MODE_USB_DEVICE_LS:
 546                 intr_mask |= DPSE_INTR_HIGH_SEL;
 547                 break;
 548         default:
 549                 /* No device connected, enable both DP/DM high interrupt */
 550                 intr_mask |= DMSE_INTR_HIGH_SEL;
 551                 intr_mask |= DPSE_INTR_HIGH_SEL;
 552                 break;
 553         }
 554
 555         writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
 556
 557         /* hold core PLL into reset */
 558         if (cfg->has_pll_override) {
 559                 qusb2_setbits(qphy->base,
 560                               cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
 561                               CORE_PLL_EN_FROM_RESET | CORE_RESET |
 562                               CORE_RESET_MUX);
 563         }
 564
 565         /* enable phy auto-resume only if device is connected on bus */
 566         if (qphy->mode != PHY_MODE_INVALID) {
 567                 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
 568                               cfg->autoresume_en);
 569                 /* Autoresume bit has to be toggled in order to enable it */
 570                 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
 571                               cfg->autoresume_en);
 572         }
 573
 574         if (!qphy->has_se_clk_scheme)
 575                 clk_disable_unprepare(qphy->ref_clk);
 576
 577         clk_disable_unprepare(qphy->cfg_ahb_clk);
 578         clk_disable_unprepare(qphy->iface_clk);
 579
 580         return 0;
 581 }
 582
 583 static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev)
 584 {
 585         struct qusb2_phy *qphy = dev_get_drvdata(dev);
 586         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 587         int ret;
 588
 589         dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);
 590
 591         if (!qphy->phy_initialized) {
 592                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
 593                 return 0;
 594         }
 595
 596         ret = clk_prepare_enable(qphy->iface_clk);
 597         if (ret) {
 598                 dev_err(dev, "failed to enable iface_clk, %d\n", ret);
 599                 return ret;
 600         }
 601
 602         ret = clk_prepare_enable(qphy->cfg_ahb_clk);
 603         if (ret) {
 604                 dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret);
 605                 goto disable_iface_clk;
 606         }
 607
 608         if (!qphy->has_se_clk_scheme) {
 609                 ret = clk_prepare_enable(qphy->ref_clk);
 610                 if (ret) {
 611                         dev_err(dev, "failed to enable ref clk, %d\n", ret);
 612                         goto disable_ahb_clk;
 613                 }
 614         }
 615
 616         writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
 617
 618         /* bring core PLL out of reset */
 619         if (cfg->has_pll_override) {
 620                 qusb2_clrbits(qphy->base,
 621                               cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
 622                               CORE_RESET | CORE_RESET_MUX);
 623         }
 624
 625         return 0;
 626
 627 disable_ahb_clk:
 628         clk_disable_unprepare(qphy->cfg_ahb_clk);
 629 disable_iface_clk:
 630         clk_disable_unprepare(qphy->iface_clk);
 631
 632         return ret;
 633 }
 634
 635 static int qusb2_phy_init(struct phy *phy)
 636 {
 637         struct qusb2_phy *qphy = phy_get_drvdata(phy);
 638         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 639         unsigned int val = 0;
 640         unsigned int clk_scheme;
 641         int ret;
 642
 643         dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__);
 644
 645         /* turn on regulator supplies */
 646         ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
 647         if (ret)
 648                 return ret;
 649
 650         ret = clk_prepare_enable(qphy->iface_clk);
 651         if (ret) {
 652                 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret);
 653                 goto poweroff_phy;
 654         }
 655
 656         /* enable ahb interface clock to program phy */
 657         ret = clk_prepare_enable(qphy->cfg_ahb_clk);
 658         if (ret) {
 659                 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
 660                 goto disable_iface_clk;
 661         }
 662
 663         /* Perform phy reset */
 664         ret = reset_control_assert(qphy->phy_reset);
 665         if (ret) {
 666                 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
 667                 goto disable_ahb_clk;
 668         }
 669
 670         /* 100 us delay to keep PHY in reset mode */
 671         usleep_range(100, 150);
 672
 673         ret = reset_control_deassert(qphy->phy_reset);
 674         if (ret) {
 675                 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
 676                 goto disable_ahb_clk;
 677         }
 678
 679         /* Disable the PHY */
 680         qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
 681                       qphy->cfg->disable_ctrl);
 682
 683         if (cfg->has_pll_test) {
 684                 /* save reset value to override reference clock scheme later */
 685                 val = readl(qphy->base + QUSB2PHY_PLL_TEST);
 686         }
 687
 688         qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,
 689                                  cfg->tbl_num);
 690
 691         /* Override board specific PHY tuning values */
 692         qusb2_phy_override_phy_params(qphy);
 693
 694         /* Set efuse value for tuning the PHY */
 695         qusb2_phy_set_tune2_param(qphy);
 696
 697         /* Enable the PHY */
 698         qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
 699                       POWER_DOWN);
 700
 701         /* Required to get phy pll lock successfully */
 702         usleep_range(150, 160);
 703
 704         /* Default is single-ended clock on msm8996 */
 705         qphy->has_se_clk_scheme = true;
 706         /*
 707          * read TCSR_PHY_CLK_SCHEME register to check if single-ended
 708          * clock scheme is selected. If yes, then disable differential
 709          * ref_clk and use single-ended clock, otherwise use differential
 710          * ref_clk only.
 711          */
 712         if (qphy->tcsr) {
 713                 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,
 714                                   &clk_scheme);
 715                 if (ret) {
 716                         dev_err(&phy->dev, "failed to read clk scheme reg\n");
 717                         goto assert_phy_reset;
 718                 }
 719
 720                 /* is it a differential clock scheme ? */
 721                 if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) {
 722                         dev_vdbg(&phy->dev, "%s(): select differential clk\n",
 723                                  __func__);
 724                         qphy->has_se_clk_scheme = false;
 725                 } else {
 726                         dev_vdbg(&phy->dev, "%s(): select single-ended clk\n",
 727                                  __func__);
 728                 }
 729         }
 730
 731         if (!qphy->has_se_clk_scheme) {
 732                 ret = clk_prepare_enable(qphy->ref_clk);
 733                 if (ret) {
 734                         dev_err(&phy->dev, "failed to enable ref clk, %d\n",
 735                                 ret);
 736                         goto assert_phy_reset;
 737                 }
 738         }
 739
 740         if (cfg->has_pll_test) {
 741                 if (!qphy->has_se_clk_scheme)
 742                         val &= ~CLK_REF_SEL;
 743                 else
 744                         val |= CLK_REF_SEL;
 745
 746                 writel(val, qphy->base + QUSB2PHY_PLL_TEST);
 747
 748                 /* ensure above write is through */
 749                 readl(qphy->base + QUSB2PHY_PLL_TEST);
 750         }
 751
 752         /* Required to get phy pll lock successfully */
 753         usleep_range(100, 110);
 754
 755         val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);
 756         if (!(val & cfg->mask_core_ready)) {
 757                 dev_err(&phy->dev,
 758                         "QUSB2PHY pll lock failed: status reg = %x\n", val);
 759                 ret = -EBUSY;
 760                 goto disable_ref_clk;
 761         }
 762         qphy->phy_initialized = true;
 763
 764         return 0;
 765
 766 disable_ref_clk:
 767         if (!qphy->has_se_clk_scheme)
 768                 clk_disable_unprepare(qphy->ref_clk);
 769 assert_phy_reset:
 770         reset_control_assert(qphy->phy_reset);
 771 disable_ahb_clk:
 772         clk_disable_unprepare(qphy->cfg_ahb_clk);
 773 disable_iface_clk:
 774         clk_disable_unprepare(qphy->iface_clk);
 775 poweroff_phy:
 776         regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
 777
 778         return ret;
 779 }
 780
 781 static int qusb2_phy_exit(struct phy *phy)
 782 {
 783         struct qusb2_phy *qphy = phy_get_drvdata(phy);
 784
 785         /* Disable the PHY */
 786         qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],
 787                       qphy->cfg->disable_ctrl);
 788
 789         if (!qphy->has_se_clk_scheme)
 790                 clk_disable_unprepare(qphy->ref_clk);
 791
 792         reset_control_assert(qphy->phy_reset);
 793
 794         clk_disable_unprepare(qphy->cfg_ahb_clk);
 795         clk_disable_unprepare(qphy->iface_clk);
 796
 797         regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
 798
 799         qphy->phy_initialized = false;
 800
 801         return 0;
 802 }
 803
 804 static const struct phy_ops qusb2_phy_gen_ops = {
 805         .init           = qusb2_phy_init,
 806         .exit           = qusb2_phy_exit,
 807         .set_mode       = qusb2_phy_set_mode,
 808         .owner          = THIS_MODULE,
 809 };
 810
 811 static const struct of_device_id qusb2_phy_of_match_table[] = {
 812         {
 813                 .compatible     = "qcom,ipq8074-qusb2-phy",
 814                 .data           = &msm8996_phy_cfg,
 815         }, {
 816                 .compatible     = "qcom,msm8996-qusb2-phy",
 817                 .data           = &msm8996_phy_cfg,
 818         }, {
 819                 .compatible     = "qcom,msm8998-qusb2-phy",
 820                 .data           = &msm8998_phy_cfg,
 821         }, {
 822                 /*
 823                  * Deprecated. Only here to support legacy device
 824                  * trees that didn't include "qcom,qusb2-v2-phy"
 825                  */
 826                 .compatible     = "qcom,sdm845-qusb2-phy",
 827                 .data           = &qusb2_v2_phy_cfg,
 828         }, {
 829                 .compatible     = "qcom,qusb2-v2-phy",
 830                 .data           = &qusb2_v2_phy_cfg,
 831         },
 832         { },
 833 };
 834 MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table);
 835
 836 static const struct dev_pm_ops qusb2_phy_pm_ops = {
 837         SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend,
 838                            qusb2_phy_runtime_resume, NULL)
 839 };
 840
 841 static int qusb2_phy_probe(struct platform_device *pdev)
 842 {
 843         struct device *dev = &pdev->dev;
 844         struct qusb2_phy *qphy;
 845         struct phy_provider *phy_provider;
 846         struct phy *generic_phy;
 847         int ret, i;
 848         int num;
 849         u32 value;
 850         struct override_params *or;
 851
 852         qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
 853         if (!qphy)
 854                 return -ENOMEM;
 855         or = &qphy->overrides;
 856
 857         qphy->base = devm_platform_ioremap_resource(pdev, 0);
 858         if (IS_ERR(qphy->base))
 859                 return PTR_ERR(qphy->base);
 860
 861         qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
 862         if (IS_ERR(qphy->cfg_ahb_clk)) {
 863                 ret = PTR_ERR(qphy->cfg_ahb_clk);
 864                 if (ret != -EPROBE_DEFER)
 865                         dev_err(dev, "failed to get cfg ahb clk, %d\n", ret);
 866                 return ret;
 867         }
 868
 869         qphy->ref_clk = devm_clk_get(dev, "ref");
 870         if (IS_ERR(qphy->ref_clk)) {
 871                 ret = PTR_ERR(qphy->ref_clk);
 872                 if (ret != -EPROBE_DEFER)
 873                         dev_err(dev, "failed to get ref clk, %d\n", ret);
 874                 return ret;
 875         }
 876
 877         qphy->iface_clk = devm_clk_get_optional(dev, "iface");
 878         if (IS_ERR(qphy->iface_clk))
 879                 return PTR_ERR(qphy->iface_clk);
 880
 881         qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);
 882         if (IS_ERR(qphy->phy_reset)) {
 883                 dev_err(dev, "failed to get phy core reset\n");
 884                 return PTR_ERR(qphy->phy_reset);
 885         }
 886
 887         num = ARRAY_SIZE(qphy->vregs);
 888         for (i = 0; i < num; i++)
 889                 qphy->vregs[i].supply = qusb2_phy_vreg_names[i];
 890
 891         ret = devm_regulator_bulk_get(dev, num, qphy->vregs);
 892         if (ret) {
 893                 if (ret != -EPROBE_DEFER)
 894                         dev_err(dev, "failed to get regulator supplies: %d\n",
 895                                 ret);
 896                 return ret;
 897         }
 898
 899         /* Get the specific init parameters of QMP phy */
 900         qphy->cfg = of_device_get_match_data(dev);
 901
 902         qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,
 903                                                         "qcom,tcsr-syscon");
 904         if (IS_ERR(qphy->tcsr)) {
 905                 dev_dbg(dev, "failed to lookup TCSR regmap\n");
 906                 qphy->tcsr = NULL;
 907         }
 908
 909         qphy->cell = devm_nvmem_cell_get(dev, NULL);
 910         if (IS_ERR(qphy->cell)) {
 911                 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)
 912                         return -EPROBE_DEFER;
 913                 qphy->cell = NULL;
 914                 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n");
 915         }
 916
 917         if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value",
 918                                   &value)) {
 919                 or->imp_res_offset.value = (u8)value;
 920                 or->imp_res_offset.override = true;
 921         }
 922
 923         if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value",
 924                                   &value)) {
 925                 or->bias_ctrl.value = (u8)value;
 926                 or->bias_ctrl.override = true;
 927         }
 928
 929         if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value",
 930                                   &value)) {
 931                 or->charge_ctrl.value = (u8)value;
 932                 or->charge_ctrl.override = true;
 933         }
 934
 935         if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value",
 936                                   &value)) {
 937                 or->hstx_trim.value = (u8)value;
 938                 or->hstx_trim.override = true;
 939         }
 940
 941         if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level",
 942                                      &value)) {
 943                 or->preemphasis.value = (u8)value;
 944                 or->preemphasis.override = true;
 945         }
 946
 947         if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width",
 948                                      &value)) {
 949                 or->preemphasis_width.value = (u8)value;
 950                 or->preemphasis_width.override = true;
 951         }
 952
 953         if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value",
 954                                   &value)) {
 955                 or->hsdisc_trim.value = (u8)value;
 956                 or->hsdisc_trim.override = true;
 957         }
 958
 959         pm_runtime_set_active(dev);
 960         pm_runtime_enable(dev);
 961         /*
 962          * Prevent runtime pm from being ON by default. Users can enable
 963          * it using power/control in sysfs.
 964          */
 965         pm_runtime_forbid(dev);
 966
 967         generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops);
 968         if (IS_ERR(generic_phy)) {
 969                 ret = PTR_ERR(generic_phy);
 970                 dev_err(dev, "failed to create phy, %d\n", ret);
 971                 pm_runtime_disable(dev);
 972                 return ret;
 973         }
 974         qphy->phy = generic_phy;
 975
 976         dev_set_drvdata(dev, qphy);
 977         phy_set_drvdata(generic_phy, qphy);
 978
 979         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 980         if (!IS_ERR(phy_provider))
 981                 dev_info(dev, "Registered Qcom-QUSB2 phy\n");
 982         else
 983                 pm_runtime_disable(dev);
 984
 985         return PTR_ERR_OR_ZERO(phy_provider);
 986 }
 987
 988 static struct platform_driver qusb2_phy_driver = {
 989         .probe          = qusb2_phy_probe,
 990         .driver = {
 991                 .name   = "qcom-qusb2-phy",
 992                 .pm     = &qusb2_phy_pm_ops,
 993                 .of_match_table = qusb2_phy_of_match_table,
 994         },
 995 };
 996
 997 module_platform_driver(qusb2_phy_driver);
 998
 999 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
1000 MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver");
1001 MODULE_LICENSE("GPL v2");