1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
6 #ifndef QCOM_PHY_QMP_H_
7 #define QCOM_PHY_QMP_H_
9 /* Only for QMP V2 PHY - QSERDES COM registers */
10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
20 #define QSERDES_COM_SYS_CLK_CTRL 0x03c
21 #define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040
22 #define QSERDES_COM_PLL_IVCO 0x048
23 #define QSERDES_COM_LOCK_CMP1_MODE0 0x04c
24 #define QSERDES_COM_LOCK_CMP2_MODE0 0x050
25 #define QSERDES_COM_LOCK_CMP3_MODE0 0x054
26 #define QSERDES_COM_LOCK_CMP1_MODE1 0x058
27 #define QSERDES_COM_LOCK_CMP2_MODE1 0x05c
28 #define QSERDES_COM_LOCK_CMP3_MODE1 0x060
29 #define QSERDES_COM_BG_TRIM 0x070
30 #define QSERDES_COM_CLK_EP_DIV 0x074
31 #define QSERDES_COM_CP_CTRL_MODE0 0x078
32 #define QSERDES_COM_CP_CTRL_MODE1 0x07c
33 #define QSERDES_COM_PLL_RCTRL_MODE0 0x084
34 #define QSERDES_COM_PLL_RCTRL_MODE1 0x088
35 #define QSERDES_COM_PLL_CCTRL_MODE0 0x090
36 #define QSERDES_COM_PLL_CCTRL_MODE1 0x094
37 #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8
38 #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac
39 #define QSERDES_COM_RESETSM_CNTRL 0x0b4
40 #define QSERDES_COM_RESTRIM_CTRL 0x0bc
41 #define QSERDES_COM_RESCODE_DIV_NUM 0x0c4
42 #define QSERDES_COM_LOCK_CMP_EN 0x0c8
43 #define QSERDES_COM_LOCK_CMP_CFG 0x0cc
44 #define QSERDES_COM_DEC_START_MODE0 0x0d0
45 #define QSERDES_COM_DEC_START_MODE1 0x0d4
46 #define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc
47 #define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0
48 #define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4
49 #define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8
50 #define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec
51 #define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0
52 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
53 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c
54 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110
55 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114
56 #define QSERDES_COM_VCO_TUNE_CTRL 0x124
57 #define QSERDES_COM_VCO_TUNE_MAP 0x128
58 #define QSERDES_COM_VCO_TUNE1_MODE0 0x12c
59 #define QSERDES_COM_VCO_TUNE2_MODE0 0x130
60 #define QSERDES_COM_VCO_TUNE1_MODE1 0x134
61 #define QSERDES_COM_VCO_TUNE2_MODE1 0x138
62 #define QSERDES_COM_VCO_TUNE_TIMER1 0x144
63 #define QSERDES_COM_VCO_TUNE_TIMER2 0x148
64 #define QSERDES_COM_BG_CTRL 0x170
65 #define QSERDES_COM_CLK_SELECT 0x174
66 #define QSERDES_COM_HSCLK_SEL 0x178
67 #define QSERDES_COM_CORECLK_DIV 0x184
68 #define QSERDES_COM_CORE_CLK_EN 0x18c
69 #define QSERDES_COM_C_READY_STATUS 0x190
70 #define QSERDES_COM_CMN_CONFIG 0x194
71 #define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
72 #define QSERDES_COM_DEBUG_BUS0 0x1a0
73 #define QSERDES_COM_DEBUG_BUS1 0x1a4
74 #define QSERDES_COM_DEBUG_BUS2 0x1a8
75 #define QSERDES_COM_DEBUG_BUS3 0x1ac
76 #define QSERDES_COM_DEBUG_BUS_SEL 0x1b0
77 #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
79 /* Only for QMP V2 PHY - TX registers */
80 #define QSERDES_TX_EMP_POST1_LVL 0x018
81 #define QSERDES_TX_SLEW_CNTL 0x040
82 #define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054
83 #define QSERDES_TX_DEBUG_BUS_SEL 0x064
84 #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068
85 #define QSERDES_TX_LANE_MODE 0x094
86 #define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac
88 /* Only for QMP V2 PHY - RX registers */
89 #define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010
90 #define QSERDES_RX_UCDR_SO_GAIN 0x01c
91 #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040
92 #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048
93 #define QSERDES_RX_RX_TERM_BW 0x090
94 #define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4
95 #define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8
96 #define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc
97 #define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0
98 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8
99 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc
100 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0
101 #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108
102 #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c
103 #define QSERDES_RX_SIGDET_ENABLES 0x110
104 #define QSERDES_RX_SIGDET_CNTRL 0x114
105 #define QSERDES_RX_SIGDET_LVL 0x118
106 #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c
107 #define QSERDES_RX_RX_BAND 0x120
108 #define QSERDES_RX_RX_INTERFACE_MODE 0x12c
110 /* Only for QMP V2 PHY - PCS registers */
111 #define QPHY_POWER_DOWN_CONTROL 0x04
112 #define QPHY_TXDEEMPH_M6DB_V0 0x24
113 #define QPHY_TXDEEMPH_M3P5DB_V0 0x28
114 #define QPHY_ENDPOINT_REFCLK_DRIVE 0x54
115 #define QPHY_RX_IDLE_DTCT_CNTRL 0x58
116 #define QPHY_POWER_STATE_CONFIG1 0x60
117 #define QPHY_POWER_STATE_CONFIG2 0x64
118 #define QPHY_POWER_STATE_CONFIG4 0x6c
119 #define QPHY_LOCK_DETECT_CONFIG1 0x80
120 #define QPHY_LOCK_DETECT_CONFIG2 0x84
121 #define QPHY_LOCK_DETECT_CONFIG3 0x88
122 #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
123 #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
124 #define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8
125 #define QPHY_OSC_DTCT_ACTIONS 0x1AC
126 #define QPHY_RX_SIGDET_LVL 0x1D8
127 #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC
128 #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0
130 /* Only for QMP V3 & V4 PHY - DP COM registers */
131 #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
132 #define QPHY_V3_DP_COM_SW_RESET 0x04
133 #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08
134 #define QPHY_V3_DP_COM_SWI_CTRL 0x0c
135 #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10
136 #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14
137 #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c
139 /* Only for QMP V3 PHY - QSERDES COM registers */
140 #define QSERDES_V3_COM_ATB_SEL1 0x000
141 #define QSERDES_V3_COM_ATB_SEL2 0x004
142 #define QSERDES_V3_COM_FREQ_UPDATE 0x008
143 #define QSERDES_V3_COM_BG_TIMER 0x00c
144 #define QSERDES_V3_COM_SSC_EN_CENTER 0x010
145 #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014
146 #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018
147 #define QSERDES_V3_COM_SSC_PER1 0x01c
148 #define QSERDES_V3_COM_SSC_PER2 0x020
149 #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024
150 #define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028
151 #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034
152 # define QSERDES_V3_COM_BIAS_EN 0x0001
153 # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002
154 # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004
155 # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008
156 # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010
157 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020
158 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040
159 #define QSERDES_V3_COM_CLK_ENABLE1 0x038
160 #define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c
161 #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040
162 #define QSERDES_V3_COM_PLL_IVCO 0x048
163 #define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098
164 #define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c
165 #define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0
166 #define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4
167 #define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8
168 #define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac
169 #define QSERDES_V3_COM_CLK_EP_DIV 0x05c
170 #define QSERDES_V3_COM_CP_CTRL_MODE0 0x060
171 #define QSERDES_V3_COM_CP_CTRL_MODE1 0x064
172 #define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068
173 #define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c
174 #define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070
175 #define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074
176 #define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080
177 #define QSERDES_V3_COM_RESETSM_CNTRL 0x088
178 #define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c
179 #define QSERDES_V3_COM_LOCK_CMP_EN 0x090
180 #define QSERDES_V3_COM_LOCK_CMP_CFG 0x094
181 #define QSERDES_V3_COM_DEC_START_MODE0 0x0b0
182 #define QSERDES_V3_COM_DEC_START_MODE1 0x0b4
183 #define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8
184 #define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc
185 #define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0
186 #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4
187 #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8
188 #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc
189 #define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0
190 #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8
191 #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc
192 #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0
193 #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4
194 #define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec
195 #define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0
196 #define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4
197 #define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8
198 #define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc
199 #define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100
200 #define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104
201 #define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108
202 #define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c
203 #define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120
204 #define QSERDES_V3_COM_CLK_SELECT 0x138
205 #define QSERDES_V3_COM_HSCLK_SEL 0x13c
206 #define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148
207 #define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c
208 #define QSERDES_V3_COM_CORE_CLK_EN 0x154
209 #define QSERDES_V3_COM_C_READY_STATUS 0x158
210 #define QSERDES_V3_COM_CMN_CONFIG 0x15c
211 #define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164
212 #define QSERDES_V3_COM_DEBUG_BUS0 0x168
213 #define QSERDES_V3_COM_DEBUG_BUS1 0x16c
214 #define QSERDES_V3_COM_DEBUG_BUS2 0x170
215 #define QSERDES_V3_COM_DEBUG_BUS3 0x174
216 #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178
217 #define QSERDES_V3_COM_CMN_MODE 0x184
219 /* Only for QMP V3 PHY - TX registers */
220 #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000
221 #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008
222 #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c
223 # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f
224 # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020
226 #define QSERDES_V3_TX_TX_DRV_LVL 0x01c
227 # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f
228 # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020
230 #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024
231 #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028
233 #define QSERDES_V3_TX_TX_BAND 0x02c
234 #define QSERDES_V3_TX_SLEW_CNTL 0x030
235 #define QSERDES_V3_TX_INTERFACE_SELECT 0x034
236 #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c
237 #define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040
238 #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044
239 #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048
240 #define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058
241 #define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c
242 #define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060
243 #define QSERDES_V3_TX_TX_POL_INV 0x064
244 #define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068
245 #define QSERDES_V3_TX_LANE_MODE_1 0x08c
246 #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4
247 #define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0
248 #define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4
249 #define QSERDES_V3_TX_VMODE_CTRL1 0x0f0
251 /* Only for QMP V3 PHY - RX registers */
252 #define QSERDES_V3_RX_UCDR_FO_GAIN 0x008
253 #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c
254 #define QSERDES_V3_RX_UCDR_SO_GAIN 0x014
255 #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024
256 #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028
257 #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c
258 #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030
259 #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
260 #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
261 #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
262 #define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044
263 #define QSERDES_V3_RX_RX_TERM_BW 0x07c
264 #define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc
265 #define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0
266 #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8
267 #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc
268 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4
269 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8
270 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc
271 #define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8
272 #define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc
273 #define QSERDES_V3_RX_SIGDET_ENABLES 0x100
274 #define QSERDES_V3_RX_SIGDET_CNTRL 0x104
275 #define QSERDES_V3_RX_SIGDET_LVL 0x108
276 #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c
277 #define QSERDES_V3_RX_RX_BAND 0x110
278 #define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c
279 #define QSERDES_V3_RX_RX_MODE_00 0x164
280 #define QSERDES_V3_RX_RX_MODE_01 0x168
282 /* Only for QMP V3 PHY - PCS registers */
283 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
284 #define QPHY_V3_PCS_TXMGN_V0 0x00c
285 #define QPHY_V3_PCS_TXMGN_V1 0x010
286 #define QPHY_V3_PCS_TXMGN_V2 0x014
287 #define QPHY_V3_PCS_TXMGN_V3 0x018
288 #define QPHY_V3_PCS_TXMGN_V4 0x01c
289 #define QPHY_V3_PCS_TXMGN_LS 0x020
290 #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c
291 #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034
292 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
293 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028
294 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c
295 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030
296 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034
297 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038
298 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c
299 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040
300 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044
301 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048
302 #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c
303 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050
304 #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054
305 #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058
306 #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c
307 #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060
308 #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064
309 #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c
310 #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070
311 #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074
312 #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078
313 #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c
314 #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080
315 #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084
316 #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088
317 #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c
318 #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
319 #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
320 #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8
321 #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0
322 #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8
323 #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc
324 #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4
325 #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8
326 #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
327 #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
328 #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
329 #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134
330 #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138
331 #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c
332 #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140
333 #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8
334 #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac
335 #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0
336 #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc
337 #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4
338 #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
339 #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
340 #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
341 #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
342 #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
344 /* Only for QMP V3 PHY - PCS_MISC registers */
345 #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c
346 #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c
347 #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44
348 #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54
349 #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c
350 #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60
352 /* QMP PHY - DP PHY registers */
353 #define QSERDES_DP_PHY_REVISION_ID0 0x000
354 #define QSERDES_DP_PHY_REVISION_ID1 0x004
355 #define QSERDES_DP_PHY_REVISION_ID2 0x008
356 #define QSERDES_DP_PHY_REVISION_ID3 0x00c
357 #define QSERDES_DP_PHY_CFG 0x010
358 #define QSERDES_DP_PHY_PD_CTL 0x018
359 # define DP_PHY_PD_CTL_PWRDN 0x001
360 # define DP_PHY_PD_CTL_PSR_PWRDN 0x002
361 # define DP_PHY_PD_CTL_AUX_PWRDN 0x004
362 # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008
363 # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010
364 # define DP_PHY_PD_CTL_PLL_PWRDN 0x020
365 # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040
366 #define QSERDES_DP_PHY_MODE 0x01c
367 #define QSERDES_DP_PHY_AUX_CFG0 0x020
368 #define QSERDES_DP_PHY_AUX_CFG1 0x024
369 #define QSERDES_DP_PHY_AUX_CFG2 0x028
370 #define QSERDES_DP_PHY_AUX_CFG3 0x02c
371 #define QSERDES_DP_PHY_AUX_CFG4 0x030
372 #define QSERDES_DP_PHY_AUX_CFG5 0x034
373 #define QSERDES_DP_PHY_AUX_CFG6 0x038
374 #define QSERDES_DP_PHY_AUX_CFG7 0x03c
375 #define QSERDES_DP_PHY_AUX_CFG8 0x040
376 #define QSERDES_DP_PHY_AUX_CFG9 0x044
378 /* Only for QMP V3 PHY - DP PHY registers */
379 #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048
380 # define PHY_AUX_STOP_ERR_MASK 0x01
381 # define PHY_AUX_DEC_ERR_MASK 0x02
382 # define PHY_AUX_SYNC_ERR_MASK 0x04
383 # define PHY_AUX_ALIGN_ERR_MASK 0x08
384 # define PHY_AUX_REQ_ERR_MASK 0x10
386 #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c
387 #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050
389 #define QSERDES_V3_DP_PHY_VCO_DIV 0x064
390 #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c
391 #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088
393 #define QSERDES_V3_DP_PHY_SPARE0 0x0ac
394 #define DP_PHY_SPARE0_MASK 0x0f
395 #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004)
397 #define QSERDES_V3_DP_PHY_STATUS 0x0c0
399 /* Only for QMP V4 PHY - QSERDES COM registers */
400 #define QSERDES_V4_COM_BG_TIMER 0x00c
401 #define QSERDES_V4_COM_SSC_EN_CENTER 0x010
402 #define QSERDES_V4_COM_SSC_PER1 0x01c
403 #define QSERDES_V4_COM_SSC_PER2 0x020
404 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024
405 #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028
406 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030
407 #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034
408 #define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044
409 #define QSERDES_V4_COM_CLK_ENABLE1 0x048
410 #define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c
411 #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050
412 #define QSERDES_V4_COM_PLL_IVCO 0x058
413 #define QSERDES_V4_COM_CMN_IPTRIM 0x060
414 #define QSERDES_V4_COM_CP_CTRL_MODE0 0x074
415 #define QSERDES_V4_COM_CP_CTRL_MODE1 0x078
416 #define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c
417 #define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080
418 #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084
419 #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088
420 #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094
421 #define QSERDES_V4_COM_RESETSM_CNTRL 0x09c
422 #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4
423 #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac
424 #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0
425 #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4
426 #define QSERDES_V4_COM_DEC_START_MODE0 0x0bc
427 #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8
428 #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4
429 #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc
430 #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0
431 #define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4
432 #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8
433 #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc
434 #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0
435 #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec
436 #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0
437 #define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108
438 #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c
439 #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110
440 #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114
441 #define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118
442 #define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c
443 #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124
444 #define QSERDES_V4_COM_CMN_STATUS 0x140
445 #define QSERDES_V4_COM_CLK_SELECT 0x154
446 #define QSERDES_V4_COM_HSCLK_SEL 0x158
447 #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c
448 #define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168
449 #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c
450 #define QSERDES_V4_COM_CORE_CLK_EN 0x174
451 #define QSERDES_V4_COM_C_READY_STATUS 0x178
452 #define QSERDES_V4_COM_CMN_CONFIG 0x17c
453 #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184
454 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
455 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
456 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
457 #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
458 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
460 /* Only for QMP V4 PHY - TX registers */
461 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x08
462 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x0c
463 #define QSERDES_V4_TX_TX_DRV_LVL 0x14
464 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x1c
465 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x20
466 #define QSERDES_V4_TX_TX_BAND 0x24
467 #define QSERDES_V4_TX_INTERFACE_SELECT 0x2c
468 #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34
469 #define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38
470 #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c
471 #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40
472 #define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x54
473 #define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x58
474 #define QSERDES_V4_TX_TX_POL_INV 0x5c
475 #define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x60
476 #define QSERDES_V4_TX_LANE_MODE_1 0x84
477 #define QSERDES_V4_TX_LANE_MODE_2 0x88
478 #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c
479 #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8
480 #define QSERDES_V4_TX_TX_INTERFACE_MODE 0xbc
481 #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8
482 #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC
483 #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0
484 #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4
485 #define QSERDES_V4_TX_VMODE_CTRL1 0xe8
486 #define QSERDES_V4_TX_PI_QEC_CTRL 0x104
488 /* Only for QMP V4 PHY - RX registers */
489 #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008
490 #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014
491 #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030
492 #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
493 #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
494 #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
495 #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044
496 #define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048
497 #define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c
498 #define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050
499 #define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054
500 #define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058
501 #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060
502 #define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064
503 #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068
504 #define QSERDES_V4_RX_AC_JTAG_MODE 0x078
505 #define QSERDES_V4_RX_RX_TERM_BW 0x080
506 #define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4
507 #define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8
508 #define QSERDES_V4_RX_GM_CAL 0x0dc
509 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
510 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
511 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
512 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
513 #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8
514 #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
515 #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100
516 #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
517 #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
518 #define QSERDES_V4_RX_SIGDET_ENABLES 0x118
519 #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c
520 #define QSERDES_V4_RX_SIGDET_LVL 0x120
521 #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124
522 #define QSERDES_V4_RX_RX_BAND 0x128
523 #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170
524 #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174
525 #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178
526 #define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c
527 #define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180
528 #define QSERDES_V4_RX_RX_MODE_01_LOW 0x184
529 #define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188
530 #define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c
531 #define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190
532 #define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194
533 #define QSERDES_V4_RX_RX_MODE_10_LOW 0x198
534 #define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c
535 #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0
536 #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4
537 #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8
538 #define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4
539 #define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8
540 #define QSERDES_V4_RX_DCC_CTRL1 0x1bc
541 #define QSERDES_V4_RX_VTH_CODE 0x1c4
543 /* Only for QMP V4 PHY - DP PHY registers */
544 #define QSERDES_V4_DP_PHY_CFG_1 0x014
545 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054
546 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058
547 #define QSERDES_V4_DP_PHY_VCO_DIV 0x070
548 #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078
549 #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c
550 #define QSERDES_V4_DP_PHY_SPARE0 0x0c8
551 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
552 #define QSERDES_V4_DP_PHY_STATUS 0x0dc
554 /* Only for QMP V4 PHY - UFS PCS registers */
555 #define QPHY_V4_PCS_UFS_PHY_START 0x000
556 #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004
557 #define QPHY_V4_PCS_UFS_SW_RESET 0x008
558 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
559 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
560 #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c
561 #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
562 #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
563 #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
564 #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
565 #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
566 #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
567 #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148
568 #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
569 #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158
570 #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160
571 #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168
572 #define QPHY_V4_PCS_UFS_READY_STATUS 0x180
573 #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
574 #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
576 /* PCIE GEN3 COM registers */
577 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
578 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
579 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
580 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
581 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
582 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
583 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
584 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
585 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
586 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
587 #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70
588 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78
589 #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c
590 #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98
591 #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4
592 #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8
593 #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0
594 #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4
595 #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc
596 #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0
597 #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc
598 #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0
599 #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8
600 #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100
601 #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108
602 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c
603 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120
604 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124
605 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128
606 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c
607 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130
608 #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150
609 #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158
610 #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178
611 #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8
612 #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc
613 #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0
614 #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0
615 #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8
616 #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0
617 #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc
618 #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c
619 #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224
620 #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228
621 #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c
623 /* PCIE GEN3 QHP Lane registers */
624 #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc
625 #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10
626 #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14
627 #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18
628 #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60
629 #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64
630 #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c
631 #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0
632 #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4
633 #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8
634 #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0
635 #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4
636 #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8
637 #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc
638 #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0
639 #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc
640 #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100
641 #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108
642 #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114
643 #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118
644 #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c
645 #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120
646 #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124
647 #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128
648 #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130
649 #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134
650 #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138
651 #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c
652 #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154
653 #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160
654 #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168
655 #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c
656 #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178
657 #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180
658 #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184
659 #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188
660 #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c
661 #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190
662 #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194
663 #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198
664 #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c
665 #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4
666 #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0
667 #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4
668 #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8
669 #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230
670 #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234
671 #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238
672 #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4
673 #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8
674 #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac
675 #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0
676 #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8
677 #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0
678 #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4
679 #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc
681 /* PCIE GEN3 PCS registers */
682 #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c
683 #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40
684 #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54
685 #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68
686 #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c
687 #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c
688 #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174
690 /* Only for QMP V4 PHY - USB/PCIe PCS registers */
691 #define QPHY_V4_PCS_SW_RESET 0x000
692 #define QPHY_V4_PCS_REVISION_ID0 0x004
693 #define QPHY_V4_PCS_REVISION_ID1 0x008
694 #define QPHY_V4_PCS_REVISION_ID2 0x00c
695 #define QPHY_V4_PCS_REVISION_ID3 0x010
696 #define QPHY_V4_PCS_PCS_STATUS1 0x014
697 #define QPHY_V4_PCS_PCS_STATUS2 0x018
698 #define QPHY_V4_PCS_PCS_STATUS3 0x01c
699 #define QPHY_V4_PCS_PCS_STATUS4 0x020
700 #define QPHY_V4_PCS_PCS_STATUS5 0x024
701 #define QPHY_V4_PCS_PCS_STATUS6 0x028
702 #define QPHY_V4_PCS_PCS_STATUS7 0x02c
703 #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030
704 #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034
705 #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038
706 #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c
707 #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040
708 #define QPHY_V4_PCS_START_CONTROL 0x044
709 #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048
710 #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c
711 #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050
712 #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054
713 #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058
714 #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c
715 #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060
716 #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064
717 #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068
718 #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c
719 #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070
720 #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074
721 #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078
722 #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c
723 #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080
724 #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084
725 #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088
726 #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c
727 #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090
728 #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094
729 #define QPHY_V4_PCS_FLL_CNTRL1 0x098
730 #define QPHY_V4_PCS_FLL_CNTRL2 0x09c
731 #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0
732 #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4
733 #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8
734 #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac
735 #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0
736 #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4
737 #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8
738 #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc
739 #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0
740 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4
741 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8
742 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc
743 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0
744 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4
745 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8
746 #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc
747 #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0
748 #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4
749 #define QPHY_V4_PCS_BIST_CTRL 0x0e8
750 #define QPHY_V4_PCS_PRBS_POLY0 0x0ec
751 #define QPHY_V4_PCS_PRBS_POLY1 0x0f0
752 #define QPHY_V4_PCS_FIXED_PAT0 0x0f4
753 #define QPHY_V4_PCS_FIXED_PAT1 0x0f8
754 #define QPHY_V4_PCS_FIXED_PAT2 0x0fc
755 #define QPHY_V4_PCS_FIXED_PAT3 0x100
756 #define QPHY_V4_PCS_FIXED_PAT4 0x104
757 #define QPHY_V4_PCS_FIXED_PAT5 0x108
758 #define QPHY_V4_PCS_FIXED_PAT6 0x10c
759 #define QPHY_V4_PCS_FIXED_PAT7 0x110
760 #define QPHY_V4_PCS_FIXED_PAT8 0x114
761 #define QPHY_V4_PCS_FIXED_PAT9 0x118
762 #define QPHY_V4_PCS_FIXED_PAT10 0x11c
763 #define QPHY_V4_PCS_FIXED_PAT11 0x120
764 #define QPHY_V4_PCS_FIXED_PAT12 0x124
765 #define QPHY_V4_PCS_FIXED_PAT13 0x128
766 #define QPHY_V4_PCS_FIXED_PAT14 0x12c
767 #define QPHY_V4_PCS_FIXED_PAT15 0x130
768 #define QPHY_V4_PCS_TXMGN_CONFIG 0x134
769 #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138
770 #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c
771 #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140
772 #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144
773 #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148
774 #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c
775 #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150
776 #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154
777 #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158
778 #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c
779 #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160
780 #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164
781 #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168
782 #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c
783 #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170
784 #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174
785 #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178
786 #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c
787 #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180
788 #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184
789 #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188
790 #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c
791 #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
792 #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
793 #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198
794 #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c
795 #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0
796 #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4
797 #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8
798 #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac
799 #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0
800 #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4
801 #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8
802 #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc
803 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0
804 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4
805 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8
806 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc
807 #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0
808 #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4
809 #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8
810 #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc
811 #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0
812 #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4
813 #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8
814 #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec
815 #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300
816 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304
817 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308
818 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c
819 #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310
820 #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314
821 #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318
822 #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c
823 #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320
824 #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324
825 #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328
826 #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c
827 #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330
828 #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334
829 #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338
830 #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c
831 #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340
832 #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344
833 #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348
834 #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c
835 #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350
836 #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354
837 #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358
839 /* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */
840 #define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618
841 #define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638
843 /* Only for QMP V4 PHY - PCS_MISC registers */
844 #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00
845 #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04
846 #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08
847 #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c
848 #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10
849 #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14
851 /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */
852 #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
853 #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14
854 #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c
855 #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40
856 #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48
857 #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50
858 #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90
859 #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4
860 #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4
861 #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc
862 #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0
864 /* Only for QMP V5 PHY - QSERDES COM registers */
865 #define QSERDES_V5_COM_PLL_IVCO 0x058
866 #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074
867 #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078
868 #define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c
869 #define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080
870 #define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084
871 #define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088
872 #define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094
873 #define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4
874 #define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac
875 #define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0
876 #define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4
877 #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc
878 #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8
879 #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4
880 #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c
881 #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124
882 #define QSERDES_V5_COM_HSCLK_SEL 0x158
883 #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c
884 #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
885 #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
886 #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4
887 #define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc
888 #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8
890 /* Only for QMP V5 PHY - TX registers */
891 #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34
892 #define QSERDES_V5_TX_RES_CODE_LANE_RX 0x38
893 #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x3c
894 #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x40
895 #define QSERDES_V5_TX_LANE_MODE_1 0x84
896 #define QSERDES_V5_TX_LANE_MODE_2 0x88
897 #define QSERDES_V5_TX_LANE_MODE_3 0x8c
898 #define QSERDES_V5_TX_LANE_MODE_4 0x90
899 #define QSERDES_V5_TX_LANE_MODE_5 0x94
900 #define QSERDES_V5_TX_RCV_DETECT_LVL_2 0xa4
901 #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0xc0
902 #define QSERDES_V5_TX_PI_QEC_CTRL 0xe4
903 #define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178
904 #define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c
905 #define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180
906 #define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184
908 /* Only for QMP V5 PHY - RX registers */
909 #define QSERDES_V5_RX_UCDR_FO_GAIN 0x008
910 #define QSERDES_V5_RX_UCDR_SO_GAIN 0x014
911 #define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030
912 #define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
913 #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
914 #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
915 #define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044
916 #define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048
917 #define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c
918 #define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050
919 #define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054
920 #define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058
921 #define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060
922 #define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064
923 #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068
924 #define QSERDES_V5_RX_AC_JTAG_MODE 0x078
925 #define QSERDES_V5_RX_RX_TERM_BW 0x080
926 #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4
927 #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8
928 #define QSERDES_V5_RX_GM_CAL 0x0dc
929 #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8
930 #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec
931 #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0
932 #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4
933 #define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8
934 #define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc
935 #define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100
936 #define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110
937 #define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114
938 #define QSERDES_V5_RX_SIGDET_ENABLES 0x118
939 #define QSERDES_V5_RX_SIGDET_CNTRL 0x11c
940 #define QSERDES_V5_RX_SIGDET_LVL 0x120
941 #define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124
942 #define QSERDES_V5_RX_RX_BAND 0x128
943 #define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c
944 #define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160
945 #define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164
946 #define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168
947 #define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c
948 #define QSERDES_V5_RX_RX_MODE_01_LOW 0x170
949 #define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174
950 #define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178
951 #define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c
952 #define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180
953 #define QSERDES_V5_RX_RX_MODE_10_LOW 0x184
954 #define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188
955 #define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c
956 #define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190
957 #define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194
958 #define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0
959 #define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
960 #define QSERDES_V5_RX_DCC_CTRL1 0x1a8
961 #define QSERDES_V5_RX_VTH_CODE 0x1b0
963 /* Only for QMP V5 PHY - UFS PCS registers */
964 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
965 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
966 #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
967 #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
968 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
969 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
970 #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
971 #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
972 #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
973 #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154
974 #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158
975 #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160
976 #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168
977 #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
978 #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
980 /* Only for QMP V5 PHY - USB3 have different offsets than V4 */
981 #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x300
982 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304
983 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308
984 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c
985 #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310
986 #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314
987 #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318
988 #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x31c
989 #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x320
990 #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324
991 #define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x328
992 #define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x32c
993 #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x330
994 #define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x334
995 #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x338
996 #define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x33c
997 #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x340
998 #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x344
999 #define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x348
1000 #define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x34c
1001 #define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x350
1002 #define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x354
1003 #define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x358
1004 #define QPHY_V5_PCS_USB3_TEST_CONTROL 0x35c
1005 #define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x360
1007 /* Only for QMP V5 PHY - UNI has 0x1000 offset for PCS_USB3 regs */
1008 #define QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x1018
1009 #define QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x103c