drivers/phy/qualcomm/phy-qcom-qmp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_address.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/reset.h>
  21 #include <linux/slab.h>
  22
  23 #include <dt-bindings/phy/phy.h>
  24
  25 #include "phy-qcom-qmp.h"
  26
  27 /* QPHY_SW_RESET bit */
  28 #define SW_RESET                                BIT(0)
  29 /* QPHY_POWER_DOWN_CONTROL */
  30 #define SW_PWRDN                                BIT(0)
  31 #define REFCLK_DRV_DSBL                         BIT(1)
  32 /* QPHY_START_CONTROL bits */
  33 #define SERDES_START                            BIT(0)
  34 #define PCS_START                               BIT(1)
  35 #define PLL_READY_GATE_EN                       BIT(3)
  36 /* QPHY_PCS_STATUS bit */
  37 #define PHYSTATUS                               BIT(6)
  38 #define PHYSTATUS_4_20                          BIT(7)
  39 /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
  40 #define PCS_READY                               BIT(0)
  41
  42 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  43 /* DP PHY soft reset */
  44 #define SW_DPPHY_RESET                          BIT(0)
  45 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  46 #define SW_DPPHY_RESET_MUX                      BIT(1)
  47 /* USB3 PHY soft reset */
  48 #define SW_USB3PHY_RESET                        BIT(2)
  49 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  50 #define SW_USB3PHY_RESET_MUX                    BIT(3)
  51
  52 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  53 #define USB3_MODE                               BIT(0) /* enables USB3 mode */
  54 #define DP_MODE                                 BIT(1) /* enables DP mode */
  55
  56 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
  57 #define ARCVR_DTCT_EN                           BIT(0)
  58 #define ALFPS_DTCT_EN                           BIT(1)
  59 #define ARCVR_DTCT_EVENT_SEL                    BIT(4)
  60
  61 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
  62 #define IRQ_CLEAR                               BIT(0)
  63
  64 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
  65 #define RCVR_DETECT                             BIT(0)
  66
  67 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
  68 #define CLAMP_EN                                BIT(0) /* enables i/o clamp_n */
  69
  70 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  71 #define POWER_DOWN_DELAY_US_MIN                 10
  72 #define POWER_DOWN_DELAY_US_MAX                 11
  73
  74 #define MAX_PROP_NAME                           32
  75
  76 /* Define the assumed distance between lanes for underspecified device trees. */
  77 #define QMP_PHY_LEGACY_LANE_STRIDE              0x400
  78
  79 struct qmp_phy_init_tbl {
  80         unsigned int offset;
  81         unsigned int val;
  82         /*
  83          * register part of layout ?
  84          * if yes, then offset gives index in the reg-layout
  85          */
  86         bool in_layout;
  87         /*
  88          * mask of lanes for which this register is written
  89          * for cases when second lane needs different values
  90          */
  91         u8 lane_mask;
  92 };
  93
  94 #define QMP_PHY_INIT_CFG(o, v)          \
  95         {                               \
  96                 .offset = o,            \
  97                 .val = v,               \
  98                 .lane_mask = 0xff,      \
  99         }
 100
 101 #define QMP_PHY_INIT_CFG_L(o, v)        \
 102         {                               \
 103                 .offset = o,            \
 104                 .val = v,               \
 105                 .in_layout = true,      \
 106                 .lane_mask = 0xff,      \
 107         }
 108
 109 #define QMP_PHY_INIT_CFG_LANE(o, v, l)  \
 110         {                               \
 111                 .offset = o,            \
 112                 .val = v,               \
 113                 .lane_mask = l,         \
 114         }
 115
 116 /* set of registers with offsets different per-PHY */
 117 enum qphy_reg_layout {
 118         /* Common block control registers */
 119         QPHY_COM_SW_RESET,
 120         QPHY_COM_POWER_DOWN_CONTROL,
 121         QPHY_COM_START_CONTROL,
 122         QPHY_COM_PCS_READY_STATUS,
 123         /* PCS registers */
 124         QPHY_PLL_LOCK_CHK_DLY_TIME,
 125         QPHY_FLL_CNTRL1,
 126         QPHY_FLL_CNTRL2,
 127         QPHY_FLL_CNT_VAL_L,
 128         QPHY_FLL_CNT_VAL_H_TOL,
 129         QPHY_FLL_MAN_CODE,
 130         QPHY_SW_RESET,
 131         QPHY_START_CTRL,
 132         QPHY_PCS_READY_STATUS,
 133         QPHY_PCS_STATUS,
 134         QPHY_PCS_AUTONOMOUS_MODE_CTRL,
 135         QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
 136         QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
 137         QPHY_PCS_POWER_DOWN_CONTROL,
 138         /* PCS_MISC registers */
 139         QPHY_PCS_MISC_TYPEC_CTRL,
 140         /* Keep last to ensure regs_layout arrays are properly initialized */
 141         QPHY_LAYOUT_SIZE
 142 };
 143
 144 static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 145         [QPHY_START_CTRL]               = 0x00,
 146         [QPHY_PCS_READY_STATUS]         = 0x168,
 147 };
 148
 149 static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = {
 150         [QPHY_SW_RESET]                         = 0x00,
 151         [QPHY_START_CTRL]                       = 0x44,
 152         [QPHY_PCS_STATUS]                       = 0x14,
 153         [QPHY_PCS_POWER_DOWN_CONTROL]           = 0x40,
 154 };
 155
 156 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
 157         [QPHY_COM_SW_RESET]             = 0x400,
 158         [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
 159         [QPHY_COM_START_CONTROL]        = 0x408,
 160         [QPHY_COM_PCS_READY_STATUS]     = 0x448,
 161         [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
 162         [QPHY_FLL_CNTRL1]               = 0xc4,
 163         [QPHY_FLL_CNTRL2]               = 0xc8,
 164         [QPHY_FLL_CNT_VAL_L]            = 0xcc,
 165         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
 166         [QPHY_FLL_MAN_CODE]             = 0xd4,
 167         [QPHY_SW_RESET]                 = 0x00,
 168         [QPHY_START_CTRL]               = 0x08,
 169         [QPHY_PCS_STATUS]               = 0x174,
 170 };
 171
 172 static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 173         [QPHY_FLL_CNTRL1]               = 0xc0,
 174         [QPHY_FLL_CNTRL2]               = 0xc4,
 175         [QPHY_FLL_CNT_VAL_L]            = 0xc8,
 176         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
 177         [QPHY_FLL_MAN_CODE]             = 0xd0,
 178         [QPHY_SW_RESET]                 = 0x00,
 179         [QPHY_START_CTRL]               = 0x08,
 180         [QPHY_PCS_STATUS]               = 0x17c,
 181         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
 182         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
 183         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
 184 };
 185
 186 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 187         [QPHY_SW_RESET]                 = 0x00,
 188         [QPHY_START_CTRL]               = 0x08,
 189         [QPHY_PCS_STATUS]               = 0x174,
 190         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
 191         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
 192         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
 193 };
 194
 195 static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
 196         [QPHY_SW_RESET]                 = 0x00,
 197         [QPHY_START_CTRL]               = 0x08,
 198         [QPHY_PCS_STATUS]               = 0x174,
 199 };
 200
 201 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
 202         [QPHY_SW_RESET]                 = 0x00,
 203         [QPHY_START_CTRL]               = 0x08,
 204         [QPHY_PCS_STATUS]               = 0x2ac,
 205 };
 206
 207 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 208         [QPHY_SW_RESET]                 = 0x00,
 209         [QPHY_START_CTRL]               = 0x44,
 210         [QPHY_PCS_STATUS]               = 0x14,
 211         [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 212         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
 213         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
 214 };
 215
 216 static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 217         [QPHY_SW_RESET]                 = 0x00,
 218         [QPHY_START_CTRL]               = 0x44,
 219         [QPHY_PCS_STATUS]               = 0x14,
 220         [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 221         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
 222         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x614,
 223 };
 224
 225 static const unsigned int sm8350_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 226         [QPHY_SW_RESET]                 = 0x00,
 227         [QPHY_START_CTRL]               = 0x44,
 228         [QPHY_PCS_STATUS]               = 0x14,
 229         [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 230         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x1008,
 231         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x1014,
 232 };
 233
 234 static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 235         [QPHY_SW_RESET]                 = 0x00,
 236         [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
 237         [QPHY_START_CTRL]               = 0x08,
 238         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
 239         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
 240         [QPHY_PCS_STATUS]               = 0x174,
 241         [QPHY_PCS_MISC_TYPEC_CTRL]      = 0x00,
 242 };
 243
 244 static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 245         [QPHY_START_CTRL]               = 0x00,
 246         [QPHY_PCS_READY_STATUS]         = 0x160,
 247 };
 248
 249 static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 250         [QPHY_START_CTRL]               = 0x00,
 251         [QPHY_PCS_READY_STATUS]         = 0x168,
 252 };
 253
 254 static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = {
 255         [QPHY_SW_RESET]                 = 0x00,
 256         [QPHY_START_CTRL]               = 0x44,
 257         [QPHY_PCS_STATUS]               = 0x14,
 258         [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 259 };
 260
 261 static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 262         [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
 263         [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
 264         [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
 265 };
 266
 267 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
 268         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
 269         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 270         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 271         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 272         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 273         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 274         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 275         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 276         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 277         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 278         /* PLL and Loop filter settings */
 279         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 280         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 281         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 282         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 283         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 284         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 285         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 286         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 287         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 288         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 289         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 290         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 291         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 292         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 293         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 294         /* SSC settings */
 295         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 296         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 297         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 298         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 299         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 300         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 301         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 302 };
 303
 304 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
 305         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
 306         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 307         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 308         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
 309         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 310         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 311         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 312         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 313         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
 314 };
 315
 316 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
 317         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 318         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
 319         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 320         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 321         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 322         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 323         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
 324         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 325         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 326         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 327         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 328         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 329         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 330         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 331         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 332         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 333         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 334         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 335         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 336         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 337         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
 338         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
 339         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
 340 };
 341
 342 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
 343         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
 344         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 345         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 346         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 347         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
 348         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 349         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 350         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 351         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
 352         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 353         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 354         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 355         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
 356         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 357         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 358         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 359         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 360         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 361         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
 362         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
 363         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 364         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
 365         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 366         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
 367         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 368         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 369         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 370         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 371         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 372         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 373         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 374         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 375         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
 376         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 377         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 378         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 379         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
 380         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 381         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 382         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 383         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 384         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 385         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
 386 };
 387
 388 static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
 389         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 390         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 391 };
 392
 393 static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
 394         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 395         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
 396         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
 397         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 398         QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
 399         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 400         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
 401         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 402         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 403         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
 404 };
 405
 406 static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
 407         QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
 408         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
 409         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 410
 411         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
 412
 413         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
 414         QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
 415         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
 416         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
 417         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
 418 };
 419
 420 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
 421         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 422         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 423         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
 424         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 425         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 426         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 427         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 428         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 429         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 430         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 431         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 432         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 433         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 434         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 435         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 436         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 437         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 438         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
 439         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
 440         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
 441         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 442         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 443         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 444         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 445         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
 446         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 447         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
 448         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 449         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 450         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 451         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
 452         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 453         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 454         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 455         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 456         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 457         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 458         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 459         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 460         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 461         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 462         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 463 };
 464
 465 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
 466         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 467         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 468         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 469         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 470 };
 471
 472 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
 473         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 474         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
 475         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 476         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
 477         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 478         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 479         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 480         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 481         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 482         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
 483         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 484         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 485         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 486         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 487 };
 488
 489 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
 490         QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 491         QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 492         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 493         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 494         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 495         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 496         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 497         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 498         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
 499         QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 500 };
 501
 502 static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
 503         QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
 504         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
 505         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
 506         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 507         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 508         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 509         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 510         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
 511         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 512         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
 513         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
 514         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
 515         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 516         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 517         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 518         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 519         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
 520         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
 521         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
 522         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 523         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
 524         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
 525         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
 526         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 527         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 528         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 529         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 530         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 531         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
 532         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
 533         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
 534         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
 535         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 536         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
 537         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
 538         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
 539         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
 540         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
 541         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
 542         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
 543         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
 544         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 545         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
 546         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
 547         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
 548         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
 549         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
 550 };
 551
 552 static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
 553         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 554         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
 555 };
 556
 557 static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
 558         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
 559         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
 560         QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
 561         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
 562         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
 563         QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
 564         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
 565         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
 566         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
 567         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
 568         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
 569 };
 570
 571 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
 572         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 573         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 574         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 575         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 576         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 577         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 578         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 579         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 580         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
 581         /* PLL and Loop filter settings */
 582         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 583         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 584         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 585         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 586         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 587         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 588         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 589         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 590         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 591         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 592         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 593         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 594         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 595         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 596         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 597         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 598         /* SSC settings */
 599         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 600         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 601         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 602         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 603         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 604         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 605         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 606 };
 607
 608 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
 609         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 610         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 611         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 612 };
 613
 614 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
 615         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 616         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 617         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 618         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 619         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
 620         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 621         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 622         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 623         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
 624         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 625 };
 626
 627 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
 628         /* FLL settings */
 629         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
 630         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
 631         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
 632         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
 633         QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
 634
 635         /* Lock Det settings */
 636         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
 637         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
 638         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
 639         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
 640 };
 641
 642 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
 643         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
 644         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
 645         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
 646         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
 647         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
 648         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
 649         QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
 650         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
 651         QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
 652         QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
 653         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
 654         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
 655         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
 656         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
 657         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
 658         QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
 659         QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
 660         QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
 661         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
 662         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
 663         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
 664         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
 665         QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
 666         QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
 667         QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
 668         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
 669         QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
 670         QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
 671         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
 672         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
 673         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
 674         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
 675         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
 676         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
 677         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
 678         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
 679         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
 680         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
 681         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
 682         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
 683         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
 684         QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
 685         QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
 686         QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
 687         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
 688         QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
 689 };
 690
 691 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
 692         QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
 693         QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
 694         QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
 695 };
 696
 697 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
 698         QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
 699         QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
 700         QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 701         QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
 702         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0x61),
 703         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 704         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
 705         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
 706         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
 707         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
 708         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 709         QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
 710         QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
 711         QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
 712         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
 713         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x01),
 714         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
 715         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
 716         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
 717         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
 718         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
 719         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
 720         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
 721         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
 722         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
 723         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
 724         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
 725         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
 726         QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
 727         QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
 728 };
 729
 730 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
 731         QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
 732         QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
 733         QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
 734         QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
 735         QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 736         QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
 737         QMP_PHY_INIT_CFG(PCS_COM_EQ_CONFIG5, 0x01),
 738         QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
 739         QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
 740         QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
 741         QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 742         QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 743         QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
 744         QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
 745         QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_PRE, 0x00),
 746         QMP_PHY_INIT_CFG(PCS_PCIE_PRESET_P10_POST, 0x58),
 747 };
 748
 749 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
 750         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
 751         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 752         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
 753         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
 754         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
 755         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 756         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 757         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
 758         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
 759         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
 760         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
 761         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
 762         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
 763         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 764         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
 765         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
 766         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 767         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
 768         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 769         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 770         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
 771         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
 772         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
 773         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 774         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
 775         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 776         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
 777         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 778         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 779         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
 780         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 781         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
 782         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
 783         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 784         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
 785         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
 786         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
 787         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 788         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 789         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 790 };
 791
 792 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
 793         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 794         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
 795         QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
 796         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 797         QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
 798         QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
 799 };
 800
 801 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
 802         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 803         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 804         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
 805         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
 806         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 807         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 808         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
 809 };
 810
 811 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
 812         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
 813         QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
 814         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
 815         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
 816         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
 817         QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
 818         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
 819         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
 820         QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
 821         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
 822         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
 823         QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
 824         QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
 825 };
 826
 827 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
 828         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 829         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 830         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
 831         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 832         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 833         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 834         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 835         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 836         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 837         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 838         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 839         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 840         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 841         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 842         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 843         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 844         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 845         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 846         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 847         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 848         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 849         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 850         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 851         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 852         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 853         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 854         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 855         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
 856         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 857         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 858         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
 859         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 860         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 861         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 862         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 863         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 864         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 865         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 866         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 867         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 868         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 869         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 870 };
 871
 872 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
 873         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 874         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 875         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 876         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 877 };
 878
 879 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
 880         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 881         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
 882         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 883         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
 884         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 885         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 886         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 887         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 888         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 889         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
 890         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
 891         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
 892         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 893         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 894         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 895         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 896 };
 897
 898 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
 899         QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 900
 901         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 902         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 903         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 904         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 905         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 906
 907         QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 908         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 909         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 910         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 911         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 912         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 913         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 914
 915         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
 916         QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 917         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
 918
 919         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
 920 };
 921
 922 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
 923         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
 924         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
 925         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
 926         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
 927         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
 928 };
 929
 930 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
 931         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
 932         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
 933         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
 934         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
 935         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
 936         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
 937         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
 938         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
 939         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
 940         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
 941         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
 942         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
 943         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
 944         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
 945         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
 946         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
 947         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
 948         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
 949         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
 950         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
 951         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
 952         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
 953         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
 954         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
 955         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
 956         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
 957         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
 958         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
 959         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
 960         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
 961         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 962         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
 963         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
 964         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
 965         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
 966         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
 967         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
 968         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
 969         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
 970         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
 971         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
 972         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
 973         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
 974         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
 975         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
 976 };
 977
 978 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
 979         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
 980         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
 981         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
 982         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
 983         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
 984         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
 985         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
 986         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
 987         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
 988         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
 989         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
 990         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
 991         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
 992         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
 993         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
 994         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
 995         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
 996         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
 997         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
 998         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
 999         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
1000         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
1001         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
1002         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
1003         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
1004         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
1005         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
1006         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
1007         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
1008         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
1009         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
1010         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
1011         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
1012         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
1013         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
1014         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
1015         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
1016         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
1017         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
1018         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
1019         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
1020         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
1021         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
1022         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
1023         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
1024         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
1025         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
1026         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
1027         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
1028         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
1029         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
1030         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
1031         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
1032         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
1033         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
1034         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
1035 };
1036
1037 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
1038 };
1039
1040 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
1041         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
1042         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
1043         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
1044         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
1045         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
1046         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
1047         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
1048 };
1049
1050 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
1051         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1052         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1053         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
1054         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1055         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1056         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1057         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
1058         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1059         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1060         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1061         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1062         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1063         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1064         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1065         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1066         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1067         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1068         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1069         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1070         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1071         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1072         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1073         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1074         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1075         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1076         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1077         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1078         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1079         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
1080         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1081         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1082         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1083         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1084         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1085         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1086         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1087 };
1088
1089 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
1090         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1091         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1092         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1093         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
1094         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1095 };
1096
1097 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
1098         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1099         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
1100         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1101         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
1102         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
1103         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1104         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
1105         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
1106         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1107         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1108         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1109         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1110         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1111         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1112         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1113         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
1114         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
1115         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1116         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1117         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1118         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1119 };
1120
1121 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
1122         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
1123         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1124         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1125         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1126         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
1127         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
1128         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1129 };
1130
1131 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
1132         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
1133         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1134         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1135         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1136         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
1137         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
1138         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1139 };
1140
1141 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
1142         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1143         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
1144         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
1145         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
1146         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
1147         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
1148         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
1149 };
1150
1151 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
1152         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
1153         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
1154         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
1155         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
1156         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
1157         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
1158         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
1159 };
1160
1161 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
1162         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
1163         QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
1164         QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
1165         QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
1166         QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
1167         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
1168         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
1169         QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1170         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
1171         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
1172         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
1173         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
1174         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
1175         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1176         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1177 };
1178
1179 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
1180         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1181         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1182         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1183         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1184         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1185         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1186         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1187         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
1188         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1189 };
1190
1191 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
1192         /* FLL settings */
1193         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1194         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1195         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1196         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1197         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1198
1199         /* Lock Det settings */
1200         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1201         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1202         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1203         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1204
1205         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
1206         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1207         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1208         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1209         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1210         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1211         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1212         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1213         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1214         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
1215         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1216         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1217         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1218         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1219         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
1220         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1221         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1222         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1223         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1224
1225         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1226         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1227         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1228         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1229         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1230         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1231         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1232         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1233         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1234         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1235         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1236 };
1237
1238 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
1239         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1240         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1241         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1242         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1243         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1244         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1245         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1246         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1247         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1248         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1249         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1250         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1251         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1252         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1253         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1254         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1255         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1256         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1257         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1258         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1259         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1260         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1261         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1262         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1263         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1264         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1265         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1266         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1267         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
1268         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1269         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1270         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1271         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1272         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1273         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1274         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1275 };
1276
1277 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
1278         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1279         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1280         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
1281         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
1282         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1283 };
1284
1285 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
1286         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
1287         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
1288         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1289         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1290         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1291         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1292         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1293         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1294         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1295         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1296         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1297 };
1298
1299 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
1300         /* FLL settings */
1301         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1302         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1303         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1304         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1305         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1306
1307         /* Lock Det settings */
1308         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1309         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1310         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1311         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1312
1313         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
1314         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1315         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1316         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
1317         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
1318         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
1319         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
1320         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1321         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1322         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
1323         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1324         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1325         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1326         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1327         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
1328         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1329         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1330         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1331         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1332
1333         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1334         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1335         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1336         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1337         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1338         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1339         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1340         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1341         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1342         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1343         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1344
1345         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
1346         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
1347 };
1348
1349 static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
1350         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
1351         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
1352         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
1353         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
1354         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
1355         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
1356         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
1357         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
1358         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
1359         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
1360         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
1361         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
1362         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
1363         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
1364         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
1365         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
1366         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
1367         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
1368         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
1369         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
1370         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
1371         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
1372         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
1373         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
1374         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
1375         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
1376         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1377         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
1378         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
1379         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
1380         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
1381         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
1382         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
1383         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
1384         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
1385         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
1386         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
1387         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
1388         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
1389         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
1390         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1391         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
1392         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
1393         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
1394         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
1395         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
1396         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
1397         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
1398         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
1399         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
1400
1401         /* Rate B */
1402         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
1403 };
1404
1405 static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = {
1406         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
1407         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
1408 };
1409
1410 static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
1411         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
1412         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
1413         QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
1414         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
1415         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
1416         QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
1417         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
1418         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
1419         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
1420         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
1421         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
1422         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1423         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1424         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
1425         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
1426 };
1427
1428 static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
1429         QMP_PHY_INIT_CFG(QPHY_RX_PWM_GEAR_BAND, 0x15),
1430         QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_CTRL2, 0x6d),
1431         QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_DRV_LVL, 0x0f),
1432         QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_DRV_LVL, 0x02),
1433         QMP_PHY_INIT_CFG(QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
1434         QMP_PHY_INIT_CFG(QPHY_RX_SYM_RESYNC_CTRL, 0x03),
1435         QMP_PHY_INIT_CFG(QPHY_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
1436         QMP_PHY_INIT_CFG(QPHY_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
1437         QMP_PHY_INIT_CFG(QPHY_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
1438 };
1439
1440 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
1441         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1442         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1443         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1444         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1445         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1446         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
1447         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
1448         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1449         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1450         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
1451         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1452         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1453         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
1454         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
1455         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
1456         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
1457         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1458         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1459         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1460         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1461         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1462         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1463         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
1464         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1465         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
1466         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
1467         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
1468         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
1469         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
1470         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
1471         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
1472         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1473         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
1474         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
1475         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
1476         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
1477
1478         /* Rate B */
1479         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
1480 };
1481
1482 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
1483         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
1484         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
1485         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1486 };
1487
1488 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
1489         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
1490         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
1491         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1492         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
1493         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1494         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
1495         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1496         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1497         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
1498         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1499         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1500         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
1501         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1502         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
1503         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1504         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
1505 };
1506
1507 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
1508         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
1509         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1510         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
1511         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
1512         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
1513         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
1514         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
1515         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
1516 };
1517
1518 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
1519         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1520         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1521         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1522         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
1523         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1524         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1525         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1526         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1527         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1528         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1529         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1530         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1531         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1532         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1533         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1534         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1535         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1536         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1537         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1538         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1539         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1540         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1541         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1542         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1543         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1544         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1545         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1546         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1547         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1548         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
1549         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
1550         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1551         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1552         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1553         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1554         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1555         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1556         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1557 };
1558
1559 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
1560         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1561         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1562         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1563         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1564 };
1565
1566 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
1567         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1568         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1569         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1570         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1571         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
1572         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1573         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
1574         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1575         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1576         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1577         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1578         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
1579         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1580         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1581         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1582         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
1583         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
1584 };
1585
1586 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
1587         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1588         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1589         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1590         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1591         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1592         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1593         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1594         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1595         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1596         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1597         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1598         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1599         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1600         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1601         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1602         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1603         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1604         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
1605         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1606         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1607         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1608         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1609         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
1610         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1611         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1612         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1613         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1614         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1615         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1616         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1617         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1618         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1619         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1620         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1621         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
1622         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1623         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1624         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1625 };
1626
1627 static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
1628         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
1629         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
1630         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1631         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
1632         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1633         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1634         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
1635         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1636         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1637         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1638         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1639         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1640         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
1641         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
1642         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
1643         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1644         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
1645         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1646         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1647         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1648         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
1649         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
1650         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
1651         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
1652
1653         /* Rate B */
1654         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
1655 };
1656
1657 static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
1658         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
1659         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
1660         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
1661         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
1662         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
1663         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
1664 };
1665
1666 static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
1667         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
1668         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
1669         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1670         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
1671         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
1672         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1673         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
1674         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1675         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
1676         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1677         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1678         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
1679         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1680         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1681         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
1682         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
1683         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
1684         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1685         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1686         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
1687         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
1688         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
1689         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
1690         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
1691         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
1692         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
1693         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
1694         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1695         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
1696         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
1697         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
1698         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
1699         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1700         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
1701
1702 };
1703
1704 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
1705         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
1706         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1707         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
1708         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
1709         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
1710         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
1711         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
1712 };
1713
1714 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
1715         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1716         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1717         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1718         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1719         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1720         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1721         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1722         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1723         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1724         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1725         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1726         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1727         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1728         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1729         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1730         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1731         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1732         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1733         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1734         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1735         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1736         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1737         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1738         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1739         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1740         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1741         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1742         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1743         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1744         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1745         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1746         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1747         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1748         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1749         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1750         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1751         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1752         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1753         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1754         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1755 };
1756
1757 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
1758         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
1759         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
1760         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1761         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1762         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1763 };
1764
1765 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
1766         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
1767         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1768         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1769         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1770         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1771         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1772         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1773         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1774         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1775         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1776         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1777         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
1778         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1779         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1780         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1781         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1782         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1783         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1784         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1785         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1786         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1787         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
1788         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
1789         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1790         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
1791         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1792         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1793         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1794         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1795         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1796         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1797         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1798         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1799         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1800         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1801         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1802 };
1803
1804 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
1805         /* Lock Det settings */
1806         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1807         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1808         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1809
1810         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1811         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1812         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1813         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1814         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1815         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1816         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1817         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1818         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1819         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1820 };
1821
1822 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
1823         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1824         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1825         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1826         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1827         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1828         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1829         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1830         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1831         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1832         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1833         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1834         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1835         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1836         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1837         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1838         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1839         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1840         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1841         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1842         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1843         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1844         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1845         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1846         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1847         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1848         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1849         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1850         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1851         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1852         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1853         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1854         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1855         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1856         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1857         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1858         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1859         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1860         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1861         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1862         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1863 };
1864
1865 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
1866         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1867         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
1868         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
1869         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
1870 };
1871
1872 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
1873         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
1874         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1875         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
1876         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
1877         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
1878         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1879         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1880         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1881         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1882         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1883         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1884         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1885         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1886         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1887         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1888         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1889         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1890         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1891         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1892         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
1893         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1894         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1895         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1896         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1897         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1898         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1899         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1900         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1901         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1902         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1903         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1904         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1905         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1906         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
1907         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1908         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1909 };
1910
1911 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
1912         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1913         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1914         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1915         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1916         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1917         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1918         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1919         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
1920         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1921         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
1922         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1923         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1924         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1925         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1926         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1927         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1928 };
1929
1930 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
1931         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
1932         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
1933         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1934         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
1935         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1936         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1937         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
1938         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
1939 };
1940
1941 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
1942         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
1943         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1944         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1945         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1946         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1947         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1948         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1949         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1950         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1951         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1952         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1953         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1954         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1955         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1956         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1957         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1958         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1959         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1960         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1961         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1962         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
1963         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
1964         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
1965         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
1966         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
1967         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1968         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
1969         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1970         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1971         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1972         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1973         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
1974         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1975         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1976         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1977         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1978         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1979         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1980 };
1981
1982 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
1983         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1984         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1985         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1986         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1987         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1988         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
1989         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1990         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1991         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1992         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1993         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1994         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1995         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1996         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1997 };
1998
1999 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
2000         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2001         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
2002         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
2003         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
2004         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
2005         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
2006 };
2007
2008 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
2009         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
2010         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
2011         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
2012         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
2013         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
2014         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
2015         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
2016         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
2017         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
2018         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
2019         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
2020         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
2021         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
2022         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
2023         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
2024         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2025         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2026         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2027         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2028         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
2029         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
2030         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
2031         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2032         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2033         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2034         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2035         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2036         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2037         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
2038         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2039         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2040         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2041         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2042         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
2043         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2044         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
2045 };
2046
2047 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
2048         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2049         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2050         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2051         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2052         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2053         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2054         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
2055         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2056         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
2057         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2058         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2059         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2060         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2061         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2062         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2063         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2064 };
2065
2066 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
2067         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
2068         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
2069         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
2070         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
2071         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
2072         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
2073         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2074         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
2075         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
2076         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
2077         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
2078         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
2079         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
2080         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
2081         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
2082         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
2083         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
2084         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
2085         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
2086         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
2087 };
2088
2089 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
2090         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
2091         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
2092         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
2093         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
2094         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
2095         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
2096         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
2097 };
2098
2099 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
2100         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
2101         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
2102         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
2103         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
2104         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
2105         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
2106         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
2107 };
2108
2109 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
2110         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
2111         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
2112         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
2113         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
2114         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
2115         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
2116         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
2117 };
2118
2119 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
2120         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
2121         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
2122         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
2123         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
2124         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
2125         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
2126         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
2127 };
2128
2129 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
2130         QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
2131         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
2132         QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
2133         QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
2134         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
2135         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
2136         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
2137         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
2138         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
2139         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
2140         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
2141         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
2142         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
2143         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
2144 };
2145
2146 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
2147         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
2148         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
2149         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
2150         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2151         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
2152         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
2153         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
2154         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
2155         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
2156         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2157         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
2158         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
2159         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
2160         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
2161         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
2162         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
2163         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
2164         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
2165         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
2166         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
2167         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
2168         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
2169         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
2170         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
2171         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
2172         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
2173         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
2174         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
2175         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
2176         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2177         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
2178         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
2179         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
2180         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
2181         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
2182         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
2183         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
2184         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2185         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2186         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2187         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2188         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
2189 };
2190
2191 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
2192         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2193         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
2194 };
2195
2196 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
2197         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
2198         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
2199         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
2200         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
2201         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
2202         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
2203         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
2204         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2205         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2206         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
2207         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2208         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
2209         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
2210         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
2211         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
2212         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
2213         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
2214         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
2215         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
2216         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
2217         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
2218         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
2219         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
2220         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
2221         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
2222         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
2223         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
2224         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
2225         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2226         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2227         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
2228         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
2229         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2230         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
2231         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
2232         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
2233 };
2234
2235 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
2236         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2237         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2238         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
2239         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
2240         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
2241 };
2242
2243 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
2244         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2245         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2246         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2247         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
2248         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
2249         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
2250         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2251 };
2252
2253 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
2254         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
2255         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
2256         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
2257         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2258         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
2259         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
2260         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
2261         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
2262         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
2263         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2264         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
2265         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
2266         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
2267         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
2268         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
2269         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
2270         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
2271         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
2272         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
2273         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
2274         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
2275         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
2276         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
2277         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
2278         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
2279         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
2280         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
2281         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
2282         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
2283         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2284         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
2285         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
2286         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
2287         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
2288         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
2289         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
2290         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2291         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2292         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
2293         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
2294         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
2295 };
2296
2297 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
2298         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
2299 };
2300
2301 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
2302         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2303         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
2304         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
2305 };
2306
2307 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
2308         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
2309         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
2310         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
2311         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2312         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2313         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
2314         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
2315         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
2316         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2317         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
2318         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
2319         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2320         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
2321         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
2322         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
2323         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
2324         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2325         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
2326         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
2327         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
2328         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
2329         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
2330         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
2331         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
2332         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
2333         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2334         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
2335         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
2336         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
2337         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
2338 };
2339
2340 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
2341         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
2342         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
2343         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2344         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
2345         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
2346         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
2347 };
2348
2349 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
2350         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2351         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
2352         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
2353 };
2354
2355 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
2356         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
2357         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
2358 };
2359
2360 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
2361         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2362         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2363         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
2364         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
2365         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
2366         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
2367         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2368 };
2369
2370 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
2371         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
2372         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
2373 };
2374
2375 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
2376         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
2377 };
2378
2379 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
2380         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
2381         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
2382         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
2383         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2384 };
2385
2386 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
2387         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
2388         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
2389 };
2390
2391 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
2392         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
2393         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
2394 };
2395
2396 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
2397         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
2398         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
2399         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
2400         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
2401         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
2402 };
2403
2404 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
2405         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
2406         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
2407         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
2408         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
2409         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
2410         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
2411         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
2412         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
2413         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
2414         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
2415         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
2416         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
2417         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
2418         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
2419         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
2420         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2421         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2422         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2423         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2424         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
2425         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
2426         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
2427         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2428         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2429         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2430         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
2431         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2432         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2433         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
2434         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2435         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2436         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2437         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2438         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
2439         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
2440         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
2441 };
2442
2443 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
2444         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
2445         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
2446         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
2447         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
2448         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
2449         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
2450         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
2451         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
2452         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
2453         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
2454         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
2455         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
2456         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
2457         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
2458         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
2459         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
2460         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
2461         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
2462         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
2463         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
2464         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
2465         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
2466         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
2467         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
2468         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
2469         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
2470         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2471         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
2472         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
2473         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
2474         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
2475         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV, 0x03),
2476         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
2477         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
2478         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
2479         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
2480         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
2481         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
2482         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
2483 };
2484
2485 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
2486         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
2487         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
2488         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
2489         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
2490         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
2491 };
2492
2493 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
2494         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
2495         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
2496         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
2497         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
2498         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
2499         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
2500         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
2501         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
2502         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
2503         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
2504         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
2505         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
2506         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
2507         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
2508         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
2509         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
2510         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
2511         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
2512         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
2513         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
2514         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
2515         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
2516         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
2517         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2518         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
2519 };
2520
2521 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
2522         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
2523         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
2524         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
2525         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
2526 };
2527
2528 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
2529         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
2530         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
2531         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
2532         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
2533         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
2534         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
2535         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
2536 };
2537
2538 static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
2539         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
2540         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
2541         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2542         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
2543         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2544         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2545         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
2546         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
2547         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2548         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
2549         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
2550         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
2551         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
2552         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
2553         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
2554         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
2555         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
2556         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
2557         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
2558         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
2559         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
2560         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
2561         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
2562         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
2563
2564         /* Rate B */
2565         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
2566 };
2567
2568 static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
2569         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
2570         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
2571         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
2572         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
2573         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
2574         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2575         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
2576         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
2577         QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
2578 };
2579
2580 static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
2581         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
2582         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
2583         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
2584         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
2585         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
2586         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
2587         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
2588         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
2589         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
2590         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
2591         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
2592         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
2593         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
2594         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
2595         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
2596         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
2597         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
2598         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
2599         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
2600         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2601         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2602         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
2603         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
2604         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
2605         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
2606         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
2607         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
2608         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
2609         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
2610         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
2611         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
2612         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
2613         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
2614         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
2615         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
2616         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
2617         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
2618 };
2619
2620 static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = {
2621         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
2622         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
2623         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
2624         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
2625         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
2626         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
2627         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_PLL_CNTL, 0x03),
2628         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
2629         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
2630         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
2631         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
2632         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
2633         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
2634         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
2635         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
2636 };
2637
2638 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
2639         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
2640         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
2641         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
2642         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
2643         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
2644         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2645         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
2646         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
2647         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
2648         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
2649 };
2650
2651 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
2652         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
2653         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2654         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2655         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
2656         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2657         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2658         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
2659         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2660         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2661         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
2662         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
2663         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
2664         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
2665         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2666         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
2667         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2668         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
2669         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
2670         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2671         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
2672         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2673         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
2674         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
2675         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
2676         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
2677         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
2678         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
2679         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
2680         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
2681         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
2682         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
2683         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
2684         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
2685         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2686         QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
2687         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
2688         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2689         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
2690 };
2691
2692 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
2693         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
2694         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
2695         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2696         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2697         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2698         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2699         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2700         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2701         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2702         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2703         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2704         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2705         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2706         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2707         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2708         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2709         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2710         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
2711 };
2712
2713 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
2714         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
2715         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
2716         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
2717         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
2718         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
2719         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
2720         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
2721 };
2722
2723 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
2724         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
2725         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
2726         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
2727         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
2728         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
2729         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
2730         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
2731         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
2732         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
2733         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
2734         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
2735         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
2736         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
2737         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
2738         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
2739         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
2740         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
2741         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
2742         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
2743         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
2744         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
2745         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
2746         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
2747         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
2748         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2749         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
2750         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
2751         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2752         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
2753         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
2754         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
2755 };
2756
2757 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
2758         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
2759         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
2760         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
2761         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
2762         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2763         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2764         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
2765         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
2766         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
2767         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
2768         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
2769         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
2770         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
2771         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
2772         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
2773         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
2774 };
2775
2776 static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
2777         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
2778         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
2779         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
2780         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
2781         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
2782         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
2783         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
2784         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
2785         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
2786         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
2787         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
2788         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
2789         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
2790         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
2791         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
2792         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
2793         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
2794         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
2795         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
2796         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
2797         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
2798         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
2799         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
2800         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
2801         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
2802         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
2803         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
2804         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
2805         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
2806         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
2807         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
2808         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
2809         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
2810         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
2811         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
2812         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
2813         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
2814         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
2815 };
2816
2817 static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
2818         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
2819         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
2820         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
2821         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
2822         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
2823 };
2824
2825 static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
2826         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
2827         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
2828         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
2829         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
2830         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
2831         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
2832         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
2833         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
2834         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
2835         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
2836         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
2837         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
2838         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
2839         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
2840         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
2841         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
2842         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
2843 };
2844
2845 static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
2846         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
2847         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
2848         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
2849         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
2850         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
2851         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
2852         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
2853         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
2854         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
2855         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
2856         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
2857         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
2858         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
2859         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
2860         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
2861         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
2862         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
2863         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
2864         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
2865         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
2866         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
2867 };
2868
2869 struct qmp_phy;
2870
2871 /* struct qmp_phy_cfg - per-PHY initialization config */
2872 struct qmp_phy_cfg {
2873         /* phy-type - PCIE/UFS/USB */
2874         unsigned int type;
2875         /* number of lanes provided by phy */
2876         int nlanes;
2877
2878         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
2879         const struct qmp_phy_init_tbl *serdes_tbl;
2880         int serdes_tbl_num;
2881         const struct qmp_phy_init_tbl *serdes_tbl_sec;
2882         int serdes_tbl_num_sec;
2883         const struct qmp_phy_init_tbl *tx_tbl;
2884         int tx_tbl_num;
2885         const struct qmp_phy_init_tbl *tx_tbl_sec;
2886         int tx_tbl_num_sec;
2887         const struct qmp_phy_init_tbl *rx_tbl;
2888         int rx_tbl_num;
2889         const struct qmp_phy_init_tbl *rx_tbl_sec;
2890         int rx_tbl_num_sec;
2891         const struct qmp_phy_init_tbl *pcs_tbl;
2892         int pcs_tbl_num;
2893         const struct qmp_phy_init_tbl *pcs_tbl_sec;
2894         int pcs_tbl_num_sec;
2895         const struct qmp_phy_init_tbl *pcs_misc_tbl;
2896         int pcs_misc_tbl_num;
2897         const struct qmp_phy_init_tbl *pcs_misc_tbl_sec;
2898         int pcs_misc_tbl_num_sec;
2899
2900         /* Init sequence for DP PHY block link rates */
2901         const struct qmp_phy_init_tbl *serdes_tbl_rbr;
2902         int serdes_tbl_rbr_num;
2903         const struct qmp_phy_init_tbl *serdes_tbl_hbr;
2904         int serdes_tbl_hbr_num;
2905         const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
2906         int serdes_tbl_hbr2_num;
2907         const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
2908         int serdes_tbl_hbr3_num;
2909
2910         /* DP PHY callbacks */
2911         int (*configure_dp_phy)(struct qmp_phy *qphy);
2912         void (*configure_dp_tx)(struct qmp_phy *qphy);
2913         int (*calibrate_dp_phy)(struct qmp_phy *qphy);
2914         void (*dp_aux_init)(struct qmp_phy *qphy);
2915
2916         /* clock ids to be requested */
2917         const char * const *clk_list;
2918         int num_clks;
2919         /* resets to be requested */
2920         const char * const *reset_list;
2921         int num_resets;
2922         /* regulators to be requested */
2923         const char * const *vreg_list;
2924         int num_vregs;
2925
2926         /* array of registers with different offsets */
2927         const unsigned int *regs;
2928
2929         unsigned int start_ctrl;
2930         unsigned int pwrdn_ctrl;
2931         unsigned int mask_com_pcs_ready;
2932         /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
2933         unsigned int phy_status;
2934
2935         /* true, if PHY has a separate PHY_COM control block */
2936         bool has_phy_com_ctrl;
2937         /* true, if PHY has a reset for individual lanes */
2938         bool has_lane_rst;
2939         /* true, if PHY needs delay after POWER_DOWN */
2940         bool has_pwrdn_delay;
2941         /* power_down delay in usec */
2942         int pwrdn_delay_min;
2943         int pwrdn_delay_max;
2944
2945         /* true, if PHY has a separate DP_COM control block */
2946         bool has_phy_dp_com_ctrl;
2947         /* true, if PHY has secondary tx/rx lanes to be configured */
2948         bool is_dual_lane_phy;
2949
2950         /* true, if PCS block has no separate SW_RESET register */
2951         bool no_pcs_sw_reset;
2952 };
2953
2954 struct qmp_phy_combo_cfg {
2955         const struct qmp_phy_cfg *usb_cfg;
2956         const struct qmp_phy_cfg *dp_cfg;
2957 };
2958
2959 /**
2960  * struct qmp_phy - per-lane phy descriptor
2961  *
2962  * @phy: generic phy
2963  * @cfg: phy specific configuration
2964  * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
2965  * @tx: iomapped memory space for lane's tx
2966  * @rx: iomapped memory space for lane's rx
2967  * @pcs: iomapped memory space for lane's pcs
2968  * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
2969  * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
2970  * @pcs_misc: iomapped memory space for lane's pcs_misc
2971  * @pipe_clk: pipe lock
2972  * @index: lane index
2973  * @qmp: QMP phy to which this lane belongs
2974  * @lane_rst: lane's reset controller
2975  * @mode: current PHY mode
2976  * @dp_aux_cfg: Display port aux config
2977  * @dp_opts: Display port optional config
2978  * @dp_clks: Display port clocks
2979  */
2980 struct qmp_phy {
2981         struct phy *phy;
2982         const struct qmp_phy_cfg *cfg;
2983         void __iomem *serdes;
2984         void __iomem *tx;
2985         void __iomem *rx;
2986         void __iomem *pcs;
2987         void __iomem *tx2;
2988         void __iomem *rx2;
2989         void __iomem *pcs_misc;
2990         struct clk *pipe_clk;
2991         unsigned int index;
2992         struct qcom_qmp *qmp;
2993         struct reset_control *lane_rst;
2994         enum phy_mode mode;
2995         unsigned int dp_aux_cfg;
2996         struct phy_configure_opts_dp dp_opts;
2997         struct qmp_phy_dp_clks *dp_clks;
2998 };
2999
3000 struct qmp_phy_dp_clks {
3001         struct qmp_phy *qphy;
3002         struct clk_hw dp_link_hw;
3003         struct clk_hw dp_pixel_hw;
3004 };
3005
3006 /**
3007  * struct qcom_qmp - structure holding QMP phy block attributes
3008  *
3009  * @dev: device
3010  * @dp_com: iomapped memory space for phy's dp_com control block
3011  *
3012  * @clks: array of clocks required by phy
3013  * @resets: array of resets required by phy
3014  * @vregs: regulator supplies bulk data
3015  *
3016  * @phys: array of per-lane phy descriptors
3017  * @phy_mutex: mutex lock for PHY common block initialization
3018  * @init_count: phy common block initialization count
3019  * @ufs_reset: optional UFS PHY reset handle
3020  */
3021 struct qcom_qmp {
3022         struct device *dev;
3023         void __iomem *dp_com;
3024
3025         struct clk_bulk_data *clks;
3026         struct reset_control **resets;
3027         struct regulator_bulk_data *vregs;
3028
3029         struct qmp_phy **phys;
3030
3031         struct mutex phy_mutex;
3032         int init_count;
3033
3034         struct reset_control *ufs_reset;
3035 };
3036
3037 static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy);
3038 static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy);
3039 static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy);
3040 static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy);
3041
3042 static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy);
3043 static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy);
3044 static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy);
3045 static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy);
3046
3047 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
3048 {
3049         u32 reg;
3050
3051         reg = readl(base + offset);
3052         reg |= val;
3053         writel(reg, base + offset);
3054
3055         /* ensure that above write is through */
3056         readl(base + offset);
3057 }
3058
3059 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
3060 {
3061         u32 reg;
3062
3063         reg = readl(base + offset);
3064         reg &= ~val;
3065         writel(reg, base + offset);
3066
3067         /* ensure that above write is through */
3068         readl(base + offset);
3069 }
3070
3071 /* list of clocks required by phy */
3072 static const char * const msm8996_phy_clk_l[] = {
3073         "aux", "cfg_ahb", "ref",
3074 };
3075
3076 static const char * const msm8996_ufs_phy_clk_l[] = {
3077         "ref",
3078 };
3079
3080 static const char * const qmp_v3_phy_clk_l[] = {
3081         "aux", "cfg_ahb", "ref", "com_aux",
3082 };
3083
3084 static const char * const sdm845_pciephy_clk_l[] = {
3085         "aux", "cfg_ahb", "ref", "refgen",
3086 };
3087
3088 static const char * const qmp_v4_phy_clk_l[] = {
3089         "aux", "ref_clk_src", "ref", "com_aux",
3090 };
3091
3092 /* the primary usb3 phy on sm8250 doesn't have a ref clock */
3093 static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
3094         "aux", "ref_clk_src", "com_aux"
3095 };
3096
3097 static const char * const sdm845_ufs_phy_clk_l[] = {
3098         "ref", "ref_aux",
3099 };
3100
3101 /* usb3 phy on sdx55 doesn't have com_aux clock */
3102 static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
3103         "aux", "cfg_ahb", "ref"
3104 };
3105
3106 static const char * const qcm2290_usb3phy_clk_l[] = {
3107         "cfg_ahb", "ref", "com_aux",
3108 };
3109
3110 /* list of resets */
3111 static const char * const msm8996_pciephy_reset_l[] = {
3112         "phy", "common", "cfg",
3113 };
3114
3115 static const char * const msm8996_usb3phy_reset_l[] = {
3116         "phy", "common",
3117 };
3118
3119 static const char * const sc7180_usb3phy_reset_l[] = {
3120         "phy",
3121 };
3122
3123 static const char * const qcm2290_usb3phy_reset_l[] = {
3124         "phy_phy", "phy",
3125 };
3126
3127 static const char * const sdm845_pciephy_reset_l[] = {
3128         "phy",
3129 };
3130
3131 /* list of regulators */
3132 static const char * const qmp_phy_vreg_l[] = {
3133         "vdda-phy", "vdda-pll",
3134 };
3135
3136 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
3137         .type                   = PHY_TYPE_USB3,
3138         .nlanes                 = 1,
3139
3140         .serdes_tbl             = ipq8074_usb3_serdes_tbl,
3141         .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
3142         .tx_tbl                 = msm8996_usb3_tx_tbl,
3143         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
3144         .rx_tbl                 = ipq8074_usb3_rx_tbl,
3145         .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
3146         .pcs_tbl                = ipq8074_usb3_pcs_tbl,
3147         .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
3148         .clk_list               = msm8996_phy_clk_l,
3149         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
3150         .reset_list             = msm8996_usb3phy_reset_l,
3151         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3152         .vreg_list              = qmp_phy_vreg_l,
3153         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3154         .regs                   = usb3phy_regs_layout,
3155
3156         .start_ctrl             = SERDES_START | PCS_START,
3157         .pwrdn_ctrl             = SW_PWRDN,
3158         .phy_status             = PHYSTATUS,
3159 };
3160
3161 static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
3162         .type                   = PHY_TYPE_PCIE,
3163         .nlanes                 = 3,
3164
3165         .serdes_tbl             = msm8996_pcie_serdes_tbl,
3166         .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
3167         .tx_tbl                 = msm8996_pcie_tx_tbl,
3168         .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
3169         .rx_tbl                 = msm8996_pcie_rx_tbl,
3170         .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
3171         .pcs_tbl                = msm8996_pcie_pcs_tbl,
3172         .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
3173         .clk_list               = msm8996_phy_clk_l,
3174         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
3175         .reset_list             = msm8996_pciephy_reset_l,
3176         .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
3177         .vreg_list              = qmp_phy_vreg_l,
3178         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3179         .regs                   = pciephy_regs_layout,
3180
3181         .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
3182         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3183         .mask_com_pcs_ready     = PCS_READY,
3184         .phy_status             = PHYSTATUS,
3185
3186         .has_phy_com_ctrl       = true,
3187         .has_lane_rst           = true,
3188         .has_pwrdn_delay        = true,
3189         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3190         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3191 };
3192
3193 static const struct qmp_phy_cfg msm8996_ufs_cfg = {
3194         .type                   = PHY_TYPE_UFS,
3195         .nlanes                 = 1,
3196
3197         .serdes_tbl             = msm8996_ufs_serdes_tbl,
3198         .serdes_tbl_num         = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
3199         .tx_tbl                 = msm8996_ufs_tx_tbl,
3200         .tx_tbl_num             = ARRAY_SIZE(msm8996_ufs_tx_tbl),
3201         .rx_tbl                 = msm8996_ufs_rx_tbl,
3202         .rx_tbl_num             = ARRAY_SIZE(msm8996_ufs_rx_tbl),
3203
3204         .clk_list               = msm8996_ufs_phy_clk_l,
3205         .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
3206
3207         .vreg_list              = qmp_phy_vreg_l,
3208         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3209
3210         .regs                   = msm8996_ufsphy_regs_layout,
3211
3212         .start_ctrl             = SERDES_START,
3213         .pwrdn_ctrl             = SW_PWRDN,
3214         .phy_status             = PHYSTATUS,
3215
3216         .no_pcs_sw_reset        = true,
3217 };
3218
3219 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
3220         .type                   = PHY_TYPE_USB3,
3221         .nlanes                 = 1,
3222
3223         .serdes_tbl             = msm8996_usb3_serdes_tbl,
3224         .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
3225         .tx_tbl                 = msm8996_usb3_tx_tbl,
3226         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
3227         .rx_tbl                 = msm8996_usb3_rx_tbl,
3228         .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
3229         .pcs_tbl                = msm8996_usb3_pcs_tbl,
3230         .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
3231         .clk_list               = msm8996_phy_clk_l,
3232         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
3233         .reset_list             = msm8996_usb3phy_reset_l,
3234         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3235         .vreg_list              = qmp_phy_vreg_l,
3236         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3237         .regs                   = usb3phy_regs_layout,
3238
3239         .start_ctrl             = SERDES_START | PCS_START,
3240         .pwrdn_ctrl             = SW_PWRDN,
3241         .phy_status             = PHYSTATUS,
3242 };
3243
3244 static const char * const ipq8074_pciephy_clk_l[] = {
3245         "aux", "cfg_ahb",
3246 };
3247 /* list of resets */
3248 static const char * const ipq8074_pciephy_reset_l[] = {
3249         "phy", "common",
3250 };
3251
3252 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
3253         .type                   = PHY_TYPE_PCIE,
3254         .nlanes                 = 1,
3255
3256         .serdes_tbl             = ipq8074_pcie_serdes_tbl,
3257         .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
3258         .tx_tbl                 = ipq8074_pcie_tx_tbl,
3259         .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
3260         .rx_tbl                 = ipq8074_pcie_rx_tbl,
3261         .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
3262         .pcs_tbl                = ipq8074_pcie_pcs_tbl,
3263         .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
3264         .clk_list               = ipq8074_pciephy_clk_l,
3265         .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
3266         .reset_list             = ipq8074_pciephy_reset_l,
3267         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3268         .vreg_list              = NULL,
3269         .num_vregs              = 0,
3270         .regs                   = pciephy_regs_layout,
3271
3272         .start_ctrl             = SERDES_START | PCS_START,
3273         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3274         .phy_status             = PHYSTATUS,
3275
3276         .has_phy_com_ctrl       = false,
3277         .has_lane_rst           = false,
3278         .has_pwrdn_delay        = true,
3279         .pwrdn_delay_min        = 995,          /* us */
3280         .pwrdn_delay_max        = 1005,         /* us */
3281 };
3282
3283 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
3284         .type                   = PHY_TYPE_PCIE,
3285         .nlanes                 = 1,
3286
3287         .serdes_tbl             = ipq6018_pcie_serdes_tbl,
3288         .serdes_tbl_num         = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
3289         .tx_tbl                 = ipq6018_pcie_tx_tbl,
3290         .tx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
3291         .rx_tbl                 = ipq6018_pcie_rx_tbl,
3292         .rx_tbl_num             = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
3293         .pcs_tbl                = ipq6018_pcie_pcs_tbl,
3294         .pcs_tbl_num            = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
3295         .clk_list               = ipq8074_pciephy_clk_l,
3296         .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
3297         .reset_list             = ipq8074_pciephy_reset_l,
3298         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3299         .vreg_list              = NULL,
3300         .num_vregs              = 0,
3301         .regs                   = ipq_pciephy_gen3_regs_layout,
3302
3303         .start_ctrl             = SERDES_START | PCS_START,
3304         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3305
3306         .has_phy_com_ctrl       = false,
3307         .has_lane_rst           = false,
3308         .has_pwrdn_delay        = true,
3309         .pwrdn_delay_min        = 995,          /* us */
3310         .pwrdn_delay_max        = 1005,         /* us */
3311 };
3312
3313 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
3314         .type = PHY_TYPE_PCIE,
3315         .nlanes = 1,
3316
3317         .serdes_tbl             = sdm845_qmp_pcie_serdes_tbl,
3318         .serdes_tbl_num         = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
3319         .tx_tbl                 = sdm845_qmp_pcie_tx_tbl,
3320         .tx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
3321         .rx_tbl                 = sdm845_qmp_pcie_rx_tbl,
3322         .rx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
3323         .pcs_tbl                = sdm845_qmp_pcie_pcs_tbl,
3324         .pcs_tbl_num            = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
3325         .pcs_misc_tbl           = sdm845_qmp_pcie_pcs_misc_tbl,
3326         .pcs_misc_tbl_num       = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
3327         .clk_list               = sdm845_pciephy_clk_l,
3328         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
3329         .reset_list             = sdm845_pciephy_reset_l,
3330         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3331         .vreg_list              = qmp_phy_vreg_l,
3332         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3333         .regs                   = sdm845_qmp_pciephy_regs_layout,
3334
3335         .start_ctrl             = PCS_START | SERDES_START,
3336         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3337         .phy_status             = PHYSTATUS,
3338
3339         .has_pwrdn_delay        = true,
3340         .pwrdn_delay_min        = 995,          /* us */
3341         .pwrdn_delay_max        = 1005,         /* us */
3342 };
3343
3344 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
3345         .type = PHY_TYPE_PCIE,
3346         .nlanes = 1,
3347
3348         .serdes_tbl             = sdm845_qhp_pcie_serdes_tbl,
3349         .serdes_tbl_num         = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
3350         .tx_tbl                 = sdm845_qhp_pcie_tx_tbl,
3351         .tx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
3352         .rx_tbl                 = sdm845_qhp_pcie_rx_tbl,
3353         .rx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
3354         .pcs_tbl                = sdm845_qhp_pcie_pcs_tbl,
3355         .pcs_tbl_num            = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
3356         .clk_list               = sdm845_pciephy_clk_l,
3357         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
3358         .reset_list             = sdm845_pciephy_reset_l,
3359         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3360         .vreg_list              = qmp_phy_vreg_l,
3361         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3362         .regs                   = sdm845_qhp_pciephy_regs_layout,
3363
3364         .start_ctrl             = PCS_START | SERDES_START,
3365         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3366         .phy_status             = PHYSTATUS,
3367
3368         .has_pwrdn_delay        = true,
3369         .pwrdn_delay_min        = 995,          /* us */
3370         .pwrdn_delay_max        = 1005,         /* us */
3371 };
3372
3373 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
3374         .type = PHY_TYPE_PCIE,
3375         .nlanes = 1,
3376
3377         .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
3378         .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3379         .serdes_tbl_sec         = sm8250_qmp_gen3x1_pcie_serdes_tbl,
3380         .serdes_tbl_num_sec     = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
3381         .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
3382         .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3383         .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
3384         .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3385         .rx_tbl_sec             = sm8250_qmp_gen3x1_pcie_rx_tbl,
3386         .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
3387         .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
3388         .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3389         .pcs_tbl_sec            = sm8250_qmp_gen3x1_pcie_pcs_tbl,
3390         .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
3391         .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
3392         .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3393         .pcs_misc_tbl_sec               = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
3394         .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
3395         .clk_list               = sdm845_pciephy_clk_l,
3396         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
3397         .reset_list             = sdm845_pciephy_reset_l,
3398         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3399         .vreg_list              = qmp_phy_vreg_l,
3400         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3401         .regs                   = sm8250_pcie_regs_layout,
3402
3403         .start_ctrl             = PCS_START | SERDES_START,
3404         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3405         .phy_status             = PHYSTATUS,
3406
3407         .has_pwrdn_delay        = true,
3408         .pwrdn_delay_min        = 995,          /* us */
3409         .pwrdn_delay_max        = 1005,         /* us */
3410 };
3411
3412 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
3413         .type = PHY_TYPE_PCIE,
3414         .nlanes = 2,
3415
3416         .serdes_tbl             = sm8250_qmp_pcie_serdes_tbl,
3417         .serdes_tbl_num         = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
3418         .tx_tbl                 = sm8250_qmp_pcie_tx_tbl,
3419         .tx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
3420         .tx_tbl_sec             = sm8250_qmp_gen3x2_pcie_tx_tbl,
3421         .tx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
3422         .rx_tbl                 = sm8250_qmp_pcie_rx_tbl,
3423         .rx_tbl_num             = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
3424         .rx_tbl_sec             = sm8250_qmp_gen3x2_pcie_rx_tbl,
3425         .rx_tbl_num_sec         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
3426         .pcs_tbl                = sm8250_qmp_pcie_pcs_tbl,
3427         .pcs_tbl_num            = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
3428         .pcs_tbl_sec            = sm8250_qmp_gen3x2_pcie_pcs_tbl,
3429         .pcs_tbl_num_sec                = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
3430         .pcs_misc_tbl           = sm8250_qmp_pcie_pcs_misc_tbl,
3431         .pcs_misc_tbl_num       = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
3432         .pcs_misc_tbl_sec               = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
3433         .pcs_misc_tbl_num_sec   = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
3434         .clk_list               = sdm845_pciephy_clk_l,
3435         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
3436         .reset_list             = sdm845_pciephy_reset_l,
3437         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3438         .vreg_list              = qmp_phy_vreg_l,
3439         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3440         .regs                   = sm8250_pcie_regs_layout,
3441
3442         .start_ctrl             = PCS_START | SERDES_START,
3443         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3444         .phy_status             = PHYSTATUS,
3445
3446         .is_dual_lane_phy       = true,
3447         .has_pwrdn_delay        = true,
3448         .pwrdn_delay_min        = 995,          /* us */
3449         .pwrdn_delay_max        = 1005,         /* us */
3450 };
3451
3452 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
3453         .type                   = PHY_TYPE_USB3,
3454         .nlanes                 = 1,
3455
3456         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
3457         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
3458         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
3459         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
3460         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
3461         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
3462         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
3463         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
3464         .clk_list               = qmp_v3_phy_clk_l,
3465         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
3466         .reset_list             = msm8996_usb3phy_reset_l,
3467         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3468         .vreg_list              = qmp_phy_vreg_l,
3469         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3470         .regs                   = qmp_v3_usb3phy_regs_layout,
3471
3472         .start_ctrl             = SERDES_START | PCS_START,
3473         .pwrdn_ctrl             = SW_PWRDN,
3474         .phy_status             = PHYSTATUS,
3475
3476         .has_pwrdn_delay        = true,
3477         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3478         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3479
3480         .has_phy_dp_com_ctrl    = true,
3481         .is_dual_lane_phy       = true,
3482 };
3483
3484 static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
3485         .type                   = PHY_TYPE_USB3,
3486         .nlanes                 = 1,
3487
3488         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
3489         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
3490         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
3491         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
3492         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
3493         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
3494         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
3495         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
3496         .clk_list               = qmp_v3_phy_clk_l,
3497         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
3498         .reset_list             = sc7180_usb3phy_reset_l,
3499         .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
3500         .vreg_list              = qmp_phy_vreg_l,
3501         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3502         .regs                   = qmp_v3_usb3phy_regs_layout,
3503
3504         .start_ctrl             = SERDES_START | PCS_START,
3505         .pwrdn_ctrl             = SW_PWRDN,
3506         .phy_status             = PHYSTATUS,
3507
3508         .has_pwrdn_delay        = true,
3509         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3510         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3511
3512         .has_phy_dp_com_ctrl    = true,
3513         .is_dual_lane_phy       = true,
3514 };
3515
3516 static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
3517         .type                   = PHY_TYPE_DP,
3518         .nlanes                 = 1,
3519
3520         .serdes_tbl             = qmp_v3_dp_serdes_tbl,
3521         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
3522         .tx_tbl                 = qmp_v3_dp_tx_tbl,
3523         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
3524
3525         .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
3526         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
3527         .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
3528         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
3529         .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
3530         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
3531         .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
3532         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
3533
3534         .clk_list               = qmp_v3_phy_clk_l,
3535         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
3536         .reset_list             = sc7180_usb3phy_reset_l,
3537         .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
3538         .vreg_list              = qmp_phy_vreg_l,
3539         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3540         .regs                   = qmp_v3_usb3phy_regs_layout,
3541
3542         .has_phy_dp_com_ctrl    = true,
3543         .is_dual_lane_phy       = true,
3544
3545         .dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
3546         .configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
3547         .configure_dp_phy = qcom_qmp_v3_phy_configure_dp_phy,
3548         .calibrate_dp_phy = qcom_qmp_v3_dp_phy_calibrate,
3549 };
3550
3551 static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = {
3552         .usb_cfg                = &sc7180_usb3phy_cfg,
3553         .dp_cfg                 = &sc7180_dpphy_cfg,
3554 };
3555
3556 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
3557         .type                   = PHY_TYPE_USB3,
3558         .nlanes                 = 1,
3559
3560         .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
3561         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
3562         .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
3563         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
3564         .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
3565         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
3566         .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
3567         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
3568         .clk_list               = qmp_v3_phy_clk_l,
3569         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
3570         .reset_list             = msm8996_usb3phy_reset_l,
3571         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3572         .vreg_list              = qmp_phy_vreg_l,
3573         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3574         .regs                   = qmp_v3_usb3phy_regs_layout,
3575
3576         .start_ctrl             = SERDES_START | PCS_START,
3577         .pwrdn_ctrl             = SW_PWRDN,
3578         .phy_status             = PHYSTATUS,
3579
3580         .has_pwrdn_delay        = true,
3581         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3582         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3583 };
3584
3585 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
3586         .type                   = PHY_TYPE_UFS,
3587         .nlanes                 = 2,
3588
3589         .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
3590         .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
3591         .tx_tbl                 = sdm845_ufsphy_tx_tbl,
3592         .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
3593         .rx_tbl                 = sdm845_ufsphy_rx_tbl,
3594         .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
3595         .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
3596         .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
3597         .clk_list               = sdm845_ufs_phy_clk_l,
3598         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3599         .vreg_list              = qmp_phy_vreg_l,
3600         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3601         .regs                   = sdm845_ufsphy_regs_layout,
3602
3603         .start_ctrl             = SERDES_START,
3604         .pwrdn_ctrl             = SW_PWRDN,
3605         .phy_status             = PHYSTATUS,
3606
3607         .is_dual_lane_phy       = true,
3608         .no_pcs_sw_reset        = true,
3609 };
3610
3611 static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
3612         .type                   = PHY_TYPE_UFS,
3613         .nlanes                 = 1,
3614
3615         .serdes_tbl             = sm6115_ufsphy_serdes_tbl,
3616         .serdes_tbl_num         = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl),
3617         .tx_tbl                 = sm6115_ufsphy_tx_tbl,
3618         .tx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_tx_tbl),
3619         .rx_tbl                 = sm6115_ufsphy_rx_tbl,
3620         .rx_tbl_num             = ARRAY_SIZE(sm6115_ufsphy_rx_tbl),
3621         .pcs_tbl                = sm6115_ufsphy_pcs_tbl,
3622         .pcs_tbl_num            = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl),
3623         .clk_list               = sdm845_ufs_phy_clk_l,
3624         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3625         .vreg_list              = qmp_phy_vreg_l,
3626         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3627         .regs                   = sm6115_ufsphy_regs_layout,
3628
3629         .start_ctrl             = SERDES_START,
3630         .pwrdn_ctrl             = SW_PWRDN,
3631
3632         .is_dual_lane_phy       = false,
3633         .no_pcs_sw_reset        = true,
3634 };
3635
3636 static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
3637         .type                   = PHY_TYPE_PCIE,
3638         .nlanes                 = 1,
3639
3640         .serdes_tbl             = msm8998_pcie_serdes_tbl,
3641         .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
3642         .tx_tbl                 = msm8998_pcie_tx_tbl,
3643         .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
3644         .rx_tbl                 = msm8998_pcie_rx_tbl,
3645         .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
3646         .pcs_tbl                = msm8998_pcie_pcs_tbl,
3647         .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
3648         .clk_list               = msm8996_phy_clk_l,
3649         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
3650         .reset_list             = ipq8074_pciephy_reset_l,
3651         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
3652         .vreg_list              = qmp_phy_vreg_l,
3653         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3654         .regs                   = pciephy_regs_layout,
3655
3656         .start_ctrl             = SERDES_START | PCS_START,
3657         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3658         .phy_status             = PHYSTATUS,
3659 };
3660
3661 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
3662         .type                   = PHY_TYPE_USB3,
3663         .nlanes                 = 1,
3664
3665         .serdes_tbl             = msm8998_usb3_serdes_tbl,
3666         .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
3667         .tx_tbl                 = msm8998_usb3_tx_tbl,
3668         .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
3669         .rx_tbl                 = msm8998_usb3_rx_tbl,
3670         .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
3671         .pcs_tbl                = msm8998_usb3_pcs_tbl,
3672         .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
3673         .clk_list               = msm8996_phy_clk_l,
3674         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
3675         .reset_list             = msm8996_usb3phy_reset_l,
3676         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3677         .vreg_list              = qmp_phy_vreg_l,
3678         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3679         .regs                   = qmp_v3_usb3phy_regs_layout,
3680
3681         .start_ctrl             = SERDES_START | PCS_START,
3682         .pwrdn_ctrl             = SW_PWRDN,
3683         .phy_status             = PHYSTATUS,
3684
3685         .is_dual_lane_phy       = true,
3686 };
3687
3688 static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
3689         .type                   = PHY_TYPE_UFS,
3690         .nlanes                 = 2,
3691
3692         .serdes_tbl             = sm8150_ufsphy_serdes_tbl,
3693         .serdes_tbl_num         = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
3694         .tx_tbl                 = sm8150_ufsphy_tx_tbl,
3695         .tx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
3696         .rx_tbl                 = sm8150_ufsphy_rx_tbl,
3697         .rx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
3698         .pcs_tbl                = sm8150_ufsphy_pcs_tbl,
3699         .pcs_tbl_num            = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
3700         .clk_list               = sdm845_ufs_phy_clk_l,
3701         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
3702         .vreg_list              = qmp_phy_vreg_l,
3703         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3704         .regs                   = sm8150_ufsphy_regs_layout,
3705
3706         .start_ctrl             = SERDES_START,
3707         .pwrdn_ctrl             = SW_PWRDN,
3708         .phy_status             = PHYSTATUS,
3709
3710         .is_dual_lane_phy       = true,
3711 };
3712
3713 static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
3714         .type                   = PHY_TYPE_USB3,
3715         .nlanes                 = 1,
3716
3717         .serdes_tbl             = sm8150_usb3_serdes_tbl,
3718         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
3719         .tx_tbl                 = sm8150_usb3_tx_tbl,
3720         .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
3721         .rx_tbl                 = sm8150_usb3_rx_tbl,
3722         .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
3723         .pcs_tbl                = sm8150_usb3_pcs_tbl,
3724         .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
3725         .clk_list               = qmp_v4_phy_clk_l,
3726         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
3727         .reset_list             = msm8996_usb3phy_reset_l,
3728         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3729         .vreg_list              = qmp_phy_vreg_l,
3730         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3731         .regs                   = qmp_v4_usb3phy_regs_layout,
3732
3733         .start_ctrl             = SERDES_START | PCS_START,
3734         .pwrdn_ctrl             = SW_PWRDN,
3735         .phy_status             = PHYSTATUS,
3736
3737
3738         .has_pwrdn_delay        = true,
3739         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3740         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3741
3742         .has_phy_dp_com_ctrl    = true,
3743         .is_dual_lane_phy       = true,
3744 };
3745
3746 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
3747         .type = PHY_TYPE_PCIE,
3748         .nlanes = 1,
3749
3750         .serdes_tbl             = sc8180x_qmp_pcie_serdes_tbl,
3751         .serdes_tbl_num         = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
3752         .tx_tbl                 = sc8180x_qmp_pcie_tx_tbl,
3753         .tx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
3754         .rx_tbl                 = sc8180x_qmp_pcie_rx_tbl,
3755         .rx_tbl_num             = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
3756         .pcs_tbl                = sc8180x_qmp_pcie_pcs_tbl,
3757         .pcs_tbl_num            = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
3758         .pcs_misc_tbl           = sc8180x_qmp_pcie_pcs_misc_tbl,
3759         .pcs_misc_tbl_num       = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
3760         .clk_list               = sdm845_pciephy_clk_l,
3761         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
3762         .reset_list             = sdm845_pciephy_reset_l,
3763         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3764         .vreg_list              = qmp_phy_vreg_l,
3765         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3766         .regs                   = sm8250_pcie_regs_layout,
3767
3768         .start_ctrl             = PCS_START | SERDES_START,
3769         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
3770
3771         .has_pwrdn_delay        = true,
3772         .pwrdn_delay_min        = 995,          /* us */
3773         .pwrdn_delay_max        = 1005,         /* us */
3774 };
3775
3776 static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
3777         .type                   = PHY_TYPE_DP,
3778         .nlanes                 = 1,
3779
3780         .serdes_tbl             = qmp_v4_dp_serdes_tbl,
3781         .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
3782         .tx_tbl                 = qmp_v4_dp_tx_tbl,
3783         .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
3784
3785         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
3786         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
3787         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
3788         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
3789         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
3790         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
3791         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
3792         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
3793
3794         .clk_list               = qmp_v3_phy_clk_l,
3795         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
3796         .reset_list             = sc7180_usb3phy_reset_l,
3797         .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
3798         .vreg_list              = qmp_phy_vreg_l,
3799         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3800         .regs                   = qmp_v3_usb3phy_regs_layout,
3801
3802         .has_phy_dp_com_ctrl    = true,
3803         .is_dual_lane_phy       = true,
3804
3805         .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
3806         .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
3807         .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
3808         .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
3809 };
3810
3811 static const struct qmp_phy_combo_cfg sc8180x_usb3dpphy_cfg = {
3812         .usb_cfg                = &sm8150_usb3phy_cfg,
3813         .dp_cfg                 = &sc8180x_dpphy_cfg,
3814 };
3815
3816 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
3817         .type                   = PHY_TYPE_USB3,
3818         .nlanes                 = 1,
3819
3820         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
3821         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3822         .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
3823         .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
3824         .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
3825         .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
3826         .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
3827         .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
3828         .clk_list               = qmp_v4_phy_clk_l,
3829         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
3830         .reset_list             = msm8996_usb3phy_reset_l,
3831         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3832         .vreg_list              = qmp_phy_vreg_l,
3833         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3834         .regs                   = qmp_v4_usb3_uniphy_regs_layout,
3835
3836         .start_ctrl             = SERDES_START | PCS_START,
3837         .pwrdn_ctrl             = SW_PWRDN,
3838         .phy_status             = PHYSTATUS,
3839
3840         .has_pwrdn_delay        = true,
3841         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3842         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3843 };
3844
3845 static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
3846         .type                   = PHY_TYPE_USB3,
3847         .nlanes                 = 1,
3848
3849         .serdes_tbl             = sm8150_usb3_serdes_tbl,
3850         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
3851         .tx_tbl                 = sm8250_usb3_tx_tbl,
3852         .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
3853         .rx_tbl                 = sm8250_usb3_rx_tbl,
3854         .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
3855         .pcs_tbl                = sm8250_usb3_pcs_tbl,
3856         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
3857         .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
3858         .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
3859         .reset_list             = msm8996_usb3phy_reset_l,
3860         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3861         .vreg_list              = qmp_phy_vreg_l,
3862         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3863         .regs                   = qmp_v4_usb3phy_regs_layout,
3864
3865         .start_ctrl             = SERDES_START | PCS_START,
3866         .pwrdn_ctrl             = SW_PWRDN,
3867         .phy_status             = PHYSTATUS,
3868
3869         .has_pwrdn_delay        = true,
3870         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3871         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3872
3873         .has_phy_dp_com_ctrl    = true,
3874         .is_dual_lane_phy       = true,
3875 };
3876
3877 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
3878         .type                   = PHY_TYPE_USB3,
3879         .nlanes                 = 1,
3880
3881         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
3882         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3883         .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
3884         .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
3885         .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
3886         .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
3887         .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
3888         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
3889         .clk_list               = qmp_v4_phy_clk_l,
3890         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
3891         .reset_list             = msm8996_usb3phy_reset_l,
3892         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3893         .vreg_list              = qmp_phy_vreg_l,
3894         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3895         .regs                   = qmp_v4_usb3_uniphy_regs_layout,
3896
3897         .start_ctrl             = SERDES_START | PCS_START,
3898         .pwrdn_ctrl             = SW_PWRDN,
3899         .phy_status             = PHYSTATUS,
3900
3901         .has_pwrdn_delay        = true,
3902         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3903         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3904 };
3905
3906 static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
3907         .type                   = PHY_TYPE_DP,
3908         .nlanes                 = 1,
3909
3910         .serdes_tbl             = qmp_v4_dp_serdes_tbl,
3911         .serdes_tbl_num         = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
3912         .tx_tbl                 = qmp_v4_dp_tx_tbl,
3913         .tx_tbl_num             = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
3914
3915         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
3916         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
3917         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
3918         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
3919         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
3920         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
3921         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
3922         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
3923
3924         .clk_list               = qmp_v4_phy_clk_l,
3925         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
3926         .reset_list             = msm8996_usb3phy_reset_l,
3927         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3928         .vreg_list              = qmp_phy_vreg_l,
3929         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3930         .regs                   = qmp_v4_usb3phy_regs_layout,
3931
3932         .has_phy_dp_com_ctrl    = true,
3933         .is_dual_lane_phy       = true,
3934
3935         .dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
3936         .configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
3937         .configure_dp_phy = qcom_qmp_v4_phy_configure_dp_phy,
3938         .calibrate_dp_phy = qcom_qmp_v4_dp_phy_calibrate,
3939 };
3940
3941 static const struct qmp_phy_combo_cfg sm8250_usb3dpphy_cfg = {
3942         .usb_cfg                = &sm8250_usb3phy_cfg,
3943         .dp_cfg                 = &sm8250_dpphy_cfg,
3944 };
3945
3946 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
3947         .type                   = PHY_TYPE_USB3,
3948         .nlanes                 = 1,
3949
3950         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
3951         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
3952         .tx_tbl                 = sdx55_usb3_uniphy_tx_tbl,
3953         .tx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
3954         .rx_tbl                 = sdx55_usb3_uniphy_rx_tbl,
3955         .rx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
3956         .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
3957         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
3958         .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
3959         .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
3960         .reset_list             = msm8996_usb3phy_reset_l,
3961         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
3962         .vreg_list              = qmp_phy_vreg_l,
3963         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3964         .regs                   = qmp_v4_usb3_uniphy_regs_layout,
3965
3966         .start_ctrl             = SERDES_START | PCS_START,
3967         .pwrdn_ctrl             = SW_PWRDN,
3968         .phy_status             = PHYSTATUS,
3969
3970         .has_pwrdn_delay        = true,
3971         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
3972         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
3973 };
3974
3975 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
3976         .type = PHY_TYPE_PCIE,
3977         .nlanes = 2,
3978
3979         .serdes_tbl             = sdx55_qmp_pcie_serdes_tbl,
3980         .serdes_tbl_num         = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
3981         .tx_tbl                 = sdx55_qmp_pcie_tx_tbl,
3982         .tx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
3983         .rx_tbl                 = sdx55_qmp_pcie_rx_tbl,
3984         .rx_tbl_num             = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
3985         .pcs_tbl                = sdx55_qmp_pcie_pcs_tbl,
3986         .pcs_tbl_num            = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
3987         .pcs_misc_tbl           = sdx55_qmp_pcie_pcs_misc_tbl,
3988         .pcs_misc_tbl_num       = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
3989         .clk_list               = sdm845_pciephy_clk_l,
3990         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
3991         .reset_list             = sdm845_pciephy_reset_l,
3992         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
3993         .vreg_list              = qmp_phy_vreg_l,
3994         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
3995         .regs                   = sm8250_pcie_regs_layout,
3996
3997         .start_ctrl             = PCS_START | SERDES_START,
3998         .pwrdn_ctrl             = SW_PWRDN,
3999         .phy_status             = PHYSTATUS_4_20,
4000
4001         .is_dual_lane_phy       = true,
4002         .has_pwrdn_delay        = true,
4003         .pwrdn_delay_min        = 995,          /* us */
4004         .pwrdn_delay_max        = 1005,         /* us */
4005 };
4006
4007 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
4008         .type                   = PHY_TYPE_UFS,
4009         .nlanes                 = 2,
4010
4011         .serdes_tbl             = sm8350_ufsphy_serdes_tbl,
4012         .serdes_tbl_num         = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl),
4013         .tx_tbl                 = sm8350_ufsphy_tx_tbl,
4014         .tx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_tx_tbl),
4015         .rx_tbl                 = sm8350_ufsphy_rx_tbl,
4016         .rx_tbl_num             = ARRAY_SIZE(sm8350_ufsphy_rx_tbl),
4017         .pcs_tbl                = sm8350_ufsphy_pcs_tbl,
4018         .pcs_tbl_num            = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl),
4019         .clk_list               = sdm845_ufs_phy_clk_l,
4020         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
4021         .vreg_list              = qmp_phy_vreg_l,
4022         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4023         .regs                   = sm8150_ufsphy_regs_layout,
4024
4025         .start_ctrl             = SERDES_START,
4026         .pwrdn_ctrl             = SW_PWRDN,
4027         .phy_status             = PHYSTATUS,
4028
4029         .is_dual_lane_phy       = true,
4030 };
4031
4032 static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
4033         .type                   = PHY_TYPE_USB3,
4034         .nlanes                 = 1,
4035
4036         .serdes_tbl             = sm8150_usb3_serdes_tbl,
4037         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
4038         .tx_tbl                 = sm8350_usb3_tx_tbl,
4039         .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
4040         .rx_tbl                 = sm8350_usb3_rx_tbl,
4041         .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
4042         .pcs_tbl                = sm8350_usb3_pcs_tbl,
4043         .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
4044         .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
4045         .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
4046         .reset_list             = msm8996_usb3phy_reset_l,
4047         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4048         .vreg_list              = qmp_phy_vreg_l,
4049         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4050         .regs                   = qmp_v4_usb3phy_regs_layout,
4051
4052         .start_ctrl             = SERDES_START | PCS_START,
4053         .pwrdn_ctrl             = SW_PWRDN,
4054         .phy_status             = PHYSTATUS,
4055
4056         .has_pwrdn_delay        = true,
4057         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
4058         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
4059
4060         .has_phy_dp_com_ctrl    = true,
4061         .is_dual_lane_phy       = true,
4062 };
4063
4064 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
4065         .type                   = PHY_TYPE_USB3,
4066         .nlanes                 = 1,
4067
4068         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
4069         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
4070         .tx_tbl                 = sm8350_usb3_uniphy_tx_tbl,
4071         .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
4072         .rx_tbl                 = sm8350_usb3_uniphy_rx_tbl,
4073         .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
4074         .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
4075         .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
4076         .clk_list               = qmp_v4_phy_clk_l,
4077         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
4078         .reset_list             = msm8996_usb3phy_reset_l,
4079         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
4080         .vreg_list              = qmp_phy_vreg_l,
4081         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4082         .regs                   = sm8350_usb3_uniphy_regs_layout,
4083
4084         .start_ctrl             = SERDES_START | PCS_START,
4085         .pwrdn_ctrl             = SW_PWRDN,
4086         .phy_status             = PHYSTATUS,
4087
4088         .has_pwrdn_delay        = true,
4089         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
4090         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
4091 };
4092
4093 static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
4094         .type                   = PHY_TYPE_USB3,
4095         .nlanes                 = 1,
4096
4097         .serdes_tbl             = qcm2290_usb3_serdes_tbl,
4098         .serdes_tbl_num         = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
4099         .tx_tbl                 = qcm2290_usb3_tx_tbl,
4100         .tx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
4101         .rx_tbl                 = qcm2290_usb3_rx_tbl,
4102         .rx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
4103         .pcs_tbl                = qcm2290_usb3_pcs_tbl,
4104         .pcs_tbl_num            = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
4105         .clk_list               = qcm2290_usb3phy_clk_l,
4106         .num_clks               = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
4107         .reset_list             = qcm2290_usb3phy_reset_l,
4108         .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
4109         .vreg_list              = qmp_phy_vreg_l,
4110         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
4111         .regs                   = qcm2290_usb3phy_regs_layout,
4112
4113         .start_ctrl             = SERDES_START | PCS_START,
4114         .pwrdn_ctrl             = SW_PWRDN,
4115         .phy_status             = PHYSTATUS,
4116
4117         .is_dual_lane_phy       = true,
4118 };
4119
4120 static void qcom_qmp_phy_configure_lane(void __iomem *base,
4121                                         const unsigned int *regs,
4122                                         const struct qmp_phy_init_tbl tbl[],
4123                                         int num,
4124                                         u8 lane_mask)
4125 {
4126         int i;
4127         const struct qmp_phy_init_tbl *t = tbl;
4128
4129         if (!t)
4130                 return;
4131
4132         for (i = 0; i < num; i++, t++) {
4133                 if (!(t->lane_mask & lane_mask))
4134                         continue;
4135
4136                 if (t->in_layout)
4137                         writel(t->val, base + regs[t->offset]);
4138                 else
4139                         writel(t->val, base + t->offset);
4140         }
4141 }
4142
4143 static void qcom_qmp_phy_configure(void __iomem *base,
4144                                    const unsigned int *regs,
4145                                    const struct qmp_phy_init_tbl tbl[],
4146                                    int num)
4147 {
4148         qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
4149 }
4150
4151 static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
4152 {
4153         struct qcom_qmp *qmp = qphy->qmp;
4154         const struct qmp_phy_cfg *cfg = qphy->cfg;
4155         void __iomem *serdes = qphy->serdes;
4156         const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4157         const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
4158         int serdes_tbl_num = cfg->serdes_tbl_num;
4159         int ret;
4160
4161         qcom_qmp_phy_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
4162         if (cfg->serdes_tbl_sec)
4163                 qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl_sec,
4164                                        cfg->serdes_tbl_num_sec);
4165
4166         if (cfg->type == PHY_TYPE_DP) {
4167                 switch (dp_opts->link_rate) {
4168                 case 1620:
4169                         qcom_qmp_phy_configure(serdes, cfg->regs,
4170                                                cfg->serdes_tbl_rbr,
4171                                                cfg->serdes_tbl_rbr_num);
4172                         break;
4173                 case 2700:
4174                         qcom_qmp_phy_configure(serdes, cfg->regs,
4175                                                cfg->serdes_tbl_hbr,
4176                                                cfg->serdes_tbl_hbr_num);
4177                         break;
4178                 case 5400:
4179                         qcom_qmp_phy_configure(serdes, cfg->regs,
4180                                                cfg->serdes_tbl_hbr2,
4181                                                cfg->serdes_tbl_hbr2_num);
4182                         break;
4183                 case 8100:
4184                         qcom_qmp_phy_configure(serdes, cfg->regs,
4185                                                cfg->serdes_tbl_hbr3,
4186                                                cfg->serdes_tbl_hbr3_num);
4187                         break;
4188                 default:
4189                         /* Other link rates aren't supported */
4190                         return -EINVAL;
4191                 }
4192         }
4193
4194
4195         if (cfg->has_phy_com_ctrl) {
4196                 void __iomem *status;
4197                 unsigned int mask, val;
4198
4199                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
4200                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
4201                              SERDES_START | PCS_START);
4202
4203                 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
4204                 mask = cfg->mask_com_pcs_ready;
4205
4206                 ret = readl_poll_timeout(status, val, (val & mask), 10,
4207                                          PHY_INIT_COMPLETE_TIMEOUT);
4208                 if (ret) {
4209                         dev_err(qmp->dev,
4210                                 "phy common block init timed-out\n");
4211                         return ret;
4212                 }
4213         }
4214
4215         return 0;
4216 }
4217
4218 static void qcom_qmp_v3_phy_dp_aux_init(struct qmp_phy *qphy)
4219 {
4220         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4221                DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
4222                qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4223
4224         /* Turn on BIAS current for PHY/PLL */
4225         writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
4226                QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
4227                qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
4228
4229         writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4230
4231         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4232                DP_PHY_PD_CTL_LANE_0_1_PWRDN |
4233                DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
4234                DP_PHY_PD_CTL_DP_CLAMP_EN,
4235                qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4236
4237         writel(QSERDES_V3_COM_BIAS_EN |
4238                QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
4239                QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
4240                QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
4241                qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
4242
4243         writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
4244         writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4245         writel(0x24, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4246         writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
4247         writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
4248         writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
4249         writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
4250         writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
4251         writel(0xbb, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
4252         writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
4253         qphy->dp_aux_cfg = 0;
4254
4255         writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
4256                PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
4257                PHY_AUX_REQ_ERR_MASK,
4258                qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
4259 }
4260
4261 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
4262         { 0x00, 0x0c, 0x15, 0x1a },
4263         { 0x02, 0x0e, 0x16, 0xff },
4264         { 0x02, 0x11, 0xff, 0xff },
4265         { 0x04, 0xff, 0xff, 0xff }
4266 };
4267
4268 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
4269         { 0x02, 0x12, 0x16, 0x1a },
4270         { 0x09, 0x19, 0x1f, 0xff },
4271         { 0x10, 0x1f, 0xff, 0xff },
4272         { 0x1f, 0xff, 0xff, 0xff }
4273 };
4274
4275 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
4276         { 0x00, 0x0c, 0x14, 0x19 },
4277         { 0x00, 0x0b, 0x12, 0xff },
4278         { 0x00, 0x0b, 0xff, 0xff },
4279         { 0x04, 0xff, 0xff, 0xff }
4280 };
4281
4282 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
4283         { 0x08, 0x0f, 0x16, 0x1f },
4284         { 0x11, 0x1e, 0x1f, 0xff },
4285         { 0x19, 0x1f, 0xff, 0xff },
4286         { 0x1f, 0xff, 0xff, 0xff }
4287 };
4288
4289 static int qcom_qmp_phy_configure_dp_swing(struct qmp_phy *qphy,
4290                 unsigned int drv_lvl_reg, unsigned int emp_post_reg)
4291 {
4292         const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4293         unsigned int v_level = 0, p_level = 0;
4294         u8 voltage_swing_cfg, pre_emphasis_cfg;
4295         int i;
4296
4297         for (i = 0; i < dp_opts->lanes; i++) {
4298                 v_level = max(v_level, dp_opts->voltage[i]);
4299                 p_level = max(p_level, dp_opts->pre[i]);
4300         }
4301
4302         if (dp_opts->link_rate <= 2700) {
4303                 voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr_rbr[v_level][p_level];
4304                 pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr_rbr[v_level][p_level];
4305         } else {
4306                 voltage_swing_cfg = qmp_dp_v3_voltage_swing_hbr3_hbr2[v_level][p_level];
4307                 pre_emphasis_cfg = qmp_dp_v3_pre_emphasis_hbr3_hbr2[v_level][p_level];
4308         }
4309
4310         /* TODO: Move check to config check */
4311         if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
4312                 return -EINVAL;
4313
4314         /* Enable MUX to use Cursor values from these registers */
4315         voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
4316         pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
4317
4318         writel(voltage_swing_cfg, qphy->tx + drv_lvl_reg);
4319         writel(pre_emphasis_cfg, qphy->tx + emp_post_reg);
4320         writel(voltage_swing_cfg, qphy->tx2 + drv_lvl_reg);
4321         writel(pre_emphasis_cfg, qphy->tx2 + emp_post_reg);
4322
4323         return 0;
4324 }
4325
4326 static void qcom_qmp_v3_phy_configure_dp_tx(struct qmp_phy *qphy)
4327 {
4328         const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4329         u32 bias_en, drvr_en;
4330
4331         if (qcom_qmp_phy_configure_dp_swing(qphy,
4332                                 QSERDES_V3_TX_TX_DRV_LVL,
4333                                 QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
4334                 return;
4335
4336         if (dp_opts->lanes == 1) {
4337                 bias_en = 0x3e;
4338                 drvr_en = 0x13;
4339         } else {
4340                 bias_en = 0x3f;
4341                 drvr_en = 0x10;
4342         }
4343
4344         writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
4345         writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
4346         writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
4347         writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
4348 }
4349
4350 static bool qcom_qmp_phy_configure_dp_mode(struct qmp_phy *qphy)
4351 {
4352         u32 val;
4353         bool reverse = false;
4354
4355         val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4356               DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
4357
4358         /*
4359          * TODO: Assume orientation is CC1 for now and two lanes, need to
4360          * use type-c connector to understand orientation and lanes.
4361          *
4362          * Otherwise val changes to be like below if this code understood
4363          * the orientation of the type-c cable.
4364          *
4365          * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
4366          *      val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
4367          * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
4368          *      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
4369          * if (orientation == ORIENTATION_CC2)
4370          *      writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
4371          */
4372         val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
4373         writel(val, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4374
4375         writel(0x5c, qphy->pcs + QSERDES_DP_PHY_MODE);
4376
4377         return reverse;
4378 }
4379
4380 static int qcom_qmp_v3_phy_configure_dp_phy(struct qmp_phy *qphy)
4381 {
4382         const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
4383         const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4384         u32 phy_vco_div, status;
4385         unsigned long pixel_freq;
4386
4387         qcom_qmp_phy_configure_dp_mode(qphy);
4388
4389         writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
4390         writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
4391
4392         switch (dp_opts->link_rate) {
4393         case 1620:
4394                 phy_vco_div = 0x1;
4395                 pixel_freq = 1620000000UL / 2;
4396                 break;
4397         case 2700:
4398                 phy_vco_div = 0x1;
4399                 pixel_freq = 2700000000UL / 2;
4400                 break;
4401         case 5400:
4402                 phy_vco_div = 0x2;
4403                 pixel_freq = 5400000000UL / 4;
4404                 break;
4405         case 8100:
4406                 phy_vco_div = 0x0;
4407                 pixel_freq = 8100000000UL / 6;
4408                 break;
4409         default:
4410                 /* Other link rates aren't supported */
4411                 return -EINVAL;
4412         }
4413         writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
4414
4415         clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
4416         clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
4417
4418         writel(0x04, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4419         writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4420         writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
4421         writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4422         writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
4423
4424         writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
4425
4426         if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
4427                         status,
4428                         ((status & BIT(0)) > 0),
4429                         500,
4430                         10000))
4431                 return -ETIMEDOUT;
4432
4433         writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4434
4435         if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
4436                         status,
4437                         ((status & BIT(1)) > 0),
4438                         500,
4439                         10000))
4440                 return -ETIMEDOUT;
4441
4442         writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
4443         udelay(2000);
4444         writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4445
4446         return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
4447                         status,
4448                         ((status & BIT(1)) > 0),
4449                         500,
4450                         10000);
4451 }
4452
4453 /*
4454  * We need to calibrate the aux setting here as many times
4455  * as the caller tries
4456  */
4457 static int qcom_qmp_v3_dp_phy_calibrate(struct qmp_phy *qphy)
4458 {
4459         static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
4460         u8 val;
4461
4462         qphy->dp_aux_cfg++;
4463         qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
4464         val = cfg1_settings[qphy->dp_aux_cfg];
4465
4466         writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4467
4468         return 0;
4469 }
4470
4471 static void qcom_qmp_v4_phy_dp_aux_init(struct qmp_phy *qphy)
4472 {
4473         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
4474                DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
4475                qphy->pcs + QSERDES_DP_PHY_PD_CTL);
4476
4477         /* Turn on BIAS current for PHY/PLL */
4478         writel(0x17, qphy->serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
4479
4480         writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG0);
4481         writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4482         writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4483         writel(0x00, qphy->pcs + QSERDES_DP_PHY_AUX_CFG3);
4484         writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG4);
4485         writel(0x26, qphy->pcs + QSERDES_DP_PHY_AUX_CFG5);
4486         writel(0x0a, qphy->pcs + QSERDES_DP_PHY_AUX_CFG6);
4487         writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG7);
4488         writel(0xb7, qphy->pcs + QSERDES_DP_PHY_AUX_CFG8);
4489         writel(0x03, qphy->pcs + QSERDES_DP_PHY_AUX_CFG9);
4490         qphy->dp_aux_cfg = 0;
4491
4492         writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
4493                PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
4494                PHY_AUX_REQ_ERR_MASK,
4495                qphy->pcs + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
4496 }
4497
4498 static void qcom_qmp_v4_phy_configure_dp_tx(struct qmp_phy *qphy)
4499 {
4500         /* Program default values before writing proper values */
4501         writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
4502         writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
4503
4504         writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4505         writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4506
4507         qcom_qmp_phy_configure_dp_swing(qphy,
4508                         QSERDES_V4_TX_TX_DRV_LVL,
4509                         QSERDES_V4_TX_TX_EMP_POST1_LVL);
4510 }
4511
4512 static int qcom_qmp_v4_phy_configure_dp_phy(struct qmp_phy *qphy)
4513 {
4514         const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
4515         const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
4516         u32 phy_vco_div, status;
4517         unsigned long pixel_freq;
4518         u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
4519         bool reverse;
4520
4521         writel(0x0f, qphy->pcs + QSERDES_V4_DP_PHY_CFG_1);
4522
4523         reverse = qcom_qmp_phy_configure_dp_mode(qphy);
4524
4525         writel(0x13, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4526         writel(0xa4, qphy->pcs + QSERDES_DP_PHY_AUX_CFG2);
4527
4528         writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
4529         writel(0x05, qphy->pcs + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
4530
4531         switch (dp_opts->link_rate) {
4532         case 1620:
4533                 phy_vco_div = 0x1;
4534                 pixel_freq = 1620000000UL / 2;
4535                 break;
4536         case 2700:
4537                 phy_vco_div = 0x1;
4538                 pixel_freq = 2700000000UL / 2;
4539                 break;
4540         case 5400:
4541                 phy_vco_div = 0x2;
4542                 pixel_freq = 5400000000UL / 4;
4543                 break;
4544         case 8100:
4545                 phy_vco_div = 0x0;
4546                 pixel_freq = 8100000000UL / 6;
4547                 break;
4548         default:
4549                 /* Other link rates aren't supported */
4550                 return -EINVAL;
4551         }
4552         writel(phy_vco_div, qphy->pcs + QSERDES_V4_DP_PHY_VCO_DIV);
4553
4554         clk_set_rate(dp_clks->dp_link_hw.clk, dp_opts->link_rate * 100000);
4555         clk_set_rate(dp_clks->dp_pixel_hw.clk, pixel_freq);
4556
4557         writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4558         writel(0x05, qphy->pcs + QSERDES_DP_PHY_CFG);
4559         writel(0x01, qphy->pcs + QSERDES_DP_PHY_CFG);
4560         writel(0x09, qphy->pcs + QSERDES_DP_PHY_CFG);
4561
4562         writel(0x20, qphy->serdes + QSERDES_V4_COM_RESETSM_CNTRL);
4563
4564         if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_C_READY_STATUS,
4565                         status,
4566                         ((status & BIT(0)) > 0),
4567                         500,
4568                         10000))
4569                 return -ETIMEDOUT;
4570
4571         if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
4572                         status,
4573                         ((status & BIT(0)) > 0),
4574                         500,
4575                         10000))
4576                 return -ETIMEDOUT;
4577
4578         if (readl_poll_timeout(qphy->serdes + QSERDES_V4_COM_CMN_STATUS,
4579                         status,
4580                         ((status & BIT(1)) > 0),
4581                         500,
4582                         10000))
4583                 return -ETIMEDOUT;
4584
4585         writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4586
4587         if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
4588                         status,
4589                         ((status & BIT(0)) > 0),
4590                         500,
4591                         10000))
4592                 return -ETIMEDOUT;
4593
4594         if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
4595                         status,
4596                         ((status & BIT(1)) > 0),
4597                         500,
4598                         10000))
4599                 return -ETIMEDOUT;
4600
4601         /*
4602          * At least for 7nm DP PHY this has to be done after enabling link
4603          * clock.
4604          */
4605
4606         if (dp_opts->lanes == 1) {
4607                 bias0_en = reverse ? 0x3e : 0x15;
4608                 bias1_en = reverse ? 0x15 : 0x3e;
4609                 drvr0_en = reverse ? 0x13 : 0x10;
4610                 drvr1_en = reverse ? 0x10 : 0x13;
4611         } else if (dp_opts->lanes == 2) {
4612                 bias0_en = reverse ? 0x3f : 0x15;
4613                 bias1_en = reverse ? 0x15 : 0x3f;
4614                 drvr0_en = 0x10;
4615                 drvr1_en = 0x10;
4616         } else {
4617                 bias0_en = 0x3f;
4618                 bias1_en = 0x3f;
4619                 drvr0_en = 0x10;
4620                 drvr1_en = 0x10;
4621         }
4622
4623         writel(drvr0_en, qphy->tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
4624         writel(bias0_en, qphy->tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
4625         writel(drvr1_en, qphy->tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
4626         writel(bias1_en, qphy->tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
4627
4628         writel(0x18, qphy->pcs + QSERDES_DP_PHY_CFG);
4629         udelay(2000);
4630         writel(0x19, qphy->pcs + QSERDES_DP_PHY_CFG);
4631
4632         if (readl_poll_timeout(qphy->pcs + QSERDES_V4_DP_PHY_STATUS,
4633                         status,
4634                         ((status & BIT(1)) > 0),
4635                         500,
4636                         10000))
4637                 return -ETIMEDOUT;
4638
4639         writel(0x0a, qphy->tx + QSERDES_V4_TX_TX_POL_INV);
4640         writel(0x0a, qphy->tx2 + QSERDES_V4_TX_TX_POL_INV);
4641
4642         writel(0x27, qphy->tx + QSERDES_V4_TX_TX_DRV_LVL);
4643         writel(0x27, qphy->tx2 + QSERDES_V4_TX_TX_DRV_LVL);
4644
4645         writel(0x20, qphy->tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4646         writel(0x20, qphy->tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
4647
4648         return 0;
4649 }
4650
4651 /*
4652  * We need to calibrate the aux setting here as many times
4653  * as the caller tries
4654  */
4655 static int qcom_qmp_v4_dp_phy_calibrate(struct qmp_phy *qphy)
4656 {
4657         static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
4658         u8 val;
4659
4660         qphy->dp_aux_cfg++;
4661         qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
4662         val = cfg1_settings[qphy->dp_aux_cfg];
4663
4664         writel(val, qphy->pcs + QSERDES_DP_PHY_AUX_CFG1);
4665
4666         return 0;
4667 }
4668
4669 static int qcom_qmp_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
4670 {
4671         const struct phy_configure_opts_dp *dp_opts = &opts->dp;
4672         struct qmp_phy *qphy = phy_get_drvdata(phy);
4673         const struct qmp_phy_cfg *cfg = qphy->cfg;
4674
4675         memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
4676         if (qphy->dp_opts.set_voltages) {
4677                 cfg->configure_dp_tx(qphy);
4678                 qphy->dp_opts.set_voltages = 0;
4679         }
4680
4681         return 0;
4682 }
4683
4684 static int qcom_qmp_dp_phy_calibrate(struct phy *phy)
4685 {
4686         struct qmp_phy *qphy = phy_get_drvdata(phy);
4687         const struct qmp_phy_cfg *cfg = qphy->cfg;
4688
4689         if (cfg->calibrate_dp_phy)
4690                 return cfg->calibrate_dp_phy(qphy);
4691
4692         return 0;
4693 }
4694
4695 static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
4696 {
4697         struct qcom_qmp *qmp = qphy->qmp;
4698         const struct qmp_phy_cfg *cfg = qphy->cfg;
4699         void __iomem *serdes = qphy->serdes;
4700         void __iomem *pcs = qphy->pcs;
4701         void __iomem *dp_com = qmp->dp_com;
4702         int ret, i;
4703
4704         mutex_lock(&qmp->phy_mutex);
4705         if (qmp->init_count++) {
4706                 mutex_unlock(&qmp->phy_mutex);
4707                 return 0;
4708         }
4709
4710         /* turn on regulator supplies */
4711         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
4712         if (ret) {
4713                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
4714                 goto err_reg_enable;
4715         }
4716
4717         for (i = 0; i < cfg->num_resets; i++) {
4718                 ret = reset_control_assert(qmp->resets[i]);
4719                 if (ret) {
4720                         dev_err(qmp->dev, "%s reset assert failed\n",
4721                                 cfg->reset_list[i]);
4722                         goto err_rst_assert;
4723                 }
4724         }
4725
4726         for (i = cfg->num_resets - 1; i >= 0; i--) {
4727                 ret = reset_control_deassert(qmp->resets[i]);
4728                 if (ret) {
4729                         dev_err(qmp->dev, "%s reset deassert failed\n",
4730                                 qphy->cfg->reset_list[i]);
4731                         goto err_rst;
4732                 }
4733         }
4734
4735         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
4736         if (ret)
4737                 goto err_rst;
4738
4739         if (cfg->has_phy_dp_com_ctrl) {
4740                 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
4741                              SW_PWRDN);
4742                 /* override hardware control for reset of qmp phy */
4743                 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
4744                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
4745                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
4746
4747                 /* Default type-c orientation, i.e CC1 */
4748                 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
4749
4750                 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
4751                              USB3_MODE | DP_MODE);
4752
4753                 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
4754                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
4755                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
4756                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
4757
4758                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
4759                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
4760         }
4761
4762         if (cfg->has_phy_com_ctrl) {
4763                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
4764                              SW_PWRDN);
4765         } else {
4766                 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
4767                         qphy_setbits(pcs,
4768                                         cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
4769                                         cfg->pwrdn_ctrl);
4770                 else
4771                         qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
4772                                         cfg->pwrdn_ctrl);
4773         }
4774
4775         mutex_unlock(&qmp->phy_mutex);
4776
4777         return 0;
4778
4779 err_rst:
4780         while (++i < cfg->num_resets)
4781                 reset_control_assert(qmp->resets[i]);
4782 err_rst_assert:
4783         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
4784 err_reg_enable:
4785         mutex_unlock(&qmp->phy_mutex);
4786
4787         return ret;
4788 }
4789
4790 static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
4791 {
4792         struct qcom_qmp *qmp = qphy->qmp;
4793         const struct qmp_phy_cfg *cfg = qphy->cfg;
4794         void __iomem *serdes = qphy->serdes;
4795         int i = cfg->num_resets;
4796
4797         mutex_lock(&qmp->phy_mutex);
4798         if (--qmp->init_count) {
4799                 mutex_unlock(&qmp->phy_mutex);
4800                 return 0;
4801         }
4802
4803         reset_control_assert(qmp->ufs_reset);
4804         if (cfg->has_phy_com_ctrl) {
4805                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
4806                              SERDES_START | PCS_START);
4807                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
4808                              SW_RESET);
4809                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
4810                              SW_PWRDN);
4811         }
4812
4813         while (--i >= 0)
4814                 reset_control_assert(qmp->resets[i]);
4815
4816         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
4817
4818         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
4819
4820         mutex_unlock(&qmp->phy_mutex);
4821
4822         return 0;
4823 }
4824
4825 static int qcom_qmp_phy_init(struct phy *phy)
4826 {
4827         struct qmp_phy *qphy = phy_get_drvdata(phy);
4828         struct qcom_qmp *qmp = qphy->qmp;
4829         const struct qmp_phy_cfg *cfg = qphy->cfg;
4830         int ret;
4831         dev_vdbg(qmp->dev, "Initializing QMP phy\n");
4832
4833         if (cfg->no_pcs_sw_reset) {
4834                 /*
4835                  * Get UFS reset, which is delayed until now to avoid a
4836                  * circular dependency where UFS needs its PHY, but the PHY
4837                  * needs this UFS reset.
4838                  */
4839                 if (!qmp->ufs_reset) {
4840                         qmp->ufs_reset =
4841                                 devm_reset_control_get_exclusive(qmp->dev,
4842                                                                  "ufsphy");
4843
4844                         if (IS_ERR(qmp->ufs_reset)) {
4845                                 ret = PTR_ERR(qmp->ufs_reset);
4846                                 dev_err(qmp->dev,
4847                                         "failed to get UFS reset: %d\n",
4848                                         ret);
4849
4850                                 qmp->ufs_reset = NULL;
4851                                 return ret;
4852                         }
4853                 }
4854
4855                 ret = reset_control_assert(qmp->ufs_reset);
4856                 if (ret)
4857                         return ret;
4858         }
4859
4860         ret = qcom_qmp_phy_com_init(qphy);
4861         if (ret)
4862                 return ret;
4863
4864         if (cfg->type == PHY_TYPE_DP)
4865                 cfg->dp_aux_init(qphy);
4866
4867         return 0;
4868 }
4869
4870 static int qcom_qmp_phy_power_on(struct phy *phy)
4871 {
4872         struct qmp_phy *qphy = phy_get_drvdata(phy);
4873         struct qcom_qmp *qmp = qphy->qmp;
4874         const struct qmp_phy_cfg *cfg = qphy->cfg;
4875         void __iomem *tx = qphy->tx;
4876         void __iomem *rx = qphy->rx;
4877         void __iomem *pcs = qphy->pcs;
4878         void __iomem *pcs_misc = qphy->pcs_misc;
4879         void __iomem *status;
4880         unsigned int mask, val, ready;
4881         int ret;
4882
4883         qcom_qmp_phy_serdes_init(qphy);
4884
4885         if (cfg->has_lane_rst) {
4886                 ret = reset_control_deassert(qphy->lane_rst);
4887                 if (ret) {
4888                         dev_err(qmp->dev, "lane%d reset deassert failed\n",
4889                                 qphy->index);
4890                         goto err_lane_rst;
4891                 }
4892         }
4893
4894         ret = clk_prepare_enable(qphy->pipe_clk);
4895         if (ret) {
4896                 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
4897                 goto err_clk_enable;
4898         }
4899
4900         /* Tx, Rx, and PCS configurations */
4901         qcom_qmp_phy_configure_lane(tx, cfg->regs,
4902                                     cfg->tx_tbl, cfg->tx_tbl_num, 1);
4903         if (cfg->tx_tbl_sec)
4904                 qcom_qmp_phy_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec,
4905                                             cfg->tx_tbl_num_sec, 1);
4906
4907         /* Configuration for other LANE for USB-DP combo PHY */
4908         if (cfg->is_dual_lane_phy) {
4909                 qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
4910                                             cfg->tx_tbl, cfg->tx_tbl_num, 2);
4911                 if (cfg->tx_tbl_sec)
4912                         qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
4913                                                     cfg->tx_tbl_sec,
4914                                                     cfg->tx_tbl_num_sec, 2);
4915         }
4916
4917         /* Configure special DP tx tunings */
4918         if (cfg->type == PHY_TYPE_DP)
4919                 cfg->configure_dp_tx(qphy);
4920
4921         qcom_qmp_phy_configure_lane(rx, cfg->regs,
4922                                     cfg->rx_tbl, cfg->rx_tbl_num, 1);
4923         if (cfg->rx_tbl_sec)
4924                 qcom_qmp_phy_configure_lane(rx, cfg->regs,
4925                                             cfg->rx_tbl_sec, cfg->rx_tbl_num_sec, 1);
4926
4927         if (cfg->is_dual_lane_phy) {
4928                 qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
4929                                             cfg->rx_tbl, cfg->rx_tbl_num, 2);
4930                 if (cfg->rx_tbl_sec)
4931                         qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
4932                                                     cfg->rx_tbl_sec,
4933                                                     cfg->rx_tbl_num_sec, 2);
4934         }
4935
4936         /* Configure link rate, swing, etc. */
4937         if (cfg->type == PHY_TYPE_DP) {
4938                 cfg->configure_dp_phy(qphy);
4939         } else {
4940                 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
4941                 if (cfg->pcs_tbl_sec)
4942                         qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl_sec,
4943                                                cfg->pcs_tbl_num_sec);
4944         }
4945
4946         ret = reset_control_deassert(qmp->ufs_reset);
4947         if (ret)
4948                 goto err_lane_rst;
4949
4950         qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
4951                                cfg->pcs_misc_tbl_num);
4952         if (cfg->pcs_misc_tbl_sec)
4953                 qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl_sec,
4954                                        cfg->pcs_misc_tbl_num_sec);
4955
4956         /*
4957          * Pull out PHY from POWER DOWN state.
4958          * This is active low enable signal to power-down PHY.
4959          */
4960         if(cfg->type == PHY_TYPE_PCIE)
4961                 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
4962
4963         if (cfg->has_pwrdn_delay)
4964                 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
4965
4966         if (cfg->type != PHY_TYPE_DP) {
4967                 /* Pull PHY out of reset state */
4968                 if (!cfg->no_pcs_sw_reset)
4969                         qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
4970                 /* start SerDes and Phy-Coding-Sublayer */
4971                 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
4972
4973                 if (cfg->type == PHY_TYPE_UFS) {
4974                         status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
4975                         mask = PCS_READY;
4976                         ready = PCS_READY;
4977                 } else {
4978                         status = pcs + cfg->regs[QPHY_PCS_STATUS];
4979                         mask = cfg->phy_status;
4980                         ready = 0;
4981                 }
4982
4983                 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
4984                                          PHY_INIT_COMPLETE_TIMEOUT);
4985                 if (ret) {
4986                         dev_err(qmp->dev, "phy initialization timed-out\n");
4987                         goto err_pcs_ready;
4988                 }
4989         }
4990         return 0;
4991
4992 err_pcs_ready:
4993         clk_disable_unprepare(qphy->pipe_clk);
4994 err_clk_enable:
4995         if (cfg->has_lane_rst)
4996                 reset_control_assert(qphy->lane_rst);
4997 err_lane_rst:
4998         return ret;
4999 }
5000
5001 static int qcom_qmp_phy_power_off(struct phy *phy)
5002 {
5003         struct qmp_phy *qphy = phy_get_drvdata(phy);
5004         const struct qmp_phy_cfg *cfg = qphy->cfg;
5005
5006         clk_disable_unprepare(qphy->pipe_clk);
5007
5008         if (cfg->type == PHY_TYPE_DP) {
5009                 /* Assert DP PHY power down */
5010                 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_DP_PHY_PD_CTL);
5011         } else {
5012                 /* PHY reset */
5013                 if (!cfg->no_pcs_sw_reset)
5014                         qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
5015
5016                 /* stop SerDes and Phy-Coding-Sublayer */
5017                 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
5018
5019                 /* Put PHY into POWER DOWN state: active low */
5020                 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
5021                         qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
5022                                      cfg->pwrdn_ctrl);
5023                 } else {
5024                         qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
5025                                         cfg->pwrdn_ctrl);
5026                 }
5027         }
5028
5029         return 0;
5030 }
5031
5032 static int qcom_qmp_phy_exit(struct phy *phy)
5033 {
5034         struct qmp_phy *qphy = phy_get_drvdata(phy);
5035         const struct qmp_phy_cfg *cfg = qphy->cfg;
5036
5037         if (cfg->has_lane_rst)
5038                 reset_control_assert(qphy->lane_rst);
5039
5040         qcom_qmp_phy_com_exit(qphy);
5041
5042         return 0;
5043 }
5044
5045 static int qcom_qmp_phy_enable(struct phy *phy)
5046 {
5047         int ret;
5048
5049         ret = qcom_qmp_phy_init(phy);
5050         if (ret)
5051                 return ret;
5052
5053         ret = qcom_qmp_phy_power_on(phy);
5054         if (ret)
5055                 qcom_qmp_phy_exit(phy);
5056
5057         return ret;
5058 }
5059
5060 static int qcom_qmp_phy_disable(struct phy *phy)
5061 {
5062         int ret;
5063
5064         ret = qcom_qmp_phy_power_off(phy);
5065         if (ret)
5066                 return ret;
5067         return qcom_qmp_phy_exit(phy);
5068 }
5069
5070 static int qcom_qmp_phy_set_mode(struct phy *phy,
5071                                  enum phy_mode mode, int submode)
5072 {
5073         struct qmp_phy *qphy = phy_get_drvdata(phy);
5074
5075         qphy->mode = mode;
5076
5077         return 0;
5078 }
5079
5080 static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
5081 {
5082         const struct qmp_phy_cfg *cfg = qphy->cfg;
5083         void __iomem *pcs = qphy->pcs;
5084         void __iomem *pcs_misc = qphy->pcs_misc;
5085         u32 intr_mask;
5086
5087         if (qphy->mode == PHY_MODE_USB_HOST_SS ||
5088             qphy->mode == PHY_MODE_USB_DEVICE_SS)
5089                 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
5090         else
5091                 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
5092
5093         /* Clear any pending interrupts status */
5094         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
5095         /* Writing 1 followed by 0 clears the interrupt */
5096         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
5097
5098         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
5099                      ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
5100
5101         /* Enable required PHY autonomous mode interrupts */
5102         qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
5103
5104         /* Enable i/o clamp_n for autonomous mode */
5105         if (pcs_misc)
5106                 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
5107 }
5108
5109 static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
5110 {
5111         const struct qmp_phy_cfg *cfg = qphy->cfg;
5112         void __iomem *pcs = qphy->pcs;
5113         void __iomem *pcs_misc = qphy->pcs_misc;
5114
5115         /* Disable i/o clamp_n on resume for normal mode */
5116         if (pcs_misc)
5117                 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
5118
5119         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
5120                      ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
5121
5122         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
5123         /* Writing 1 followed by 0 clears the interrupt */
5124         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
5125 }
5126
5127 static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
5128 {
5129         struct qcom_qmp *qmp = dev_get_drvdata(dev);
5130         struct qmp_phy *qphy = qmp->phys[0];
5131         const struct qmp_phy_cfg *cfg = qphy->cfg;
5132
5133         dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
5134
5135         /* Supported only for USB3 PHY and luckily USB3 is the first phy */
5136         if (cfg->type != PHY_TYPE_USB3)
5137                 return 0;
5138
5139         if (!qmp->init_count) {
5140                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
5141                 return 0;
5142         }
5143
5144         qcom_qmp_phy_enable_autonomous_mode(qphy);
5145
5146         clk_disable_unprepare(qphy->pipe_clk);
5147         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
5148
5149         return 0;
5150 }
5151
5152 static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
5153 {
5154         struct qcom_qmp *qmp = dev_get_drvdata(dev);
5155         struct qmp_phy *qphy = qmp->phys[0];
5156         const struct qmp_phy_cfg *cfg = qphy->cfg;
5157         int ret = 0;
5158
5159         dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
5160
5161         /* Supported only for USB3 PHY and luckily USB3 is the first phy */
5162         if (cfg->type != PHY_TYPE_USB3)
5163                 return 0;
5164
5165         if (!qmp->init_count) {
5166                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
5167                 return 0;
5168         }
5169
5170         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
5171         if (ret)
5172                 return ret;
5173
5174         ret = clk_prepare_enable(qphy->pipe_clk);
5175         if (ret) {
5176                 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
5177                 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
5178                 return ret;
5179         }
5180
5181         qcom_qmp_phy_disable_autonomous_mode(qphy);
5182
5183         return 0;
5184 }
5185
5186 static int qcom_qmp_phy_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
5187 {
5188         struct qcom_qmp *qmp = dev_get_drvdata(dev);
5189         int num = cfg->num_vregs;
5190         int i;
5191
5192         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
5193         if (!qmp->vregs)
5194                 return -ENOMEM;
5195
5196         for (i = 0; i < num; i++)
5197                 qmp->vregs[i].supply = cfg->vreg_list[i];
5198
5199         return devm_regulator_bulk_get(dev, num, qmp->vregs);
5200 }
5201
5202 static int qcom_qmp_phy_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
5203 {
5204         struct qcom_qmp *qmp = dev_get_drvdata(dev);
5205         int i;
5206
5207         qmp->resets = devm_kcalloc(dev, cfg->num_resets,
5208                                    sizeof(*qmp->resets), GFP_KERNEL);
5209         if (!qmp->resets)
5210                 return -ENOMEM;
5211
5212         for (i = 0; i < cfg->num_resets; i++) {
5213                 struct reset_control *rst;
5214                 const char *name = cfg->reset_list[i];
5215
5216                 rst = devm_reset_control_get(dev, name);
5217                 if (IS_ERR(rst)) {
5218                         dev_err(dev, "failed to get %s reset\n", name);
5219                         return PTR_ERR(rst);
5220                 }
5221                 qmp->resets[i] = rst;
5222         }
5223
5224         return 0;
5225 }
5226
5227 static int qcom_qmp_phy_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
5228 {
5229         struct qcom_qmp *qmp = dev_get_drvdata(dev);
5230         int num = cfg->num_clks;
5231         int i;
5232
5233         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
5234         if (!qmp->clks)
5235                 return -ENOMEM;
5236
5237         for (i = 0; i < num; i++)
5238                 qmp->clks[i].id = cfg->clk_list[i];
5239
5240         return devm_clk_bulk_get(dev, num, qmp->clks);
5241 }
5242
5243 static void phy_clk_release_provider(void *res)
5244 {
5245         of_clk_del_provider(res);
5246 }
5247
5248 /*
5249  * Register a fixed rate pipe clock.
5250  *
5251  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
5252  * controls it. The <s>_pipe_clk coming out of the GCC is requested
5253  * by the PHY driver for its operations.
5254  * We register the <s>_pipe_clksrc here. The gcc driver takes care
5255  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
5256  * Below picture shows this relationship.
5257  *
5258  *         +---------------+
5259  *         |   PHY block   |<<---------------------------------------+
5260  *         |               |                                         |
5261  *         |   +-------+   |                   +-----+               |
5262  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
5263  *    clk  |   +-------+   |                   +-----+
5264  *         +---------------+
5265  */
5266 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
5267 {
5268         struct clk_fixed_rate *fixed;
5269         struct clk_init_data init = { };
5270         int ret;
5271
5272         ret = of_property_read_string(np, "clock-output-names", &init.name);
5273         if (ret) {
5274                 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
5275                 return ret;
5276         }
5277
5278         fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
5279         if (!fixed)
5280                 return -ENOMEM;
5281
5282         init.ops = &clk_fixed_rate_ops;
5283
5284         /* controllers using QMP phys use 125MHz pipe clock interface */
5285         fixed->fixed_rate = 125000000;
5286         fixed->hw.init = &init;
5287
5288         ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
5289         if (ret)
5290                 return ret;
5291
5292         ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
5293         if (ret)
5294                 return ret;
5295
5296         /*
5297          * Roll a devm action because the clock provider is the child node, but
5298          * the child node is not actually a device.
5299          */
5300         return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
5301 }
5302
5303 /*
5304  * Display Port PLL driver block diagram for branch clocks
5305  *
5306  *              +------------------------------+
5307  *              |         DP_VCO_CLK           |
5308  *              |                              |
5309  *              |    +-------------------+     |
5310  *              |    |   (DP PLL/VCO)    |     |
5311  *              |    +---------+---------+     |
5312  *              |              v               |
5313  *              |   +----------+-----------+   |
5314  *              |   | hsclk_divsel_clk_src |   |
5315  *              |   +----------+-----------+   |
5316  *              +------------------------------+
5317  *                              |
5318  *          +---------<---------v------------>----------+
5319  *          |                                           |
5320  * +--------v----------------+                          |
5321  * |    dp_phy_pll_link_clk  |                          |
5322  * |     link_clk            |                          |
5323  * +--------+----------------+                          |
5324  *          |                                           |
5325  *          |                                           |
5326  *          v                                           v
5327  * Input to DISPCC block                                |
5328  * for link clk, crypto clk                             |
5329  * and interface clock                                  |
5330  *                                                      |
5331  *                                                      |
5332  *      +--------<------------+-----------------+---<---+
5333  *      |                     |                 |
5334  * +----v---------+  +--------v-----+  +--------v------+
5335  * | vco_divided  |  | vco_divided  |  | vco_divided   |
5336  * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
5337  * |              |  |              |  |               |
5338  * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
5339  * +-------+------+  +-----+--------+  +--------+------+
5340  *         |                 |                  |
5341  *         v---->----------v-------------<------v
5342  *                         |
5343  *              +----------+-----------------+
5344  *              |   dp_phy_pll_vco_div_clk   |
5345  *              +---------+------------------+
5346  *                        |
5347  *                        v
5348  *              Input to DISPCC block
5349  *              for DP pixel clock
5350  *
5351  */
5352 static int qcom_qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw,
5353                                                 struct clk_rate_request *req)
5354 {
5355         switch (req->rate) {
5356         case 1620000000UL / 2:
5357         case 2700000000UL / 2:
5358         /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
5359                 return 0;
5360         default:
5361                 return -EINVAL;
5362         }
5363 }
5364
5365 static unsigned long
5366 qcom_qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
5367 {
5368         const struct qmp_phy_dp_clks *dp_clks;
5369         const struct qmp_phy *qphy;
5370         const struct phy_configure_opts_dp *dp_opts;
5371
5372         dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_pixel_hw);
5373         qphy = dp_clks->qphy;
5374         dp_opts = &qphy->dp_opts;
5375
5376         switch (dp_opts->link_rate) {
5377         case 1620:
5378                 return 1620000000UL / 2;
5379         case 2700:
5380                 return 2700000000UL / 2;
5381         case 5400:
5382                 return 5400000000UL / 4;
5383         case 8100:
5384                 return 8100000000UL / 6;
5385         default:
5386                 return 0;
5387         }
5388 }
5389
5390 static const struct clk_ops qcom_qmp_dp_pixel_clk_ops = {
5391         .determine_rate = qcom_qmp_dp_pixel_clk_determine_rate,
5392         .recalc_rate = qcom_qmp_dp_pixel_clk_recalc_rate,
5393 };
5394
5395 static int qcom_qmp_dp_link_clk_determine_rate(struct clk_hw *hw,
5396                                                struct clk_rate_request *req)
5397 {
5398         switch (req->rate) {
5399         case 162000000:
5400         case 270000000:
5401         case 540000000:
5402         case 810000000:
5403                 return 0;
5404         default:
5405                 return -EINVAL;
5406         }
5407 }
5408
5409 static unsigned long
5410 qcom_qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
5411 {
5412         const struct qmp_phy_dp_clks *dp_clks;
5413         const struct qmp_phy *qphy;
5414         const struct phy_configure_opts_dp *dp_opts;
5415
5416         dp_clks = container_of(hw, struct qmp_phy_dp_clks, dp_link_hw);
5417         qphy = dp_clks->qphy;
5418         dp_opts = &qphy->dp_opts;
5419
5420         switch (dp_opts->link_rate) {
5421         case 1620:
5422         case 2700:
5423         case 5400:
5424         case 8100:
5425                 return dp_opts->link_rate * 100000;
5426         default:
5427                 return 0;
5428         }
5429 }
5430
5431 static const struct clk_ops qcom_qmp_dp_link_clk_ops = {
5432         .determine_rate = qcom_qmp_dp_link_clk_determine_rate,
5433         .recalc_rate = qcom_qmp_dp_link_clk_recalc_rate,
5434 };
5435
5436 static struct clk_hw *
5437 qcom_qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
5438 {
5439         struct qmp_phy_dp_clks *dp_clks = data;
5440         unsigned int idx = clkspec->args[0];
5441
5442         if (idx >= 2) {
5443                 pr_err("%s: invalid index %u\n", __func__, idx);
5444                 return ERR_PTR(-EINVAL);
5445         }
5446
5447         if (idx == 0)
5448                 return &dp_clks->dp_link_hw;
5449
5450         return &dp_clks->dp_pixel_hw;
5451 }
5452
5453 static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
5454                                 struct device_node *np)
5455 {
5456         struct clk_init_data init = { };
5457         struct qmp_phy_dp_clks *dp_clks;
5458         char name[64];
5459         int ret;
5460
5461         dp_clks = devm_kzalloc(qmp->dev, sizeof(*dp_clks), GFP_KERNEL);
5462         if (!dp_clks)
5463                 return -ENOMEM;
5464
5465         dp_clks->qphy = qphy;
5466         qphy->dp_clks = dp_clks;
5467
5468         snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
5469         init.ops = &qcom_qmp_dp_link_clk_ops;
5470         init.name = name;
5471         dp_clks->dp_link_hw.init = &init;
5472         ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_link_hw);
5473         if (ret)
5474                 return ret;
5475
5476         snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
5477         init.ops = &qcom_qmp_dp_pixel_clk_ops;
5478         init.name = name;
5479         dp_clks->dp_pixel_hw.init = &init;
5480         ret = devm_clk_hw_register(qmp->dev, &dp_clks->dp_pixel_hw);
5481         if (ret)
5482                 return ret;
5483
5484         ret = of_clk_add_hw_provider(np, qcom_qmp_dp_clks_hw_get, dp_clks);
5485         if (ret)
5486                 return ret;
5487
5488         /*
5489          * Roll a devm action because the clock provider is the child node, but
5490          * the child node is not actually a device.
5491          */
5492         return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
5493 }
5494
5495 static const struct phy_ops qcom_qmp_phy_gen_ops = {
5496         .init           = qcom_qmp_phy_enable,
5497         .exit           = qcom_qmp_phy_disable,
5498         .set_mode       = qcom_qmp_phy_set_mode,
5499         .owner          = THIS_MODULE,
5500 };
5501
5502 static const struct phy_ops qcom_qmp_phy_dp_ops = {
5503         .init           = qcom_qmp_phy_init,
5504         .configure      = qcom_qmp_dp_phy_configure,
5505         .power_on       = qcom_qmp_phy_power_on,
5506         .calibrate      = qcom_qmp_dp_phy_calibrate,
5507         .power_off      = qcom_qmp_phy_power_off,
5508         .exit           = qcom_qmp_phy_exit,
5509         .set_mode       = qcom_qmp_phy_set_mode,
5510         .owner          = THIS_MODULE,
5511 };
5512
5513 static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
5514         .power_on       = qcom_qmp_phy_enable,
5515         .power_off      = qcom_qmp_phy_disable,
5516         .set_mode       = qcom_qmp_phy_set_mode,
5517         .owner          = THIS_MODULE,
5518 };
5519
5520 static
5521 int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id,
5522                         void __iomem *serdes, const struct qmp_phy_cfg *cfg)
5523 {
5524         struct qcom_qmp *qmp = dev_get_drvdata(dev);
5525         struct phy *generic_phy;
5526         struct qmp_phy *qphy;
5527         const struct phy_ops *ops;
5528         char prop_name[MAX_PROP_NAME];
5529         int ret;
5530
5531         qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
5532         if (!qphy)
5533                 return -ENOMEM;
5534
5535         qphy->cfg = cfg;
5536         qphy->serdes = serdes;
5537         /*
5538          * Get memory resources for each phy lane:
5539          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
5540          * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
5541          * For single lane PHYs: pcs_misc (optional) -> 3.
5542          */
5543         qphy->tx = of_iomap(np, 0);
5544         if (!qphy->tx)
5545                 return -ENOMEM;
5546
5547         qphy->rx = of_iomap(np, 1);
5548         if (!qphy->rx)
5549                 return -ENOMEM;
5550
5551         qphy->pcs = of_iomap(np, 2);
5552         if (!qphy->pcs)
5553                 return -ENOMEM;
5554
5555         /*
5556          * If this is a dual-lane PHY, then there should be registers for the
5557          * second lane. Some old device trees did not specify this, so fall
5558          * back to old legacy behavior of assuming they can be reached at an
5559          * offset from the first lane.
5560          */
5561         if (cfg->is_dual_lane_phy) {
5562                 qphy->tx2 = of_iomap(np, 3);
5563                 qphy->rx2 = of_iomap(np, 4);
5564                 if (!qphy->tx2 || !qphy->rx2) {
5565                         dev_warn(dev,
5566                                  "Underspecified device tree, falling back to legacy register regions\n");
5567
5568                         /* In the old version, pcs_misc is at index 3. */
5569                         qphy->pcs_misc = qphy->tx2;
5570                         qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
5571                         qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
5572
5573                 } else {
5574                         qphy->pcs_misc = of_iomap(np, 5);
5575                 }
5576
5577         } else {
5578                 qphy->pcs_misc = of_iomap(np, 3);
5579         }
5580
5581         if (!qphy->pcs_misc)
5582                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
5583
5584         /*
5585          * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
5586          * based phys, so they essentially have pipe clock. So,
5587          * we return error in case phy is USB3 or PIPE type.
5588          * Otherwise, we initialize pipe clock to NULL for
5589          * all phys that don't need this.
5590          */
5591         snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
5592         qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
5593         if (IS_ERR(qphy->pipe_clk)) {
5594                 if (cfg->type == PHY_TYPE_PCIE ||
5595                     cfg->type == PHY_TYPE_USB3) {
5596                         ret = PTR_ERR(qphy->pipe_clk);
5597                         if (ret != -EPROBE_DEFER)
5598                                 dev_err(dev,
5599                                         "failed to get lane%d pipe_clk, %d\n",
5600                                         id, ret);
5601                         return ret;
5602                 }
5603                 qphy->pipe_clk = NULL;
5604         }
5605
5606         /* Get lane reset, if any */
5607         if (cfg->has_lane_rst) {
5608                 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
5609                 qphy->lane_rst = of_reset_control_get(np, prop_name);
5610                 if (IS_ERR(qphy->lane_rst)) {
5611                         dev_err(dev, "failed to get lane%d reset\n", id);
5612                         return PTR_ERR(qphy->lane_rst);
5613                 }
5614         }
5615
5616         if (cfg->type == PHY_TYPE_UFS || cfg->type == PHY_TYPE_PCIE)
5617                 ops = &qcom_qmp_pcie_ufs_ops;
5618         else if (cfg->type == PHY_TYPE_DP)
5619                 ops = &qcom_qmp_phy_dp_ops;
5620         else
5621                 ops = &qcom_qmp_phy_gen_ops;
5622
5623         generic_phy = devm_phy_create(dev, np, ops);
5624         if (IS_ERR(generic_phy)) {
5625                 ret = PTR_ERR(generic_phy);
5626                 dev_err(dev, "failed to create qphy %d\n", ret);
5627                 return ret;
5628         }
5629
5630         qphy->phy = generic_phy;
5631         qphy->index = id;
5632         qphy->qmp = qmp;
5633         qmp->phys[id] = qphy;
5634         phy_set_drvdata(generic_phy, qphy);
5635
5636         return 0;
5637 }
5638
5639 static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
5640         {
5641                 .compatible = "qcom,ipq8074-qmp-usb3-phy",
5642                 .data = &ipq8074_usb3phy_cfg,
5643         }, {
5644                 .compatible = "qcom,msm8996-qmp-pcie-phy",
5645                 .data = &msm8996_pciephy_cfg,
5646         }, {
5647                 .compatible = "qcom,msm8996-qmp-ufs-phy",
5648                 .data = &msm8996_ufs_cfg,
5649         }, {
5650                 .compatible = "qcom,msm8996-qmp-usb3-phy",
5651                 .data = &msm8996_usb3phy_cfg,
5652         }, {
5653                 .compatible = "qcom,msm8998-qmp-pcie-phy",
5654                 .data = &msm8998_pciephy_cfg,
5655         }, {
5656                 .compatible = "qcom,msm8998-qmp-ufs-phy",
5657                 .data = &sdm845_ufsphy_cfg,
5658         }, {
5659                 .compatible = "qcom,ipq8074-qmp-pcie-phy",
5660                 .data = &ipq8074_pciephy_cfg,
5661         }, {
5662                 .compatible = "qcom,ipq6018-qmp-pcie-phy",
5663                 .data = &ipq6018_pciephy_cfg,
5664         }, {
5665                 .compatible = "qcom,ipq6018-qmp-usb3-phy",
5666                 .data = &ipq8074_usb3phy_cfg,
5667         }, {
5668                 .compatible = "qcom,sc7180-qmp-usb3-phy",
5669                 .data = &sc7180_usb3phy_cfg,
5670         }, {
5671                 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
5672                 /* It's a combo phy */
5673         }, {
5674                 .compatible = "qcom,sc8180x-qmp-pcie-phy",
5675                 .data = &sc8180x_pciephy_cfg,
5676         }, {
5677                 .compatible = "qcom,sc8180x-qmp-ufs-phy",
5678                 .data = &sm8150_ufsphy_cfg,
5679         }, {
5680                 .compatible = "qcom,sc8180x-qmp-usb3-phy",
5681                 .data = &sm8150_usb3phy_cfg,
5682         }, {
5683                 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
5684                 /* It's a combo phy */
5685         }, {
5686                 .compatible = "qcom,sdm845-qhp-pcie-phy",
5687                 .data = &sdm845_qhp_pciephy_cfg,
5688         }, {
5689                 .compatible = "qcom,sdm845-qmp-pcie-phy",
5690                 .data = &sdm845_qmp_pciephy_cfg,
5691         }, {
5692                 .compatible = "qcom,sdm845-qmp-usb3-phy",
5693                 .data = &qmp_v3_usb3phy_cfg,
5694         }, {
5695                 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
5696                 .data = &qmp_v3_usb3_uniphy_cfg,
5697         }, {
5698                 .compatible = "qcom,sdm845-qmp-ufs-phy",
5699                 .data = &sdm845_ufsphy_cfg,
5700         }, {
5701                 .compatible = "qcom,msm8998-qmp-usb3-phy",
5702                 .data = &msm8998_usb3phy_cfg,
5703         }, {
5704                 .compatible = "qcom,sm6115-qmp-ufs-phy",
5705                 .data = &sm6115_ufsphy_cfg,
5706         }, {
5707                 .compatible = "qcom,sm8150-qmp-ufs-phy",
5708                 .data = &sm8150_ufsphy_cfg,
5709         }, {
5710                 .compatible = "qcom,sm8250-qmp-ufs-phy",
5711                 .data = &sm8150_ufsphy_cfg,
5712         }, {
5713                 .compatible = "qcom,sm8150-qmp-usb3-phy",
5714                 .data = &sm8150_usb3phy_cfg,
5715         }, {
5716                 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
5717                 .data = &sm8150_usb3_uniphy_cfg,
5718         }, {
5719                 .compatible = "qcom,sm8250-qmp-usb3-phy",
5720                 .data = &sm8250_usb3phy_cfg,
5721         }, {
5722                 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
5723                 /* It's a combo phy */
5724         }, {
5725                 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
5726                 .data = &sm8250_usb3_uniphy_cfg,
5727         }, {
5728                 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
5729                 .data = &sm8250_qmp_gen3x1_pciephy_cfg,
5730         }, {
5731                 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
5732                 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
5733         }, {
5734                 .compatible = "qcom,sm8350-qmp-ufs-phy",
5735                 .data = &sm8350_ufsphy_cfg,
5736         }, {
5737                 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
5738                 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
5739         }, {
5740                 .compatible = "qcom,sdx55-qmp-pcie-phy",
5741                 .data = &sdx55_qmp_pciephy_cfg,
5742         }, {
5743                 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
5744                 .data = &sdx55_usb3_uniphy_cfg,
5745         }, {
5746                 .compatible = "qcom,sm8350-qmp-usb3-phy",
5747                 .data = &sm8350_usb3phy_cfg,
5748         }, {
5749                 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
5750                 .data = &sm8350_usb3_uniphy_cfg,
5751         }, {
5752                 .compatible = "qcom,qcm2290-qmp-usb3-phy",
5753                 .data = &qcm2290_usb3phy_cfg,
5754         },
5755         { },
5756 };
5757 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
5758
5759 static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = {
5760         {
5761                 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
5762                 .data = &sc7180_usb3dpphy_cfg,
5763         },
5764         {
5765                 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
5766                 .data = &sm8250_usb3dpphy_cfg,
5767         },
5768         {
5769                 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
5770                 .data = &sc8180x_usb3dpphy_cfg,
5771         },
5772         { }
5773 };
5774
5775 static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
5776         SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
5777                            qcom_qmp_phy_runtime_resume, NULL)
5778 };
5779
5780 static int qcom_qmp_phy_probe(struct platform_device *pdev)
5781 {
5782         struct qcom_qmp *qmp;
5783         struct device *dev = &pdev->dev;
5784         struct device_node *child;
5785         struct phy_provider *phy_provider;
5786         void __iomem *serdes;
5787         void __iomem *usb_serdes;
5788         void __iomem *dp_serdes = NULL;
5789         const struct qmp_phy_combo_cfg *combo_cfg = NULL;
5790         const struct qmp_phy_cfg *cfg = NULL;
5791         const struct qmp_phy_cfg *usb_cfg = NULL;
5792         const struct qmp_phy_cfg *dp_cfg = NULL;
5793         int num, id, expected_phys;
5794         int ret;
5795
5796         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
5797         if (!qmp)
5798                 return -ENOMEM;
5799
5800         qmp->dev = dev;
5801         dev_set_drvdata(dev, qmp);
5802
5803         /* Get the specific init parameters of QMP phy */
5804         cfg = of_device_get_match_data(dev);
5805         if (!cfg) {
5806                 const struct of_device_id *match;
5807
5808                 match = of_match_device(qcom_qmp_combo_phy_of_match_table, dev);
5809                 if (!match)
5810                         return -EINVAL;
5811
5812                 combo_cfg = match->data;
5813                 if (!combo_cfg)
5814                         return -EINVAL;
5815
5816                 usb_cfg = combo_cfg->usb_cfg;
5817                 cfg = usb_cfg; /* Setup clks and regulators */
5818         }
5819
5820         /* per PHY serdes; usually located at base address */
5821         usb_serdes = serdes = devm_platform_ioremap_resource(pdev, 0);
5822         if (IS_ERR(serdes))
5823                 return PTR_ERR(serdes);
5824
5825         /* per PHY dp_com; if PHY has dp_com control block */
5826         if (combo_cfg || cfg->has_phy_dp_com_ctrl) {
5827                 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
5828                 if (IS_ERR(qmp->dp_com))
5829                         return PTR_ERR(qmp->dp_com);
5830         }
5831
5832         if (combo_cfg) {
5833                 /* Only two serdes for combo PHY */
5834                 dp_serdes = devm_platform_ioremap_resource(pdev, 2);
5835                 if (IS_ERR(dp_serdes))
5836                         return PTR_ERR(dp_serdes);
5837
5838                 dp_cfg = combo_cfg->dp_cfg;
5839                 expected_phys = 2;
5840         } else {
5841                 expected_phys = cfg->nlanes;
5842         }
5843
5844         mutex_init(&qmp->phy_mutex);
5845
5846         ret = qcom_qmp_phy_clk_init(dev, cfg);
5847         if (ret)
5848                 return ret;
5849
5850         ret = qcom_qmp_phy_reset_init(dev, cfg);
5851         if (ret)
5852                 return ret;
5853
5854         ret = qcom_qmp_phy_vreg_init(dev, cfg);
5855         if (ret) {
5856                 if (ret != -EPROBE_DEFER)
5857                         dev_err(dev, "failed to get regulator supplies: %d\n",
5858                                 ret);
5859                 return ret;
5860         }
5861
5862         num = of_get_available_child_count(dev->of_node);
5863         /* do we have a rogue child node ? */
5864         if (num > expected_phys)
5865                 return -EINVAL;
5866
5867         qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
5868         if (!qmp->phys)
5869                 return -ENOMEM;
5870
5871         pm_runtime_set_active(dev);
5872         pm_runtime_enable(dev);
5873         /*
5874          * Prevent runtime pm from being ON by default. Users can enable
5875          * it using power/control in sysfs.
5876          */
5877         pm_runtime_forbid(dev);
5878
5879         id = 0;
5880         for_each_available_child_of_node(dev->of_node, child) {
5881                 if (of_node_name_eq(child, "dp-phy")) {
5882                         cfg = dp_cfg;
5883                         serdes = dp_serdes;
5884                 } else if (of_node_name_eq(child, "usb3-phy")) {
5885                         cfg = usb_cfg;
5886                         serdes = usb_serdes;
5887                 }
5888
5889                 /* Create per-lane phy */
5890                 ret = qcom_qmp_phy_create(dev, child, id, serdes, cfg);
5891                 if (ret) {
5892                         dev_err(dev, "failed to create lane%d phy, %d\n",
5893                                 id, ret);
5894                         goto err_node_put;
5895                 }
5896
5897                 /*
5898                  * Register the pipe clock provided by phy.
5899                  * See function description to see details of this pipe clock.
5900                  */
5901                 if (cfg->type == PHY_TYPE_USB3 || cfg->type == PHY_TYPE_PCIE) {
5902                         ret = phy_pipe_clk_register(qmp, child);
5903                         if (ret) {
5904                                 dev_err(qmp->dev,
5905                                         "failed to register pipe clock source\n");
5906                                 goto err_node_put;
5907                         }
5908                 } else if (cfg->type == PHY_TYPE_DP) {
5909                         ret = phy_dp_clks_register(qmp, qmp->phys[id], child);
5910                         if (ret) {
5911                                 dev_err(qmp->dev,
5912                                         "failed to register DP clock source\n");
5913                                 goto err_node_put;
5914                         }
5915                 }
5916                 id++;
5917         }
5918
5919         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
5920         if (!IS_ERR(phy_provider))
5921                 dev_info(dev, "Registered Qcom-QMP phy\n");
5922         else
5923                 pm_runtime_disable(dev);
5924
5925         return PTR_ERR_OR_ZERO(phy_provider);
5926
5927 err_node_put:
5928         pm_runtime_disable(dev);
5929         of_node_put(child);
5930         return ret;
5931 }
5932
5933 static struct platform_driver qcom_qmp_phy_driver = {
5934         .probe          = qcom_qmp_phy_probe,
5935         .driver = {
5936                 .name   = "qcom-qmp-phy",
5937                 .pm     = &qcom_qmp_phy_pm_ops,
5938                 .of_match_table = qcom_qmp_phy_of_match_table,
5939         },
5940 };
5941
5942 module_platform_driver(qcom_qmp_phy_driver);
5943
5944 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
5945 MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
5946 MODULE_LICENSE("GPL v2");