drivers/phy/qualcomm/phy-qcom-qmp.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_address.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/reset.h>
  21 #include <linux/slab.h>
  22
  23 #include <dt-bindings/phy/phy.h>
  24
  25 #include "phy-qcom-qmp.h"
  26
  27 /* QPHY_SW_RESET bit */
  28 #define SW_RESET                                BIT(0)
  29 /* QPHY_POWER_DOWN_CONTROL */
  30 #define SW_PWRDN                                BIT(0)
  31 #define REFCLK_DRV_DSBL                         BIT(1)
  32 /* QPHY_START_CONTROL bits */
  33 #define SERDES_START                            BIT(0)
  34 #define PCS_START                               BIT(1)
  35 #define PLL_READY_GATE_EN                       BIT(3)
  36 /* QPHY_PCS_STATUS bit */
  37 #define PHYSTATUS                               BIT(6)
  38 /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
  39 #define PCS_READY                               BIT(0)
  40
  41 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  42 /* DP PHY soft reset */
  43 #define SW_DPPHY_RESET                          BIT(0)
  44 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  45 #define SW_DPPHY_RESET_MUX                      BIT(1)
  46 /* USB3 PHY soft reset */
  47 #define SW_USB3PHY_RESET                        BIT(2)
  48 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  49 #define SW_USB3PHY_RESET_MUX                    BIT(3)
  50
  51 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  52 #define USB3_MODE                               BIT(0) /* enables USB3 mode */
  53 #define DP_MODE                                 BIT(1) /* enables DP mode */
  54
  55 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
  56 #define ARCVR_DTCT_EN                           BIT(0)
  57 #define ALFPS_DTCT_EN                           BIT(1)
  58 #define ARCVR_DTCT_EVENT_SEL                    BIT(4)
  59
  60 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
  61 #define IRQ_CLEAR                               BIT(0)
  62
  63 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
  64 #define RCVR_DETECT                             BIT(0)
  65
  66 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
  67 #define CLAMP_EN                                BIT(0) /* enables i/o clamp_n */
  68
  69 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  70 #define POWER_DOWN_DELAY_US_MIN                 10
  71 #define POWER_DOWN_DELAY_US_MAX                 11
  72
  73 #define MAX_PROP_NAME                           32
  74
  75 /* Define the assumed distance between lanes for underspecified device trees. */
  76 #define QMP_PHY_LEGACY_LANE_STRIDE              0x400
  77
  78 struct qmp_phy_init_tbl {
  79         unsigned int offset;
  80         unsigned int val;
  81         /*
  82          * register part of layout ?
  83          * if yes, then offset gives index in the reg-layout
  84          */
  85         bool in_layout;
  86         /*
  87          * mask of lanes for which this register is written
  88          * for cases when second lane needs different values
  89          */
  90         u8 lane_mask;
  91 };
  92
  93 #define QMP_PHY_INIT_CFG(o, v)          \
  94         {                               \
  95                 .offset = o,            \
  96                 .val = v,               \
  97                 .lane_mask = 0xff,      \
  98         }
  99
 100 #define QMP_PHY_INIT_CFG_L(o, v)        \
 101         {                               \
 102                 .offset = o,            \
 103                 .val = v,               \
 104                 .in_layout = true,      \
 105                 .lane_mask = 0xff,      \
 106         }
 107
 108 #define QMP_PHY_INIT_CFG_LANE(o, v, l)  \
 109         {                               \
 110                 .offset = o,            \
 111                 .val = v,               \
 112                 .lane_mask = l,         \
 113         }
 114
 115 /* set of registers with offsets different per-PHY */
 116 enum qphy_reg_layout {
 117         /* Common block control registers */
 118         QPHY_COM_SW_RESET,
 119         QPHY_COM_POWER_DOWN_CONTROL,
 120         QPHY_COM_START_CONTROL,
 121         QPHY_COM_PCS_READY_STATUS,
 122         /* PCS registers */
 123         QPHY_PLL_LOCK_CHK_DLY_TIME,
 124         QPHY_FLL_CNTRL1,
 125         QPHY_FLL_CNTRL2,
 126         QPHY_FLL_CNT_VAL_L,
 127         QPHY_FLL_CNT_VAL_H_TOL,
 128         QPHY_FLL_MAN_CODE,
 129         QPHY_SW_RESET,
 130         QPHY_START_CTRL,
 131         QPHY_PCS_READY_STATUS,
 132         QPHY_PCS_STATUS,
 133         QPHY_PCS_AUTONOMOUS_MODE_CTRL,
 134         QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
 135         QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
 136         QPHY_PCS_POWER_DOWN_CONTROL,
 137         /* Keep last to ensure regs_layout arrays are properly initialized */
 138         QPHY_LAYOUT_SIZE
 139 };
 140
 141 static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 142         [QPHY_START_CTRL]               = 0x00,
 143         [QPHY_PCS_READY_STATUS]         = 0x168,
 144 };
 145
 146 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
 147         [QPHY_COM_SW_RESET]             = 0x400,
 148         [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
 149         [QPHY_COM_START_CONTROL]        = 0x408,
 150         [QPHY_COM_PCS_READY_STATUS]     = 0x448,
 151         [QPHY_PLL_LOCK_CHK_DLY_TIME]    = 0xa8,
 152         [QPHY_FLL_CNTRL1]               = 0xc4,
 153         [QPHY_FLL_CNTRL2]               = 0xc8,
 154         [QPHY_FLL_CNT_VAL_L]            = 0xcc,
 155         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xd0,
 156         [QPHY_FLL_MAN_CODE]             = 0xd4,
 157         [QPHY_SW_RESET]                 = 0x00,
 158         [QPHY_START_CTRL]               = 0x08,
 159         [QPHY_PCS_STATUS]               = 0x174,
 160 };
 161
 162 static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 163         [QPHY_FLL_CNTRL1]               = 0xc0,
 164         [QPHY_FLL_CNTRL2]               = 0xc4,
 165         [QPHY_FLL_CNT_VAL_L]            = 0xc8,
 166         [QPHY_FLL_CNT_VAL_H_TOL]        = 0xcc,
 167         [QPHY_FLL_MAN_CODE]             = 0xd0,
 168         [QPHY_SW_RESET]                 = 0x00,
 169         [QPHY_START_CTRL]               = 0x08,
 170         [QPHY_PCS_STATUS]               = 0x17c,
 171         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
 172         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
 173         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
 174 };
 175
 176 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 177         [QPHY_SW_RESET]                 = 0x00,
 178         [QPHY_START_CTRL]               = 0x08,
 179         [QPHY_PCS_STATUS]               = 0x174,
 180         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
 181         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
 182         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
 183 };
 184
 185 static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
 186         [QPHY_SW_RESET]                 = 0x00,
 187         [QPHY_START_CTRL]               = 0x08,
 188         [QPHY_PCS_STATUS]               = 0x174,
 189 };
 190
 191 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
 192         [QPHY_SW_RESET]                 = 0x00,
 193         [QPHY_START_CTRL]               = 0x08,
 194         [QPHY_PCS_STATUS]               = 0x2ac,
 195 };
 196
 197 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 198         [QPHY_SW_RESET]                 = 0x00,
 199         [QPHY_START_CTRL]               = 0x44,
 200         [QPHY_PCS_STATUS]               = 0x14,
 201         [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 202         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x308,
 203         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x314,
 204 };
 205
 206 static const unsigned int qmp_v4_usb3_uniphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 207         [QPHY_SW_RESET]                 = 0x00,
 208         [QPHY_START_CTRL]               = 0x44,
 209         [QPHY_PCS_STATUS]               = 0x14,
 210         [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 211         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x608,
 212         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x614,
 213 };
 214
 215 static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 216         [QPHY_START_CTRL]               = 0x00,
 217         [QPHY_PCS_READY_STATUS]         = 0x160,
 218 };
 219
 220 static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
 221         [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
 222         [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
 223         [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
 224 };
 225
 226 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
 227         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
 228         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 229         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 230         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 231         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 232         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 233         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 234         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 235         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 236         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 237         /* PLL and Loop filter settings */
 238         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 239         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 240         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 241         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 242         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 243         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 244         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 245         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 246         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 247         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 248         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 249         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 250         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 251         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 252         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 253         /* SSC settings */
 254         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 255         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 256         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 257         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 258         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 259         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 260         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 261 };
 262
 263 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
 264         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
 265         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 266         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 267         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
 268         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 269         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 270         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 271         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 272         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
 273 };
 274
 275 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
 276         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 277         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
 278         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 279         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 280         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 281         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 282         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
 283         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 284         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 285         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 286         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 287         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 288         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 289         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 290         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 291         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 292         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 293         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 294         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 295         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 296         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
 297         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
 298         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
 299 };
 300
 301 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
 302         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
 303         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 304         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 305         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 306         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
 307         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 308         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 309         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 310         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
 311         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 312         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 313         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 314         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
 315         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 316         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 317         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 318         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 319         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 320         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
 321         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
 322         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 323         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
 324         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 325         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
 326         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 327         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 328         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 329         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 330         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 331         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 332         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 333         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 334         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
 335         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 336         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 337         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 338         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
 339         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 340         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 341         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 342         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 343         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 344         QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
 345 };
 346
 347 static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
 348         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 349         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 350 };
 351
 352 static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
 353         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 354         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
 355         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
 356         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 357         QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
 358         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 359         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
 360         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 361         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 362         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
 363 };
 364
 365 static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
 366         QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
 367         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
 368         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 369
 370         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
 371
 372         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
 373         QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
 374         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
 375         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
 376         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
 377 };
 378
 379 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
 380         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 381         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 382         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
 383         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 384         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 385         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 386         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 387         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 388         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 389         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 390         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 391         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 392         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 393         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 394         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 395         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 396         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 397         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
 398         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
 399         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
 400         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 401         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 402         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 403         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 404         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
 405         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 406         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
 407         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 408         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 409         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 410         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
 411         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 412         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 413         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 414         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 415         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 416         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 417         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 418         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 419         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 420         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 421         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 422 };
 423
 424 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
 425         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 426         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 427         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 428         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 429 };
 430
 431 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
 432         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 433         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
 434         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 435         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
 436         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 437         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 438         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 439         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 440         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 441         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
 442         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 443         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 444         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 445         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 446 };
 447
 448 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
 449         QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 450         QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 451         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 452         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 453         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 454         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 455         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 456         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 457         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
 458         QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 459 };
 460
 461 static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
 462         QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01),
 463         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
 464         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
 465         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 466         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 467         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 468         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 469         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
 470         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 471         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
 472         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
 473         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
 474         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 475         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 476         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 477         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 478         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
 479         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
 480         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
 481         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 482         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
 483         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
 484         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
 485         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 486         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 487         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 488         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 489         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 490         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
 491         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
 492         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
 493         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
 494         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 495         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
 496         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
 497         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
 498         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
 499         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
 500         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
 501         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
 502         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
 503         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 504         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
 505         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
 506         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
 507         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
 508         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
 509 };
 510
 511 static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = {
 512         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 513         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
 514 };
 515
 516 static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
 517         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
 518         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
 519         QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
 520         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
 521         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
 522         QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
 523         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
 524         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
 525         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
 526         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
 527         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
 528 };
 529
 530 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
 531         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 532         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 533         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 534         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 535         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 536         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 537         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 538         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 539         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
 540         /* PLL and Loop filter settings */
 541         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 542         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 543         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 544         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 545         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 546         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 547         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 548         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 549         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 550         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 551         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 552         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 553         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 554         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 555         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 556         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 557         /* SSC settings */
 558         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 559         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 560         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 561         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 562         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 563         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 564         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 565 };
 566
 567 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
 568         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 569         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 570         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 571 };
 572
 573 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
 574         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 575         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 576         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 577         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 578         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
 579         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 580         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 581         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 582         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
 583         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 584 };
 585
 586 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
 587         /* FLL settings */
 588         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
 589         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
 590         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
 591         QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
 592         QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
 593
 594         /* Lock Det settings */
 595         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
 596         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
 597         QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
 598         QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
 599 };
 600
 601 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
 602         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
 603         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 604         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
 605         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
 606         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
 607         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 608         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 609         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
 610         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
 611         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
 612         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
 613         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
 614         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
 615         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 616         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
 617         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
 618         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 619         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
 620         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 621         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 622         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
 623         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
 624         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
 625         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 626         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
 627         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 628         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
 629         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 630         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 631         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
 632         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 633         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
 634         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
 635         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 636         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
 637         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
 638         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
 639         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 640         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 641         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 642 };
 643
 644 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
 645         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 646         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
 647         QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
 648         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 649         QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
 650         QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
 651 };
 652
 653 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
 654         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 655         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 656         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
 657         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
 658         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 659         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 660         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
 661 };
 662
 663 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
 664         QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x4),
 665         QMP_PHY_INIT_CFG(QPHY_OSC_DTCT_ACTIONS, 0x0),
 666         QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
 667         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
 668         QMP_PHY_INIT_CFG(QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
 669         QMP_PHY_INIT_CFG(QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
 670         QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
 671         QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x73),
 672         QMP_PHY_INIT_CFG(QPHY_RX_SIGDET_LVL, 0x99),
 673         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M6DB_V0, 0x15),
 674         QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0xe),
 675         QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0),
 676         QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
 677 };
 678
 679 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
 680         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 681         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 682         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
 683         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 684         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 685         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 686         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 687         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 688         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 689         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 690         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 691         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 692         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 693         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 694         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 695         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 696         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 697         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 698         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 699         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 700         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 701         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 702         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 703         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 704         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 705         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 706         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 707         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
 708         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 709         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 710         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
 711         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 712         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 713         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 714         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 715         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 716         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 717         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 718         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 719         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 720         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 721         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 722 };
 723
 724 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
 725         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 726         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 727         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 728         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 729 };
 730
 731 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
 732         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 733         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
 734         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 735         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
 736         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 737         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 738         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 739         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 740         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 741         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
 742         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
 743         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
 744         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 745         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 746         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 747         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 748 };
 749
 750 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
 751         QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 752
 753         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 754         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 755         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 756         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 757         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 758
 759         QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 760         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 761         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 762         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 763         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 764         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 765         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 766
 767         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
 768         QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 769         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
 770
 771         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
 772 };
 773
 774 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
 775         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
 776         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
 777         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
 778         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
 779         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
 780 };
 781
 782 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
 783         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
 784         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
 785         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
 786         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
 787         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
 788         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
 789         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
 790         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
 791         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
 792         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
 793         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
 794         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
 795         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
 796         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
 797         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
 798         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
 799         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
 800         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
 801         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
 802         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
 803         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
 804         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
 805         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
 806         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
 807         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
 808         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
 809         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
 810         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
 811         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
 812         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
 813         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 814         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
 815         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
 816         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
 817         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
 818         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
 819         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
 820         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
 821         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
 822         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
 823         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
 824         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
 825         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
 826         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
 827         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
 828 };
 829
 830 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
 831         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
 832         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
 833         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
 834         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
 835         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
 836         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
 837         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
 838         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
 839         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
 840         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
 841         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
 842         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
 843         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
 844         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
 845         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
 846         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
 847         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
 848         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
 849         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
 850         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
 851         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
 852         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
 853         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
 854         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
 855         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
 856         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
 857         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
 858         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
 859         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
 860         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
 861         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
 862         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
 863         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
 864         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
 865         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
 866         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
 867         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
 868         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
 869         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
 870         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
 871         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
 872         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
 873         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
 874         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
 875         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
 876         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
 877         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
 878         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
 879         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
 880         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
 881         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
 882         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
 883         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
 884         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
 885         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
 886         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
 887 };
 888
 889 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
 890 };
 891
 892 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
 893         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
 894         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
 895         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
 896         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
 897         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
 898         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
 899         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
 900 };
 901
 902 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
 903         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 904         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 905         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 906         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 907         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 908         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 909         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
 910         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 911         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 912         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 913         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 914         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 915         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 916         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 917         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 918         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 919         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 920         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 921         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 922         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 923         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 924         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 925         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 926         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 927         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 928         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 929         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 930         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 931         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 932         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 933         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 934         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 935         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 936         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 937         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 938         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 939 };
 940
 941 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
 942         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 943         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 944         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 945         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 946         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 947 };
 948
 949 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
 950         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 951         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 952         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 953         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 954         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 955         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 956         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 957         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 958         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 959 };
 960
 961 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
 962         /* FLL settings */
 963         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 964         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 965         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 966         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 967         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 968
 969         /* Lock Det settings */
 970         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 971         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 972         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 973         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 974
 975         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 976         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 977         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 978         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 979         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 980         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 981         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 982         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 983         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 984         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 985         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 986         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 987         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 988         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 989         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 990         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 991         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 992         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 993         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 994
 995         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 996         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 997         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 998         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 999         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1000         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1001         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1002         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1003         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1004         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1005         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1006 };
1007
1008 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
1009         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1010         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1011         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1012         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1013         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1014         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1015         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1016         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1017         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1018         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1019         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1020         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1021         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1022         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1023         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1024         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1025         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1026         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1027         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1028         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1029         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1030         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1031         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1032         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1033         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1034         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1035         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1036         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1037         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
1038         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1039         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1040         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1041         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1042         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1043         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1044         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1045 };
1046
1047 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
1048         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1049         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1050         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
1051         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
1052         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
1053 };
1054
1055 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
1056         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
1057         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
1058         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1059         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1060         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1061         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1062         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1063         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1064         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1065         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1066         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1067 };
1068
1069 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
1070         /* FLL settings */
1071         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1072         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1073         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1074         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1075         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1076
1077         /* Lock Det settings */
1078         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1079         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1080         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1081         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1082
1083         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
1084         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1085         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1086         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
1087         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
1088         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
1089         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
1090         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1091         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1092         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
1093         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1094         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1095         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1096         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1097         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
1098         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1099         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1100         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1101         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1102
1103         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1104         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1105         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1106         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1107         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1108         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1109         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1110         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1111         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1112         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1113         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1114
1115         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
1116         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
1117 };
1118
1119 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
1120         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
1121         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1122         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1123         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1124         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1125         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
1126         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
1127         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1128         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
1129         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
1130         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
1131         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1132         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
1133         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
1134         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
1135         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
1136         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1137         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1138         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1139         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1140         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1141         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1142         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
1143         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1144         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
1145         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
1146         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
1147         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
1148         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
1149         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
1150         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
1151         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
1152         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
1153         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
1154         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
1155         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
1156
1157         /* Rate B */
1158         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
1159 };
1160
1161 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = {
1162         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
1163         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
1164         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
1165 };
1166
1167 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
1168         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
1169         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
1170         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1171         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
1172         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1173         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
1174         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1175         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1176         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
1177         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
1178         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
1179         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
1180         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1181         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
1182         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1183         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
1184 };
1185
1186 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
1187         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL2, 0x6e),
1188         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1189         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL, 0x02),
1190         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SYM_RESYNC_CTRL, 0x03),
1191         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_MID_TERM_CTRL1, 0x43),
1192         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_CTRL1, 0x0f),
1193         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_MIN_HIBERN8_TIME, 0x9a),
1194         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
1195 };
1196
1197 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
1198         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
1199         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
1200         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
1201         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
1202         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
1203         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
1204         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
1205         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
1206         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
1207         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
1208         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
1209         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
1210         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
1211         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
1212         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
1213         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1214         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1215         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
1216         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
1217         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
1218         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
1219         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
1220         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
1221         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
1222         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
1223         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
1224         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
1225         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
1226         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
1227         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
1228         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
1229         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
1230         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
1231         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
1232         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
1233         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
1234         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
1235         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
1236 };
1237
1238 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
1239         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1240         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1241         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
1242         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1243 };
1244
1245 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
1246         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1247         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1248         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1249         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1250         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
1251         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1252         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
1253         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
1254         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1255         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1256         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1257         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
1258         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1259         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1260         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1261         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
1262         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
1263 };
1264
1265 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
1266         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1267         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1268         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1269         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
1270         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1271         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1272         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1273         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1274         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
1275         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1276         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
1277         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
1278         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
1279         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
1280         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
1281         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
1282         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
1283         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
1284         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
1285         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
1286         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
1287         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
1288         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
1289         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
1290         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
1291         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
1292         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
1293         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
1294         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1295         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1296         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1297         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1298         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1299         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1300         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
1301         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1302         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1303         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1304 };
1305
1306 static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
1307         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
1308         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
1309         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1310         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
1311         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1312         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1313         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
1314         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1315         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1316         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1317         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1318         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1319         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
1320         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
1321         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
1322         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1323         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
1324         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1325         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1326         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1327         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
1328         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
1329         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
1330         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
1331
1332         /* Rate B */
1333         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
1334 };
1335
1336 static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
1337         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
1338         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
1339         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
1340         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
1341         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
1342         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
1343 };
1344
1345 static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
1346         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
1347         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
1348         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1349         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
1350         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
1351         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
1352         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
1353         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
1354         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
1355         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1356         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1357         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
1358         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
1359         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
1360         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
1361         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
1362         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
1363         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1364         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1365         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
1366         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
1367         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
1368         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
1369         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
1370         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
1371         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
1372         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
1373         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1374         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
1375         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
1376         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
1377         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
1378         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1379         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
1380
1381 };
1382
1383 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
1384         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
1385         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
1386         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
1387         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
1388         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
1389         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
1390         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
1391 };
1392
1393 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
1394         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1395         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1396         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1397         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1398         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1399         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1400         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1401         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1402         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1403         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1404         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1405         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1406         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1407         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1408         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1409         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1410         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1411         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1412         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1413         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1414         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1415         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1416         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1417         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1418         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1419         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1420         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1421         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1422         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1423         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1424         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1425         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1426         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1427         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1428         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1429         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1430         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1431         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1432         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1433         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1434 };
1435
1436 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
1437         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
1438         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
1439         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1440         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1441         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1442 };
1443
1444 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
1445         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
1446         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1447         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1448         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1449         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1450         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1451         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1452         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1453         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1454         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1455         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1456         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
1457         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1458         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1459         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1460         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1461         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1462         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1463         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1464         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1465         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1466         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
1467         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
1468         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1469         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
1470         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1471         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1472         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1473         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1474         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1475         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1476         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1477         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1478         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1479         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1480         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1481 };
1482
1483 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
1484         /* Lock Det settings */
1485         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1486         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1487         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1488
1489         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1490         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1491         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1492         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1493         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1494         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1495         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1496         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1497         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1498         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1499 };
1500
1501 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
1502         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
1503         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1504         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1505         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1506         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
1507         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
1508         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
1509         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1510         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1511         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1512         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1513         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1514         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
1515         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
1516         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
1517         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
1518         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
1519         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
1520         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
1521         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
1522         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
1523         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1524         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
1525         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1526         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
1527         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
1528         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1529         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1530         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1531         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1532         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1533         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
1534         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1535         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1536         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1537         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1538         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1539         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1540         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1541         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1542 };
1543
1544 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
1545         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1546         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
1547         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
1548         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
1549 };
1550
1551 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
1552         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
1553         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1554         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
1555         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
1556         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
1557         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
1558         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
1559         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1560         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1561         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1562         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1563         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1564         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1565         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1566         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1567         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1568         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1569         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1570         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1571         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
1572         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1573         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1574         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1575         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1576         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1577         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1578         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1579         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1580         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1581         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1582         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1583         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1584         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1585         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
1586         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
1587         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1588 };
1589
1590 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
1591         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1592         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1593         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1594         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1595         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1596         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1597         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1598         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
1599         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1600         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
1601         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1602         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1603         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1604         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1605         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1606         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1607 };
1608
1609 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
1610         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
1611         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
1612         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1613         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
1614         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1615         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1616         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
1617         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
1618 };
1619
1620 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
1621         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
1622         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1623         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1624         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1625         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1626         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1627         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1628         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1629         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1630         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1631         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1632         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1633         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1634         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1635         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1636         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1637         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1638         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1639         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1640         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1641         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
1642         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
1643         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
1644         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
1645         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
1646         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1647         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
1648         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1649         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1650         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1651         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1652         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
1653         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1654         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1655         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1656         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1657         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1658         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
1659 };
1660
1661 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
1662         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1663         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1664         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1665         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1666         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1667         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
1668         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1669         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1670         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1671         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1672         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1673         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1674         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1675         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1676 };
1677
1678 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
1679         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1680         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1681         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
1682         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
1683         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1684         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
1685 };
1686
1687 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
1688         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
1689         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
1690         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
1691         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
1692         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
1693         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
1694         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1695         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1696         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1697         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1698         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1699         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
1700         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1701         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
1702         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
1703         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1704         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1705         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1706         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1707         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
1708         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1709         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1710         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1711         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1712         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1713         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1714         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1715         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1716         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1717         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1718         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1719         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1720         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1721         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
1722         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1723         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1724 };
1725
1726 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
1727         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1728         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1729         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1730         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1731         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1732         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1733         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
1734         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1735         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2, 0x07),
1736         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1737         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1738         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1739         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1740         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1741         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1742         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1743 };
1744
1745 /* struct qmp_phy_cfg - per-PHY initialization config */
1746 struct qmp_phy_cfg {
1747         /* phy-type - PCIE/UFS/USB */
1748         unsigned int type;
1749         /* number of lanes provided by phy */
1750         int nlanes;
1751
1752         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1753         const struct qmp_phy_init_tbl *serdes_tbl;
1754         int serdes_tbl_num;
1755         const struct qmp_phy_init_tbl *tx_tbl;
1756         int tx_tbl_num;
1757         const struct qmp_phy_init_tbl *rx_tbl;
1758         int rx_tbl_num;
1759         const struct qmp_phy_init_tbl *pcs_tbl;
1760         int pcs_tbl_num;
1761         const struct qmp_phy_init_tbl *pcs_misc_tbl;
1762         int pcs_misc_tbl_num;
1763
1764         /* clock ids to be requested */
1765         const char * const *clk_list;
1766         int num_clks;
1767         /* resets to be requested */
1768         const char * const *reset_list;
1769         int num_resets;
1770         /* regulators to be requested */
1771         const char * const *vreg_list;
1772         int num_vregs;
1773
1774         /* array of registers with different offsets */
1775         const unsigned int *regs;
1776
1777         unsigned int start_ctrl;
1778         unsigned int pwrdn_ctrl;
1779         unsigned int mask_com_pcs_ready;
1780
1781         /* true, if PHY has a separate PHY_COM control block */
1782         bool has_phy_com_ctrl;
1783         /* true, if PHY has a reset for individual lanes */
1784         bool has_lane_rst;
1785         /* true, if PHY needs delay after POWER_DOWN */
1786         bool has_pwrdn_delay;
1787         /* power_down delay in usec */
1788         int pwrdn_delay_min;
1789         int pwrdn_delay_max;
1790
1791         /* true, if PHY has a separate DP_COM control block */
1792         bool has_phy_dp_com_ctrl;
1793         /* true, if PHY has secondary tx/rx lanes to be configured */
1794         bool is_dual_lane_phy;
1795
1796         /* true, if PCS block has no separate SW_RESET register */
1797         bool no_pcs_sw_reset;
1798 };
1799
1800 /**
1801  * struct qmp_phy - per-lane phy descriptor
1802  *
1803  * @phy: generic phy
1804  * @tx: iomapped memory space for lane's tx
1805  * @rx: iomapped memory space for lane's rx
1806  * @pcs: iomapped memory space for lane's pcs
1807  * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
1808  * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
1809  * @pcs_misc: iomapped memory space for lane's pcs_misc
1810  * @pipe_clk: pipe lock
1811  * @index: lane index
1812  * @qmp: QMP phy to which this lane belongs
1813  * @lane_rst: lane's reset controller
1814  */
1815 struct qmp_phy {
1816         struct phy *phy;
1817         void __iomem *tx;
1818         void __iomem *rx;
1819         void __iomem *pcs;
1820         void __iomem *tx2;
1821         void __iomem *rx2;
1822         void __iomem *pcs_misc;
1823         struct clk *pipe_clk;
1824         unsigned int index;
1825         struct qcom_qmp *qmp;
1826         struct reset_control *lane_rst;
1827 };
1828
1829 /**
1830  * struct qcom_qmp - structure holding QMP phy block attributes
1831  *
1832  * @dev: device
1833  * @serdes: iomapped memory space for phy's serdes
1834  * @dp_com: iomapped memory space for phy's dp_com control block
1835  *
1836  * @clks: array of clocks required by phy
1837  * @resets: array of resets required by phy
1838  * @vregs: regulator supplies bulk data
1839  *
1840  * @cfg: phy specific configuration
1841  * @phys: array of per-lane phy descriptors
1842  * @phy_mutex: mutex lock for PHY common block initialization
1843  * @init_count: phy common block initialization count
1844  * @phy_initialized: indicate if PHY has been initialized
1845  * @mode: current PHY mode
1846  * @ufs_reset: optional UFS PHY reset handle
1847  */
1848 struct qcom_qmp {
1849         struct device *dev;
1850         void __iomem *serdes;
1851         void __iomem *dp_com;
1852
1853         struct clk_bulk_data *clks;
1854         struct reset_control **resets;
1855         struct regulator_bulk_data *vregs;
1856
1857         const struct qmp_phy_cfg *cfg;
1858         struct qmp_phy **phys;
1859
1860         struct mutex phy_mutex;
1861         int init_count;
1862         bool phy_initialized;
1863         enum phy_mode mode;
1864
1865         struct reset_control *ufs_reset;
1866 };
1867
1868 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1869 {
1870         u32 reg;
1871
1872         reg = readl(base + offset);
1873         reg |= val;
1874         writel(reg, base + offset);
1875
1876         /* ensure that above write is through */
1877         readl(base + offset);
1878 }
1879
1880 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1881 {
1882         u32 reg;
1883
1884         reg = readl(base + offset);
1885         reg &= ~val;
1886         writel(reg, base + offset);
1887
1888         /* ensure that above write is through */
1889         readl(base + offset);
1890 }
1891
1892 /* list of clocks required by phy */
1893 static const char * const msm8996_phy_clk_l[] = {
1894         "aux", "cfg_ahb", "ref",
1895 };
1896
1897 static const char * const msm8996_ufs_phy_clk_l[] = {
1898         "ref",
1899 };
1900
1901 static const char * const qmp_v3_phy_clk_l[] = {
1902         "aux", "cfg_ahb", "ref", "com_aux",
1903 };
1904
1905 static const char * const sdm845_pciephy_clk_l[] = {
1906         "aux", "cfg_ahb", "ref", "refgen",
1907 };
1908
1909 static const char * const qmp_v4_phy_clk_l[] = {
1910         "aux", "ref_clk_src", "ref", "com_aux",
1911 };
1912
1913 /* the primary usb3 phy on sm8250 doesn't have a ref clock */
1914 static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
1915         "aux", "ref_clk_src", "com_aux"
1916 };
1917
1918 static const char * const sdm845_ufs_phy_clk_l[] = {
1919         "ref", "ref_aux",
1920 };
1921
1922 /* list of resets */
1923 static const char * const msm8996_pciephy_reset_l[] = {
1924         "phy", "common", "cfg",
1925 };
1926
1927 static const char * const msm8996_usb3phy_reset_l[] = {
1928         "phy", "common",
1929 };
1930
1931 static const char * const sc7180_usb3phy_reset_l[] = {
1932         "phy",
1933 };
1934
1935 static const char * const sdm845_pciephy_reset_l[] = {
1936         "phy",
1937 };
1938
1939 /* list of regulators */
1940 static const char * const qmp_phy_vreg_l[] = {
1941         "vdda-phy", "vdda-pll",
1942 };
1943
1944 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
1945         .type                   = PHY_TYPE_USB3,
1946         .nlanes                 = 1,
1947
1948         .serdes_tbl             = ipq8074_usb3_serdes_tbl,
1949         .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
1950         .tx_tbl                 = msm8996_usb3_tx_tbl,
1951         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1952         .rx_tbl                 = ipq8074_usb3_rx_tbl,
1953         .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
1954         .pcs_tbl                = ipq8074_usb3_pcs_tbl,
1955         .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
1956         .clk_list               = msm8996_phy_clk_l,
1957         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1958         .reset_list             = msm8996_usb3phy_reset_l,
1959         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1960         .vreg_list              = qmp_phy_vreg_l,
1961         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1962         .regs                   = usb3phy_regs_layout,
1963
1964         .start_ctrl             = SERDES_START | PCS_START,
1965         .pwrdn_ctrl             = SW_PWRDN,
1966 };
1967
1968 static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
1969         .type                   = PHY_TYPE_PCIE,
1970         .nlanes                 = 3,
1971
1972         .serdes_tbl             = msm8996_pcie_serdes_tbl,
1973         .serdes_tbl_num         = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
1974         .tx_tbl                 = msm8996_pcie_tx_tbl,
1975         .tx_tbl_num             = ARRAY_SIZE(msm8996_pcie_tx_tbl),
1976         .rx_tbl                 = msm8996_pcie_rx_tbl,
1977         .rx_tbl_num             = ARRAY_SIZE(msm8996_pcie_rx_tbl),
1978         .pcs_tbl                = msm8996_pcie_pcs_tbl,
1979         .pcs_tbl_num            = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
1980         .clk_list               = msm8996_phy_clk_l,
1981         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1982         .reset_list             = msm8996_pciephy_reset_l,
1983         .num_resets             = ARRAY_SIZE(msm8996_pciephy_reset_l),
1984         .vreg_list              = qmp_phy_vreg_l,
1985         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1986         .regs                   = pciephy_regs_layout,
1987
1988         .start_ctrl             = PCS_START | PLL_READY_GATE_EN,
1989         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
1990         .mask_com_pcs_ready     = PCS_READY,
1991
1992         .has_phy_com_ctrl       = true,
1993         .has_lane_rst           = true,
1994         .has_pwrdn_delay        = true,
1995         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1996         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1997 };
1998
1999 static const struct qmp_phy_cfg msm8996_ufs_cfg = {
2000         .type                   = PHY_TYPE_UFS,
2001         .nlanes                 = 1,
2002
2003         .serdes_tbl             = msm8996_ufs_serdes_tbl,
2004         .serdes_tbl_num         = ARRAY_SIZE(msm8996_ufs_serdes_tbl),
2005         .tx_tbl                 = msm8996_ufs_tx_tbl,
2006         .tx_tbl_num             = ARRAY_SIZE(msm8996_ufs_tx_tbl),
2007         .rx_tbl                 = msm8996_ufs_rx_tbl,
2008         .rx_tbl_num             = ARRAY_SIZE(msm8996_ufs_rx_tbl),
2009
2010         .clk_list               = msm8996_ufs_phy_clk_l,
2011         .num_clks               = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
2012
2013         .vreg_list              = qmp_phy_vreg_l,
2014         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2015
2016         .regs                   = msm8996_ufsphy_regs_layout,
2017
2018         .start_ctrl             = SERDES_START,
2019         .pwrdn_ctrl             = SW_PWRDN,
2020
2021         .no_pcs_sw_reset        = true,
2022 };
2023
2024 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
2025         .type                   = PHY_TYPE_USB3,
2026         .nlanes                 = 1,
2027
2028         .serdes_tbl             = msm8996_usb3_serdes_tbl,
2029         .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
2030         .tx_tbl                 = msm8996_usb3_tx_tbl,
2031         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
2032         .rx_tbl                 = msm8996_usb3_rx_tbl,
2033         .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
2034         .pcs_tbl                = msm8996_usb3_pcs_tbl,
2035         .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
2036         .clk_list               = msm8996_phy_clk_l,
2037         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
2038         .reset_list             = msm8996_usb3phy_reset_l,
2039         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2040         .vreg_list              = qmp_phy_vreg_l,
2041         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2042         .regs                   = usb3phy_regs_layout,
2043
2044         .start_ctrl             = SERDES_START | PCS_START,
2045         .pwrdn_ctrl             = SW_PWRDN,
2046 };
2047
2048 static const char * const ipq8074_pciephy_clk_l[] = {
2049         "aux", "cfg_ahb",
2050 };
2051 /* list of resets */
2052 static const char * const ipq8074_pciephy_reset_l[] = {
2053         "phy", "common",
2054 };
2055
2056 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
2057         .type                   = PHY_TYPE_PCIE,
2058         .nlanes                 = 1,
2059
2060         .serdes_tbl             = ipq8074_pcie_serdes_tbl,
2061         .serdes_tbl_num         = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
2062         .tx_tbl                 = ipq8074_pcie_tx_tbl,
2063         .tx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
2064         .rx_tbl                 = ipq8074_pcie_rx_tbl,
2065         .rx_tbl_num             = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
2066         .pcs_tbl                = ipq8074_pcie_pcs_tbl,
2067         .pcs_tbl_num            = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
2068         .clk_list               = ipq8074_pciephy_clk_l,
2069         .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
2070         .reset_list             = ipq8074_pciephy_reset_l,
2071         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2072         .vreg_list              = NULL,
2073         .num_vregs              = 0,
2074         .regs                   = pciephy_regs_layout,
2075
2076         .start_ctrl             = SERDES_START | PCS_START,
2077         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2078
2079         .has_phy_com_ctrl       = false,
2080         .has_lane_rst           = false,
2081         .has_pwrdn_delay        = true,
2082         .pwrdn_delay_min        = 995,          /* us */
2083         .pwrdn_delay_max        = 1005,         /* us */
2084 };
2085
2086 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
2087         .type = PHY_TYPE_PCIE,
2088         .nlanes = 1,
2089
2090         .serdes_tbl             = sdm845_qmp_pcie_serdes_tbl,
2091         .serdes_tbl_num         = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
2092         .tx_tbl                 = sdm845_qmp_pcie_tx_tbl,
2093         .tx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
2094         .rx_tbl                 = sdm845_qmp_pcie_rx_tbl,
2095         .rx_tbl_num             = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
2096         .pcs_tbl                = sdm845_qmp_pcie_pcs_tbl,
2097         .pcs_tbl_num            = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
2098         .pcs_misc_tbl           = sdm845_qmp_pcie_pcs_misc_tbl,
2099         .pcs_misc_tbl_num       = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
2100         .clk_list               = sdm845_pciephy_clk_l,
2101         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
2102         .reset_list             = sdm845_pciephy_reset_l,
2103         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2104         .vreg_list              = qmp_phy_vreg_l,
2105         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2106         .regs                   = sdm845_qmp_pciephy_regs_layout,
2107
2108         .start_ctrl             = PCS_START | SERDES_START,
2109         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2110
2111         .has_pwrdn_delay        = true,
2112         .pwrdn_delay_min        = 995,          /* us */
2113         .pwrdn_delay_max        = 1005,         /* us */
2114 };
2115
2116 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
2117         .type = PHY_TYPE_PCIE,
2118         .nlanes = 1,
2119
2120         .serdes_tbl             = sdm845_qhp_pcie_serdes_tbl,
2121         .serdes_tbl_num         = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
2122         .tx_tbl                 = sdm845_qhp_pcie_tx_tbl,
2123         .tx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
2124         .rx_tbl                 = sdm845_qhp_pcie_rx_tbl,
2125         .rx_tbl_num             = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
2126         .pcs_tbl                = sdm845_qhp_pcie_pcs_tbl,
2127         .pcs_tbl_num            = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
2128         .clk_list               = sdm845_pciephy_clk_l,
2129         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
2130         .reset_list             = sdm845_pciephy_reset_l,
2131         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2132         .vreg_list              = qmp_phy_vreg_l,
2133         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2134         .regs                   = sdm845_qhp_pciephy_regs_layout,
2135
2136         .start_ctrl             = PCS_START | SERDES_START,
2137         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2138
2139         .has_pwrdn_delay        = true,
2140         .pwrdn_delay_min        = 995,          /* us */
2141         .pwrdn_delay_max        = 1005,         /* us */
2142 };
2143
2144 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
2145         .type                   = PHY_TYPE_USB3,
2146         .nlanes                 = 1,
2147
2148         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
2149         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
2150         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
2151         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
2152         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
2153         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
2154         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
2155         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
2156         .clk_list               = qmp_v3_phy_clk_l,
2157         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
2158         .reset_list             = msm8996_usb3phy_reset_l,
2159         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2160         .vreg_list              = qmp_phy_vreg_l,
2161         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2162         .regs                   = qmp_v3_usb3phy_regs_layout,
2163
2164         .start_ctrl             = SERDES_START | PCS_START,
2165         .pwrdn_ctrl             = SW_PWRDN,
2166
2167         .has_pwrdn_delay        = true,
2168         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
2169         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
2170
2171         .has_phy_dp_com_ctrl    = true,
2172         .is_dual_lane_phy       = true,
2173 };
2174
2175 static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
2176         .type                   = PHY_TYPE_USB3,
2177         .nlanes                 = 1,
2178
2179         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
2180         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
2181         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
2182         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
2183         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
2184         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
2185         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
2186         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
2187         .clk_list               = qmp_v3_phy_clk_l,
2188         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
2189         .reset_list             = sc7180_usb3phy_reset_l,
2190         .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
2191         .vreg_list              = qmp_phy_vreg_l,
2192         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2193         .regs                   = qmp_v3_usb3phy_regs_layout,
2194
2195         .start_ctrl             = SERDES_START | PCS_START,
2196         .pwrdn_ctrl             = SW_PWRDN,
2197
2198         .has_pwrdn_delay        = true,
2199         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
2200         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
2201
2202         .has_phy_dp_com_ctrl    = true,
2203         .is_dual_lane_phy       = true,
2204 };
2205
2206 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
2207         .type                   = PHY_TYPE_USB3,
2208         .nlanes                 = 1,
2209
2210         .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
2211         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
2212         .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
2213         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
2214         .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
2215         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
2216         .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
2217         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
2218         .clk_list               = qmp_v3_phy_clk_l,
2219         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
2220         .reset_list             = msm8996_usb3phy_reset_l,
2221         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2222         .vreg_list              = qmp_phy_vreg_l,
2223         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2224         .regs                   = qmp_v3_usb3phy_regs_layout,
2225
2226         .start_ctrl             = SERDES_START | PCS_START,
2227         .pwrdn_ctrl             = SW_PWRDN,
2228
2229         .has_pwrdn_delay        = true,
2230         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
2231         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
2232 };
2233
2234 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
2235         .type                   = PHY_TYPE_UFS,
2236         .nlanes                 = 2,
2237
2238         .serdes_tbl             = sdm845_ufsphy_serdes_tbl,
2239         .serdes_tbl_num         = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl),
2240         .tx_tbl                 = sdm845_ufsphy_tx_tbl,
2241         .tx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_tx_tbl),
2242         .rx_tbl                 = sdm845_ufsphy_rx_tbl,
2243         .rx_tbl_num             = ARRAY_SIZE(sdm845_ufsphy_rx_tbl),
2244         .pcs_tbl                = sdm845_ufsphy_pcs_tbl,
2245         .pcs_tbl_num            = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl),
2246         .clk_list               = sdm845_ufs_phy_clk_l,
2247         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
2248         .vreg_list              = qmp_phy_vreg_l,
2249         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2250         .regs                   = sdm845_ufsphy_regs_layout,
2251
2252         .start_ctrl             = SERDES_START,
2253         .pwrdn_ctrl             = SW_PWRDN,
2254
2255         .is_dual_lane_phy       = true,
2256         .no_pcs_sw_reset        = true,
2257 };
2258
2259 static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
2260         .type                   = PHY_TYPE_PCIE,
2261         .nlanes                 = 1,
2262
2263         .serdes_tbl             = msm8998_pcie_serdes_tbl,
2264         .serdes_tbl_num         = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
2265         .tx_tbl                 = msm8998_pcie_tx_tbl,
2266         .tx_tbl_num             = ARRAY_SIZE(msm8998_pcie_tx_tbl),
2267         .rx_tbl                 = msm8998_pcie_rx_tbl,
2268         .rx_tbl_num             = ARRAY_SIZE(msm8998_pcie_rx_tbl),
2269         .pcs_tbl                = msm8998_pcie_pcs_tbl,
2270         .pcs_tbl_num            = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
2271         .clk_list               = msm8996_phy_clk_l,
2272         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
2273         .reset_list             = ipq8074_pciephy_reset_l,
2274         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2275         .vreg_list              = qmp_phy_vreg_l,
2276         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2277         .regs                   = pciephy_regs_layout,
2278
2279         .start_ctrl             = SERDES_START | PCS_START,
2280         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2281 };
2282
2283 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
2284         .type                   = PHY_TYPE_USB3,
2285         .nlanes                 = 1,
2286
2287         .serdes_tbl             = msm8998_usb3_serdes_tbl,
2288         .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
2289         .tx_tbl                 = msm8998_usb3_tx_tbl,
2290         .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
2291         .rx_tbl                 = msm8998_usb3_rx_tbl,
2292         .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
2293         .pcs_tbl                = msm8998_usb3_pcs_tbl,
2294         .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
2295         .clk_list               = msm8996_phy_clk_l,
2296         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
2297         .reset_list             = msm8996_usb3phy_reset_l,
2298         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2299         .vreg_list              = qmp_phy_vreg_l,
2300         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2301         .regs                   = qmp_v3_usb3phy_regs_layout,
2302
2303         .start_ctrl             = SERDES_START | PCS_START,
2304         .pwrdn_ctrl             = SW_PWRDN,
2305
2306         .is_dual_lane_phy       = true,
2307 };
2308
2309 static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
2310         .type                   = PHY_TYPE_UFS,
2311         .nlanes                 = 2,
2312
2313         .serdes_tbl             = sm8150_ufsphy_serdes_tbl,
2314         .serdes_tbl_num         = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl),
2315         .tx_tbl                 = sm8150_ufsphy_tx_tbl,
2316         .tx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_tx_tbl),
2317         .rx_tbl                 = sm8150_ufsphy_rx_tbl,
2318         .rx_tbl_num             = ARRAY_SIZE(sm8150_ufsphy_rx_tbl),
2319         .pcs_tbl                = sm8150_ufsphy_pcs_tbl,
2320         .pcs_tbl_num            = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl),
2321         .clk_list               = sdm845_ufs_phy_clk_l,
2322         .num_clks               = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
2323         .vreg_list              = qmp_phy_vreg_l,
2324         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2325         .regs                   = sm8150_ufsphy_regs_layout,
2326
2327         .start_ctrl             = SERDES_START,
2328         .pwrdn_ctrl             = SW_PWRDN,
2329
2330         .is_dual_lane_phy       = true,
2331 };
2332
2333 static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
2334         .type                   = PHY_TYPE_USB3,
2335         .nlanes                 = 1,
2336
2337         .serdes_tbl             = sm8150_usb3_serdes_tbl,
2338         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
2339         .tx_tbl                 = sm8150_usb3_tx_tbl,
2340         .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
2341         .rx_tbl                 = sm8150_usb3_rx_tbl,
2342         .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
2343         .pcs_tbl                = sm8150_usb3_pcs_tbl,
2344         .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
2345         .clk_list               = qmp_v4_phy_clk_l,
2346         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
2347         .reset_list             = msm8996_usb3phy_reset_l,
2348         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2349         .vreg_list              = qmp_phy_vreg_l,
2350         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2351         .regs                   = qmp_v4_usb3phy_regs_layout,
2352
2353         .start_ctrl             = SERDES_START | PCS_START,
2354         .pwrdn_ctrl             = SW_PWRDN,
2355
2356         .has_pwrdn_delay        = true,
2357         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
2358         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
2359
2360         .has_phy_dp_com_ctrl    = true,
2361         .is_dual_lane_phy       = true,
2362 };
2363
2364 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
2365         .type                   = PHY_TYPE_USB3,
2366         .nlanes                 = 1,
2367
2368         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
2369         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
2370         .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
2371         .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
2372         .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
2373         .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
2374         .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
2375         .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
2376         .clk_list               = qmp_v4_phy_clk_l,
2377         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
2378         .reset_list             = msm8996_usb3phy_reset_l,
2379         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2380         .vreg_list              = qmp_phy_vreg_l,
2381         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2382         .regs                   = qmp_v4_usb3_uniphy_regs_layout,
2383
2384         .start_ctrl             = SERDES_START | PCS_START,
2385         .pwrdn_ctrl             = SW_PWRDN,
2386
2387         .has_pwrdn_delay        = true,
2388         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
2389         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
2390 };
2391
2392 static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
2393         .type                   = PHY_TYPE_USB3,
2394         .nlanes                 = 1,
2395
2396         .serdes_tbl             = sm8150_usb3_serdes_tbl,
2397         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
2398         .tx_tbl                 = sm8250_usb3_tx_tbl,
2399         .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
2400         .rx_tbl                 = sm8250_usb3_rx_tbl,
2401         .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
2402         .pcs_tbl                = sm8250_usb3_pcs_tbl,
2403         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
2404         .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
2405         .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
2406         .reset_list             = msm8996_usb3phy_reset_l,
2407         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2408         .vreg_list              = qmp_phy_vreg_l,
2409         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2410         .regs                   = qmp_v4_usb3phy_regs_layout,
2411
2412         .start_ctrl             = SERDES_START | PCS_START,
2413         .pwrdn_ctrl             = SW_PWRDN,
2414
2415         .has_pwrdn_delay        = true,
2416         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
2417         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
2418
2419         .has_phy_dp_com_ctrl    = true,
2420         .is_dual_lane_phy       = true,
2421 };
2422
2423 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
2424         .type                   = PHY_TYPE_USB3,
2425         .nlanes                 = 1,
2426
2427         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
2428         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
2429         .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
2430         .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
2431         .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
2432         .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
2433         .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
2434         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
2435         .clk_list               = qmp_v4_phy_clk_l,
2436         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
2437         .reset_list             = msm8996_usb3phy_reset_l,
2438         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2439         .vreg_list              = qmp_phy_vreg_l,
2440         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2441         .regs                   = qmp_v4_usb3_uniphy_regs_layout,
2442
2443         .start_ctrl             = SERDES_START | PCS_START,
2444         .pwrdn_ctrl             = SW_PWRDN,
2445
2446         .has_pwrdn_delay        = true,
2447         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
2448         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
2449 };
2450
2451 static void qcom_qmp_phy_configure_lane(void __iomem *base,
2452                                         const unsigned int *regs,
2453                                         const struct qmp_phy_init_tbl tbl[],
2454                                         int num,
2455                                         u8 lane_mask)
2456 {
2457         int i;
2458         const struct qmp_phy_init_tbl *t = tbl;
2459
2460         if (!t)
2461                 return;
2462
2463         for (i = 0; i < num; i++, t++) {
2464                 if (!(t->lane_mask & lane_mask))
2465                         continue;
2466
2467                 if (t->in_layout)
2468                         writel(t->val, base + regs[t->offset]);
2469                 else
2470                         writel(t->val, base + t->offset);
2471         }
2472 }
2473
2474 static void qcom_qmp_phy_configure(void __iomem *base,
2475                                    const unsigned int *regs,
2476                                    const struct qmp_phy_init_tbl tbl[],
2477                                    int num)
2478 {
2479         qcom_qmp_phy_configure_lane(base, regs, tbl, num, 0xff);
2480 }
2481
2482 static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
2483 {
2484         struct qcom_qmp *qmp = qphy->qmp;
2485         const struct qmp_phy_cfg *cfg = qmp->cfg;
2486         void __iomem *serdes = qmp->serdes;
2487         void __iomem *pcs = qphy->pcs;
2488         void __iomem *dp_com = qmp->dp_com;
2489         int ret, i;
2490
2491         mutex_lock(&qmp->phy_mutex);
2492         if (qmp->init_count++) {
2493                 mutex_unlock(&qmp->phy_mutex);
2494                 return 0;
2495         }
2496
2497         /* turn on regulator supplies */
2498         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
2499         if (ret) {
2500                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
2501                 goto err_reg_enable;
2502         }
2503
2504         for (i = 0; i < cfg->num_resets; i++) {
2505                 ret = reset_control_assert(qmp->resets[i]);
2506                 if (ret) {
2507                         dev_err(qmp->dev, "%s reset assert failed\n",
2508                                 cfg->reset_list[i]);
2509                         goto err_rst_assert;
2510                 }
2511         }
2512
2513         for (i = cfg->num_resets - 1; i >= 0; i--) {
2514                 ret = reset_control_deassert(qmp->resets[i]);
2515                 if (ret) {
2516                         dev_err(qmp->dev, "%s reset deassert failed\n",
2517                                 qmp->cfg->reset_list[i]);
2518                         goto err_rst;
2519                 }
2520         }
2521
2522         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2523         if (ret) {
2524                 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
2525                 goto err_rst;
2526         }
2527
2528         if (cfg->has_phy_dp_com_ctrl) {
2529                 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
2530                              SW_PWRDN);
2531                 /* override hardware control for reset of qmp phy */
2532                 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2533                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2534                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2535
2536                 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
2537                              USB3_MODE | DP_MODE);
2538
2539                 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
2540                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2541                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2542                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2543         }
2544
2545         if (cfg->has_phy_com_ctrl) {
2546                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
2547                              SW_PWRDN);
2548         } else {
2549                 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
2550                         qphy_setbits(pcs,
2551                                         cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2552                                         cfg->pwrdn_ctrl);
2553                 else
2554                         qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
2555                                         cfg->pwrdn_ctrl);
2556         }
2557
2558         /* Serdes configuration */
2559         qcom_qmp_phy_configure(serdes, cfg->regs, cfg->serdes_tbl,
2560                                cfg->serdes_tbl_num);
2561
2562         if (cfg->has_phy_com_ctrl) {
2563                 void __iomem *status;
2564                 unsigned int mask, val;
2565
2566                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
2567                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
2568                              SERDES_START | PCS_START);
2569
2570                 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
2571                 mask = cfg->mask_com_pcs_ready;
2572
2573                 ret = readl_poll_timeout(status, val, (val & mask), 10,
2574                                          PHY_INIT_COMPLETE_TIMEOUT);
2575                 if (ret) {
2576                         dev_err(qmp->dev,
2577                                 "phy common block init timed-out\n");
2578                         goto err_com_init;
2579                 }
2580         }
2581
2582         mutex_unlock(&qmp->phy_mutex);
2583
2584         return 0;
2585
2586 err_com_init:
2587         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2588 err_rst:
2589         while (++i < cfg->num_resets)
2590                 reset_control_assert(qmp->resets[i]);
2591 err_rst_assert:
2592         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2593 err_reg_enable:
2594         mutex_unlock(&qmp->phy_mutex);
2595
2596         return ret;
2597 }
2598
2599 static int qcom_qmp_phy_com_exit(struct qcom_qmp *qmp)
2600 {
2601         const struct qmp_phy_cfg *cfg = qmp->cfg;
2602         void __iomem *serdes = qmp->serdes;
2603         int i = cfg->num_resets;
2604
2605         mutex_lock(&qmp->phy_mutex);
2606         if (--qmp->init_count) {
2607                 mutex_unlock(&qmp->phy_mutex);
2608                 return 0;
2609         }
2610
2611         reset_control_assert(qmp->ufs_reset);
2612         if (cfg->has_phy_com_ctrl) {
2613                 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
2614                              SERDES_START | PCS_START);
2615                 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
2616                              SW_RESET);
2617                 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
2618                              SW_PWRDN);
2619         }
2620
2621         while (--i >= 0)
2622                 reset_control_assert(qmp->resets[i]);
2623
2624         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2625
2626         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2627
2628         mutex_unlock(&qmp->phy_mutex);
2629
2630         return 0;
2631 }
2632
2633 static int qcom_qmp_phy_enable(struct phy *phy)
2634 {
2635         struct qmp_phy *qphy = phy_get_drvdata(phy);
2636         struct qcom_qmp *qmp = qphy->qmp;
2637         const struct qmp_phy_cfg *cfg = qmp->cfg;
2638         void __iomem *tx = qphy->tx;
2639         void __iomem *rx = qphy->rx;
2640         void __iomem *pcs = qphy->pcs;
2641         void __iomem *pcs_misc = qphy->pcs_misc;
2642         void __iomem *dp_com = qmp->dp_com;
2643         void __iomem *status;
2644         unsigned int mask, val, ready;
2645         int ret;
2646
2647         dev_vdbg(qmp->dev, "Initializing QMP phy\n");
2648
2649         if (cfg->no_pcs_sw_reset) {
2650                 /*
2651                  * Get UFS reset, which is delayed until now to avoid a
2652                  * circular dependency where UFS needs its PHY, but the PHY
2653                  * needs this UFS reset.
2654                  */
2655                 if (!qmp->ufs_reset) {
2656                         qmp->ufs_reset =
2657                                 devm_reset_control_get_exclusive(qmp->dev,
2658                                                                  "ufsphy");
2659
2660                         if (IS_ERR(qmp->ufs_reset)) {
2661                                 ret = PTR_ERR(qmp->ufs_reset);
2662                                 dev_err(qmp->dev,
2663                                         "failed to get UFS reset: %d\n",
2664                                         ret);
2665
2666                                 qmp->ufs_reset = NULL;
2667                                 return ret;
2668                         }
2669                 }
2670
2671                 ret = reset_control_assert(qmp->ufs_reset);
2672                 if (ret)
2673                         goto err_lane_rst;
2674         }
2675
2676         ret = qcom_qmp_phy_com_init(qphy);
2677         if (ret)
2678                 return ret;
2679
2680         if (cfg->has_lane_rst) {
2681                 ret = reset_control_deassert(qphy->lane_rst);
2682                 if (ret) {
2683                         dev_err(qmp->dev, "lane%d reset deassert failed\n",
2684                                 qphy->index);
2685                         goto err_lane_rst;
2686                 }
2687         }
2688
2689         ret = clk_prepare_enable(qphy->pipe_clk);
2690         if (ret) {
2691                 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
2692                 goto err_clk_enable;
2693         }
2694
2695         /* Tx, Rx, and PCS configurations */
2696         qcom_qmp_phy_configure_lane(tx, cfg->regs,
2697                                     cfg->tx_tbl, cfg->tx_tbl_num, 1);
2698         /* Configuration for other LANE for USB-DP combo PHY */
2699         if (cfg->is_dual_lane_phy)
2700                 qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
2701                                             cfg->tx_tbl, cfg->tx_tbl_num, 2);
2702
2703         qcom_qmp_phy_configure_lane(rx, cfg->regs,
2704                                     cfg->rx_tbl, cfg->rx_tbl_num, 1);
2705         if (cfg->is_dual_lane_phy)
2706                 qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
2707                                             cfg->rx_tbl, cfg->rx_tbl_num, 2);
2708
2709         qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
2710         ret = reset_control_deassert(qmp->ufs_reset);
2711         if (ret)
2712                 goto err_lane_rst;
2713
2714         qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl,
2715                                cfg->pcs_misc_tbl_num);
2716
2717         /*
2718          * Pull out PHY from POWER DOWN state.
2719          * This is active low enable signal to power-down PHY.
2720          */
2721         if(cfg->type == PHY_TYPE_PCIE)
2722                 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
2723
2724         if (cfg->has_pwrdn_delay)
2725                 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
2726
2727         /* Pull PHY out of reset state */
2728         if (!cfg->no_pcs_sw_reset)
2729                 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2730
2731         if (cfg->has_phy_dp_com_ctrl)
2732                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
2733
2734         /* start SerDes and Phy-Coding-Sublayer */
2735         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
2736
2737         if (cfg->type == PHY_TYPE_UFS) {
2738                 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
2739                 mask = PCS_READY;
2740                 ready = PCS_READY;
2741         } else {
2742                 status = pcs + cfg->regs[QPHY_PCS_STATUS];
2743                 mask = PHYSTATUS;
2744                 ready = 0;
2745         }
2746
2747         ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
2748                                  PHY_INIT_COMPLETE_TIMEOUT);
2749         if (ret) {
2750                 dev_err(qmp->dev, "phy initialization timed-out\n");
2751                 goto err_pcs_ready;
2752         }
2753         qmp->phy_initialized = true;
2754         return 0;
2755
2756 err_pcs_ready:
2757         reset_control_assert(qmp->ufs_reset);
2758         clk_disable_unprepare(qphy->pipe_clk);
2759 err_clk_enable:
2760         if (cfg->has_lane_rst)
2761                 reset_control_assert(qphy->lane_rst);
2762 err_lane_rst:
2763         qcom_qmp_phy_com_exit(qmp);
2764
2765         return ret;
2766 }
2767
2768 static int qcom_qmp_phy_disable(struct phy *phy)
2769 {
2770         struct qmp_phy *qphy = phy_get_drvdata(phy);
2771         struct qcom_qmp *qmp = qphy->qmp;
2772         const struct qmp_phy_cfg *cfg = qmp->cfg;
2773
2774         clk_disable_unprepare(qphy->pipe_clk);
2775
2776         /* PHY reset */
2777         if (!cfg->no_pcs_sw_reset)
2778                 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2779
2780         /* stop SerDes and Phy-Coding-Sublayer */
2781         qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
2782
2783         /* Put PHY into POWER DOWN state: active low */
2784         if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
2785                 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2786                              cfg->pwrdn_ctrl);
2787         } else {
2788                 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
2789                                 cfg->pwrdn_ctrl);
2790         }
2791
2792         if (cfg->has_lane_rst)
2793                 reset_control_assert(qphy->lane_rst);
2794
2795         qcom_qmp_phy_com_exit(qmp);
2796
2797         qmp->phy_initialized = false;
2798
2799         return 0;
2800 }
2801
2802 static int qcom_qmp_phy_set_mode(struct phy *phy,
2803                                  enum phy_mode mode, int submode)
2804 {
2805         struct qmp_phy *qphy = phy_get_drvdata(phy);
2806         struct qcom_qmp *qmp = qphy->qmp;
2807
2808         qmp->mode = mode;
2809
2810         return 0;
2811 }
2812
2813 static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
2814 {
2815         struct qcom_qmp *qmp = qphy->qmp;
2816         const struct qmp_phy_cfg *cfg = qmp->cfg;
2817         void __iomem *pcs = qphy->pcs;
2818         void __iomem *pcs_misc = qphy->pcs_misc;
2819         u32 intr_mask;
2820
2821         if (qmp->mode == PHY_MODE_USB_HOST_SS ||
2822             qmp->mode == PHY_MODE_USB_DEVICE_SS)
2823                 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
2824         else
2825                 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
2826
2827         /* Clear any pending interrupts status */
2828         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2829         /* Writing 1 followed by 0 clears the interrupt */
2830         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2831
2832         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2833                      ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
2834
2835         /* Enable required PHY autonomous mode interrupts */
2836         qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
2837
2838         /* Enable i/o clamp_n for autonomous mode */
2839         if (pcs_misc)
2840                 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2841 }
2842
2843 static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
2844 {
2845         struct qcom_qmp *qmp = qphy->qmp;
2846         const struct qmp_phy_cfg *cfg = qmp->cfg;
2847         void __iomem *pcs = qphy->pcs;
2848         void __iomem *pcs_misc = qphy->pcs_misc;
2849
2850         /* Disable i/o clamp_n on resume for normal mode */
2851         if (pcs_misc)
2852                 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2853
2854         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2855                      ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
2856
2857         qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2858         /* Writing 1 followed by 0 clears the interrupt */
2859         qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2860 }
2861
2862 static int __maybe_unused qcom_qmp_phy_runtime_suspend(struct device *dev)
2863 {
2864         struct qcom_qmp *qmp = dev_get_drvdata(dev);
2865         struct qmp_phy *qphy = qmp->phys[0];
2866         const struct qmp_phy_cfg *cfg = qmp->cfg;
2867
2868         dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
2869
2870         /* Supported only for USB3 PHY */
2871         if (cfg->type != PHY_TYPE_USB3)
2872                 return 0;
2873
2874         if (!qmp->phy_initialized) {
2875                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2876                 return 0;
2877         }
2878
2879         qcom_qmp_phy_enable_autonomous_mode(qphy);
2880
2881         clk_disable_unprepare(qphy->pipe_clk);
2882         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2883
2884         return 0;
2885 }
2886
2887 static int __maybe_unused qcom_qmp_phy_runtime_resume(struct device *dev)
2888 {
2889         struct qcom_qmp *qmp = dev_get_drvdata(dev);
2890         struct qmp_phy *qphy = qmp->phys[0];
2891         const struct qmp_phy_cfg *cfg = qmp->cfg;
2892         int ret = 0;
2893
2894         dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
2895
2896         /* Supported only for USB3 PHY */
2897         if (cfg->type != PHY_TYPE_USB3)
2898                 return 0;
2899
2900         if (!qmp->phy_initialized) {
2901                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2902                 return 0;
2903         }
2904
2905         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2906         if (ret) {
2907                 dev_err(qmp->dev, "failed to enable clks, err=%d\n", ret);
2908                 return ret;
2909         }
2910
2911         ret = clk_prepare_enable(qphy->pipe_clk);
2912         if (ret) {
2913                 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
2914                 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2915                 return ret;
2916         }
2917
2918         qcom_qmp_phy_disable_autonomous_mode(qphy);
2919
2920         return 0;
2921 }
2922
2923 static int qcom_qmp_phy_vreg_init(struct device *dev)
2924 {
2925         struct qcom_qmp *qmp = dev_get_drvdata(dev);
2926         int num = qmp->cfg->num_vregs;
2927         int i;
2928
2929         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
2930         if (!qmp->vregs)
2931                 return -ENOMEM;
2932
2933         for (i = 0; i < num; i++)
2934                 qmp->vregs[i].supply = qmp->cfg->vreg_list[i];
2935
2936         return devm_regulator_bulk_get(dev, num, qmp->vregs);
2937 }
2938
2939 static int qcom_qmp_phy_reset_init(struct device *dev)
2940 {
2941         struct qcom_qmp *qmp = dev_get_drvdata(dev);
2942         int i;
2943
2944         qmp->resets = devm_kcalloc(dev, qmp->cfg->num_resets,
2945                                    sizeof(*qmp->resets), GFP_KERNEL);
2946         if (!qmp->resets)
2947                 return -ENOMEM;
2948
2949         for (i = 0; i < qmp->cfg->num_resets; i++) {
2950                 struct reset_control *rst;
2951                 const char *name = qmp->cfg->reset_list[i];
2952
2953                 rst = devm_reset_control_get(dev, name);
2954                 if (IS_ERR(rst)) {
2955                         dev_err(dev, "failed to get %s reset\n", name);
2956                         return PTR_ERR(rst);
2957                 }
2958                 qmp->resets[i] = rst;
2959         }
2960
2961         return 0;
2962 }
2963
2964 static int qcom_qmp_phy_clk_init(struct device *dev)
2965 {
2966         struct qcom_qmp *qmp = dev_get_drvdata(dev);
2967         int num = qmp->cfg->num_clks;
2968         int i;
2969
2970         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
2971         if (!qmp->clks)
2972                 return -ENOMEM;
2973
2974         for (i = 0; i < num; i++)
2975                 qmp->clks[i].id = qmp->cfg->clk_list[i];
2976
2977         return devm_clk_bulk_get(dev, num, qmp->clks);
2978 }
2979
2980 static void phy_pipe_clk_release_provider(void *res)
2981 {
2982         of_clk_del_provider(res);
2983 }
2984
2985 /*
2986  * Register a fixed rate pipe clock.
2987  *
2988  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
2989  * controls it. The <s>_pipe_clk coming out of the GCC is requested
2990  * by the PHY driver for its operations.
2991  * We register the <s>_pipe_clksrc here. The gcc driver takes care
2992  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
2993  * Below picture shows this relationship.
2994  *
2995  *         +---------------+
2996  *         |   PHY block   |<<---------------------------------------+
2997  *         |               |                                         |
2998  *         |   +-------+   |                   +-----+               |
2999  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
3000  *    clk  |   +-------+   |                   +-----+
3001  *         +---------------+
3002  */
3003 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
3004 {
3005         struct clk_fixed_rate *fixed;
3006         struct clk_init_data init = { };
3007         int ret;
3008
3009         if ((qmp->cfg->type != PHY_TYPE_USB3) &&
3010             (qmp->cfg->type != PHY_TYPE_PCIE)) {
3011                 /* not all phys register pipe clocks, so return success */
3012                 return 0;
3013         }
3014
3015         ret = of_property_read_string(np, "clock-output-names", &init.name);
3016         if (ret) {
3017                 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
3018                 return ret;
3019         }
3020
3021         fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
3022         if (!fixed)
3023                 return -ENOMEM;
3024
3025         init.ops = &clk_fixed_rate_ops;
3026
3027         /* controllers using QMP phys use 125MHz pipe clock interface */
3028         fixed->fixed_rate = 125000000;
3029         fixed->hw.init = &init;
3030
3031         ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
3032         if (ret)
3033                 return ret;
3034
3035         ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
3036         if (ret)
3037                 return ret;
3038
3039         /*
3040          * Roll a devm action because the clock provider is the child node, but
3041          * the child node is not actually a device.
3042          */
3043         ret = devm_add_action(qmp->dev, phy_pipe_clk_release_provider, np);
3044         if (ret)
3045                 phy_pipe_clk_release_provider(np);
3046
3047         return ret;
3048 }
3049
3050 static const struct phy_ops qcom_qmp_phy_gen_ops = {
3051         .init           = qcom_qmp_phy_enable,
3052         .exit           = qcom_qmp_phy_disable,
3053         .set_mode       = qcom_qmp_phy_set_mode,
3054         .owner          = THIS_MODULE,
3055 };
3056
3057 static const struct phy_ops qcom_qmp_pcie_ufs_ops = {
3058         .power_on       = qcom_qmp_phy_enable,
3059         .power_off      = qcom_qmp_phy_disable,
3060         .set_mode       = qcom_qmp_phy_set_mode,
3061         .owner          = THIS_MODULE,
3062 };
3063
3064 static
3065 int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
3066 {
3067         struct qcom_qmp *qmp = dev_get_drvdata(dev);
3068         struct phy *generic_phy;
3069         struct qmp_phy *qphy;
3070         const struct phy_ops *ops = &qcom_qmp_phy_gen_ops;
3071         char prop_name[MAX_PROP_NAME];
3072         int ret;
3073
3074         qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
3075         if (!qphy)
3076                 return -ENOMEM;
3077
3078         /*
3079          * Get memory resources for each phy lane:
3080          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
3081          * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
3082          * For single lane PHYs: pcs_misc (optional) -> 3.
3083          */
3084         qphy->tx = of_iomap(np, 0);
3085         if (!qphy->tx)
3086                 return -ENOMEM;
3087
3088         qphy->rx = of_iomap(np, 1);
3089         if (!qphy->rx)
3090                 return -ENOMEM;
3091
3092         qphy->pcs = of_iomap(np, 2);
3093         if (!qphy->pcs)
3094                 return -ENOMEM;
3095
3096         /*
3097          * If this is a dual-lane PHY, then there should be registers for the
3098          * second lane. Some old device trees did not specify this, so fall
3099          * back to old legacy behavior of assuming they can be reached at an
3100          * offset from the first lane.
3101          */
3102         if (qmp->cfg->is_dual_lane_phy) {
3103                 qphy->tx2 = of_iomap(np, 3);
3104                 qphy->rx2 = of_iomap(np, 4);
3105                 if (!qphy->tx2 || !qphy->rx2) {
3106                         dev_warn(dev,
3107                                  "Underspecified device tree, falling back to legacy register regions\n");
3108
3109                         /* In the old version, pcs_misc is at index 3. */
3110                         qphy->pcs_misc = qphy->tx2;
3111                         qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
3112                         qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
3113
3114                 } else {
3115                         qphy->pcs_misc = of_iomap(np, 5);
3116                 }
3117
3118         } else {
3119                 qphy->pcs_misc = of_iomap(np, 3);
3120         }
3121
3122         if (!qphy->pcs_misc)
3123                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
3124
3125         /*
3126          * Get PHY's Pipe clock, if any. USB3 and PCIe are PIPE3
3127          * based phys, so they essentially have pipe clock. So,
3128          * we return error in case phy is USB3 or PIPE type.
3129          * Otherwise, we initialize pipe clock to NULL for
3130          * all phys that don't need this.
3131          */
3132         snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
3133         qphy->pipe_clk = of_clk_get_by_name(np, prop_name);
3134         if (IS_ERR(qphy->pipe_clk)) {
3135                 if (qmp->cfg->type == PHY_TYPE_PCIE ||
3136                     qmp->cfg->type == PHY_TYPE_USB3) {
3137                         ret = PTR_ERR(qphy->pipe_clk);
3138                         if (ret != -EPROBE_DEFER)
3139                                 dev_err(dev,
3140                                         "failed to get lane%d pipe_clk, %d\n",
3141                                         id, ret);
3142                         return ret;
3143                 }
3144                 qphy->pipe_clk = NULL;
3145         }
3146
3147         /* Get lane reset, if any */
3148         if (qmp->cfg->has_lane_rst) {
3149                 snprintf(prop_name, sizeof(prop_name), "lane%d", id);
3150                 qphy->lane_rst = of_reset_control_get(np, prop_name);
3151                 if (IS_ERR(qphy->lane_rst)) {
3152                         dev_err(dev, "failed to get lane%d reset\n", id);
3153                         return PTR_ERR(qphy->lane_rst);
3154                 }
3155         }
3156
3157         if (qmp->cfg->type == PHY_TYPE_UFS || qmp->cfg->type == PHY_TYPE_PCIE)
3158                 ops = &qcom_qmp_pcie_ufs_ops;
3159
3160         generic_phy = devm_phy_create(dev, np, ops);
3161         if (IS_ERR(generic_phy)) {
3162                 ret = PTR_ERR(generic_phy);
3163                 dev_err(dev, "failed to create qphy %d\n", ret);
3164                 return ret;
3165         }
3166
3167         qphy->phy = generic_phy;
3168         qphy->index = id;
3169         qphy->qmp = qmp;
3170         qmp->phys[id] = qphy;
3171         phy_set_drvdata(generic_phy, qphy);
3172
3173         return 0;
3174 }
3175
3176 static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
3177         {
3178                 .compatible = "qcom,ipq8074-qmp-usb3-phy",
3179                 .data = &ipq8074_usb3phy_cfg,
3180         }, {
3181                 .compatible = "qcom,msm8996-qmp-pcie-phy",
3182                 .data = &msm8996_pciephy_cfg,
3183         }, {
3184                 .compatible = "qcom,msm8996-qmp-ufs-phy",
3185                 .data = &msm8996_ufs_cfg,
3186         }, {
3187                 .compatible = "qcom,msm8996-qmp-usb3-phy",
3188                 .data = &msm8996_usb3phy_cfg,
3189         }, {
3190                 .compatible = "qcom,msm8998-qmp-pcie-phy",
3191                 .data = &msm8998_pciephy_cfg,
3192         }, {
3193                 .compatible = "qcom,msm8998-qmp-ufs-phy",
3194                 .data = &sdm845_ufsphy_cfg,
3195         }, {
3196                 .compatible = "qcom,ipq8074-qmp-pcie-phy",
3197                 .data = &ipq8074_pciephy_cfg,
3198         }, {
3199                 .compatible = "qcom,sc7180-qmp-usb3-phy",
3200                 .data = &sc7180_usb3phy_cfg,
3201         }, {
3202                 .compatible = "qcom,sdm845-qhp-pcie-phy",
3203                 .data = &sdm845_qhp_pciephy_cfg,
3204         }, {
3205                 .compatible = "qcom,sdm845-qmp-pcie-phy",
3206                 .data = &sdm845_qmp_pciephy_cfg,
3207         }, {
3208                 .compatible = "qcom,sdm845-qmp-usb3-phy",
3209                 .data = &qmp_v3_usb3phy_cfg,
3210         }, {
3211                 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
3212                 .data = &qmp_v3_usb3_uniphy_cfg,
3213         }, {
3214                 .compatible = "qcom,sdm845-qmp-ufs-phy",
3215                 .data = &sdm845_ufsphy_cfg,
3216         }, {
3217                 .compatible = "qcom,msm8998-qmp-usb3-phy",
3218                 .data = &msm8998_usb3phy_cfg,
3219         }, {
3220                 .compatible = "qcom,sm8150-qmp-ufs-phy",
3221                 .data = &sm8150_ufsphy_cfg,
3222         }, {
3223                 .compatible = "qcom,sm8250-qmp-ufs-phy",
3224                 .data = &sm8150_ufsphy_cfg,
3225         }, {
3226                 .compatible = "qcom,sm8150-qmp-usb3-phy",
3227                 .data = &sm8150_usb3phy_cfg,
3228         }, {
3229                 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
3230                 .data = &sm8150_usb3_uniphy_cfg,
3231         }, {
3232                 .compatible = "qcom,sm8250-qmp-usb3-phy",
3233                 .data = &sm8250_usb3phy_cfg,
3234         }, {
3235                 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
3236                 .data = &sm8250_usb3_uniphy_cfg,
3237         },
3238         { },
3239 };
3240 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_of_match_table);
3241
3242 static const struct dev_pm_ops qcom_qmp_phy_pm_ops = {
3243         SET_RUNTIME_PM_OPS(qcom_qmp_phy_runtime_suspend,
3244                            qcom_qmp_phy_runtime_resume, NULL)
3245 };
3246
3247 static int qcom_qmp_phy_probe(struct platform_device *pdev)
3248 {
3249         struct qcom_qmp *qmp;
3250         struct device *dev = &pdev->dev;
3251         struct resource *res;
3252         struct device_node *child;
3253         struct phy_provider *phy_provider;
3254         void __iomem *base;
3255         int num, id;
3256         int ret;
3257
3258         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
3259         if (!qmp)
3260                 return -ENOMEM;
3261
3262         qmp->dev = dev;
3263         dev_set_drvdata(dev, qmp);
3264
3265         /* Get the specific init parameters of QMP phy */
3266         qmp->cfg = of_device_get_match_data(dev);
3267         if (!qmp->cfg)
3268                 return -EINVAL;
3269
3270         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3271         base = devm_ioremap_resource(dev, res);
3272         if (IS_ERR(base))
3273                 return PTR_ERR(base);
3274
3275         /* per PHY serdes; usually located at base address */
3276         qmp->serdes = base;
3277
3278         /* per PHY dp_com; if PHY has dp_com control block */
3279         if (qmp->cfg->has_phy_dp_com_ctrl) {
3280                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
3281                                                    "dp_com");
3282                 base = devm_ioremap_resource(dev, res);
3283                 if (IS_ERR(base))
3284                         return PTR_ERR(base);
3285
3286                 qmp->dp_com = base;
3287         }
3288
3289         mutex_init(&qmp->phy_mutex);
3290
3291         ret = qcom_qmp_phy_clk_init(dev);
3292         if (ret)
3293                 return ret;
3294
3295         ret = qcom_qmp_phy_reset_init(dev);
3296         if (ret)
3297                 return ret;
3298
3299         ret = qcom_qmp_phy_vreg_init(dev);
3300         if (ret) {
3301                 if (ret != -EPROBE_DEFER)
3302                         dev_err(dev, "failed to get regulator supplies: %d\n",
3303                                 ret);
3304                 return ret;
3305         }
3306
3307         num = of_get_available_child_count(dev->of_node);
3308         /* do we have a rogue child node ? */
3309         if (num > qmp->cfg->nlanes)
3310                 return -EINVAL;
3311
3312         qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
3313         if (!qmp->phys)
3314                 return -ENOMEM;
3315
3316         id = 0;
3317         pm_runtime_set_active(dev);
3318         pm_runtime_enable(dev);
3319         /*
3320          * Prevent runtime pm from being ON by default. Users can enable
3321          * it using power/control in sysfs.
3322          */
3323         pm_runtime_forbid(dev);
3324
3325         for_each_available_child_of_node(dev->of_node, child) {
3326                 /* Create per-lane phy */
3327                 ret = qcom_qmp_phy_create(dev, child, id);
3328                 if (ret) {
3329                         dev_err(dev, "failed to create lane%d phy, %d\n",
3330                                 id, ret);
3331                         goto err_node_put;
3332                 }
3333
3334                 /*
3335                  * Register the pipe clock provided by phy.
3336                  * See function description to see details of this pipe clock.
3337                  */
3338                 ret = phy_pipe_clk_register(qmp, child);
3339                 if (ret) {
3340                         dev_err(qmp->dev,
3341                                 "failed to register pipe clock source\n");
3342                         goto err_node_put;
3343                 }
3344                 id++;
3345         }
3346
3347         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
3348         if (!IS_ERR(phy_provider))
3349                 dev_info(dev, "Registered Qcom-QMP phy\n");
3350         else
3351                 pm_runtime_disable(dev);
3352
3353         return PTR_ERR_OR_ZERO(phy_provider);
3354
3355 err_node_put:
3356         pm_runtime_disable(dev);
3357         of_node_put(child);
3358         return ret;
3359 }
3360
3361 static struct platform_driver qcom_qmp_phy_driver = {
3362         .probe          = qcom_qmp_phy_probe,
3363         .driver = {
3364                 .name   = "qcom-qmp-phy",
3365                 .pm     = &qcom_qmp_phy_pm_ops,
3366                 .of_match_table = qcom_qmp_phy_of_match_table,
3367         },
3368 };
3369
3370 module_platform_driver(qcom_qmp_phy_driver);
3371
3372 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
3373 MODULE_DESCRIPTION("Qualcomm QMP PHY driver");
3374 MODULE_LICENSE("GPL v2");