drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/reset.h>
  20 #include <linux/slab.h>
  21
  22 #include <ufs/unipro.h>
  23
  24 #include "phy-qcom-qmp-common.h"
  25
  26 #include "phy-qcom-qmp.h"
  27 #include "phy-qcom-qmp-pcs-ufs-v2.h"
  28 #include "phy-qcom-qmp-pcs-ufs-v3.h"
  29 #include "phy-qcom-qmp-pcs-ufs-v4.h"
  30 #include "phy-qcom-qmp-pcs-ufs-v5.h"
  31 #include "phy-qcom-qmp-pcs-ufs-v6.h"
  32
  33 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
  34
  35 /* QPHY_PCS_READY_STATUS bit */
  36 #define PCS_READY                               BIT(0)
  37
  38 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  39
  40 #define NUM_OVERLAY                             2
  41
  42 /* set of registers with offsets different per-PHY */
  43 enum qphy_reg_layout {
  44         /* PCS registers */
  45         QPHY_SW_RESET,
  46         QPHY_START_CTRL,
  47         QPHY_PCS_READY_STATUS,
  48         QPHY_PCS_POWER_DOWN_CONTROL,
  49         /* Keep last to ensure regs_layout arrays are properly initialized */
  50         QPHY_LAYOUT_SIZE
  51 };
  52
  53 static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
  54         [QPHY_START_CTRL]               = QPHY_V2_PCS_UFS_PHY_START,
  55         [QPHY_PCS_READY_STATUS]         = QPHY_V2_PCS_UFS_READY_STATUS,
  56         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL,
  57 };
  58
  59 static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
  60         [QPHY_START_CTRL]               = QPHY_V3_PCS_UFS_PHY_START,
  61         [QPHY_PCS_READY_STATUS]         = QPHY_V3_PCS_UFS_READY_STATUS,
  62         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL,
  63 };
  64
  65 static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
  66         [QPHY_START_CTRL]               = QPHY_V4_PCS_UFS_PHY_START,
  67         [QPHY_PCS_READY_STATUS]         = QPHY_V4_PCS_UFS_READY_STATUS,
  68         [QPHY_SW_RESET]                 = QPHY_V4_PCS_UFS_SW_RESET,
  69         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL,
  70 };
  71
  72 static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
  73         [QPHY_START_CTRL]               = QPHY_V5_PCS_UFS_PHY_START,
  74         [QPHY_PCS_READY_STATUS]         = QPHY_V5_PCS_UFS_READY_STATUS,
  75         [QPHY_SW_RESET]                 = QPHY_V5_PCS_UFS_SW_RESET,
  76         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,
  77 };
  78
  79 static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
  80         [QPHY_START_CTRL]               = QPHY_V6_PCS_UFS_PHY_START,
  81         [QPHY_PCS_READY_STATUS]         = QPHY_V6_PCS_UFS_READY_STATUS,
  82         [QPHY_SW_RESET]                 = QPHY_V6_PCS_UFS_SW_RESET,
  83         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,
  84 };
  85
  86 static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = {
  87         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
  88         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
  89         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
  90         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
  91         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
  92         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
  93         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05),
  94         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
  95         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
  96         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
  97         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
  98         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
  99         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 100         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 101         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 102         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
 103         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54),
 104         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
 105         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 106         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
 107         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
 108         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
 109         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 110         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 111         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 112         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 113         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 114         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
 115         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
 116         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
 117         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
 118         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 119         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
 120         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
 121         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
 122         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
 123         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
 124         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
 125         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
 126         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
 127         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 128         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
 129         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
 130         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
 131         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
 132         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
 133 };
 134
 135 static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = {
 136         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 137         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
 138 };
 139
 140 static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = {
 141         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
 142         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
 143         QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
 144         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18),
 145         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
 146         QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b),
 147         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff),
 148         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f),
 149         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff),
 150         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f),
 151         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
 152 };
 153
 154 static const struct qmp_phy_init_tbl sc7280_ufsphy_tx[] = {
 155         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
 156         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
 157         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
 158         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
 159         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
 160         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
 161 };
 162
 163 static const struct qmp_phy_init_tbl sc7280_ufsphy_rx[] = {
 164         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
 165         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
 166         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 167         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
 168         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
 169         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
 170         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
 171         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 172         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
 173         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
 174         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
 175         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
 176         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 177         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 178         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
 179         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
 180         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
 181         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 182         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 183         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d),
 184         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d),
 185         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed),
 186         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
 187         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c),
 188         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
 189         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
 190         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
 191         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
 192         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
 193         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
 194         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
 195         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
 196         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
 197         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
 198         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 199 };
 200
 201 static const struct qmp_phy_init_tbl sc7280_ufsphy_pcs[] = {
 202         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
 203         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
 204         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 205         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 206         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
 207         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
 208         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 209         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03),
 210         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16),
 211         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8),
 212         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa),
 213         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06),
 214         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03),
 215         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03),
 216 };
 217
 218 static const struct qmp_phy_init_tbl sc7280_ufsphy_hs_g4_rx[] = {
 219         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
 220         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
 221         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 222         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
 223         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
 224         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
 225         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
 226         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 227         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
 228         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
 229         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
 230         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
 231         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
 232         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
 233         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
 234         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
 235         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
 236         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
 237         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
 238         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
 239         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
 240         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
 241         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
 242         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
 243         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 244         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
 245         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
 246         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
 247         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
 248         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
 249         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
 250         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
 251         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
 252         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
 253         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
 254         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
 255         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 256         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f),
 257 };
 258
 259 static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = {
 260         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
 261         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 262         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 263         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
 264         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 265         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 266         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 267         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 268         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
 269         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01),
 270         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 271         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 272         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 273         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 274         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 275         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
 276         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04),
 277         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
 278         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 279         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
 280         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
 281         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
 282         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 283         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 284         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 285         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 286         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 287         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
 288         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
 289         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
 290         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
 291         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 292         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98),
 293         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
 294         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
 295         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
 296         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
 297         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
 298         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
 299         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
 300         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 301         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
 302         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
 303         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
 304         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
 305         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
 306         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 307         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 308         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff),
 309         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
 310 };
 311
 312 static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = {
 313         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
 314 };
 315
 316 static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = {
 317         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 318         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 319 };
 320
 321 static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = {
 322         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
 323         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
 324         QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
 325         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
 326         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
 327         QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B),
 328         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
 329         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
 330         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
 331         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
 332         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
 333         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
 334         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
 335         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
 336         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
 337 };
 338
 339 static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = {
 340         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15),
 341         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
 342         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
 343         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 344         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
 345         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
 346         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL, 0x12),
 347         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f),
 348         QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
 349 };
 350
 351 static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = {
 352         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 353         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 354         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
 355         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 356         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 357         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5),
 358         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 359         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 360         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 361         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 362         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
 363         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 364         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04),
 365         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05),
 366         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff),
 367         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00),
 368         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 369         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 370         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 371         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 372         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 373         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 374         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda),
 375         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 376         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff),
 377         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c),
 378         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98),
 379         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06),
 380         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16),
 381         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36),
 382         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
 383         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
 384         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1),
 385         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00),
 386         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32),
 387         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f),
 388 };
 389
 390 static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = {
 391         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
 392 };
 393
 394 static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = {
 395         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 396         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
 397         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
 398 };
 399
 400 static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = {
 401         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
 402         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
 403         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 404         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 405         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 406         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
 407         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 408         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 409         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
 410         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
 411         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
 412         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
 413         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 414         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
 415         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 416         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
 417 };
 418
 419 static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = {
 420         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e),
 421         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
 422         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 423         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
 424         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 425         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
 426         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a),
 427         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 428 };
 429
 430 static const struct qmp_phy_init_tbl sm7150_ufsphy_rx[] = {
 431         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
 432         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
 433         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 434         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 435         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 436         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b),
 437         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 438         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 439         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
 440         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
 441         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
 442         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04),
 443         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5b),
 444         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81),
 445         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 446         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
 447 };
 448
 449 static const struct qmp_phy_init_tbl sm7150_ufsphy_pcs[] = {
 450         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6f),
 451         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
 452         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 453         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03),
 454         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 455         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f),
 456         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
 457         QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 458 };
 459
 460 static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {
 461         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
 462         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
 463         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
 464         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01),
 465         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 466         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
 467         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00),
 468         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 469         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
 470         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 471         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 472         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 473         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff),
 474         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c),
 475         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
 476         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 477         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98),
 478         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 479         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 480         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 481         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32),
 482         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f),
 483         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
 484         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
 485 };
 486
 487 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = {
 488         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
 489 };
 490
 491 static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = {
 492         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
 493         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
 494         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
 495         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
 496         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05),
 497         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
 498 };
 499
 500 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = {
 501         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75),
 502 };
 503
 504 static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
 505         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
 506         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
 507         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 508         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18),
 509         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
 510         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 511         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1),
 512         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 513         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80),
 514         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
 515         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
 516         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b),
 517         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 518         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 519         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d),
 520         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
 521         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10),
 522         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 523         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 524         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36),
 525         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36),
 526         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6),
 527         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b),
 528         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d),
 529         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0),
 530         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8),
 531         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
 532         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
 533         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
 534         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0),
 535         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8),
 536         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
 537         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
 538         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
 539 };
 540
 541 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = {
 542         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
 543         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
 544         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
 545         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
 546         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
 547         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
 548         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
 549         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
 550         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
 551         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
 552         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 553         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c),
 554         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
 555         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
 556         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
 557         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
 558 };
 559
 560 static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
 561         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
 562         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
 563         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 564         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 565         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
 566         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
 567         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 568 };
 569
 570 static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = {
 571         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10),
 572         QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
 573 };
 574
 575 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = {
 576         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5),
 577 };
 578
 579 static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = {
 580         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
 581         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81),
 582         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e),
 583         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f),
 584         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
 585         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
 586         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09),
 587         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
 588         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
 589         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20),
 590         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80),
 591         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
 592         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
 593         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
 594         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
 595         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 596         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c),
 597         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d),
 598         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d),
 599         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed),
 600         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c),
 601 };
 602
 603 static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
 604         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
 605         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
 606         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
 607         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
 608         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
 609         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
 610         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
 611         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 612         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
 613         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
 614         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
 615         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
 616         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
 617         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
 618         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
 619         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 620         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
 621         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
 622         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
 623         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
 624         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
 625         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
 626         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
 627         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),
 628 };
 629
 630 static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = {
 631         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
 632 };
 633
 634 static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = {
 635         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
 636         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
 637         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
 638         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
 639         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
 640         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
 641         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
 642         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 643         QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
 644 };
 645
 646 static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = {
 647         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
 648         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
 649         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
 650         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
 651         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
 652         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
 653         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
 654         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
 655         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
 656         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
 657         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
 658         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
 659         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
 660         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
 661         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 662         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 663         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
 664         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
 665         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
 666         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 667         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 668         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
 669         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
 670         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
 671         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
 672         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
 673         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
 674         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
 675         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
 676         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
 677         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
 678         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
 679         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
 680         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
 681         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
 682         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
 683         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
 684 };
 685
 686 static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = {
 687         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
 688         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
 689         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
 690         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 691         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
 692         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
 693         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
 694         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 695 };
 696
 697 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = {
 698         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5),
 699 };
 700
 701 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = {
 702         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81),
 703         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f),
 704         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
 705         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 706         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 707         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20),
 708         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80),
 709         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
 710         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf),
 711         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf),
 712         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
 713         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f),
 714         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d),
 715         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d),
 716         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d),
 717         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed),
 718         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c),
 719 };
 720
 721 static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = {
 722         QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),
 723 };
 724
 725 static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
 726         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
 727         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
 728         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
 729         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
 730         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
 731         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
 732         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
 733         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
 734         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
 735         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
 736         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
 737 };
 738
 739 static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
 740         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
 741 };
 742
 743 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
 744         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
 745         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
 746         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
 747         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
 748         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
 749         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
 750         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
 751         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
 752         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
 753 };
 754
 755 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
 756         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
 757         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
 758         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
 759         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
 760 };
 761
 762 static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
 763         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
 764         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
 765 };
 766
 767 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
 768         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
 769 };
 770
 771 static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
 772         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
 773
 774         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
 775         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
 776         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
 777         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
 778
 779         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
 780         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
 781
 782         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
 783         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
 784         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
 785         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
 786 };
 787
 788 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
 789         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
 790 };
 791
 792 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
 793         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
 794         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
 795         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
 796         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
 797         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
 798         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
 799         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
 800         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
 801         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
 802         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
 803         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
 804         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
 805         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
 806 };
 807
 808 static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
 809         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
 810         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
 811         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 812         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 813 };
 814
 815 static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
 816         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
 817         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
 818         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
 819 };
 820
 821 static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
 822         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
 823         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
 824         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
 825 };
 826
 827 static const struct qmp_phy_init_tbl sm8650_ufsphy_serdes[] = {
 828         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
 829         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
 830         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
 831         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
 832         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
 833         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
 834         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
 835         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
 836         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
 837         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
 838         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
 839         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
 840         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
 841         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
 842         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
 843         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
 844         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
 845         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
 846         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
 847         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
 848 };
 849
 850 static const struct qmp_phy_init_tbl sm8650_ufsphy_tx[] = {
 851         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
 852         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
 853 };
 854
 855 static const struct qmp_phy_init_tbl sm8650_ufsphy_rx[] = {
 856         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
 857         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0f),
 858         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
 859         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
 860         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
 861         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a),
 862         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60),
 863         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e),
 864         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60),
 865         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e),
 866         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e),
 867         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36),
 868         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
 869         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
 870         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
 871         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_SATURATION, 0x1f),
 872         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94),
 873         QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0, 0xfa),
 874 };
 875
 876 static const struct qmp_phy_init_tbl sm8650_ufsphy_pcs[] = {
 877         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x00),
 878         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
 879         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0xc1),
 880         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
 881         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
 882         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
 883         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
 884         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
 885         QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
 886 };
 887
 888 struct qmp_ufs_offsets {
 889         u16 serdes;
 890         u16 pcs;
 891         u16 tx;
 892         u16 rx;
 893         u16 tx2;
 894         u16 rx2;
 895 };
 896
 897 struct qmp_phy_cfg_tbls {
 898         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
 899         const struct qmp_phy_init_tbl *serdes;
 900         int serdes_num;
 901         const struct qmp_phy_init_tbl *tx;
 902         int tx_num;
 903         const struct qmp_phy_init_tbl *rx;
 904         int rx_num;
 905         const struct qmp_phy_init_tbl *pcs;
 906         int pcs_num;
 907         /* Maximum supported Gear of this tbls */
 908         u32 max_gear;
 909 };
 910
 911 /* struct qmp_phy_cfg - per-PHY initialization config */
 912 struct qmp_phy_cfg {
 913         int lanes;
 914
 915         const struct qmp_ufs_offsets *offsets;
 916         /* Maximum supported Gear of this config */
 917         u32 max_supported_gear;
 918
 919         /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
 920         const struct qmp_phy_cfg_tbls tbls;
 921         /* Additional sequence for HS Series B */
 922         const struct qmp_phy_cfg_tbls tbls_hs_b;
 923         /* Additional sequence for different HS Gears */
 924         const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY];
 925
 926         /* regulators to be requested */
 927         const char * const *vreg_list;
 928         int num_vregs;
 929
 930         /* array of registers with different offsets */
 931         const unsigned int *regs;
 932
 933         /* true, if PCS block has no separate SW_RESET register */
 934         bool no_pcs_sw_reset;
 935 };
 936
 937 struct qmp_ufs {
 938         struct device *dev;
 939
 940         const struct qmp_phy_cfg *cfg;
 941
 942         void __iomem *serdes;
 943         void __iomem *pcs;
 944         void __iomem *pcs_misc;
 945         void __iomem *tx;
 946         void __iomem *rx;
 947         void __iomem *tx2;
 948         void __iomem *rx2;
 949
 950         struct clk_bulk_data *clks;
 951         int num_clks;
 952         struct regulator_bulk_data *vregs;
 953         struct reset_control *ufs_reset;
 954
 955         struct phy *phy;
 956         u32 mode;
 957         u32 submode;
 958 };
 959
 960 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
 961 {
 962         u32 reg;
 963
 964         reg = readl(base + offset);
 965         reg |= val;
 966         writel(reg, base + offset);
 967
 968         /* ensure that above write is through */
 969         readl(base + offset);
 970 }
 971
 972 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
 973 {
 974         u32 reg;
 975
 976         reg = readl(base + offset);
 977         reg &= ~val;
 978         writel(reg, base + offset);
 979
 980         /* ensure that above write is through */
 981         readl(base + offset);
 982 }
 983
 984 /* list of regulators */
 985 static const char * const qmp_phy_vreg_l[] = {
 986         "vdda-phy", "vdda-pll",
 987 };
 988
 989 static const struct qmp_ufs_offsets qmp_ufs_offsets = {
 990         .serdes         = 0,
 991         .pcs            = 0xc00,
 992         .tx             = 0x400,
 993         .rx             = 0x600,
 994         .tx2            = 0x800,
 995         .rx2            = 0xa00,
 996 };
 997
 998 static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {
 999         .serdes         = 0,
1000         .pcs            = 0x0400,
1001         .tx             = 0x1000,
1002         .rx             = 0x1200,
1003         .tx2            = 0x1800,
1004         .rx2            = 0x1a00,
1005 };
1006
1007 static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
1008         .lanes                  = 1,
1009
1010         .offsets                = &qmp_ufs_offsets,
1011         .max_supported_gear     = UFS_HS_G3,
1012
1013         .tbls = {
1014                 .serdes         = msm8996_ufsphy_serdes,
1015                 .serdes_num     = ARRAY_SIZE(msm8996_ufsphy_serdes),
1016                 .tx             = msm8996_ufsphy_tx,
1017                 .tx_num         = ARRAY_SIZE(msm8996_ufsphy_tx),
1018                 .rx             = msm8996_ufsphy_rx,
1019                 .rx_num         = ARRAY_SIZE(msm8996_ufsphy_rx),
1020         },
1021
1022         .vreg_list              = qmp_phy_vreg_l,
1023         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1024
1025         .regs                   = ufsphy_v2_regs_layout,
1026
1027         .no_pcs_sw_reset        = true,
1028 };
1029
1030 static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
1031         .lanes                  = 2,
1032
1033         .offsets                = &qmp_ufs_offsets,
1034         .max_supported_gear     = UFS_HS_G4,
1035
1036         .tbls = {
1037                 .serdes         = sm8350_ufsphy_serdes,
1038                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_serdes),
1039                 .tx             = sm8350_ufsphy_tx,
1040                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_tx),
1041                 .rx             = sm8350_ufsphy_rx,
1042                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_rx),
1043                 .pcs            = sm8350_ufsphy_pcs,
1044                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_pcs),
1045         },
1046         .tbls_hs_b = {
1047                 .serdes         = sm8350_ufsphy_hs_b_serdes,
1048                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1049         },
1050         .tbls_hs_overlay[0] = {
1051                 .tx             = sm8350_ufsphy_g4_tx,
1052                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1053                 .rx             = sm8350_ufsphy_g4_rx,
1054                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1055                 .pcs            = sm8350_ufsphy_g4_pcs,
1056                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1057                 .max_gear       = UFS_HS_G4,
1058         },
1059         .vreg_list              = qmp_phy_vreg_l,
1060         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1061         .regs                   = ufsphy_v5_regs_layout,
1062 };
1063
1064 static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {
1065         .lanes                  = 2,
1066
1067         .offsets                = &qmp_ufs_offsets,
1068         .max_supported_gear     = UFS_HS_G4,
1069
1070         .tbls = {
1071                 .serdes         = sm8150_ufsphy_serdes,
1072                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_serdes),
1073                 .tx             = sc7280_ufsphy_tx,
1074                 .tx_num         = ARRAY_SIZE(sc7280_ufsphy_tx),
1075                 .rx             = sc7280_ufsphy_rx,
1076                 .rx_num         = ARRAY_SIZE(sc7280_ufsphy_rx),
1077                 .pcs            = sc7280_ufsphy_pcs,
1078                 .pcs_num        = ARRAY_SIZE(sc7280_ufsphy_pcs),
1079         },
1080         .tbls_hs_b = {
1081                 .serdes         = sm8150_ufsphy_hs_b_serdes,
1082                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1083         },
1084         .tbls_hs_overlay[0] = {
1085                 .tx             = sm8250_ufsphy_hs_g4_tx,
1086                 .tx_num         = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
1087                 .rx             = sc7280_ufsphy_hs_g4_rx,
1088                 .rx_num         = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
1089                 .pcs            = sm8150_ufsphy_hs_g4_pcs,
1090                 .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1091                 .max_gear       = UFS_HS_G4,
1092         },
1093         .vreg_list              = qmp_phy_vreg_l,
1094         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1095         .regs                   = ufsphy_v4_regs_layout,
1096 };
1097
1098 static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
1099         .lanes                  = 2,
1100
1101         .offsets                = &qmp_ufs_offsets,
1102         .max_supported_gear     = UFS_HS_G4,
1103
1104         .tbls = {
1105                 .serdes         = sm8350_ufsphy_serdes,
1106                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_serdes),
1107                 .tx             = sm8350_ufsphy_tx,
1108                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_tx),
1109                 .rx             = sm8350_ufsphy_rx,
1110                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_rx),
1111                 .pcs            = sm8350_ufsphy_pcs,
1112                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_pcs),
1113         },
1114         .tbls_hs_b = {
1115                 .serdes         = sm8350_ufsphy_hs_b_serdes,
1116                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1117         },
1118         .tbls_hs_overlay[0] = {
1119                 .tx             = sm8350_ufsphy_g4_tx,
1120                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1121                 .rx             = sm8350_ufsphy_g4_rx,
1122                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1123                 .pcs            = sm8350_ufsphy_g4_pcs,
1124                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1125                 .max_gear       = UFS_HS_G4,
1126         },
1127         .vreg_list              = qmp_phy_vreg_l,
1128         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1129         .regs                   = ufsphy_v5_regs_layout,
1130 };
1131
1132 static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
1133         .lanes                  = 2,
1134
1135         .offsets                = &qmp_ufs_offsets,
1136         .max_supported_gear     = UFS_HS_G3,
1137
1138         .tbls = {
1139                 .serdes         = sdm845_ufsphy_serdes,
1140                 .serdes_num     = ARRAY_SIZE(sdm845_ufsphy_serdes),
1141                 .tx             = sdm845_ufsphy_tx,
1142                 .tx_num         = ARRAY_SIZE(sdm845_ufsphy_tx),
1143                 .rx             = sdm845_ufsphy_rx,
1144                 .rx_num         = ARRAY_SIZE(sdm845_ufsphy_rx),
1145                 .pcs            = sdm845_ufsphy_pcs,
1146                 .pcs_num        = ARRAY_SIZE(sdm845_ufsphy_pcs),
1147         },
1148         .tbls_hs_b = {
1149                 .serdes         = sdm845_ufsphy_hs_b_serdes,
1150                 .serdes_num     = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
1151         },
1152         .vreg_list              = qmp_phy_vreg_l,
1153         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1154         .regs                   = ufsphy_v3_regs_layout,
1155
1156         .no_pcs_sw_reset        = true,
1157 };
1158
1159 static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
1160         .lanes                  = 1,
1161
1162         .offsets                = &qmp_ufs_offsets,
1163         .max_supported_gear     = UFS_HS_G3,
1164
1165         .tbls = {
1166                 .serdes         = sm6115_ufsphy_serdes,
1167                 .serdes_num     = ARRAY_SIZE(sm6115_ufsphy_serdes),
1168                 .tx             = sm6115_ufsphy_tx,
1169                 .tx_num         = ARRAY_SIZE(sm6115_ufsphy_tx),
1170                 .rx             = sm6115_ufsphy_rx,
1171                 .rx_num         = ARRAY_SIZE(sm6115_ufsphy_rx),
1172                 .pcs            = sm6115_ufsphy_pcs,
1173                 .pcs_num        = ARRAY_SIZE(sm6115_ufsphy_pcs),
1174         },
1175         .tbls_hs_b = {
1176                 .serdes         = sm6115_ufsphy_hs_b_serdes,
1177                 .serdes_num     = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes),
1178         },
1179         .vreg_list              = qmp_phy_vreg_l,
1180         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1181         .regs                   = ufsphy_v2_regs_layout,
1182
1183         .no_pcs_sw_reset        = true,
1184 };
1185
1186 static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {
1187         .lanes                  = 1,
1188
1189         .offsets                = &qmp_ufs_offsets,
1190         .max_supported_gear     = UFS_HS_G3,
1191
1192         .tbls = {
1193                 .serdes         = sdm845_ufsphy_serdes,
1194                 .serdes_num     = ARRAY_SIZE(sdm845_ufsphy_serdes),
1195                 .tx             = sdm845_ufsphy_tx,
1196                 .tx_num         = ARRAY_SIZE(sdm845_ufsphy_tx),
1197                 .rx             = sm7150_ufsphy_rx,
1198                 .rx_num         = ARRAY_SIZE(sm7150_ufsphy_rx),
1199                 .pcs            = sm7150_ufsphy_pcs,
1200                 .pcs_num        = ARRAY_SIZE(sm7150_ufsphy_pcs),
1201         },
1202         .tbls_hs_b = {
1203                 .serdes         = sdm845_ufsphy_hs_b_serdes,
1204                 .serdes_num     = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes),
1205         },
1206         .vreg_list              = qmp_phy_vreg_l,
1207         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1208         .regs                   = ufsphy_v3_regs_layout,
1209
1210         .no_pcs_sw_reset        = true,
1211 };
1212
1213 static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
1214         .lanes                  = 2,
1215
1216         .offsets                = &qmp_ufs_offsets,
1217         .max_supported_gear     = UFS_HS_G4,
1218
1219         .tbls = {
1220                 .serdes         = sm8150_ufsphy_serdes,
1221                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_serdes),
1222                 .tx             = sm8150_ufsphy_tx,
1223                 .tx_num         = ARRAY_SIZE(sm8150_ufsphy_tx),
1224                 .rx             = sm8150_ufsphy_rx,
1225                 .rx_num         = ARRAY_SIZE(sm8150_ufsphy_rx),
1226                 .pcs            = sm8150_ufsphy_pcs,
1227                 .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_pcs),
1228         },
1229         .tbls_hs_b = {
1230                 .serdes         = sm8150_ufsphy_hs_b_serdes,
1231                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1232         },
1233         .tbls_hs_overlay[0] = {
1234                 .tx             = sm8150_ufsphy_hs_g4_tx,
1235                 .tx_num         = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
1236                 .rx             = sm8150_ufsphy_hs_g4_rx,
1237                 .rx_num         = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
1238                 .pcs            = sm8150_ufsphy_hs_g4_pcs,
1239                 .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1240                 .max_gear       = UFS_HS_G4,
1241         },
1242         .vreg_list              = qmp_phy_vreg_l,
1243         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1244         .regs                   = ufsphy_v4_regs_layout,
1245 };
1246
1247 static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
1248         .lanes                  = 2,
1249
1250         .offsets                = &qmp_ufs_offsets,
1251         .max_supported_gear     = UFS_HS_G4,
1252
1253         .tbls = {
1254                 .serdes         = sm8150_ufsphy_serdes,
1255                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_serdes),
1256                 .tx             = sm8150_ufsphy_tx,
1257                 .tx_num         = ARRAY_SIZE(sm8150_ufsphy_tx),
1258                 .rx             = sm8150_ufsphy_rx,
1259                 .rx_num         = ARRAY_SIZE(sm8150_ufsphy_rx),
1260                 .pcs            = sm8150_ufsphy_pcs,
1261                 .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_pcs),
1262         },
1263         .tbls_hs_b = {
1264                 .serdes         = sm8150_ufsphy_hs_b_serdes,
1265                 .serdes_num     = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
1266         },
1267         .tbls_hs_overlay[0] = {
1268                 .tx             = sm8250_ufsphy_hs_g4_tx,
1269                 .tx_num         = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
1270                 .rx             = sm8250_ufsphy_hs_g4_rx,
1271                 .rx_num         = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
1272                 .pcs            = sm8150_ufsphy_hs_g4_pcs,
1273                 .pcs_num        = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
1274                 .max_gear       = UFS_HS_G4,
1275         },
1276         .vreg_list              = qmp_phy_vreg_l,
1277         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1278         .regs                   = ufsphy_v4_regs_layout,
1279 };
1280
1281 static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
1282         .lanes                  = 2,
1283
1284         .offsets                = &qmp_ufs_offsets,
1285         .max_supported_gear     = UFS_HS_G4,
1286
1287         .tbls = {
1288                 .serdes         = sm8350_ufsphy_serdes,
1289                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_serdes),
1290                 .tx             = sm8350_ufsphy_tx,
1291                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_tx),
1292                 .rx             = sm8350_ufsphy_rx,
1293                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_rx),
1294                 .pcs            = sm8350_ufsphy_pcs,
1295                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_pcs),
1296         },
1297         .tbls_hs_b = {
1298                 .serdes         = sm8350_ufsphy_hs_b_serdes,
1299                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1300         },
1301         .tbls_hs_overlay[0] = {
1302                 .tx             = sm8350_ufsphy_g4_tx,
1303                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1304                 .rx             = sm8350_ufsphy_g4_rx,
1305                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1306                 .pcs            = sm8350_ufsphy_g4_pcs,
1307                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1308                 .max_gear       = UFS_HS_G4,
1309         },
1310         .vreg_list              = qmp_phy_vreg_l,
1311         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1312         .regs                   = ufsphy_v5_regs_layout,
1313 };
1314
1315 static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
1316         .lanes                  = 2,
1317
1318         .offsets                = &qmp_ufs_offsets,
1319         .max_supported_gear     = UFS_HS_G4,
1320
1321         .tbls = {
1322                 .serdes         = sm8350_ufsphy_serdes,
1323                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_serdes),
1324                 .tx             = sm8350_ufsphy_tx,
1325                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_tx),
1326                 .rx             = sm8350_ufsphy_rx,
1327                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_rx),
1328                 .pcs            = sm8350_ufsphy_pcs,
1329                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_pcs),
1330         },
1331         .tbls_hs_b = {
1332                 .serdes         = sm8350_ufsphy_hs_b_serdes,
1333                 .serdes_num     = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
1334         },
1335         .tbls_hs_overlay[0] = {
1336                 .tx             = sm8350_ufsphy_g4_tx,
1337                 .tx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
1338                 .rx             = sm8350_ufsphy_g4_rx,
1339                 .rx_num         = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
1340                 .pcs            = sm8350_ufsphy_g4_pcs,
1341                 .pcs_num        = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
1342                 .max_gear       = UFS_HS_G4,
1343         },
1344         .vreg_list              = qmp_phy_vreg_l,
1345         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1346         .regs                   = ufsphy_v5_regs_layout,
1347 };
1348
1349 static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
1350         .lanes                  = 2,
1351
1352         .offsets                = &qmp_ufs_offsets_v6,
1353         .max_supported_gear     = UFS_HS_G5,
1354
1355         .tbls = {
1356                 .serdes         = sm8550_ufsphy_serdes,
1357                 .serdes_num     = ARRAY_SIZE(sm8550_ufsphy_serdes),
1358                 .tx             = sm8550_ufsphy_tx,
1359                 .tx_num         = ARRAY_SIZE(sm8550_ufsphy_tx),
1360                 .rx             = sm8550_ufsphy_rx,
1361                 .rx_num         = ARRAY_SIZE(sm8550_ufsphy_rx),
1362                 .pcs            = sm8550_ufsphy_pcs,
1363                 .pcs_num        = ARRAY_SIZE(sm8550_ufsphy_pcs),
1364         },
1365         .tbls_hs_b = {
1366                 .serdes         = sm8550_ufsphy_hs_b_serdes,
1367                 .serdes_num     = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
1368         },
1369         .tbls_hs_overlay[0] = {
1370                 .serdes         = sm8550_ufsphy_g4_serdes,
1371                 .serdes_num     = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
1372                 .tx             = sm8550_ufsphy_g4_tx,
1373                 .tx_num         = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
1374                 .rx             = sm8550_ufsphy_g4_rx,
1375                 .rx_num         = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
1376                 .pcs            = sm8550_ufsphy_g4_pcs,
1377                 .pcs_num        = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
1378                 .max_gear       = UFS_HS_G4,
1379         },
1380         .tbls_hs_overlay[1] = {
1381                 .serdes         = sm8550_ufsphy_g5_serdes,
1382                 .serdes_num     = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
1383                 .rx             = sm8550_ufsphy_g5_rx,
1384                 .rx_num         = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
1385                 .pcs            = sm8550_ufsphy_g5_pcs,
1386                 .pcs_num        = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
1387                 .max_gear       = UFS_HS_G5,
1388         },
1389         .vreg_list              = qmp_phy_vreg_l,
1390         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1391         .regs                   = ufsphy_v6_regs_layout,
1392 };
1393
1394 static const struct qmp_phy_cfg sm8650_ufsphy_cfg = {
1395         .lanes                  = 2,
1396
1397         .offsets                = &qmp_ufs_offsets_v6,
1398         .max_supported_gear     = UFS_HS_G5,
1399
1400         .tbls = {
1401                 .serdes         = sm8650_ufsphy_serdes,
1402                 .serdes_num     = ARRAY_SIZE(sm8650_ufsphy_serdes),
1403                 .tx             = sm8650_ufsphy_tx,
1404                 .tx_num         = ARRAY_SIZE(sm8650_ufsphy_tx),
1405                 .rx             = sm8650_ufsphy_rx,
1406                 .rx_num         = ARRAY_SIZE(sm8650_ufsphy_rx),
1407                 .pcs            = sm8650_ufsphy_pcs,
1408                 .pcs_num        = ARRAY_SIZE(sm8650_ufsphy_pcs),
1409         },
1410         .vreg_list              = qmp_phy_vreg_l,
1411         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1412         .regs                   = ufsphy_v6_regs_layout,
1413 };
1414
1415 static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1416 {
1417         void __iomem *serdes = qmp->serdes;
1418
1419         qmp_configure(serdes, tbls->serdes, tbls->serdes_num);
1420 }
1421
1422 static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1423 {
1424         const struct qmp_phy_cfg *cfg = qmp->cfg;
1425         void __iomem *tx = qmp->tx;
1426         void __iomem *rx = qmp->rx;
1427
1428         qmp_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
1429         qmp_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
1430
1431         if (cfg->lanes >= 2) {
1432                 qmp_configure_lane(qmp->tx2, tbls->tx, tbls->tx_num, 2);
1433                 qmp_configure_lane(qmp->rx2, tbls->rx, tbls->rx_num, 2);
1434         }
1435 }
1436
1437 static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls)
1438 {
1439         void __iomem *pcs = qmp->pcs;
1440
1441         qmp_configure(pcs, tbls->pcs, tbls->pcs_num);
1442 }
1443
1444 static int qmp_ufs_get_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
1445 {
1446         u32 max_gear, floor_max_gear = cfg->max_supported_gear;
1447         int idx, ret = -EINVAL;
1448
1449         for (idx = NUM_OVERLAY - 1; idx >= 0; idx--) {
1450                 max_gear = cfg->tbls_hs_overlay[idx].max_gear;
1451
1452                 /* Skip if the table is not available */
1453                 if (max_gear == 0)
1454                         continue;
1455
1456                 /* Direct matching, bail */
1457                 if (qmp->submode == max_gear)
1458                         return idx;
1459
1460                 /* If no direct matching, the lowest gear is the best matching */
1461                 if (max_gear < floor_max_gear) {
1462                         ret = idx;
1463                         floor_max_gear = max_gear;
1464                 }
1465         }
1466
1467         return ret;
1468 }
1469
1470 static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
1471 {
1472         int i;
1473
1474         qmp_ufs_serdes_init(qmp, &cfg->tbls);
1475         qmp_ufs_lanes_init(qmp, &cfg->tbls);
1476         qmp_ufs_pcs_init(qmp, &cfg->tbls);
1477
1478         i = qmp_ufs_get_gear_overlay(qmp, cfg);
1479         if (i >= 0) {
1480                 qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_overlay[i]);
1481                 qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_overlay[i]);
1482                 qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
1483         }
1484
1485         if (qmp->mode == PHY_MODE_UFS_HS_B)
1486                 qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
1487 }
1488
1489 static int qmp_ufs_com_init(struct qmp_ufs *qmp)
1490 {
1491         const struct qmp_phy_cfg *cfg = qmp->cfg;
1492         void __iomem *pcs = qmp->pcs;
1493         int ret;
1494
1495         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1496         if (ret) {
1497                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1498                 return ret;
1499         }
1500
1501         ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
1502         if (ret)
1503                 goto err_disable_regulators;
1504
1505         qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
1506
1507         return 0;
1508
1509 err_disable_regulators:
1510         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1511
1512         return ret;
1513 }
1514
1515 static int qmp_ufs_com_exit(struct qmp_ufs *qmp)
1516 {
1517         const struct qmp_phy_cfg *cfg = qmp->cfg;
1518
1519         reset_control_assert(qmp->ufs_reset);
1520
1521         clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1522
1523         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1524
1525         return 0;
1526 }
1527
1528 static int qmp_ufs_init(struct phy *phy)
1529 {
1530         struct qmp_ufs *qmp = phy_get_drvdata(phy);
1531         const struct qmp_phy_cfg *cfg = qmp->cfg;
1532         int ret;
1533         dev_vdbg(qmp->dev, "Initializing QMP phy\n");
1534
1535         if (cfg->no_pcs_sw_reset) {
1536                 /*
1537                  * Get UFS reset, which is delayed until now to avoid a
1538                  * circular dependency where UFS needs its PHY, but the PHY
1539                  * needs this UFS reset.
1540                  */
1541                 if (!qmp->ufs_reset) {
1542                         qmp->ufs_reset =
1543                                 devm_reset_control_get_exclusive(qmp->dev,
1544                                                                  "ufsphy");
1545
1546                         if (IS_ERR(qmp->ufs_reset)) {
1547                                 ret = PTR_ERR(qmp->ufs_reset);
1548                                 dev_err(qmp->dev,
1549                                         "failed to get UFS reset: %d\n",
1550                                         ret);
1551
1552                                 qmp->ufs_reset = NULL;
1553                                 return ret;
1554                         }
1555                 }
1556
1557                 ret = reset_control_assert(qmp->ufs_reset);
1558                 if (ret)
1559                         return ret;
1560         }
1561
1562         ret = qmp_ufs_com_init(qmp);
1563         if (ret)
1564                 return ret;
1565
1566         return 0;
1567 }
1568
1569 static int qmp_ufs_power_on(struct phy *phy)
1570 {
1571         struct qmp_ufs *qmp = phy_get_drvdata(phy);
1572         const struct qmp_phy_cfg *cfg = qmp->cfg;
1573         void __iomem *pcs = qmp->pcs;
1574         void __iomem *status;
1575         unsigned int val;
1576         int ret;
1577
1578         qmp_ufs_init_registers(qmp, cfg);
1579
1580         ret = reset_control_deassert(qmp->ufs_reset);
1581         if (ret)
1582                 return ret;
1583
1584         /* Pull PHY out of reset state */
1585         if (!cfg->no_pcs_sw_reset)
1586                 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1587
1588         /* start SerDes */
1589         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START);
1590
1591         status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
1592         ret = readl_poll_timeout(status, val, (val & PCS_READY), 200,
1593                                  PHY_INIT_COMPLETE_TIMEOUT);
1594         if (ret) {
1595                 dev_err(qmp->dev, "phy initialization timed-out\n");
1596                 return ret;
1597         }
1598
1599         return 0;
1600 }
1601
1602 static int qmp_ufs_power_off(struct phy *phy)
1603 {
1604         struct qmp_ufs *qmp = phy_get_drvdata(phy);
1605         const struct qmp_phy_cfg *cfg = qmp->cfg;
1606
1607         /* PHY reset */
1608         if (!cfg->no_pcs_sw_reset)
1609                 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1610
1611         /* stop SerDes */
1612         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], SERDES_START);
1613
1614         /* Put PHY into POWER DOWN state: active low */
1615         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
1616                         SW_PWRDN);
1617
1618         return 0;
1619 }
1620
1621 static int qmp_ufs_exit(struct phy *phy)
1622 {
1623         struct qmp_ufs *qmp = phy_get_drvdata(phy);
1624
1625         qmp_ufs_com_exit(qmp);
1626
1627         return 0;
1628 }
1629
1630 static int qmp_ufs_enable(struct phy *phy)
1631 {
1632         int ret;
1633
1634         ret = qmp_ufs_init(phy);
1635         if (ret)
1636                 return ret;
1637
1638         ret = qmp_ufs_power_on(phy);
1639         if (ret)
1640                 qmp_ufs_exit(phy);
1641
1642         return ret;
1643 }
1644
1645 static int qmp_ufs_disable(struct phy *phy)
1646 {
1647         int ret;
1648
1649         ret = qmp_ufs_power_off(phy);
1650         if (ret)
1651                 return ret;
1652         return qmp_ufs_exit(phy);
1653 }
1654
1655 static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
1656 {
1657         struct qmp_ufs *qmp = phy_get_drvdata(phy);
1658         const struct qmp_phy_cfg *cfg = qmp->cfg;
1659
1660         if (submode > cfg->max_supported_gear || submode == 0) {
1661                 dev_err(qmp->dev, "Invalid PHY submode %d\n", submode);
1662                 return -EINVAL;
1663         }
1664
1665         qmp->mode = mode;
1666         qmp->submode = submode;
1667
1668         return 0;
1669 }
1670
1671 static const struct phy_ops qcom_qmp_ufs_phy_ops = {
1672         .power_on       = qmp_ufs_enable,
1673         .power_off      = qmp_ufs_disable,
1674         .set_mode       = qmp_ufs_set_mode,
1675         .owner          = THIS_MODULE,
1676 };
1677
1678 static int qmp_ufs_vreg_init(struct qmp_ufs *qmp)
1679 {
1680         const struct qmp_phy_cfg *cfg = qmp->cfg;
1681         struct device *dev = qmp->dev;
1682         int num = cfg->num_vregs;
1683         int i;
1684
1685         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
1686         if (!qmp->vregs)
1687                 return -ENOMEM;
1688
1689         for (i = 0; i < num; i++)
1690                 qmp->vregs[i].supply = cfg->vreg_list[i];
1691
1692         return devm_regulator_bulk_get(dev, num, qmp->vregs);
1693 }
1694
1695 static int qmp_ufs_clk_init(struct qmp_ufs *qmp)
1696 {
1697         struct device *dev = qmp->dev;
1698
1699         qmp->num_clks = devm_clk_bulk_get_all(dev, &qmp->clks);
1700         if (qmp->num_clks < 0)
1701                 return qmp->num_clks;
1702
1703         return 0;
1704 }
1705
1706 static void qmp_ufs_clk_release_provider(void *res)
1707 {
1708         of_clk_del_provider(res);
1709 }
1710
1711 #define UFS_SYMBOL_CLOCKS 3
1712
1713 static int qmp_ufs_register_clocks(struct qmp_ufs *qmp, struct device_node *np)
1714 {
1715         struct clk_hw_onecell_data *clk_data;
1716         struct clk_hw *hw;
1717         char name[64];
1718         int ret;
1719
1720         clk_data = devm_kzalloc(qmp->dev,
1721                                 struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS),
1722                                 GFP_KERNEL);
1723         if (!clk_data)
1724                 return -ENOMEM;
1725
1726         clk_data->num = UFS_SYMBOL_CLOCKS;
1727
1728         snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev));
1729         hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1730         if (IS_ERR(hw))
1731                 return PTR_ERR(hw);
1732
1733         clk_data->hws[0] = hw;
1734
1735         snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev));
1736         hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1737         if (IS_ERR(hw))
1738                 return PTR_ERR(hw);
1739
1740         clk_data->hws[1] = hw;
1741
1742         snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev));
1743         hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
1744         if (IS_ERR(hw))
1745                 return PTR_ERR(hw);
1746
1747         clk_data->hws[2] = hw;
1748
1749         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
1750         if (ret)
1751                 return ret;
1752
1753         /*
1754          * Roll a devm action because the clock provider can be a child node.
1755          */
1756         return devm_add_action_or_reset(qmp->dev, qmp_ufs_clk_release_provider, np);
1757 }
1758
1759 static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np)
1760 {
1761         struct platform_device *pdev = to_platform_device(qmp->dev);
1762         const struct qmp_phy_cfg *cfg = qmp->cfg;
1763         struct device *dev = qmp->dev;
1764
1765         qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
1766         if (IS_ERR(qmp->serdes))
1767                 return PTR_ERR(qmp->serdes);
1768
1769         /*
1770          * Get memory resources for the PHY:
1771          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
1772          * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
1773          * For single lane PHYs: pcs_misc (optional) -> 3.
1774          */
1775         qmp->tx = devm_of_iomap(dev, np, 0, NULL);
1776         if (IS_ERR(qmp->tx))
1777                 return PTR_ERR(qmp->tx);
1778
1779         qmp->rx = devm_of_iomap(dev, np, 1, NULL);
1780         if (IS_ERR(qmp->rx))
1781                 return PTR_ERR(qmp->rx);
1782
1783         qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
1784         if (IS_ERR(qmp->pcs))
1785                 return PTR_ERR(qmp->pcs);
1786
1787         if (cfg->lanes >= 2) {
1788                 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
1789                 if (IS_ERR(qmp->tx2))
1790                         return PTR_ERR(qmp->tx2);
1791
1792                 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
1793                 if (IS_ERR(qmp->rx2))
1794                         return PTR_ERR(qmp->rx2);
1795
1796                 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
1797         } else {
1798                 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
1799         }
1800
1801         if (IS_ERR(qmp->pcs_misc))
1802                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
1803
1804         return 0;
1805 }
1806
1807 static int qmp_ufs_parse_dt(struct qmp_ufs *qmp)
1808 {
1809         struct platform_device *pdev = to_platform_device(qmp->dev);
1810         const struct qmp_phy_cfg *cfg = qmp->cfg;
1811         const struct qmp_ufs_offsets *offs = cfg->offsets;
1812         void __iomem *base;
1813
1814         if (!offs)
1815                 return -EINVAL;
1816
1817         base = devm_platform_ioremap_resource(pdev, 0);
1818         if (IS_ERR(base))
1819                 return PTR_ERR(base);
1820
1821         qmp->serdes = base + offs->serdes;
1822         qmp->pcs = base + offs->pcs;
1823         qmp->tx = base + offs->tx;
1824         qmp->rx = base + offs->rx;
1825
1826         if (cfg->lanes >= 2) {
1827                 qmp->tx2 = base + offs->tx2;
1828                 qmp->rx2 = base + offs->rx2;
1829         }
1830
1831         return 0;
1832 }
1833
1834 static int qmp_ufs_probe(struct platform_device *pdev)
1835 {
1836         struct device *dev = &pdev->dev;
1837         struct phy_provider *phy_provider;
1838         struct device_node *np;
1839         struct qmp_ufs *qmp;
1840         int ret;
1841
1842         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
1843         if (!qmp)
1844                 return -ENOMEM;
1845
1846         qmp->dev = dev;
1847
1848         qmp->cfg = of_device_get_match_data(dev);
1849         if (!qmp->cfg)
1850                 return -EINVAL;
1851
1852         ret = qmp_ufs_clk_init(qmp);
1853         if (ret)
1854                 return ret;
1855
1856         ret = qmp_ufs_vreg_init(qmp);
1857         if (ret)
1858                 return ret;
1859
1860         /* Check for legacy binding with child node. */
1861         np = of_get_next_available_child(dev->of_node, NULL);
1862         if (np) {
1863                 ret = qmp_ufs_parse_dt_legacy(qmp, np);
1864         } else {
1865                 np = of_node_get(dev->of_node);
1866                 ret = qmp_ufs_parse_dt(qmp);
1867         }
1868         if (ret)
1869                 goto err_node_put;
1870
1871         ret = qmp_ufs_register_clocks(qmp, np);
1872         if (ret)
1873                 goto err_node_put;
1874
1875         qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops);
1876         if (IS_ERR(qmp->phy)) {
1877                 ret = PTR_ERR(qmp->phy);
1878                 dev_err(dev, "failed to create PHY: %d\n", ret);
1879                 goto err_node_put;
1880         }
1881
1882         phy_set_drvdata(qmp->phy, qmp);
1883
1884         of_node_put(np);
1885
1886         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1887
1888         return PTR_ERR_OR_ZERO(phy_provider);
1889
1890 err_node_put:
1891         of_node_put(np);
1892         return ret;
1893 }
1894
1895 static const struct of_device_id qmp_ufs_of_match_table[] = {
1896         {
1897                 .compatible = "qcom,msm8996-qmp-ufs-phy",
1898                 .data = &msm8996_ufsphy_cfg,
1899         }, {
1900                 .compatible = "qcom,msm8998-qmp-ufs-phy",
1901                 .data = &sdm845_ufsphy_cfg,
1902         }, {
1903                 .compatible = "qcom,sa8775p-qmp-ufs-phy",
1904                 .data = &sa8775p_ufsphy_cfg,
1905         }, {
1906                 .compatible = "qcom,sc7180-qmp-ufs-phy",
1907                 .data = &sm7150_ufsphy_cfg,
1908         }, {
1909                 .compatible = "qcom,sc7280-qmp-ufs-phy",
1910                 .data = &sc7280_ufsphy_cfg,
1911         }, {
1912                 .compatible = "qcom,sc8180x-qmp-ufs-phy",
1913                 .data = &sm8150_ufsphy_cfg,
1914         }, {
1915                 .compatible = "qcom,sc8280xp-qmp-ufs-phy",
1916                 .data = &sc8280xp_ufsphy_cfg,
1917         }, {
1918                 .compatible = "qcom,sdm845-qmp-ufs-phy",
1919                 .data = &sdm845_ufsphy_cfg,
1920         }, {
1921                 .compatible = "qcom,sm6115-qmp-ufs-phy",
1922                 .data = &sm6115_ufsphy_cfg,
1923         }, {
1924                 .compatible = "qcom,sm6125-qmp-ufs-phy",
1925                 .data = &sm6115_ufsphy_cfg,
1926         }, {
1927                 .compatible = "qcom,sm6350-qmp-ufs-phy",
1928                 .data = &sdm845_ufsphy_cfg,
1929         }, {
1930                 .compatible = "qcom,sm7150-qmp-ufs-phy",
1931                 .data = &sm7150_ufsphy_cfg,
1932         }, {
1933                 .compatible = "qcom,sm8150-qmp-ufs-phy",
1934                 .data = &sm8150_ufsphy_cfg,
1935         }, {
1936                 .compatible = "qcom,sm8250-qmp-ufs-phy",
1937                 .data = &sm8250_ufsphy_cfg,
1938         }, {
1939                 .compatible = "qcom,sm8350-qmp-ufs-phy",
1940                 .data = &sm8350_ufsphy_cfg,
1941         }, {
1942                 .compatible = "qcom,sm8450-qmp-ufs-phy",
1943                 .data = &sm8450_ufsphy_cfg,
1944         }, {
1945                 .compatible = "qcom,sm8550-qmp-ufs-phy",
1946                 .data = &sm8550_ufsphy_cfg,
1947         }, {
1948                 .compatible = "qcom,sm8650-qmp-ufs-phy",
1949                 .data = &sm8650_ufsphy_cfg,
1950         },
1951         { },
1952 };
1953 MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table);
1954
1955 static struct platform_driver qmp_ufs_driver = {
1956         .probe          = qmp_ufs_probe,
1957         .driver = {
1958                 .name   = "qcom-qmp-ufs-phy",
1959                 .of_match_table = qmp_ufs_of_match_table,
1960         },
1961 };
1962
1963 module_platform_driver(qmp_ufs_driver);
1964
1965 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
1966 MODULE_DESCRIPTION("Qualcomm QMP UFS PHY driver");
1967 MODULE_LICENSE("GPL v2");