drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #ifndef QCOM_PHY_QMP_QSERDES_TXRX_H_
   7 #define QCOM_PHY_QMP_QSERDES_TXRX_H_
   8
   9 /* Only for QMP V2 PHY - TX registers */
  10 #define QSERDES_TX_BIST_MODE_LANENO                     0x000
  11 #define QSERDES_TX_BIST_INVERT                          0x004
  12 #define QSERDES_TX_CLKBUF_ENABLE                        0x008
  13 #define QSERDES_TX_CMN_CONTROL_ONE                      0x00c
  14 #define QSERDES_TX_CMN_CONTROL_TWO                      0x010
  15 #define QSERDES_TX_CMN_CONTROL_THREE                    0x014
  16 #define QSERDES_TX_TX_EMP_POST1_LVL                     0x018
  17 #define QSERDES_TX_TX_POST2_EMPH                        0x01c
  18 #define QSERDES_TX_TX_BOOST_LVL_UP_DN                   0x020
  19 #define QSERDES_TX_HP_PD_ENABLES                        0x024
  20 #define QSERDES_TX_TX_IDLE_LVL_LARGE_AMP                0x028
  21 #define QSERDES_TX_TX_DRV_LVL                           0x02c
  22 #define QSERDES_TX_TX_DRV_LVL_OFFSET                    0x030
  23 #define QSERDES_TX_RESET_TSYNC_EN                       0x034
  24 #define QSERDES_TX_PRE_STALL_LDO_BOOST_EN               0x038
  25 #define QSERDES_TX_TX_BAND                              0x03c
  26 #define QSERDES_TX_SLEW_CNTL                            0x040
  27 #define QSERDES_TX_INTERFACE_SELECT                     0x044
  28 #define QSERDES_TX_LPB_EN                               0x048
  29 #define QSERDES_TX_RES_CODE_LANE_TX                     0x04c
  30 #define QSERDES_TX_RES_CODE_LANE_RX                     0x050
  31 #define QSERDES_TX_RES_CODE_LANE_OFFSET                 0x054
  32 #define QSERDES_TX_PERL_LENGTH1                         0x058
  33 #define QSERDES_TX_PERL_LENGTH2                         0x05c
  34 #define QSERDES_TX_SERDES_BYP_EN_OUT                    0x060
  35 #define QSERDES_TX_DEBUG_BUS_SEL                        0x064
  36 #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN     0x068
  37 #define QSERDES_TX_TX_POL_INV                           0x06c
  38 #define QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN           0x070
  39 #define QSERDES_TX_BIST_PATTERN1                        0x074
  40 #define QSERDES_TX_BIST_PATTERN2                        0x078
  41 #define QSERDES_TX_BIST_PATTERN3                        0x07c
  42 #define QSERDES_TX_BIST_PATTERN4                        0x080
  43 #define QSERDES_TX_BIST_PATTERN5                        0x084
  44 #define QSERDES_TX_BIST_PATTERN6                        0x088
  45 #define QSERDES_TX_BIST_PATTERN7                        0x08c
  46 #define QSERDES_TX_BIST_PATTERN8                        0x090
  47 #define QSERDES_TX_LANE_MODE                            0x094
  48 #define QSERDES_TX_IDAC_CAL_LANE_MODE                   0x098
  49 #define QSERDES_TX_IDAC_CAL_LANE_MODE_CONFIGURATION     0x09c
  50 #define QSERDES_TX_ATB_SEL1                             0x0a0
  51 #define QSERDES_TX_ATB_SEL2                             0x0a4
  52 #define QSERDES_TX_RCV_DETECT_LVL                       0x0a8
  53 #define QSERDES_TX_RCV_DETECT_LVL_2                     0x0ac
  54 #define QSERDES_TX_PRBS_SEED1                           0x0b0
  55 #define QSERDES_TX_PRBS_SEED2                           0x0b4
  56 #define QSERDES_TX_PRBS_SEED3                           0x0b8
  57 #define QSERDES_TX_PRBS_SEED4                           0x0bc
  58 #define QSERDES_TX_RESET_GEN                            0x0c0
  59 #define QSERDES_TX_RESET_GEN_MUXES                      0x0c4
  60 #define QSERDES_TX_TRAN_DRVR_EMP_EN                     0x0c8
  61 #define QSERDES_TX_TX_INTERFACE_MODE                    0x0cc
  62 #define QSERDES_TX_PWM_CTRL                             0x0d0
  63 #define QSERDES_TX_PWM_ENCODED_OR_DATA                  0x0d4
  64 #define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND2             0x0d8
  65 #define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND2             0x0dc
  66 #define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND2             0x0e0
  67 #define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND2             0x0e4
  68 #define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND0_1           0x0e8
  69 #define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND0_1           0x0ec
  70 #define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND0_1           0x0f0
  71 #define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND0_1           0x0f4
  72 #define QSERDES_TX_VMODE_CTRL1                          0x0f8
  73 #define QSERDES_TX_VMODE_CTRL2                          0x0fc
  74 #define QSERDES_TX_TX_ALOG_INTF_OBSV_CNTL               0x100
  75 #define QSERDES_TX_BIST_STATUS                          0x104
  76 #define QSERDES_TX_BIST_ERROR_COUNT1                    0x108
  77 #define QSERDES_TX_BIST_ERROR_COUNT2                    0x10c
  78 #define QSERDES_TX_TX_ALOG_INTF_OBSV                    0x110
  79
  80 /* Only for QMP V2 PHY - RX registers */
  81 #define QSERDES_RX_UCDR_FO_GAIN_HALF                    0x000
  82 #define QSERDES_RX_UCDR_FO_GAIN_QUARTER                 0x004
  83 #define QSERDES_RX_UCDR_FO_GAIN_EIGHTH                  0x008
  84 #define QSERDES_RX_UCDR_FO_GAIN                         0x00c
  85 #define QSERDES_RX_UCDR_SO_GAIN_HALF                    0x010
  86 #define QSERDES_RX_UCDR_SO_GAIN_QUARTER                 0x014
  87 #define QSERDES_RX_UCDR_SO_GAIN_EIGHTH                  0x018
  88 #define QSERDES_RX_UCDR_SO_GAIN                         0x01c
  89 #define QSERDES_RX_UCDR_SVS_FO_GAIN_HALF                0x020
  90 #define QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER             0x024
  91 #define QSERDES_RX_UCDR_SVS_FO_GAIN_EIGHTH              0x028
  92 #define QSERDES_RX_UCDR_SVS_FO_GAIN                     0x02c
  93 #define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF                0x030
  94 #define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER             0x034
  95 #define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH              0x038
  96 #define QSERDES_RX_UCDR_SVS_SO_GAIN                     0x03c
  97 #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN                0x040
  98 #define QSERDES_RX_UCDR_FD_GAIN                         0x044
  99 #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE        0x048
 100 #define QSERDES_RX_UCDR_FO_TO_SO_DELAY                  0x04c
 101 #define QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW              0x050
 102 #define QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH             0x054
 103 #define QSERDES_RX_UCDR_MODULATE                        0x058
 104 #define QSERDES_RX_UCDR_PI_CONTROLS                     0x05c
 105 #define QSERDES_RX_RBIST_CONTROL                        0x060
 106 #define QSERDES_RX_AUX_CONTROL                          0x064
 107 #define QSERDES_RX_AUX_DATA_TCOARSE                     0x068
 108 #define QSERDES_RX_AUX_DATA_TFINE_LSB                   0x06c
 109 #define QSERDES_RX_AUX_DATA_TFINE_MSB                   0x070
 110 #define QSERDES_RX_RCLK_AUXDATA_SEL                     0x074
 111 #define QSERDES_RX_AC_JTAG_ENABLE                       0x078
 112 #define QSERDES_RX_AC_JTAG_INITP                        0x07c
 113 #define QSERDES_RX_AC_JTAG_INITN                        0x080
 114 #define QSERDES_RX_AC_JTAG_LVL                          0x084
 115 #define QSERDES_RX_AC_JTAG_MODE                         0x088
 116 #define QSERDES_RX_AC_JTAG_RESET                        0x08c
 117 #define QSERDES_RX_RX_TERM_BW                           0x090
 118 #define QSERDES_RX_RX_RCVR_IQ_EN                        0x094
 119 #define QSERDES_RX_RX_IDAC_I_DC_OFFSETS                 0x098
 120 #define QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS              0x09c
 121 #define QSERDES_RX_RX_IDAC_Q_DC_OFFSETS                 0x0a0
 122 #define QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS              0x0a4
 123 #define QSERDES_RX_RX_IDAC_A_DC_OFFSETS                 0x0a8
 124 #define QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS              0x0ac
 125 #define QSERDES_RX_RX_IDAC_EN                           0x0b0
 126 #define QSERDES_RX_RX_IDAC_ENABLES                      0x0b4
 127 #define QSERDES_RX_RX_IDAC_SIGN                         0x0b8
 128 #define QSERDES_RX_RX_HIGHZ_HIGHRATE                    0x0bc
 129 #define QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET   0x0c0
 130 #define QSERDES_RX_RX_EQ_GAIN1_LSB                      0x0c4
 131 #define QSERDES_RX_RX_EQ_GAIN1_MSB                      0x0c8
 132 #define QSERDES_RX_RX_EQ_GAIN2_LSB                      0x0cc
 133 #define QSERDES_RX_RX_EQ_GAIN2_MSB                      0x0d0
 134 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1                0x0d4
 135 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2                0x0d8
 136 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3                0x0dc
 137 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4                0x0e0
 138 #define QSERDES_RX_RX_IDAC_CAL_CONFIGURATION            0x0e4
 139 #define QSERDES_RX_RX_IDAC_TSETTLE_LOW                  0x0e8
 140 #define QSERDES_RX_RX_IDAC_TSETTLE_HIGH                 0x0ec
 141 #define QSERDES_RX_RX_IDAC_ENDSAMP_LOW                  0x0f0
 142 #define QSERDES_RX_RX_IDAC_ENDSAMP_HIGH                 0x0f4
 143 #define QSERDES_RX_RX_IDAC_MIDPOINT_LOW                 0x0f8
 144 #define QSERDES_RX_RX_IDAC_MIDPOINT_HIGH                0x0fc
 145 #define QSERDES_RX_RX_EQ_OFFSET_LSB                     0x100
 146 #define QSERDES_RX_RX_EQ_OFFSET_MSB                     0x104
 147 #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1          0x108
 148 #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2             0x10c
 149 #define QSERDES_RX_SIGDET_ENABLES                       0x110
 150 #define QSERDES_RX_SIGDET_CNTRL                         0x114
 151 #define QSERDES_RX_SIGDET_LVL                           0x118
 152 #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL                0x11c
 153 #define QSERDES_RX_RX_BAND                              0x120
 154 #define QSERDES_RX_CDR_FREEZE_UP_DN                     0x124
 155 #define QSERDES_RX_CDR_RESET_OVERRIDE                   0x128
 156 #define QSERDES_RX_RX_INTERFACE_MODE                    0x12c
 157 #define QSERDES_RX_JITTER_GEN_MODE                      0x130
 158 #define QSERDES_RX_BUJ_AMP                              0x134
 159 #define QSERDES_RX_SJ_AMP1                              0x138
 160 #define QSERDES_RX_SJ_AMP2                              0x13c
 161 #define QSERDES_RX_SJ_PER1                              0x140
 162 #define QSERDES_RX_SJ_PER2                              0x144
 163 #define QSERDES_RX_BUJ_STEP_FREQ1                       0x148
 164 #define QSERDES_RX_BUJ_STEP_FREQ2                       0x14c
 165 #define QSERDES_RX_PPM_OFFSET1                          0x150
 166 #define QSERDES_RX_PPM_OFFSET2                          0x154
 167 #define QSERDES_RX_SIGN_PPM_PERIOD1                     0x158
 168 #define QSERDES_RX_SIGN_PPM_PERIOD2                     0x15c
 169 #define QSERDES_RX_SSC_CTRL                             0x160
 170 #define QSERDES_RX_SSC_COUNT1                           0x164
 171 #define QSERDES_RX_SSC_COUNT2                           0x168
 172 #define QSERDES_RX_RX_ALOG_INTF_OBSV_CNTL               0x16c
 173 #define QSERDES_RX_RX_PWM_ENABLE_AND_DATA               0x170
 174 #define QSERDES_RX_RX_PWM_GEAR1_TIMEOUT_COUNT           0x174
 175 #define QSERDES_RX_RX_PWM_GEAR2_TIMEOUT_COUNT           0x178
 176 #define QSERDES_RX_RX_PWM_GEAR3_TIMEOUT_COUNT           0x17c
 177 #define QSERDES_RX_RX_PWM_GEAR4_TIMEOUT_COUNT           0x180
 178 #define QSERDES_RX_PI_CTRL1                             0x184
 179 #define QSERDES_RX_PI_CTRL2                             0x188
 180 #define QSERDES_RX_PI_QUAD                              0x18c
 181 #define QSERDES_RX_IDATA1                               0x190
 182 #define QSERDES_RX_IDATA2                               0x194
 183 #define QSERDES_RX_AUX_DATA1                            0x198
 184 #define QSERDES_RX_AUX_DATA2                            0x19c
 185 #define QSERDES_RX_AC_JTAG_OUTP                         0x1a0
 186 #define QSERDES_RX_AC_JTAG_OUTN                         0x1a4
 187 #define QSERDES_RX_RX_SIGDET                            0x1a8
 188 #define QSERDES_RX_RX_VDCOFF                            0x1ac
 189 #define QSERDES_RX_IDAC_CAL_ON                          0x1b0
 190 #define QSERDES_RX_IDAC_STATUS_I                        0x1b4
 191 #define QSERDES_RX_IDAC_STATUS_IBAR                     0x1b8
 192 #define QSERDES_RX_IDAC_STATUS_Q                        0x1bc
 193 #define QSERDES_RX_IDAC_STATUS_QBAR                     0x1c0
 194 #define QSERDES_RX_IDAC_STATUS_A                        0x1c4
 195 #define QSERDES_RX_IDAC_STATUS_ABAR                     0x1c8
 196 #define QSERDES_RX_CALST_STATUS_I                       0x1cc
 197 #define QSERDES_RX_CALST_STATUS_Q                       0x1d0
 198 #define QSERDES_RX_CALST_STATUS_A                       0x1d4
 199 #define QSERDES_RX_RX_ALOG_INTF_OBSV                    0x1d8
 200 #define QSERDES_RX_READ_EQCODE                          0x1dc
 201 #define QSERDES_RX_READ_OFFSETCODE                      0x1e0
 202 #define QSERDES_RX_IA_ERROR_COUNTER_LOW                 0x1e4
 203 #define QSERDES_RX_IA_ERROR_COUNTER_HIGH                0x1e8
 204
 205 #endif