drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #ifndef QCOM_PHY_QMP_PCS_V2_H_
   7 #define QCOM_PHY_QMP_PCS_V2_H_
   8
   9 /* Only for QMP V2 PHY - PCS registers */
  10 #define QPHY_V2_PCS_SW_RESET                            0x000
  11 #define QPHY_V2_PCS_POWER_DOWN_CONTROL                  0x004
  12 #define QPHY_V2_PCS_START_CONTROL                       0x008
  13 #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0                    0x024
  14 #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0                  0x028
  15 #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE               0x054
  16 #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL                  0x058
  17 #define QPHY_V2_PCS_POWER_STATE_CONFIG1                 0x060
  18 #define QPHY_V2_PCS_POWER_STATE_CONFIG2                 0x064
  19 #define QPHY_V2_PCS_POWER_STATE_CONFIG4                 0x06c
  20 #define QPHY_V2_PCS_LOCK_DETECT_CONFIG1                 0x080
  21 #define QPHY_V2_PCS_LOCK_DETECT_CONFIG2                 0x084
  22 #define QPHY_V2_PCS_LOCK_DETECT_CONFIG3                 0x088
  23 #define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK         0x0a0
  24 #define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK           0x0a4
  25 #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME               0x0a8
  26 #define QPHY_V2_PCS_FLL_CNTRL1                          0x0c0
  27 #define QPHY_V2_PCS_FLL_CNTRL2                          0x0c4
  28 #define QPHY_V2_PCS_FLL_CNT_VAL_L                       0x0c8
  29 #define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL                   0x0cc
  30 #define QPHY_V2_PCS_FLL_MAN_CODE                        0x0d0
  31 #define QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL                0x0d4
  32 #define QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR               0x0d8
  33 #define QPHY_V2_PCS_LFPS_RXTERM_IRQ_STATUS              0x178
  34 #define QPHY_V2_PCS_USB_PCS_STATUS                      0x17c /* USB */
  35 #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB    0x1a8
  36 #define QPHY_V2_PCS_OSC_DTCT_ACTIONS                    0x1ac
  37 #define QPHY_V2_PCS_RX_SIGDET_LVL                       0x1d8
  38 #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB     0x1dc
  39 #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB     0x1e0
  40
  41 #define QPHY_V2_PCS_PCI_PCS_STATUS                      0x174 /* PCI */
  42
  43 #endif