1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
7 #include <linux/clk-provider.h>
8 #include <linux/delay.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
15 #include <linux/of_address.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/slab.h>
22 #include "phy-qcom-qmp-common.h"
24 #include "phy-qcom-qmp.h"
26 /* QPHY_START_CONTROL bits */
27 #define PLL_READY_GATE_EN BIT(3)
29 /* QPHY_COM_PCS_READY_STATUS bit */
30 #define PCS_READY BIT(0)
32 #define PHY_INIT_COMPLETE_TIMEOUT 10000
33 #define POWER_DOWN_DELAY_US_MIN 10
34 #define POWER_DOWN_DELAY_US_MAX 20
36 /* set of registers with offsets different per-PHY */
37 enum qphy_reg_layout {
38 /* Common block control registers */
40 QPHY_COM_POWER_DOWN_CONTROL,
41 QPHY_COM_START_CONTROL,
42 QPHY_COM_PCS_READY_STATUS,
47 /* Keep last to ensure regs_layout arrays are properly initialized */
51 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
52 [QPHY_COM_SW_RESET] = 0x400,
53 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
54 [QPHY_COM_START_CONTROL] = 0x408,
55 [QPHY_COM_PCS_READY_STATUS] = 0x448,
56 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
57 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
58 [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS,
61 static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
62 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
63 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
64 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
65 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
66 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
67 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
68 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
69 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
70 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
71 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
72 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
73 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
74 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
75 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
76 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
77 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
78 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
79 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
80 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
81 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
82 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
83 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
84 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
85 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
86 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
87 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
88 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
89 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
90 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
91 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
92 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
93 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
94 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
95 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
96 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
97 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
98 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
99 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
100 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
101 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
102 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
103 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
104 QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
107 static const struct qmp_phy_init_tbl msm8996_pcie_tx_tbl[] = {
108 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
109 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
112 static const struct qmp_phy_init_tbl msm8996_pcie_rx_tbl[] = {
113 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
114 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
115 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
116 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
117 QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
118 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
119 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
120 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
121 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
122 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
125 static const struct qmp_phy_init_tbl msm8996_pcie_pcs_tbl[] = {
126 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL, 0x4c),
127 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
128 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
130 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x05),
132 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x05),
133 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_DOWN_CONTROL, 0x02),
134 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG4, 0x00),
135 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG1, 0xa3),
136 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
139 /* struct qmp_phy_cfg - per-PHY initialization config */
141 /* number of PHYs provided by this block */
144 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
145 const struct qmp_phy_init_tbl *serdes_tbl;
147 const struct qmp_phy_init_tbl *tx_tbl;
149 const struct qmp_phy_init_tbl *rx_tbl;
151 const struct qmp_phy_init_tbl *pcs_tbl;
154 /* clock ids to be requested */
155 const char * const *clk_list;
157 /* resets to be requested */
158 const char * const *reset_list;
160 /* regulators to be requested */
161 const char * const *vreg_list;
164 /* array of registers with different offsets */
165 const unsigned int *regs;
169 * struct qmp_phy - per-lane phy descriptor
172 * @cfg: phy specific configuration
173 * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
174 * @tx: iomapped memory space for lane's tx
175 * @rx: iomapped memory space for lane's rx
176 * @pcs: iomapped memory space for lane's pcs
177 * @pipe_clk: pipe clock
179 * @qmp: QMP phy to which this lane belongs
180 * @lane_rst: lane's reset controller
184 const struct qmp_phy_cfg *cfg;
185 void __iomem *serdes;
189 struct clk *pipe_clk;
191 struct qcom_qmp *qmp;
192 struct reset_control *lane_rst;
196 * struct qcom_qmp - structure holding QMP phy block attributes
200 * @clks: array of clocks required by phy
201 * @resets: array of resets required by phy
202 * @vregs: regulator supplies bulk data
204 * @phys: array of per-lane phy descriptors
205 * @phy_mutex: mutex lock for PHY common block initialization
206 * @init_count: phy common block initialization count
211 struct clk_bulk_data *clks;
212 struct reset_control_bulk_data *resets;
213 struct regulator_bulk_data *vregs;
215 struct qmp_phy **phys;
217 struct mutex phy_mutex;
221 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
225 reg = readl(base + offset);
227 writel(reg, base + offset);
229 /* ensure that above write is through */
230 readl(base + offset);
233 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
237 reg = readl(base + offset);
239 writel(reg, base + offset);
241 /* ensure that above write is through */
242 readl(base + offset);
245 /* list of clocks required by phy */
246 static const char * const msm8996_phy_clk_l[] = {
247 "aux", "cfg_ahb", "ref",
251 static const char * const msm8996_pciephy_reset_l[] = {
252 "phy", "common", "cfg",
255 /* list of regulators */
256 static const char * const qmp_phy_vreg_l[] = {
257 "vdda-phy", "vdda-pll",
260 static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
263 .serdes_tbl = msm8996_pcie_serdes_tbl,
264 .serdes_tbl_num = ARRAY_SIZE(msm8996_pcie_serdes_tbl),
265 .tx_tbl = msm8996_pcie_tx_tbl,
266 .tx_tbl_num = ARRAY_SIZE(msm8996_pcie_tx_tbl),
267 .rx_tbl = msm8996_pcie_rx_tbl,
268 .rx_tbl_num = ARRAY_SIZE(msm8996_pcie_rx_tbl),
269 .pcs_tbl = msm8996_pcie_pcs_tbl,
270 .pcs_tbl_num = ARRAY_SIZE(msm8996_pcie_pcs_tbl),
271 .clk_list = msm8996_phy_clk_l,
272 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
273 .reset_list = msm8996_pciephy_reset_l,
274 .num_resets = ARRAY_SIZE(msm8996_pciephy_reset_l),
275 .vreg_list = qmp_phy_vreg_l,
276 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
277 .regs = pciephy_regs_layout,
280 static int qmp_pcie_msm8996_serdes_init(struct qmp_phy *qphy)
282 struct qcom_qmp *qmp = qphy->qmp;
283 const struct qmp_phy_cfg *cfg = qphy->cfg;
284 void __iomem *serdes = qphy->serdes;
285 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
286 int serdes_tbl_num = cfg->serdes_tbl_num;
287 void __iomem *status;
291 qmp_configure(serdes, serdes_tbl, serdes_tbl_num);
293 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET], SW_RESET);
294 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
295 SERDES_START | PCS_START);
297 status = serdes + cfg->regs[QPHY_COM_PCS_READY_STATUS];
298 ret = readl_poll_timeout(status, val, (val & PCS_READY), 200,
299 PHY_INIT_COMPLETE_TIMEOUT);
302 "phy common block init timed-out\n");
309 static int qmp_pcie_msm8996_com_init(struct qmp_phy *qphy)
311 struct qcom_qmp *qmp = qphy->qmp;
312 const struct qmp_phy_cfg *cfg = qphy->cfg;
313 void __iomem *serdes = qphy->serdes;
316 mutex_lock(&qmp->phy_mutex);
317 if (qmp->init_count++) {
318 mutex_unlock(&qmp->phy_mutex);
322 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
324 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
325 goto err_decrement_count;
328 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
330 dev_err(qmp->dev, "reset assert failed\n");
331 goto err_disable_regulators;
334 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
336 dev_err(qmp->dev, "reset deassert failed\n");
337 goto err_disable_regulators;
340 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
342 goto err_assert_reset;
344 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
347 mutex_unlock(&qmp->phy_mutex);
352 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
353 err_disable_regulators:
354 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
357 mutex_unlock(&qmp->phy_mutex);
362 static int qmp_pcie_msm8996_com_exit(struct qmp_phy *qphy)
364 struct qcom_qmp *qmp = qphy->qmp;
365 const struct qmp_phy_cfg *cfg = qphy->cfg;
366 void __iomem *serdes = qphy->serdes;
368 mutex_lock(&qmp->phy_mutex);
369 if (--qmp->init_count) {
370 mutex_unlock(&qmp->phy_mutex);
374 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
375 SERDES_START | PCS_START);
376 qphy_clrbits(serdes, cfg->regs[QPHY_COM_SW_RESET],
378 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
381 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
383 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
385 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
387 mutex_unlock(&qmp->phy_mutex);
392 static int qmp_pcie_msm8996_init(struct phy *phy)
394 struct qmp_phy *qphy = phy_get_drvdata(phy);
395 struct qcom_qmp *qmp = qphy->qmp;
397 dev_vdbg(qmp->dev, "Initializing QMP phy\n");
399 ret = qmp_pcie_msm8996_com_init(qphy);
406 static int qmp_pcie_msm8996_power_on(struct phy *phy)
408 struct qmp_phy *qphy = phy_get_drvdata(phy);
409 struct qcom_qmp *qmp = qphy->qmp;
410 const struct qmp_phy_cfg *cfg = qphy->cfg;
411 void __iomem *tx = qphy->tx;
412 void __iomem *rx = qphy->rx;
413 void __iomem *pcs = qphy->pcs;
414 void __iomem *status;
418 qmp_pcie_msm8996_serdes_init(qphy);
420 ret = reset_control_deassert(qphy->lane_rst);
422 dev_err(qmp->dev, "lane%d reset deassert failed\n",
427 ret = clk_prepare_enable(qphy->pipe_clk);
429 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
433 /* Tx, Rx, and PCS configurations */
434 qmp_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
435 qmp_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
436 qmp_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
439 * Pull out PHY from POWER DOWN state.
440 * This is active low enable signal to power-down PHY.
442 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
443 SW_PWRDN | REFCLK_DRV_DSBL);
445 usleep_range(POWER_DOWN_DELAY_US_MIN, POWER_DOWN_DELAY_US_MAX);
447 /* Pull PHY out of reset state */
448 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
450 /* start SerDes and Phy-Coding-Sublayer */
451 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL],
452 PCS_START | PLL_READY_GATE_EN);
454 status = pcs + cfg->regs[QPHY_PCS_STATUS];
455 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
456 PHY_INIT_COMPLETE_TIMEOUT);
458 dev_err(qmp->dev, "phy initialization timed-out\n");
459 goto err_disable_pipe_clk;
464 err_disable_pipe_clk:
465 clk_disable_unprepare(qphy->pipe_clk);
467 reset_control_assert(qphy->lane_rst);
472 static int qmp_pcie_msm8996_power_off(struct phy *phy)
474 struct qmp_phy *qphy = phy_get_drvdata(phy);
475 const struct qmp_phy_cfg *cfg = qphy->cfg;
477 clk_disable_unprepare(qphy->pipe_clk);
480 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
482 /* stop SerDes and Phy-Coding-Sublayer */
483 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL],
484 SERDES_START | PCS_START);
486 /* Put PHY into POWER DOWN state: active low */
487 qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
488 SW_PWRDN | REFCLK_DRV_DSBL);
493 static int qmp_pcie_msm8996_exit(struct phy *phy)
495 struct qmp_phy *qphy = phy_get_drvdata(phy);
497 reset_control_assert(qphy->lane_rst);
499 qmp_pcie_msm8996_com_exit(qphy);
504 static int qmp_pcie_msm8996_enable(struct phy *phy)
508 ret = qmp_pcie_msm8996_init(phy);
512 ret = qmp_pcie_msm8996_power_on(phy);
514 qmp_pcie_msm8996_exit(phy);
519 static int qmp_pcie_msm8996_disable(struct phy *phy)
523 ret = qmp_pcie_msm8996_power_off(phy);
526 return qmp_pcie_msm8996_exit(phy);
529 static int qmp_pcie_msm8996_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
531 struct qcom_qmp *qmp = dev_get_drvdata(dev);
532 int num = cfg->num_vregs;
535 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
539 for (i = 0; i < num; i++)
540 qmp->vregs[i].supply = cfg->vreg_list[i];
542 return devm_regulator_bulk_get(dev, num, qmp->vregs);
545 static int qmp_pcie_msm8996_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
547 struct qcom_qmp *qmp = dev_get_drvdata(dev);
551 qmp->resets = devm_kcalloc(dev, cfg->num_resets,
552 sizeof(*qmp->resets), GFP_KERNEL);
556 for (i = 0; i < cfg->num_resets; i++)
557 qmp->resets[i].id = cfg->reset_list[i];
559 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
561 return dev_err_probe(dev, ret, "failed to get resets\n");
566 static int qmp_pcie_msm8996_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
568 struct qcom_qmp *qmp = dev_get_drvdata(dev);
569 int num = cfg->num_clks;
572 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
576 for (i = 0; i < num; i++)
577 qmp->clks[i].id = cfg->clk_list[i];
579 return devm_clk_bulk_get(dev, num, qmp->clks);
582 static void phy_clk_release_provider(void *res)
584 of_clk_del_provider(res);
588 * Register a fixed rate pipe clock.
590 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
591 * controls it. The <s>_pipe_clk coming out of the GCC is requested
592 * by the PHY driver for its operations.
593 * We register the <s>_pipe_clksrc here. The gcc driver takes care
594 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
595 * Below picture shows this relationship.
598 * | PHY block |<<---------------------------------------+
600 * | +-------+ | +-----+ |
601 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
602 * clk | +-------+ | +-----+
605 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
607 struct clk_fixed_rate *fixed;
608 struct clk_init_data init = { };
611 ret = of_property_read_string(np, "clock-output-names", &init.name);
613 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
617 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
621 init.ops = &clk_fixed_rate_ops;
623 /* controllers using QMP phys use 125MHz pipe clock interface */
624 fixed->fixed_rate = 125000000;
625 fixed->hw.init = &init;
627 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
631 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
636 * Roll a devm action because the clock provider is the child node, but
637 * the child node is not actually a device.
639 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
642 static const struct phy_ops qmp_pcie_msm8996_ops = {
643 .power_on = qmp_pcie_msm8996_enable,
644 .power_off = qmp_pcie_msm8996_disable,
645 .owner = THIS_MODULE,
648 static void qcom_qmp_reset_control_put(void *data)
650 reset_control_put(data);
653 static int qmp_pcie_msm8996_create(struct device *dev, struct device_node *np, int id,
654 void __iomem *serdes, const struct qmp_phy_cfg *cfg)
656 struct qcom_qmp *qmp = dev_get_drvdata(dev);
657 struct phy *generic_phy;
658 struct qmp_phy *qphy;
661 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
666 qphy->serdes = serdes;
668 * Get memory resources for each PHY:
669 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
671 qphy->tx = devm_of_iomap(dev, np, 0, NULL);
672 if (IS_ERR(qphy->tx))
673 return PTR_ERR(qphy->tx);
675 qphy->rx = devm_of_iomap(dev, np, 1, NULL);
676 if (IS_ERR(qphy->rx))
677 return PTR_ERR(qphy->rx);
679 qphy->pcs = devm_of_iomap(dev, np, 2, NULL);
680 if (IS_ERR(qphy->pcs))
681 return PTR_ERR(qphy->pcs);
683 qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
684 if (IS_ERR(qphy->pipe_clk)) {
685 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk),
686 "failed to get lane%d pipe clock\n", id);
689 qphy->lane_rst = of_reset_control_get_exclusive_by_index(np, 0);
690 if (IS_ERR(qphy->lane_rst)) {
691 dev_err(dev, "failed to get lane%d reset\n", id);
692 return PTR_ERR(qphy->lane_rst);
694 ret = devm_add_action_or_reset(dev, qcom_qmp_reset_control_put,
699 generic_phy = devm_phy_create(dev, np, &qmp_pcie_msm8996_ops);
700 if (IS_ERR(generic_phy)) {
701 ret = PTR_ERR(generic_phy);
702 dev_err(dev, "failed to create qphy %d\n", ret);
706 qphy->phy = generic_phy;
709 qmp->phys[id] = qphy;
710 phy_set_drvdata(generic_phy, qphy);
715 static const struct of_device_id qmp_pcie_msm8996_of_match_table[] = {
717 .compatible = "qcom,msm8996-qmp-pcie-phy",
718 .data = &msm8996_pciephy_cfg,
722 MODULE_DEVICE_TABLE(of, qmp_pcie_msm8996_of_match_table);
724 static int qmp_pcie_msm8996_probe(struct platform_device *pdev)
726 struct qcom_qmp *qmp;
727 struct device *dev = &pdev->dev;
728 struct device_node *child;
729 struct phy_provider *phy_provider;
730 void __iomem *serdes;
731 const struct qmp_phy_cfg *cfg = NULL;
732 int num, id, expected_phys;
735 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
740 dev_set_drvdata(dev, qmp);
742 cfg = of_device_get_match_data(dev);
746 serdes = devm_platform_ioremap_resource(pdev, 0);
748 return PTR_ERR(serdes);
750 expected_phys = cfg->num_phys;
752 mutex_init(&qmp->phy_mutex);
754 ret = qmp_pcie_msm8996_clk_init(dev, cfg);
758 ret = qmp_pcie_msm8996_reset_init(dev, cfg);
762 ret = qmp_pcie_msm8996_vreg_init(dev, cfg);
766 num = of_get_available_child_count(dev->of_node);
767 /* do we have a rogue child node ? */
768 if (num > expected_phys)
771 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
776 for_each_available_child_of_node(dev->of_node, child) {
777 /* Create per-lane phy */
778 ret = qmp_pcie_msm8996_create(dev, child, id, serdes, cfg);
780 dev_err(dev, "failed to create lane%d phy, %d\n",
786 * Register the pipe clock provided by phy.
787 * See function description to see details of this pipe clock.
789 ret = phy_pipe_clk_register(qmp, child);
792 "failed to register pipe clock source\n");
799 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
801 return PTR_ERR_OR_ZERO(phy_provider);
808 static struct platform_driver qmp_pcie_msm8996_driver = {
809 .probe = qmp_pcie_msm8996_probe,
811 .name = "qcom-qmp-msm8996-pcie-phy",
812 .of_match_table = qmp_pcie_msm8996_of_match_table,
816 module_platform_driver(qmp_pcie_msm8996_driver);
818 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
819 MODULE_DESCRIPTION("Qualcomm QMP MSM8996 PCIe PHY driver");
820 MODULE_LICENSE("GPL v2");