1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2013 NVIDIA Corporation
4 * Copyright (C) 2018 Cadence Design Systems Inc.
7 #include <linux/errno.h>
8 #include <linux/export.h>
9 #include <linux/kernel.h>
10 #include <linux/time64.h>
12 #include <linux/phy/phy.h>
13 #include <linux/phy/phy-mipi-dphy.h>
16 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
17 * from the valid ranges specified in Section 6.9, Table 14, Page 41
18 * of the D-PHY specification (v1.2).
20 int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
23 struct phy_configure_opts_mipi_dphy *cfg)
25 unsigned long long hs_clk_rate;
26 unsigned long long ui;
31 hs_clk_rate = pixel_clock * bpp;
32 do_div(hs_clk_rate, lanes);
34 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate);
35 do_div(ui, hs_clk_rate);
38 cfg->clk_post = 60000 + 52 * ui;
40 cfg->clk_prepare = 38000;
41 cfg->clk_settle = 95000;
43 cfg->clk_trail = 60000;
44 cfg->clk_zero = 262000;
47 cfg->hs_exit = 100000;
48 cfg->hs_prepare = 40000 + 4 * ui;
49 cfg->hs_zero = 105000 + 6 * ui;
50 cfg->hs_settle = 85000 + 6 * ui;
54 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40)
55 * contains this formula as:
57 * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui)
59 * where n = 1 for forward-direction HS mode and n = 4 for reverse-
60 * direction HS mode. There's only one setting and this function does
61 * not parameterize on anything other that ui, so this code will
62 * assumes that reverse-direction HS mode is supported and uses n = 4.
64 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui);
68 cfg->ta_get = 5 * cfg->lpx;
69 cfg->ta_go = 4 * cfg->lpx;
70 cfg->ta_sure = cfg->lpx;
73 cfg->hs_clk_rate = hs_clk_rate;
78 EXPORT_SYMBOL(phy_mipi_dphy_get_default_config);
81 * Validate D-PHY configuration according to MIPI D-PHY specification
82 * (v1.2, Section Section 6.9 "Global Operation Timing Parameters").
84 int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg)
86 unsigned long long ui;
91 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate);
92 do_div(ui, cfg->hs_clk_rate);
94 if (cfg->clk_miss > 60000)
97 if (cfg->clk_post < (60000 + 52 * ui))
100 if (cfg->clk_pre < 8)
103 if (cfg->clk_prepare < 38000 || cfg->clk_prepare > 95000)
106 if (cfg->clk_settle < 95000 || cfg->clk_settle > 300000)
109 if (cfg->clk_term_en > 38000)
112 if (cfg->clk_trail < 60000)
115 if ((cfg->clk_prepare + cfg->clk_zero) < 300000)
118 if (cfg->d_term_en > (35000 + 4 * ui))
121 if (cfg->eot > (105000 + 12 * ui))
124 if (cfg->hs_exit < 100000)
127 if (cfg->hs_prepare < (40000 + 4 * ui) ||
128 cfg->hs_prepare > (85000 + 6 * ui))
131 if ((cfg->hs_prepare + cfg->hs_zero) < (145000 + 10 * ui))
134 if ((cfg->hs_settle < (85000 + 6 * ui)) ||
135 (cfg->hs_settle > (145000 + 10 * ui)))
138 if (cfg->hs_skip < 40000 || cfg->hs_skip > (55000 + 4 * ui))
141 if (cfg->hs_trail < max(8 * ui, 60000 + 4 * ui))
147 if (cfg->lpx < 50000)
150 if (cfg->ta_get != (5 * cfg->lpx))
153 if (cfg->ta_go != (4 * cfg->lpx))
156 if (cfg->ta_sure < cfg->lpx || cfg->ta_sure > (2 * cfg->lpx))
159 if (cfg->wakeup < 1000)
164 EXPORT_SYMBOL(phy_mipi_dphy_config_validate);