1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence Torrent SD0801 PHY driver.
5 * Copyright 2018 Cadence Design Systems, Inc.
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/phy/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/reset.h>
25 #include <linux/regmap.h>
27 #define REF_CLK_19_2MHZ 19200000
28 #define REF_CLK_25MHZ 25000000
29 #define REF_CLK_100MHZ 100000000
31 #define MAX_NUM_LANES 4
32 #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */
34 #define NUM_SSC_MODE 3
36 #define NUM_PHY_TYPE 6
38 #define POLL_TIMEOUT_US 5000
39 #define PLL_LOCK_TIMEOUT 100000
41 #define TORRENT_COMMON_CDB_OFFSET 0x0
43 #define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
44 ((0x4000 << (block_offset)) + \
45 (((ln) << 9) << (reg_offset)))
47 #define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
48 ((0x8000 << (block_offset)) + \
49 (((ln) << 9) << (reg_offset)))
51 #define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \
52 (0xC000 << (block_offset))
54 #define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
55 ((0xD000 << (block_offset)) + \
56 (((ln) << 8) << (reg_offset)))
58 #define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \
59 (0xE000 << (block_offset))
61 #define TORRENT_DPTX_PHY_OFFSET 0x0
64 * register offsets from DPTX PHY register block base (i.e MHDP
65 * register base + 0x30a00)
67 #define PHY_AUX_CTRL 0x04
68 #define PHY_RESET 0x20
69 #define PMA_TX_ELEC_IDLE_MASK 0xF0U
70 #define PMA_TX_ELEC_IDLE_SHIFT 4
71 #define PHY_L00_RESET_N_MASK 0x01U
72 #define PHY_PMA_XCVR_PLLCLK_EN 0x24
73 #define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28
74 #define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c
75 #define PHY_POWER_STATE_LN_0 0x0000
76 #define PHY_POWER_STATE_LN_1 0x0008
77 #define PHY_POWER_STATE_LN_2 0x0010
78 #define PHY_POWER_STATE_LN_3 0x0018
79 #define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU
80 #define PHY_PMA_XCVR_POWER_STATE_ACK 0x30
81 #define PHY_PMA_CMN_READY 0x34
84 * register offsets from SD0801 PHY register block base (i.e MHDP
85 * register base + 0x500000)
87 #define CMN_SSM_BANDGAP_TMR 0x0021U
88 #define CMN_SSM_BIAS_TMR 0x0022U
89 #define CMN_PLLSM0_PLLPRE_TMR 0x002AU
90 #define CMN_PLLSM0_PLLLOCK_TMR 0x002CU
91 #define CMN_PLLSM1_PLLPRE_TMR 0x0032U
92 #define CMN_PLLSM1_PLLLOCK_TMR 0x0034U
93 #define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U
94 #define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U
95 #define CMN_CDIAG_REFCLK_OVRD 0x004CU
96 #define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U
97 #define CMN_BGCAL_INIT_TMR 0x0064U
98 #define CMN_BGCAL_ITER_TMR 0x0065U
99 #define CMN_IBCAL_INIT_TMR 0x0074U
100 #define CMN_PLL0_VCOCAL_TCTRL 0x0082U
101 #define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U
102 #define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U
103 #define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U
104 #define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U
105 #define CMN_PLL0_INTDIV_M0 0x0090U
106 #define CMN_PLL0_FRACDIVL_M0 0x0091U
107 #define CMN_PLL0_FRACDIVH_M0 0x0092U
108 #define CMN_PLL0_HIGH_THR_M0 0x0093U
109 #define CMN_PLL0_DSM_DIAG_M0 0x0094U
110 #define CMN_PLL0_DSM_FBH_OVRD_M0 0x0095U
111 #define CMN_PLL0_SS_CTRL1_M0 0x0098U
112 #define CMN_PLL0_SS_CTRL2_M0 0x0099U
113 #define CMN_PLL0_SS_CTRL3_M0 0x009AU
114 #define CMN_PLL0_SS_CTRL4_M0 0x009BU
115 #define CMN_PLL0_LOCK_REFCNT_START 0x009CU
116 #define CMN_PLL0_LOCK_PLLCNT_START 0x009EU
117 #define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU
118 #define CMN_PLL0_INTDIV_M1 0x00A0U
119 #define CMN_PLL0_FRACDIVH_M1 0x00A2U
120 #define CMN_PLL0_HIGH_THR_M1 0x00A3U
121 #define CMN_PLL0_DSM_DIAG_M1 0x00A4U
122 #define CMN_PLL0_SS_CTRL1_M1 0x00A8U
123 #define CMN_PLL0_SS_CTRL2_M1 0x00A9U
124 #define CMN_PLL0_SS_CTRL3_M1 0x00AAU
125 #define CMN_PLL0_SS_CTRL4_M1 0x00ABU
126 #define CMN_PLL1_VCOCAL_TCTRL 0x00C2U
127 #define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U
128 #define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U
129 #define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U
130 #define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U
131 #define CMN_PLL1_INTDIV_M0 0x00D0U
132 #define CMN_PLL1_FRACDIVL_M0 0x00D1U
133 #define CMN_PLL1_FRACDIVH_M0 0x00D2U
134 #define CMN_PLL1_HIGH_THR_M0 0x00D3U
135 #define CMN_PLL1_DSM_DIAG_M0 0x00D4U
136 #define CMN_PLL1_DSM_FBH_OVRD_M0 0x00D5U
137 #define CMN_PLL1_DSM_FBL_OVRD_M0 0x00D6U
138 #define CMN_PLL1_SS_CTRL1_M0 0x00D8U
139 #define CMN_PLL1_SS_CTRL2_M0 0x00D9U
140 #define CMN_PLL1_SS_CTRL3_M0 0x00DAU
141 #define CMN_PLL1_SS_CTRL4_M0 0x00DBU
142 #define CMN_PLL1_LOCK_REFCNT_START 0x00DCU
143 #define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU
144 #define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU
145 #define CMN_TXPUCAL_TUNE 0x0103U
146 #define CMN_TXPUCAL_INIT_TMR 0x0104U
147 #define CMN_TXPUCAL_ITER_TMR 0x0105U
148 #define CMN_TXPDCAL_TUNE 0x010BU
149 #define CMN_TXPDCAL_INIT_TMR 0x010CU
150 #define CMN_TXPDCAL_ITER_TMR 0x010DU
151 #define CMN_RXCAL_INIT_TMR 0x0114U
152 #define CMN_RXCAL_ITER_TMR 0x0115U
153 #define CMN_SD_CAL_INIT_TMR 0x0124U
154 #define CMN_SD_CAL_ITER_TMR 0x0125U
155 #define CMN_SD_CAL_REFTIM_START 0x0126U
156 #define CMN_SD_CAL_PLLCNT_START 0x0128U
157 #define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U
158 #define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U
159 #define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U
160 #define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U
161 #define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U
162 #define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U
163 #define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01B1U
164 #define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U
165 #define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U
166 #define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U
167 #define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U
168 #define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U
169 #define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U
170 #define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U
171 #define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U
172 #define CMN_DIAG_BIAS_OVRD1 0x01E1U
174 /* PMA TX Lane registers */
175 #define TX_TXCC_CTRL 0x0040U
176 #define TX_TXCC_CPOST_MULT_00 0x004CU
177 #define TX_TXCC_CPOST_MULT_01 0x004DU
178 #define TX_TXCC_MGNFS_MULT_000 0x0050U
179 #define TX_TXCC_MGNFS_MULT_100 0x0054U
180 #define DRV_DIAG_TX_DRV 0x00C6U
181 #define XCVR_DIAG_PLLDRC_CTRL 0x00E5U
182 #define XCVR_DIAG_HSCLK_SEL 0x00E6U
183 #define XCVR_DIAG_HSCLK_DIV 0x00E7U
184 #define XCVR_DIAG_RXCLK_CTRL 0x00E9U
185 #define XCVR_DIAG_BIDI_CTRL 0x00EAU
186 #define XCVR_DIAG_PSC_OVRD 0x00EBU
187 #define TX_PSC_A0 0x0100U
188 #define TX_PSC_A1 0x0101U
189 #define TX_PSC_A2 0x0102U
190 #define TX_PSC_A3 0x0103U
191 #define TX_RCVDET_ST_TMR 0x0123U
192 #define TX_DIAG_ACYA 0x01E7U
193 #define TX_DIAG_ACYA_HBDC_MASK 0x0001U
195 /* PMA RX Lane registers */
196 #define RX_PSC_A0 0x0000U
197 #define RX_PSC_A1 0x0001U
198 #define RX_PSC_A2 0x0002U
199 #define RX_PSC_A3 0x0003U
200 #define RX_PSC_CAL 0x0006U
201 #define RX_CDRLF_CNFG 0x0080U
202 #define RX_CDRLF_CNFG3 0x0082U
203 #define RX_SIGDET_HL_FILT_TMR 0x0090U
204 #define RX_REE_GCSM1_CTRL 0x0108U
205 #define RX_REE_GCSM1_EQENM_PH1 0x0109U
206 #define RX_REE_GCSM1_EQENM_PH2 0x010AU
207 #define RX_REE_GCSM2_CTRL 0x0110U
208 #define RX_REE_PERGCSM_CTRL 0x0118U
209 #define RX_REE_ATTEN_THR 0x0149U
210 #define RX_REE_TAP1_CLIP 0x0171U
211 #define RX_REE_TAP2TON_CLIP 0x0172U
212 #define RX_REE_SMGM_CTRL1 0x0177U
213 #define RX_REE_SMGM_CTRL2 0x0178U
214 #define RX_DIAG_DFE_CTRL 0x01E0U
215 #define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U
216 #define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U
217 #define RX_DIAG_NQST_CTRL 0x01E5U
218 #define RX_DIAG_SIGDET_TUNE 0x01E8U
219 #define RX_DIAG_PI_RATE 0x01F4U
220 #define RX_DIAG_PI_CAP 0x01F5U
221 #define RX_DIAG_ACYA 0x01FFU
223 /* PHY PCS common registers */
224 #define PHY_PIPE_CMN_CTRL1 0x0000U
225 #define PHY_PLL_CFG 0x000EU
226 #define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U
227 #define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U
228 #define PHY_PIPE_USB3_GEN2_POST_CFG1 0x0023U
230 /* PHY PCS lane registers */
231 #define PHY_PCS_ISO_LINK_CTRL 0x000BU
233 /* PHY PMA common registers */
234 #define PHY_PMA_CMN_CTRL1 0x0000U
235 #define PHY_PMA_CMN_CTRL2 0x0001U
236 #define PHY_PMA_PLL_RAW_CTRL 0x0003U
238 #define CDNS_TORRENT_OUTPUT_CLOCKS 3
240 static const char * const clk_names[] = {
241 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
242 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
243 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
246 static const struct reg_field phy_pll_cfg =
247 REG_FIELD(PHY_PLL_CFG, 0, 1);
249 static const struct reg_field phy_pma_cmn_ctrl_1 =
250 REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0);
252 static const struct reg_field phy_pma_cmn_ctrl_2 =
253 REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7);
255 static const struct reg_field phy_pma_pll_raw_ctrl =
256 REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1);
258 static const struct reg_field phy_reset_ctrl =
259 REG_FIELD(PHY_RESET, 8, 8);
261 static const struct reg_field phy_pcs_iso_link_ctrl_1 =
262 REG_FIELD(PHY_PCS_ISO_LINK_CTRL, 1, 1);
264 static const struct reg_field phy_pipe_cmn_ctrl1_0 = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0);
266 static const struct reg_field cmn_cdiag_refclk_ovrd_4 =
267 REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4);
269 #define REFCLK_OUT_NUM_CMN_CONFIG 4
271 enum cdns_torrent_refclk_out_cmn {
272 CMN_CDIAG_REFCLK_DRV0_CTRL_1,
273 CMN_CDIAG_REFCLK_DRV0_CTRL_4,
274 CMN_CDIAG_REFCLK_DRV0_CTRL_5,
275 CMN_CDIAG_REFCLK_DRV0_CTRL_6,
278 static const struct reg_field refclk_out_cmn_cfg[] = {
279 [CMN_CDIAG_REFCLK_DRV0_CTRL_1] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1),
280 [CMN_CDIAG_REFCLK_DRV0_CTRL_4] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4),
281 [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5),
282 [CMN_CDIAG_REFCLK_DRV0_CTRL_6] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6),
285 static const int refclk_driver_parent_index[] = {
286 CDNS_TORRENT_DERIVED_REFCLK,
287 CDNS_TORRENT_RECEIVED_REFCLK
290 static u32 cdns_torrent_refclk_driver_mux_table[] = { 1, 0 };
292 enum cdns_torrent_phy_type {
301 enum cdns_torrent_ref_clk {
307 enum cdns_torrent_ssc_mode {
313 struct cdns_torrent_inst {
316 enum cdns_torrent_phy_type phy_type;
318 struct reset_control *lnk_rst;
319 enum cdns_torrent_ssc_mode ssc_mode;
322 struct cdns_torrent_phy {
323 void __iomem *base; /* DPTX registers base */
324 void __iomem *sd_base; /* SD0801 registers base */
325 u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
326 struct reset_control *phy_rst;
327 struct reset_control *apb_rst;
330 enum cdns_torrent_ref_clk ref_clk_rate;
331 struct cdns_torrent_inst phys[MAX_NUM_LANES];
333 const struct cdns_torrent_data *init_data;
334 struct regmap *regmap_common_cdb;
335 struct regmap *regmap_phy_pcs_common_cdb;
336 struct regmap *regmap_phy_pma_common_cdb;
337 struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
338 struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
339 struct regmap *regmap_phy_pcs_lane_cdb[MAX_NUM_LANES];
340 struct regmap *regmap_dptx_phy_reg;
341 struct regmap_field *phy_pll_cfg;
342 struct regmap_field *phy_pipe_cmn_ctrl1_0;
343 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
344 struct regmap_field *phy_pma_cmn_ctrl_1;
345 struct regmap_field *phy_pma_cmn_ctrl_2;
346 struct regmap_field *phy_pma_pll_raw_ctrl;
347 struct regmap_field *phy_reset_ctrl;
348 struct regmap_field *phy_pcs_iso_link_ctrl_1[MAX_NUM_LANES];
349 struct clk_hw_onecell_data *clk_hw_data;
352 enum phy_powerstate {
354 /* Powerstate A1 is unused */
359 struct cdns_torrent_refclk_driver {
361 struct regmap_field *cmn_fields[REFCLK_OUT_NUM_CMN_CONFIG];
362 struct clk_init_data clk_data;
365 #define to_cdns_torrent_refclk_driver(_hw) \
366 container_of(_hw, struct cdns_torrent_refclk_driver, hw)
368 struct cdns_torrent_derived_refclk {
370 struct regmap_field *phy_pipe_cmn_ctrl1_0;
371 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
372 struct clk_init_data clk_data;
375 #define to_cdns_torrent_derived_refclk(_hw) \
376 container_of(_hw, struct cdns_torrent_derived_refclk, hw)
378 struct cdns_torrent_received_refclk {
380 struct regmap_field *phy_pipe_cmn_ctrl1_0;
381 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
382 struct clk_init_data clk_data;
385 #define to_cdns_torrent_received_refclk(_hw) \
386 container_of(_hw, struct cdns_torrent_received_refclk, hw)
388 struct cdns_reg_pairs {
393 struct cdns_torrent_vals {
394 struct cdns_reg_pairs *reg_pairs;
398 struct cdns_torrent_data {
399 u8 block_offset_shift;
401 struct cdns_torrent_vals *link_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
403 struct cdns_torrent_vals *xcvr_diag_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
405 struct cdns_torrent_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
407 struct cdns_torrent_vals *cmn_vals[NUM_REF_CLK][NUM_PHY_TYPE]
408 [NUM_PHY_TYPE][NUM_SSC_MODE];
409 struct cdns_torrent_vals *tx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE]
410 [NUM_PHY_TYPE][NUM_SSC_MODE];
411 struct cdns_torrent_vals *rx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE]
412 [NUM_PHY_TYPE][NUM_SSC_MODE];
415 struct cdns_regmap_cdb_context {
421 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
423 struct cdns_regmap_cdb_context *ctx = context;
424 u32 offset = reg << ctx->reg_offset_shift;
426 writew(val, ctx->base + offset);
431 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
433 struct cdns_regmap_cdb_context *ctx = context;
434 u32 offset = reg << ctx->reg_offset_shift;
436 *val = readw(ctx->base + offset);
440 static int cdns_regmap_dptx_write(void *context, unsigned int reg,
443 struct cdns_regmap_cdb_context *ctx = context;
446 writel(val, ctx->base + offset);
451 static int cdns_regmap_dptx_read(void *context, unsigned int reg,
454 struct cdns_regmap_cdb_context *ctx = context;
457 *val = readl(ctx->base + offset);
461 #define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \
463 .name = "torrent_tx_lane" n "_cdb", \
466 .reg_write = cdns_regmap_write, \
467 .reg_read = cdns_regmap_read, \
470 #define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \
472 .name = "torrent_rx_lane" n "_cdb", \
475 .reg_write = cdns_regmap_write, \
476 .reg_read = cdns_regmap_read, \
479 static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = {
480 TORRENT_TX_LANE_CDB_REGMAP_CONF("0"),
481 TORRENT_TX_LANE_CDB_REGMAP_CONF("1"),
482 TORRENT_TX_LANE_CDB_REGMAP_CONF("2"),
483 TORRENT_TX_LANE_CDB_REGMAP_CONF("3"),
486 static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = {
487 TORRENT_RX_LANE_CDB_REGMAP_CONF("0"),
488 TORRENT_RX_LANE_CDB_REGMAP_CONF("1"),
489 TORRENT_RX_LANE_CDB_REGMAP_CONF("2"),
490 TORRENT_RX_LANE_CDB_REGMAP_CONF("3"),
493 static const struct regmap_config cdns_torrent_common_cdb_config = {
494 .name = "torrent_common_cdb",
497 .reg_write = cdns_regmap_write,
498 .reg_read = cdns_regmap_read,
501 #define TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \
503 .name = "torrent_phy_pcs_lane" n "_cdb", \
506 .reg_write = cdns_regmap_write, \
507 .reg_read = cdns_regmap_read, \
510 static const struct regmap_config cdns_torrent_phy_pcs_lane_cdb_config[] = {
511 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("0"),
512 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("1"),
513 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("2"),
514 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("3"),
517 static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = {
518 .name = "torrent_phy_pcs_cmn_cdb",
521 .reg_write = cdns_regmap_write,
522 .reg_read = cdns_regmap_read,
525 static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = {
526 .name = "torrent_phy_pma_cmn_cdb",
529 .reg_write = cdns_regmap_write,
530 .reg_read = cdns_regmap_read,
533 static const struct regmap_config cdns_torrent_dptx_phy_config = {
534 .name = "torrent_dptx_phy",
537 .reg_write = cdns_regmap_dptx_write,
538 .reg_read = cdns_regmap_dptx_read,
541 /* PHY mmr access functions */
543 static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val)
545 regmap_write(regmap, offset, val);
548 static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset)
552 regmap_read(regmap, offset, &val);
556 /* DPTX mmr access functions */
558 static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val)
560 regmap_write(regmap, offset, val);
563 static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset)
567 regmap_read(regmap, offset, &val);
572 * Structure used to store values of PHY registers for voltage-related
573 * coefficients, for particular voltage swing and pre-emphasis level. Values
574 * are shared across all physical lanes.
576 struct coefficients {
577 /* Value of DRV_DIAG_TX_DRV register to use */
579 /* Value of TX_TXCC_MGNFS_MULT_000 register to use */
581 /* Value of TX_TXCC_CPOST_MULT_00 register to use */
586 * Array consists of values of voltage-related registers for sd0801 PHY. A value
587 * of 0xFFFF is a placeholder for invalid combination, and will never be used.
589 static const struct coefficients vltg_coeff[4][4] = {
590 /* voltage swing 0, pre-emphasis 0->3 */
591 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A,
592 .cpost_mult = 0x0000},
593 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
594 .cpost_mult = 0x0014},
595 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012,
596 .cpost_mult = 0x0020},
597 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
598 .cpost_mult = 0x002A}
601 /* voltage swing 1, pre-emphasis 0->3 */
602 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
603 .cpost_mult = 0x0000},
604 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
605 .cpost_mult = 0x0012},
606 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
607 .cpost_mult = 0x001F},
608 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
609 .cpost_mult = 0xFFFF}
612 /* voltage swing 2, pre-emphasis 0->3 */
613 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
614 .cpost_mult = 0x0000},
615 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
616 .cpost_mult = 0x0013},
617 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
618 .cpost_mult = 0xFFFF},
619 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
620 .cpost_mult = 0xFFFF}
623 /* voltage swing 3, pre-emphasis 0->3 */
624 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
625 .cpost_mult = 0x0000},
626 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
627 .cpost_mult = 0xFFFF},
628 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
629 .cpost_mult = 0xFFFF},
630 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
631 .cpost_mult = 0xFFFF}
635 static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type)
639 return "DisplayPort";
654 * Set registers responsible for enabling and configuring SSC, with second and
655 * third register values provided by parameters.
658 void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy,
659 u32 ctrl2_val, u32 ctrl3_val)
661 struct regmap *regmap = cdns_phy->regmap_common_cdb;
663 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
664 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
665 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val);
666 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
667 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
668 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
669 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val);
670 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
674 void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
677 struct regmap *regmap = cdns_phy->regmap_common_cdb;
679 /* Assumes 19.2 MHz refclock */
681 /* Setting VCO for 10.8GHz */
684 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0119);
685 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);
686 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
687 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00BC);
688 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
689 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0119);
690 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);
691 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
692 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00BC);
693 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0012);
695 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A, 0x006A);
697 /* Setting VCO for 9.72GHz */
701 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01FA);
702 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);
703 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
704 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0152);
705 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
706 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01FA);
707 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);
708 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
709 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0152);
710 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
712 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD, 0x0069);
714 /* Setting VCO for 8.64GHz */
717 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01C2);
718 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
719 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
720 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x012C);
721 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
722 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01C2);
723 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
724 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
725 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x012C);
726 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
728 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536, 0x0069);
730 /* Setting VCO for 8.1GHz */
732 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01A5);
733 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xE000);
734 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
735 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x011A);
736 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
737 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01A5);
738 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xE000);
739 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
740 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x011A);
741 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
743 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7, 0x006A);
748 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);
749 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
750 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);
751 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
753 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);
754 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);
755 /* Set reset register values to disable SSC */
756 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
757 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
758 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
759 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
760 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
761 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
762 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
763 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
764 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
765 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
768 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099);
769 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099);
770 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099);
771 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
775 * Set registers responsible for enabling and configuring SSC, with second
776 * register value provided by a parameter.
778 static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy,
781 struct regmap *regmap = cdns_phy->regmap_common_cdb;
783 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
784 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
785 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F);
786 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
787 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
788 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
789 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F);
790 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
794 void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
797 struct regmap *regmap = cdns_phy->regmap_common_cdb;
799 /* Assumes 25 MHz refclock */
801 /* Setting VCO for 10.8GHz */
804 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0);
805 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
806 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
807 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120);
808 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0);
809 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
810 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
811 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120);
813 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423);
815 /* Setting VCO for 9.72GHz */
819 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184);
820 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD);
821 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
822 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104);
823 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184);
824 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD);
825 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
826 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104);
828 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9);
830 /* Setting VCO for 8.64GHz */
833 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159);
834 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A);
835 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
836 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7);
837 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159);
838 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A);
839 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
840 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7);
842 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F);
844 /* Setting VCO for 8.1GHz */
846 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144);
847 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
848 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
849 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8);
850 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144);
851 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
852 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
853 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8);
855 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A);
859 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
860 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
863 cdns_torrent_phy_write(regmap,
864 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315);
865 cdns_torrent_phy_write(regmap,
866 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
867 cdns_torrent_phy_write(regmap,
868 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315);
869 cdns_torrent_phy_write(regmap,
870 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
872 cdns_torrent_phy_write(regmap,
873 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317);
874 cdns_torrent_phy_write(regmap,
875 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317);
876 /* Set reset register values to disable SSC */
877 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
878 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
879 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
880 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
881 cdns_torrent_phy_write(regmap,
882 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
883 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
884 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
885 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
886 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
887 cdns_torrent_phy_write(regmap,
888 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
891 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7);
892 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7);
893 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7);
894 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
898 void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy,
901 struct regmap *regmap = cdns_phy->regmap_common_cdb;
903 /* Assumes 100 MHz refclock */
905 /* Setting VCO for 10.8GHz */
908 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028);
909 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022);
910 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022);
911 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C);
913 /* Setting VCO for 9.72GHz */
917 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
918 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
919 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
920 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
921 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
922 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
923 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
924 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
925 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061);
926 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061);
927 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333);
928 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333);
929 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
930 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
931 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042);
932 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042);
933 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
934 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
936 /* Setting VCO for 8.64GHz */
939 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
940 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
941 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
942 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
943 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
944 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
945 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
946 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
947 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056);
948 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056);
949 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666);
950 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666);
951 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
952 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
953 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A);
954 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A);
955 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
956 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
958 /* Setting VCO for 8.1GHz */
960 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
961 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
962 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
963 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
964 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
965 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
966 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
967 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
968 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051);
969 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051);
970 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
971 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
972 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036);
973 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036);
974 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
975 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
981 * Enable or disable PLL for selected lanes.
983 static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
984 struct phy_configure_opts_dp *dp,
989 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
992 * Used to determine, which bits to check for or enable in
993 * PHY_PMA_XCVR_PLLCLK_EN register.
996 /* Used to enable or disable lanes. */
999 /* Select values of registers and mask, depending on enabled lane
1002 switch (dp->lanes) {
1005 pll_bits = 0x00000001;
1009 pll_bits = 0x00000003;
1011 /* lanes 0-3, all */
1013 pll_bits = 0x0000000F;
1020 pll_val = 0x00000000;
1022 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val);
1024 /* Wait for acknowledgment from PHY. */
1025 ret = regmap_read_poll_timeout(regmap,
1026 PHY_PMA_XCVR_PLLCLK_EN_ACK,
1028 (rd_val & pll_bits) == pll_val,
1029 0, POLL_TIMEOUT_US);
1034 static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
1036 enum phy_powerstate powerstate)
1038 /* Register value for power state for a single byte. */
1044 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1046 switch (powerstate) {
1047 case (POWERSTATE_A0):
1050 case (POWERSTATE_A2):
1059 /* Select values of registers and mask, depending on enabled
1062 switch (num_lanes) {
1071 | (value_part << 8));
1074 /* lanes 0-3, all */
1078 | (value_part << 16)
1079 | (value_part << 24));
1084 /* Set power state A<n>. */
1085 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);
1086 /* Wait, until PHY acknowledges power state completion. */
1087 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,
1088 read_val, (read_val & mask) == value, 0,
1090 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
1096 static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
1098 unsigned int read_val;
1100 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1103 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
1106 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
1107 read_val, read_val & 1,
1108 0, POLL_TIMEOUT_US);
1109 if (ret == -ETIMEDOUT) {
1110 dev_err(cdns_phy->dev,
1111 "timeout waiting for link PLL clock enable ack\n");
1117 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
1122 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
1128 static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
1132 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1134 ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,
1135 reg & 1, 0, POLL_TIMEOUT_US);
1136 if (ret == -ETIMEDOUT) {
1137 dev_err(cdns_phy->dev,
1138 "timeout waiting for PMA common ready\n");
1145 static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
1146 u32 rate, u32 num_lanes)
1148 unsigned int clk_sel_val = 0;
1149 unsigned int hsclk_div_val = 0;
1154 clk_sel_val = 0x0f01;
1160 clk_sel_val = 0x0701;
1164 clk_sel_val = 0x0b00;
1169 clk_sel_val = 0x0301;
1173 clk_sel_val = 0x0200;
1178 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1179 CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
1180 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1181 CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
1183 /* PMA lane configuration to deal with multi-link operation */
1184 for (i = 0; i < num_lanes; i++)
1185 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i],
1186 XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
1190 * Perform register operations related to setting link rate, once powerstate is
1191 * set and PLL disable request was processed.
1193 static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
1194 struct phy_configure_opts_dp *dp)
1198 /* Disable the cmn_pll0_en before re-programming the new data rate. */
1199 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0);
1202 * Wait for PLL ready de-assertion.
1203 * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1
1205 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1207 ((read_val >> 2) & 0x01) != 0,
1208 0, POLL_TIMEOUT_US);
1213 /* DP Rate Change - VCO Output settings. */
1214 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
1215 /* PMA common configuration 19.2MHz */
1216 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc);
1217 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
1218 /* PMA common configuration 25MHz */
1219 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc);
1220 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
1221 /* PMA common configuration 100MHz */
1222 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, dp->link_rate, dp->ssc);
1224 cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes);
1226 /* Enable the cmn_pll0_en. */
1227 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x3);
1230 * Wait for PLL ready assertion.
1231 * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1
1233 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1235 (read_val & 0x01) != 0,
1236 0, POLL_TIMEOUT_US);
1241 * Verify, that parameters to configure PHY with are correct.
1243 static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst,
1244 struct phy_configure_opts_dp *dp)
1248 /* If changing link rate was required, verify it's supported. */
1250 switch (dp->link_rate) {
1259 /* valid bit rate */
1266 /* Verify lane count. */
1267 switch (dp->lanes) {
1271 /* valid lane count. */
1277 /* Check against actual number of PHY's lanes. */
1278 if (dp->lanes > inst->num_lanes)
1282 * If changing voltages is required, check swing and pre-emphasis
1285 if (dp->set_voltages) {
1286 /* Lane count verified previously. */
1287 for (i = 0; i < dp->lanes; i++) {
1288 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
1291 /* Sum of voltage swing and pre-emphasis levels cannot
1294 if (dp->voltage[i] + dp->pre[i] > 3)
1302 /* Set power state A0 and PLL clock enable to 0 on enabled lanes. */
1303 static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
1306 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1307 u32 pwr_state = cdns_torrent_dp_read(regmap,
1308 PHY_PMA_XCVR_POWER_STATE_REQ);
1309 u32 pll_clk_en = cdns_torrent_dp_read(regmap,
1310 PHY_PMA_XCVR_PLLCLK_EN);
1312 /* Lane 0 is always enabled. */
1313 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
1314 PHY_POWER_STATE_LN_0);
1315 pll_clk_en &= ~0x01U;
1317 if (num_lanes > 1) {
1319 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
1320 PHY_POWER_STATE_LN_1);
1321 pll_clk_en &= ~(0x01U << 1);
1324 if (num_lanes > 2) {
1326 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
1327 PHY_POWER_STATE_LN_2);
1328 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
1329 PHY_POWER_STATE_LN_3);
1330 pll_clk_en &= ~(0x01U << 2);
1331 pll_clk_en &= ~(0x01U << 3);
1334 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
1335 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);
1338 /* Configure lane count as required. */
1339 static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
1340 struct phy_configure_opts_dp *dp)
1344 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1345 u8 lane_mask = (1 << dp->lanes) - 1;
1347 value = cdns_torrent_dp_read(regmap, PHY_RESET);
1348 /* clear pma_tx_elec_idle_ln_* bits. */
1349 value &= ~PMA_TX_ELEC_IDLE_MASK;
1350 /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */
1351 value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) &
1352 PMA_TX_ELEC_IDLE_MASK;
1353 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1355 /* reset the link by asserting phy_l00_reset_n low */
1356 cdns_torrent_dp_write(regmap, PHY_RESET,
1357 value & (~PHY_L00_RESET_N_MASK));
1360 * Assert lane reset on unused lanes and lane 0 so they remain in reset
1361 * and powered down when re-enabling the link
1363 value = (value & 0x0000FFF0) | (0x0000000E & lane_mask);
1364 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1366 cdns_torrent_dp_set_a0_pll(cdns_phy, dp->lanes);
1368 /* release phy_l0*_reset_n based on used laneCount */
1369 value = (value & 0x0000FFF0) | (0x0000000F & lane_mask);
1370 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1372 /* Wait, until PHY gets ready after releasing PHY reset signal. */
1373 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
1379 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
1380 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
1382 ret = cdns_torrent_dp_run(cdns_phy, dp->lanes);
1387 /* Configure link rate as required. */
1388 static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy,
1389 struct phy_configure_opts_dp *dp)
1393 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
1397 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, false);
1402 ret = cdns_torrent_dp_configure_rate(cdns_phy, dp);
1407 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, true);
1410 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
1414 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
1423 /* Configure voltage swing and pre-emphasis for all enabled lanes. */
1424 static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy,
1425 struct phy_configure_opts_dp *dp)
1430 for (lane = 0; lane < dp->lanes; lane++) {
1431 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
1434 * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the
1435 * current state of the analog TX driver.
1437 val |= TX_DIAG_ACYA_HBDC_MASK;
1438 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1441 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1442 TX_TXCC_CTRL, 0x08A4);
1443 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv;
1444 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1445 DRV_DIAG_TX_DRV, val);
1446 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult;
1447 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1448 TX_TXCC_MGNFS_MULT_000,
1450 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult;
1451 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1452 TX_TXCC_CPOST_MULT_00,
1455 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
1458 * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of
1459 * analog TX driver to reflect the new programmed one.
1461 val &= ~TX_DIAG_ACYA_HBDC_MASK;
1462 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1467 static int cdns_torrent_dp_configure(struct phy *phy,
1468 union phy_configure_opts *opts)
1470 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1471 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1474 ret = cdns_torrent_dp_verify_config(inst, &opts->dp);
1476 dev_err(&phy->dev, "invalid params for phy configure\n");
1480 if (opts->dp.set_lanes) {
1481 ret = cdns_torrent_dp_set_lanes(cdns_phy, &opts->dp);
1483 dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n");
1488 if (opts->dp.set_rate) {
1489 ret = cdns_torrent_dp_set_rate(cdns_phy, &opts->dp);
1491 dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n");
1496 if (opts->dp.set_voltages)
1497 cdns_torrent_dp_set_voltages(cdns_phy, &opts->dp);
1502 static int cdns_torrent_phy_on(struct phy *phy)
1504 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1505 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1509 if (cdns_phy->nsubnodes == 1) {
1510 /* Take the PHY lane group out of reset */
1511 reset_control_deassert(inst->lnk_rst);
1513 /* Take the PHY out of reset */
1514 ret = reset_control_deassert(cdns_phy->phy_rst);
1520 * Wait for cmn_ready assertion
1521 * PHY_PMA_CMN_CTRL1[0] == 1
1523 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
1524 read_val, read_val, 1000,
1527 dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
1531 if (inst->phy_type == TYPE_PCIE || inst->phy_type == TYPE_USB) {
1532 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pcs_iso_link_ctrl_1[inst->mlane],
1533 read_val, !read_val, 1000,
1535 if (ret == -ETIMEDOUT) {
1536 dev_err(cdns_phy->dev, "Timeout waiting for PHY status ready\n");
1544 static int cdns_torrent_phy_off(struct phy *phy)
1546 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1547 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1550 if (cdns_phy->nsubnodes != 1)
1553 ret = reset_control_assert(cdns_phy->phy_rst);
1557 return reset_control_assert(inst->lnk_rst);
1560 static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy,
1561 struct cdns_torrent_inst *inst)
1563 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1564 unsigned char lane_bits;
1566 cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
1569 * Set lines power state to A0
1570 * Set lines pll clk enable to 0
1572 cdns_torrent_dp_set_a0_pll(cdns_phy, inst->num_lanes);
1575 * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on
1578 lane_bits = (1 << inst->num_lanes) - 1;
1579 cdns_torrent_dp_write(regmap, PHY_RESET,
1580 ((0xF & ~lane_bits) << 4) | (0xF & lane_bits));
1582 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
1583 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
1586 * PHY PMA registers configuration functions
1587 * Initialize PHY with max supported link rate, without SSC.
1589 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
1590 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
1591 cdns_phy->max_bit_rate,
1593 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
1594 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
1595 cdns_phy->max_bit_rate,
1597 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
1598 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy,
1599 cdns_phy->max_bit_rate,
1602 cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate,
1605 /* take out of reset */
1606 regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1);
1609 static int cdns_torrent_dp_start(struct cdns_torrent_phy *cdns_phy,
1610 struct cdns_torrent_inst *inst,
1615 cdns_torrent_phy_on(phy);
1617 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
1621 ret = cdns_torrent_dp_run(cdns_phy, inst->num_lanes);
1626 static int cdns_torrent_dp_init(struct phy *phy)
1628 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1629 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1631 switch (cdns_phy->ref_clk_rate) {
1635 /* Valid Ref Clock Rate */
1638 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
1642 cdns_torrent_dp_common_init(cdns_phy, inst);
1644 return cdns_torrent_dp_start(cdns_phy, inst, phy);
1647 static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
1649 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1651 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 1);
1652 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 1);
1657 static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw)
1659 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1661 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 0);
1662 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 0);
1665 static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw)
1667 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1670 regmap_field_read(derived_refclk->cmn_cdiag_refclk_ovrd_4, &val);
1675 static const struct clk_ops cdns_torrent_derived_refclk_ops = {
1676 .enable = cdns_torrent_derived_refclk_enable,
1677 .disable = cdns_torrent_derived_refclk_disable,
1678 .is_enabled = cdns_torrent_derived_refclk_is_enabled,
1681 static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy)
1683 struct cdns_torrent_derived_refclk *derived_refclk;
1684 struct device *dev = cdns_phy->dev;
1685 struct clk_init_data *init;
1686 const char *parent_name;
1692 derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL);
1693 if (!derived_refclk)
1696 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
1697 clk_names[CDNS_TORRENT_DERIVED_REFCLK]);
1699 clk = devm_clk_get_optional(dev, "phy_en_refclk");
1701 dev_err(dev, "No parent clock for derived_refclk\n");
1702 return PTR_ERR(clk);
1705 init = &derived_refclk->clk_data;
1708 parent_name = __clk_get_name(clk);
1709 init->parent_names = &parent_name;
1710 init->num_parents = 1;
1712 init->ops = &cdns_torrent_derived_refclk_ops;
1714 init->name = clk_name;
1716 derived_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0;
1717 derived_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4;
1719 derived_refclk->hw.init = init;
1721 hw = &derived_refclk->hw;
1722 ret = devm_clk_hw_register(dev, hw);
1726 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_DERIVED_REFCLK] = hw;
1731 static int cdns_torrent_received_refclk_enable(struct clk_hw *hw)
1733 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1735 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 1);
1740 static void cdns_torrent_received_refclk_disable(struct clk_hw *hw)
1742 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1744 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 0);
1747 static int cdns_torrent_received_refclk_is_enabled(struct clk_hw *hw)
1749 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1752 regmap_field_read(received_refclk->phy_pipe_cmn_ctrl1_0, &val);
1753 regmap_field_read(received_refclk->cmn_cdiag_refclk_ovrd_4, &cmn_val);
1755 return val && !cmn_val;
1758 static const struct clk_ops cdns_torrent_received_refclk_ops = {
1759 .enable = cdns_torrent_received_refclk_enable,
1760 .disable = cdns_torrent_received_refclk_disable,
1761 .is_enabled = cdns_torrent_received_refclk_is_enabled,
1764 static int cdns_torrent_received_refclk_register(struct cdns_torrent_phy *cdns_phy)
1766 struct cdns_torrent_received_refclk *received_refclk;
1767 struct device *dev = cdns_phy->dev;
1768 struct clk_init_data *init;
1769 const char *parent_name;
1775 received_refclk = devm_kzalloc(dev, sizeof(*received_refclk), GFP_KERNEL);
1776 if (!received_refclk)
1779 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
1780 clk_names[CDNS_TORRENT_RECEIVED_REFCLK]);
1782 clk = devm_clk_get_optional(dev, "phy_en_refclk");
1784 dev_err(dev, "No parent clock for received_refclk\n");
1785 return PTR_ERR(clk);
1788 init = &received_refclk->clk_data;
1791 parent_name = __clk_get_name(clk);
1792 init->parent_names = &parent_name;
1793 init->num_parents = 1;
1795 init->ops = &cdns_torrent_received_refclk_ops;
1797 init->name = clk_name;
1799 received_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0;
1800 received_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4;
1802 received_refclk->hw.init = init;
1804 hw = &received_refclk->hw;
1805 ret = devm_clk_hw_register(dev, hw);
1809 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_RECEIVED_REFCLK] = hw;
1814 static int cdns_torrent_refclk_driver_enable(struct clk_hw *hw)
1816 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1818 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0);
1819 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1);
1820 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0);
1825 static void cdns_torrent_refclk_driver_disable(struct clk_hw *hw)
1827 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1829 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 1);
1832 static int cdns_torrent_refclk_driver_is_enabled(struct clk_hw *hw)
1834 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1837 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], &val);
1842 static u8 cdns_torrent_refclk_driver_get_parent(struct clk_hw *hw)
1844 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1847 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], &val);
1848 return clk_mux_val_to_index(hw, cdns_torrent_refclk_driver_mux_table, 0, val);
1851 static int cdns_torrent_refclk_driver_set_parent(struct clk_hw *hw, u8 index)
1853 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1856 val = cdns_torrent_refclk_driver_mux_table[index];
1857 return regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], val);
1860 static const struct clk_ops cdns_torrent_refclk_driver_ops = {
1861 .enable = cdns_torrent_refclk_driver_enable,
1862 .disable = cdns_torrent_refclk_driver_disable,
1863 .is_enabled = cdns_torrent_refclk_driver_is_enabled,
1864 .determine_rate = __clk_mux_determine_rate,
1865 .set_parent = cdns_torrent_refclk_driver_set_parent,
1866 .get_parent = cdns_torrent_refclk_driver_get_parent,
1869 static int cdns_torrent_refclk_driver_register(struct cdns_torrent_phy *cdns_phy)
1871 struct cdns_torrent_refclk_driver *refclk_driver;
1872 struct device *dev = cdns_phy->dev;
1873 struct regmap_field *field;
1874 struct clk_init_data *init;
1875 const char **parent_names;
1876 unsigned int num_parents;
1877 struct regmap *regmap;
1882 refclk_driver = devm_kzalloc(dev, sizeof(*refclk_driver), GFP_KERNEL);
1886 num_parents = ARRAY_SIZE(refclk_driver_parent_index);
1887 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL);
1891 for (i = 0; i < num_parents; i++) {
1892 hw = cdns_phy->clk_hw_data->hws[refclk_driver_parent_index[i]];
1893 if (IS_ERR_OR_NULL(hw)) {
1894 dev_err(dev, "No parent clock for refclk driver clock\n");
1895 return IS_ERR(hw) ? PTR_ERR(hw) : -ENOENT;
1897 parent_names[i] = clk_hw_get_name(hw);
1900 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
1901 clk_names[CDNS_TORRENT_REFCLK_DRIVER]);
1903 init = &refclk_driver->clk_data;
1905 init->ops = &cdns_torrent_refclk_driver_ops;
1906 init->flags = CLK_SET_RATE_NO_REPARENT;
1907 init->parent_names = parent_names;
1908 init->num_parents = num_parents;
1909 init->name = clk_name;
1911 regmap = cdns_phy->regmap_common_cdb;
1913 for (i = 0; i < REFCLK_OUT_NUM_CMN_CONFIG; i++) {
1914 field = devm_regmap_field_alloc(dev, regmap, refclk_out_cmn_cfg[i]);
1915 if (IS_ERR(field)) {
1916 dev_err(dev, "Refclk driver CMN reg field init failed\n");
1917 return PTR_ERR(field);
1919 refclk_driver->cmn_fields[i] = field;
1922 /* Enable Derived reference clock as default */
1923 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1);
1925 refclk_driver->hw.init = init;
1927 hw = &refclk_driver->hw;
1928 ret = devm_clk_hw_register(dev, hw);
1932 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_REFCLK_DRIVER] = hw;
1937 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
1939 u8 reg_offset_shift,
1940 const struct regmap_config *config)
1942 struct cdns_regmap_cdb_context *ctx;
1944 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1946 return ERR_PTR(-ENOMEM);
1949 ctx->base = base + block_offset;
1950 ctx->reg_offset_shift = reg_offset_shift;
1952 return devm_regmap_init(dev, NULL, ctx, config);
1955 static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy)
1957 struct device *dev = cdns_phy->dev;
1958 struct regmap_field *field;
1959 struct regmap *regmap;
1961 regmap = cdns_phy->regmap_dptx_phy_reg;
1962 field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl);
1963 if (IS_ERR(field)) {
1964 dev_err(dev, "PHY_RESET reg field init failed\n");
1965 return PTR_ERR(field);
1967 cdns_phy->phy_reset_ctrl = field;
1972 static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy)
1974 struct device *dev = cdns_phy->dev;
1975 struct regmap_field *field;
1976 struct regmap *regmap;
1979 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
1980 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg);
1981 if (IS_ERR(field)) {
1982 dev_err(dev, "PHY_PLL_CFG reg field init failed\n");
1983 return PTR_ERR(field);
1985 cdns_phy->phy_pll_cfg = field;
1987 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
1988 field = devm_regmap_field_alloc(dev, regmap, phy_pipe_cmn_ctrl1_0);
1989 if (IS_ERR(field)) {
1990 dev_err(dev, "phy_pipe_cmn_ctrl1_0 reg field init failed\n");
1991 return PTR_ERR(field);
1993 cdns_phy->phy_pipe_cmn_ctrl1_0 = field;
1995 regmap = cdns_phy->regmap_common_cdb;
1996 field = devm_regmap_field_alloc(dev, regmap, cmn_cdiag_refclk_ovrd_4);
1997 if (IS_ERR(field)) {
1998 dev_err(dev, "cmn_cdiag_refclk_ovrd_4 reg field init failed\n");
1999 return PTR_ERR(field);
2001 cdns_phy->cmn_cdiag_refclk_ovrd_4 = field;
2003 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2004 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1);
2005 if (IS_ERR(field)) {
2006 dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n");
2007 return PTR_ERR(field);
2009 cdns_phy->phy_pma_cmn_ctrl_1 = field;
2011 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2012 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2);
2013 if (IS_ERR(field)) {
2014 dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n");
2015 return PTR_ERR(field);
2017 cdns_phy->phy_pma_cmn_ctrl_2 = field;
2019 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2020 field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl);
2021 if (IS_ERR(field)) {
2022 dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n");
2023 return PTR_ERR(field);
2025 cdns_phy->phy_pma_pll_raw_ctrl = field;
2027 for (i = 0; i < MAX_NUM_LANES; i++) {
2028 regmap = cdns_phy->regmap_phy_pcs_lane_cdb[i];
2029 field = devm_regmap_field_alloc(dev, regmap, phy_pcs_iso_link_ctrl_1);
2030 if (IS_ERR(field)) {
2031 dev_err(dev, "PHY_PCS_ISO_LINK_CTRL reg field init for ln %d failed\n", i);
2032 return PTR_ERR(field);
2034 cdns_phy->phy_pcs_iso_link_ctrl_1[i] = field;
2040 static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy)
2042 void __iomem *base = cdns_phy->base;
2043 struct device *dev = cdns_phy->dev;
2044 struct regmap *regmap;
2045 u8 reg_offset_shift;
2048 reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
2050 block_offset = TORRENT_DPTX_PHY_OFFSET;
2051 regmap = cdns_regmap_init(dev, base, block_offset,
2053 &cdns_torrent_dptx_phy_config);
2054 if (IS_ERR(regmap)) {
2055 dev_err(dev, "Failed to init DPTX PHY regmap\n");
2056 return PTR_ERR(regmap);
2058 cdns_phy->regmap_dptx_phy_reg = regmap;
2063 static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy)
2065 void __iomem *sd_base = cdns_phy->sd_base;
2066 u8 block_offset_shift, reg_offset_shift;
2067 struct device *dev = cdns_phy->dev;
2068 struct regmap *regmap;
2072 block_offset_shift = cdns_phy->init_data->block_offset_shift;
2073 reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
2075 for (i = 0; i < MAX_NUM_LANES; i++) {
2076 block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift,
2078 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2080 &cdns_torrent_tx_lane_cdb_config[i]);
2081 if (IS_ERR(regmap)) {
2082 dev_err(dev, "Failed to init tx lane CDB regmap\n");
2083 return PTR_ERR(regmap);
2085 cdns_phy->regmap_tx_lane_cdb[i] = regmap;
2087 block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift,
2089 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2091 &cdns_torrent_rx_lane_cdb_config[i]);
2092 if (IS_ERR(regmap)) {
2093 dev_err(dev, "Failed to init rx lane CDB regmap\n");
2094 return PTR_ERR(regmap);
2096 cdns_phy->regmap_rx_lane_cdb[i] = regmap;
2098 block_offset = TORRENT_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift,
2100 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2102 &cdns_torrent_phy_pcs_lane_cdb_config[i]);
2103 if (IS_ERR(regmap)) {
2104 dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n");
2105 return PTR_ERR(regmap);
2107 cdns_phy->regmap_phy_pcs_lane_cdb[i] = regmap;
2110 block_offset = TORRENT_COMMON_CDB_OFFSET;
2111 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2113 &cdns_torrent_common_cdb_config);
2114 if (IS_ERR(regmap)) {
2115 dev_err(dev, "Failed to init common CDB regmap\n");
2116 return PTR_ERR(regmap);
2118 cdns_phy->regmap_common_cdb = regmap;
2120 block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift);
2121 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2123 &cdns_torrent_phy_pcs_cmn_cdb_config);
2124 if (IS_ERR(regmap)) {
2125 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
2126 return PTR_ERR(regmap);
2128 cdns_phy->regmap_phy_pcs_common_cdb = regmap;
2130 block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift);
2131 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2133 &cdns_torrent_phy_pma_cmn_cdb_config);
2134 if (IS_ERR(regmap)) {
2135 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
2136 return PTR_ERR(regmap);
2138 cdns_phy->regmap_phy_pma_common_cdb = regmap;
2143 static int cdns_torrent_phy_init(struct phy *phy)
2145 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
2146 const struct cdns_torrent_data *init_data = cdns_phy->init_data;
2147 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
2148 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
2149 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
2150 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
2151 enum cdns_torrent_phy_type phy_type = inst->phy_type;
2152 enum cdns_torrent_ssc_mode ssc = inst->ssc_mode;
2153 struct cdns_torrent_vals *pcs_cmn_vals;
2154 struct cdns_reg_pairs *reg_pairs;
2155 struct regmap *regmap;
2159 if (cdns_phy->nsubnodes > 1)
2163 * Spread spectrum generation is not required or supported
2166 if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII)
2169 /* PHY configuration specific registers for single link */
2170 link_cmn_vals = init_data->link_cmn_vals[phy_type][TYPE_NONE][ssc];
2171 if (link_cmn_vals) {
2172 reg_pairs = link_cmn_vals->reg_pairs;
2173 num_regs = link_cmn_vals->num_regs;
2174 regmap = cdns_phy->regmap_common_cdb;
2177 * First array value in link_cmn_vals must be of
2178 * PHY_PLL_CFG register
2180 regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val);
2182 for (i = 1; i < num_regs; i++)
2183 regmap_write(regmap, reg_pairs[i].off,
2187 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_type][TYPE_NONE][ssc];
2188 if (xcvr_diag_vals) {
2189 reg_pairs = xcvr_diag_vals->reg_pairs;
2190 num_regs = xcvr_diag_vals->num_regs;
2191 for (i = 0; i < inst->num_lanes; i++) {
2192 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
2193 for (j = 0; j < num_regs; j++)
2194 regmap_write(regmap, reg_pairs[j].off,
2199 /* PHY PCS common registers configurations */
2200 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
2202 reg_pairs = pcs_cmn_vals->reg_pairs;
2203 num_regs = pcs_cmn_vals->num_regs;
2204 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2205 for (i = 0; i < num_regs; i++)
2206 regmap_write(regmap, reg_pairs[i].off,
2210 /* PMA common registers configurations */
2211 cmn_vals = init_data->cmn_vals[ref_clk][phy_type][TYPE_NONE][ssc];
2213 reg_pairs = cmn_vals->reg_pairs;
2214 num_regs = cmn_vals->num_regs;
2215 regmap = cdns_phy->regmap_common_cdb;
2216 for (i = 0; i < num_regs; i++)
2217 regmap_write(regmap, reg_pairs[i].off,
2221 /* PMA TX lane registers configurations */
2222 tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc];
2224 reg_pairs = tx_ln_vals->reg_pairs;
2225 num_regs = tx_ln_vals->num_regs;
2226 for (i = 0; i < inst->num_lanes; i++) {
2227 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
2228 for (j = 0; j < num_regs; j++)
2229 regmap_write(regmap, reg_pairs[j].off,
2234 /* PMA RX lane registers configurations */
2235 rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc];
2237 reg_pairs = rx_ln_vals->reg_pairs;
2238 num_regs = rx_ln_vals->num_regs;
2239 for (i = 0; i < inst->num_lanes; i++) {
2240 regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane];
2241 for (j = 0; j < num_regs; j++)
2242 regmap_write(regmap, reg_pairs[j].off,
2247 if (phy_type == TYPE_DP)
2248 return cdns_torrent_dp_init(phy);
2253 static const struct phy_ops cdns_torrent_phy_ops = {
2254 .init = cdns_torrent_phy_init,
2255 .configure = cdns_torrent_dp_configure,
2256 .power_on = cdns_torrent_phy_on,
2257 .power_off = cdns_torrent_phy_off,
2258 .owner = THIS_MODULE,
2261 static int cdns_torrent_noop_phy_on(struct phy *phy)
2263 /* Give 5ms to 10ms delay for the PIPE clock to be stable */
2264 usleep_range(5000, 10000);
2269 static const struct phy_ops noop_ops = {
2270 .power_on = cdns_torrent_noop_phy_on,
2271 .owner = THIS_MODULE,
2275 int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
2277 const struct cdns_torrent_data *init_data = cdns_phy->init_data;
2278 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
2279 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
2280 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
2281 enum cdns_torrent_phy_type phy_t1, phy_t2;
2282 struct cdns_torrent_vals *pcs_cmn_vals;
2283 int i, j, node, mlane, num_lanes, ret;
2284 struct cdns_reg_pairs *reg_pairs;
2285 enum cdns_torrent_ssc_mode ssc;
2286 struct regmap *regmap;
2289 /* Maximum 2 links (subnodes) are supported */
2290 if (cdns_phy->nsubnodes != 2)
2293 phy_t1 = cdns_phy->phys[0].phy_type;
2294 phy_t2 = cdns_phy->phys[1].phy_type;
2297 * First configure the PHY for first link with phy_t1. Get the array
2298 * values as [phy_t1][phy_t2][ssc].
2300 for (node = 0; node < cdns_phy->nsubnodes; node++) {
2303 * If first link with phy_t1 is configured, then
2304 * configure the PHY for second link with phy_t2.
2305 * Get the array values as [phy_t2][phy_t1][ssc].
2307 swap(phy_t1, phy_t2);
2310 mlane = cdns_phy->phys[node].mlane;
2311 ssc = cdns_phy->phys[node].ssc_mode;
2312 num_lanes = cdns_phy->phys[node].num_lanes;
2315 * PHY configuration specific registers:
2316 * link_cmn_vals depend on combination of PHY types being
2317 * configured and are common for both PHY types, so array
2318 * values should be same for [phy_t1][phy_t2][ssc] and
2319 * [phy_t2][phy_t1][ssc].
2320 * xcvr_diag_vals also depend on combination of PHY types
2321 * being configured, but these can be different for particular
2322 * PHY type and are per lane.
2324 link_cmn_vals = init_data->link_cmn_vals[phy_t1][phy_t2][ssc];
2325 if (link_cmn_vals) {
2326 reg_pairs = link_cmn_vals->reg_pairs;
2327 num_regs = link_cmn_vals->num_regs;
2328 regmap = cdns_phy->regmap_common_cdb;
2331 * First array value in link_cmn_vals must be of
2332 * PHY_PLL_CFG register
2334 regmap_field_write(cdns_phy->phy_pll_cfg,
2337 for (i = 1; i < num_regs; i++)
2338 regmap_write(regmap, reg_pairs[i].off,
2342 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_t1][phy_t2][ssc];
2343 if (xcvr_diag_vals) {
2344 reg_pairs = xcvr_diag_vals->reg_pairs;
2345 num_regs = xcvr_diag_vals->num_regs;
2346 for (i = 0; i < num_lanes; i++) {
2347 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
2348 for (j = 0; j < num_regs; j++)
2349 regmap_write(regmap, reg_pairs[j].off,
2354 /* PHY PCS common registers configurations */
2355 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc];
2357 reg_pairs = pcs_cmn_vals->reg_pairs;
2358 num_regs = pcs_cmn_vals->num_regs;
2359 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2360 for (i = 0; i < num_regs; i++)
2361 regmap_write(regmap, reg_pairs[i].off,
2365 /* PMA common registers configurations */
2366 cmn_vals = init_data->cmn_vals[ref_clk][phy_t1][phy_t2][ssc];
2368 reg_pairs = cmn_vals->reg_pairs;
2369 num_regs = cmn_vals->num_regs;
2370 regmap = cdns_phy->regmap_common_cdb;
2371 for (i = 0; i < num_regs; i++)
2372 regmap_write(regmap, reg_pairs[i].off,
2376 /* PMA TX lane registers configurations */
2377 tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_t1][phy_t2][ssc];
2379 reg_pairs = tx_ln_vals->reg_pairs;
2380 num_regs = tx_ln_vals->num_regs;
2381 for (i = 0; i < num_lanes; i++) {
2382 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
2383 for (j = 0; j < num_regs; j++)
2384 regmap_write(regmap, reg_pairs[j].off,
2389 /* PMA RX lane registers configurations */
2390 rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_t1][phy_t2][ssc];
2392 reg_pairs = rx_ln_vals->reg_pairs;
2393 num_regs = rx_ln_vals->num_regs;
2394 for (i = 0; i < num_lanes; i++) {
2395 regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane];
2396 for (j = 0; j < num_regs; j++)
2397 regmap_write(regmap, reg_pairs[j].off,
2402 reset_control_deassert(cdns_phy->phys[node].lnk_rst);
2405 /* Take the PHY out of reset */
2406 ret = reset_control_deassert(cdns_phy->phy_rst);
2413 static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy)
2415 struct device *dev = cdns_phy->dev;
2417 of_clk_del_provider(dev->of_node);
2420 static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy)
2422 struct device *dev = cdns_phy->dev;
2423 struct device_node *node = dev->of_node;
2424 struct clk_hw_onecell_data *data;
2427 data = devm_kzalloc(dev, struct_size(data, hws, CDNS_TORRENT_OUTPUT_CLOCKS), GFP_KERNEL);
2431 data->num = CDNS_TORRENT_OUTPUT_CLOCKS;
2432 cdns_phy->clk_hw_data = data;
2434 ret = cdns_torrent_derived_refclk_register(cdns_phy);
2436 dev_err(dev, "failed to register derived refclk\n");
2440 ret = cdns_torrent_received_refclk_register(cdns_phy);
2442 dev_err(dev, "failed to register received refclk\n");
2446 ret = cdns_torrent_refclk_driver_register(cdns_phy);
2448 dev_err(dev, "failed to register refclk driver\n");
2452 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data);
2454 dev_err(dev, "Failed to add clock provider: %s\n", node->name);
2461 static int cdns_torrent_reset(struct cdns_torrent_phy *cdns_phy)
2463 struct device *dev = cdns_phy->dev;
2465 cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0);
2466 if (IS_ERR(cdns_phy->phy_rst)) {
2467 dev_err(dev, "%s: failed to get reset\n",
2468 dev->of_node->full_name);
2469 return PTR_ERR(cdns_phy->phy_rst);
2472 cdns_phy->apb_rst = devm_reset_control_get_optional_exclusive(dev, "torrent_apb");
2473 if (IS_ERR(cdns_phy->apb_rst)) {
2474 dev_err(dev, "%s: failed to get apb reset\n",
2475 dev->of_node->full_name);
2476 return PTR_ERR(cdns_phy->apb_rst);
2482 static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy)
2484 struct device *dev = cdns_phy->dev;
2485 unsigned long ref_clk_rate;
2488 cdns_phy->clk = devm_clk_get(dev, "refclk");
2489 if (IS_ERR(cdns_phy->clk)) {
2490 dev_err(dev, "phy ref clock not found\n");
2491 return PTR_ERR(cdns_phy->clk);
2494 ret = clk_prepare_enable(cdns_phy->clk);
2496 dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
2500 ref_clk_rate = clk_get_rate(cdns_phy->clk);
2501 if (!ref_clk_rate) {
2502 dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
2503 clk_disable_unprepare(cdns_phy->clk);
2507 switch (ref_clk_rate) {
2508 case REF_CLK_19_2MHZ:
2509 cdns_phy->ref_clk_rate = CLK_19_2_MHZ;
2512 cdns_phy->ref_clk_rate = CLK_25_MHZ;
2514 case REF_CLK_100MHZ:
2515 cdns_phy->ref_clk_rate = CLK_100_MHZ;
2518 dev_err(cdns_phy->dev, "Invalid Ref Clock Rate\n");
2519 clk_disable_unprepare(cdns_phy->clk);
2526 static int cdns_torrent_phy_probe(struct platform_device *pdev)
2528 struct cdns_torrent_phy *cdns_phy;
2529 struct device *dev = &pdev->dev;
2530 struct phy_provider *phy_provider;
2531 const struct cdns_torrent_data *data;
2532 struct device_node *child;
2533 int ret, subnodes, node = 0, i;
2534 u32 total_num_lanes = 0;
2535 int already_configured;
2536 u8 init_dp_regmap = 0;
2539 /* Get init data for this PHY */
2540 data = of_device_get_match_data(dev);
2544 cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
2548 dev_set_drvdata(dev, cdns_phy);
2549 cdns_phy->dev = dev;
2550 cdns_phy->init_data = data;
2552 cdns_phy->sd_base = devm_platform_ioremap_resource(pdev, 0);
2553 if (IS_ERR(cdns_phy->sd_base))
2554 return PTR_ERR(cdns_phy->sd_base);
2556 subnodes = of_get_available_child_count(dev->of_node);
2557 if (subnodes == 0) {
2558 dev_err(dev, "No available link subnodes found\n");
2562 ret = cdns_torrent_regmap_init(cdns_phy);
2566 ret = cdns_torrent_regfield_init(cdns_phy);
2570 ret = cdns_torrent_clk_register(cdns_phy);
2574 regmap_field_read(cdns_phy->phy_pma_cmn_ctrl_1, &already_configured);
2576 if (!already_configured) {
2577 ret = cdns_torrent_reset(cdns_phy);
2581 ret = cdns_torrent_clk(cdns_phy);
2586 reset_control_deassert(cdns_phy->apb_rst);
2589 for_each_available_child_of_node(dev->of_node, child) {
2592 /* PHY subnode name must be 'phy'. */
2593 if (!(of_node_name_eq(child, "phy")))
2596 cdns_phy->phys[node].lnk_rst =
2597 of_reset_control_array_get_exclusive(child);
2598 if (IS_ERR(cdns_phy->phys[node].lnk_rst)) {
2599 dev_err(dev, "%s: failed to get reset\n",
2601 ret = PTR_ERR(cdns_phy->phys[node].lnk_rst);
2605 if (of_property_read_u32(child, "reg",
2606 &cdns_phy->phys[node].mlane)) {
2607 dev_err(dev, "%s: No \"reg\"-property.\n",
2613 if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) {
2614 dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n",
2622 cdns_phy->phys[node].phy_type = TYPE_PCIE;
2625 cdns_phy->phys[node].phy_type = TYPE_DP;
2627 case PHY_TYPE_SGMII:
2628 cdns_phy->phys[node].phy_type = TYPE_SGMII;
2630 case PHY_TYPE_QSGMII:
2631 cdns_phy->phys[node].phy_type = TYPE_QSGMII;
2634 cdns_phy->phys[node].phy_type = TYPE_USB;
2637 dev_err(dev, "Unsupported protocol\n");
2642 if (of_property_read_u32(child, "cdns,num-lanes",
2643 &cdns_phy->phys[node].num_lanes)) {
2644 dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n",
2650 total_num_lanes += cdns_phy->phys[node].num_lanes;
2653 cdns_phy->phys[node].ssc_mode = NO_SSC;
2654 of_property_read_u32(child, "cdns,ssc-mode",
2655 &cdns_phy->phys[node].ssc_mode);
2657 if (!already_configured)
2658 gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops);
2660 gphy = devm_phy_create(dev, child, &noop_ops);
2662 ret = PTR_ERR(gphy);
2666 if (cdns_phy->phys[node].phy_type == TYPE_DP) {
2667 switch (cdns_phy->phys[node].num_lanes) {
2671 /* valid number of lanes */
2674 dev_err(dev, "unsupported number of lanes: %d\n",
2675 cdns_phy->phys[node].num_lanes);
2680 cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE;
2681 of_property_read_u32(child, "cdns,max-bit-rate",
2682 &cdns_phy->max_bit_rate);
2684 switch (cdns_phy->max_bit_rate) {
2693 /* valid bit rate */
2696 dev_err(dev, "unsupported max bit rate: %dMbps\n",
2697 cdns_phy->max_bit_rate);
2702 /* DPTX registers */
2703 cdns_phy->base = devm_platform_ioremap_resource(pdev, 1);
2704 if (IS_ERR(cdns_phy->base)) {
2705 ret = PTR_ERR(cdns_phy->base);
2709 if (!init_dp_regmap) {
2710 ret = cdns_torrent_dp_regmap_init(cdns_phy);
2714 ret = cdns_torrent_dp_regfield_init(cdns_phy);
2721 dev_dbg(dev, "DP max bit rate %d.%03d Gbps\n",
2722 cdns_phy->max_bit_rate / 1000,
2723 cdns_phy->max_bit_rate % 1000);
2725 gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes;
2726 gphy->attrs.max_link_rate = cdns_phy->max_bit_rate;
2727 gphy->attrs.mode = PHY_MODE_DP;
2730 cdns_phy->phys[node].phy = gphy;
2731 phy_set_drvdata(gphy, &cdns_phy->phys[node]);
2735 cdns_phy->nsubnodes = node;
2737 if (total_num_lanes > MAX_NUM_LANES) {
2738 dev_err(dev, "Invalid lane configuration\n");
2743 if (cdns_phy->nsubnodes > 1 && !already_configured) {
2744 ret = cdns_torrent_phy_configure_multilink(cdns_phy);
2749 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2750 if (IS_ERR(phy_provider)) {
2751 ret = PTR_ERR(phy_provider);
2755 if (cdns_phy->nsubnodes > 1)
2756 dev_dbg(dev, "Multi-link: %s (%d lanes) & %s (%d lanes)",
2757 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
2758 cdns_phy->phys[0].num_lanes,
2759 cdns_torrent_get_phy_type(cdns_phy->phys[1].phy_type),
2760 cdns_phy->phys[1].num_lanes);
2762 dev_dbg(dev, "Single link: %s (%d lanes)",
2763 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
2764 cdns_phy->phys[0].num_lanes);
2771 for (i = 0; i < node; i++)
2772 reset_control_put(cdns_phy->phys[i].lnk_rst);
2774 reset_control_assert(cdns_phy->apb_rst);
2775 clk_disable_unprepare(cdns_phy->clk);
2777 cdns_torrent_clk_cleanup(cdns_phy);
2781 static void cdns_torrent_phy_remove(struct platform_device *pdev)
2783 struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev);
2786 reset_control_assert(cdns_phy->phy_rst);
2787 reset_control_assert(cdns_phy->apb_rst);
2788 for (i = 0; i < cdns_phy->nsubnodes; i++) {
2789 reset_control_assert(cdns_phy->phys[i].lnk_rst);
2790 reset_control_put(cdns_phy->phys[i].lnk_rst);
2793 clk_disable_unprepare(cdns_phy->clk);
2794 cdns_torrent_clk_cleanup(cdns_phy);
2797 /* Single DisplayPort(DP) link configuration */
2798 static struct cdns_reg_pairs sl_dp_link_cmn_regs[] = {
2799 {0x0000, PHY_PLL_CFG},
2802 static struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = {
2803 {0x0000, XCVR_DIAG_HSCLK_SEL},
2804 {0x0001, XCVR_DIAG_PLLDRC_CTRL}
2807 static struct cdns_torrent_vals sl_dp_link_cmn_vals = {
2808 .reg_pairs = sl_dp_link_cmn_regs,
2809 .num_regs = ARRAY_SIZE(sl_dp_link_cmn_regs),
2812 static struct cdns_torrent_vals sl_dp_xcvr_diag_ln_vals = {
2813 .reg_pairs = sl_dp_xcvr_diag_ln_regs,
2814 .num_regs = ARRAY_SIZE(sl_dp_xcvr_diag_ln_regs),
2817 /* Single DP, 19.2 MHz Ref clk, no SSC */
2818 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = {
2819 {0x0014, CMN_SSM_BIAS_TMR},
2820 {0x0027, CMN_PLLSM0_PLLPRE_TMR},
2821 {0x00A1, CMN_PLLSM0_PLLLOCK_TMR},
2822 {0x0027, CMN_PLLSM1_PLLPRE_TMR},
2823 {0x00A1, CMN_PLLSM1_PLLLOCK_TMR},
2824 {0x0060, CMN_BGCAL_INIT_TMR},
2825 {0x0060, CMN_BGCAL_ITER_TMR},
2826 {0x0014, CMN_IBCAL_INIT_TMR},
2827 {0x0018, CMN_TXPUCAL_INIT_TMR},
2828 {0x0005, CMN_TXPUCAL_ITER_TMR},
2829 {0x0018, CMN_TXPDCAL_INIT_TMR},
2830 {0x0005, CMN_TXPDCAL_ITER_TMR},
2831 {0x0240, CMN_RXCAL_INIT_TMR},
2832 {0x0005, CMN_RXCAL_ITER_TMR},
2833 {0x0002, CMN_SD_CAL_INIT_TMR},
2834 {0x0002, CMN_SD_CAL_ITER_TMR},
2835 {0x000B, CMN_SD_CAL_REFTIM_START},
2836 {0x0137, CMN_SD_CAL_PLLCNT_START},
2837 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
2838 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
2839 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
2840 {0x0004, CMN_PLL0_DSM_DIAG_M0},
2841 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
2842 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
2843 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
2844 {0x0004, CMN_PLL1_DSM_DIAG_M0},
2845 {0x00C0, CMN_PLL0_VCOCAL_INIT_TMR},
2846 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
2847 {0x00C0, CMN_PLL1_VCOCAL_INIT_TMR},
2848 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
2849 {0x0260, CMN_PLL0_VCOCAL_REFTIM_START},
2850 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2851 {0x0260, CMN_PLL1_VCOCAL_REFTIM_START},
2852 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
2855 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = {
2856 {0x0780, TX_RCVDET_ST_TMR},
2857 {0x00FB, TX_PSC_A0},
2858 {0x04AA, TX_PSC_A2},
2859 {0x04AA, TX_PSC_A3},
2860 {0x000F, XCVR_DIAG_BIDI_CTRL}
2863 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = {
2864 {0x0000, RX_PSC_A0},
2865 {0x0000, RX_PSC_A2},
2866 {0x0000, RX_PSC_A3},
2867 {0x0000, RX_PSC_CAL},
2868 {0x0000, RX_REE_GCSM1_CTRL},
2869 {0x0000, RX_REE_GCSM2_CTRL},
2870 {0x0000, RX_REE_PERGCSM_CTRL}
2873 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_cmn_vals = {
2874 .reg_pairs = sl_dp_19_2_no_ssc_cmn_regs,
2875 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_cmn_regs),
2878 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_tx_ln_vals = {
2879 .reg_pairs = sl_dp_19_2_no_ssc_tx_ln_regs,
2880 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_tx_ln_regs),
2883 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_rx_ln_vals = {
2884 .reg_pairs = sl_dp_19_2_no_ssc_rx_ln_regs,
2885 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_rx_ln_regs),
2888 /* Single DP, 25 MHz Ref clk, no SSC */
2889 static struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = {
2890 {0x0019, CMN_SSM_BIAS_TMR},
2891 {0x0032, CMN_PLLSM0_PLLPRE_TMR},
2892 {0x00D1, CMN_PLLSM0_PLLLOCK_TMR},
2893 {0x0032, CMN_PLLSM1_PLLPRE_TMR},
2894 {0x00D1, CMN_PLLSM1_PLLLOCK_TMR},
2895 {0x007D, CMN_BGCAL_INIT_TMR},
2896 {0x007D, CMN_BGCAL_ITER_TMR},
2897 {0x0019, CMN_IBCAL_INIT_TMR},
2898 {0x001E, CMN_TXPUCAL_INIT_TMR},
2899 {0x0006, CMN_TXPUCAL_ITER_TMR},
2900 {0x001E, CMN_TXPDCAL_INIT_TMR},
2901 {0x0006, CMN_TXPDCAL_ITER_TMR},
2902 {0x02EE, CMN_RXCAL_INIT_TMR},
2903 {0x0006, CMN_RXCAL_ITER_TMR},
2904 {0x0002, CMN_SD_CAL_INIT_TMR},
2905 {0x0002, CMN_SD_CAL_ITER_TMR},
2906 {0x000E, CMN_SD_CAL_REFTIM_START},
2907 {0x012B, CMN_SD_CAL_PLLCNT_START},
2908 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
2909 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
2910 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
2911 {0x0004, CMN_PLL0_DSM_DIAG_M0},
2912 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
2913 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
2914 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
2915 {0x0004, CMN_PLL1_DSM_DIAG_M0},
2916 {0x00FA, CMN_PLL0_VCOCAL_INIT_TMR},
2917 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
2918 {0x00FA, CMN_PLL1_VCOCAL_INIT_TMR},
2919 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
2920 {0x0317, CMN_PLL0_VCOCAL_REFTIM_START},
2921 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2922 {0x0317, CMN_PLL1_VCOCAL_REFTIM_START},
2923 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
2926 static struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = {
2927 {0x09C4, TX_RCVDET_ST_TMR},
2928 {0x00FB, TX_PSC_A0},
2929 {0x04AA, TX_PSC_A2},
2930 {0x04AA, TX_PSC_A3},
2931 {0x000F, XCVR_DIAG_BIDI_CTRL}
2934 static struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = {
2935 {0x0000, RX_PSC_A0},
2936 {0x0000, RX_PSC_A2},
2937 {0x0000, RX_PSC_A3},
2938 {0x0000, RX_PSC_CAL},
2939 {0x0000, RX_REE_GCSM1_CTRL},
2940 {0x0000, RX_REE_GCSM2_CTRL},
2941 {0x0000, RX_REE_PERGCSM_CTRL}
2944 static struct cdns_torrent_vals sl_dp_25_no_ssc_cmn_vals = {
2945 .reg_pairs = sl_dp_25_no_ssc_cmn_regs,
2946 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_cmn_regs),
2949 static struct cdns_torrent_vals sl_dp_25_no_ssc_tx_ln_vals = {
2950 .reg_pairs = sl_dp_25_no_ssc_tx_ln_regs,
2951 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_tx_ln_regs),
2954 static struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = {
2955 .reg_pairs = sl_dp_25_no_ssc_rx_ln_regs,
2956 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_rx_ln_regs),
2959 /* Single DP, 100 MHz Ref clk, no SSC */
2960 static struct cdns_reg_pairs sl_dp_100_no_ssc_cmn_regs[] = {
2961 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2962 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
2965 static struct cdns_reg_pairs sl_dp_100_no_ssc_tx_ln_regs[] = {
2966 {0x00FB, TX_PSC_A0},
2967 {0x04AA, TX_PSC_A2},
2968 {0x04AA, TX_PSC_A3},
2969 {0x000F, XCVR_DIAG_BIDI_CTRL}
2972 static struct cdns_reg_pairs sl_dp_100_no_ssc_rx_ln_regs[] = {
2973 {0x0000, RX_PSC_A0},
2974 {0x0000, RX_PSC_A2},
2975 {0x0000, RX_PSC_A3},
2976 {0x0000, RX_PSC_CAL},
2977 {0x0000, RX_REE_GCSM1_CTRL},
2978 {0x0000, RX_REE_GCSM2_CTRL},
2979 {0x0000, RX_REE_PERGCSM_CTRL}
2982 static struct cdns_torrent_vals sl_dp_100_no_ssc_cmn_vals = {
2983 .reg_pairs = sl_dp_100_no_ssc_cmn_regs,
2984 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_cmn_regs),
2987 static struct cdns_torrent_vals sl_dp_100_no_ssc_tx_ln_vals = {
2988 .reg_pairs = sl_dp_100_no_ssc_tx_ln_regs,
2989 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_tx_ln_regs),
2992 static struct cdns_torrent_vals sl_dp_100_no_ssc_rx_ln_vals = {
2993 .reg_pairs = sl_dp_100_no_ssc_rx_ln_regs,
2994 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_rx_ln_regs),
2997 /* USB and SGMII/QSGMII link configuration */
2998 static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {
2999 {0x0002, PHY_PLL_CFG},
3000 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0},
3001 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
3004 static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = {
3005 {0x0000, XCVR_DIAG_HSCLK_SEL},
3006 {0x0001, XCVR_DIAG_HSCLK_DIV},
3007 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
3010 static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = {
3011 {0x0011, XCVR_DIAG_HSCLK_SEL},
3012 {0x0003, XCVR_DIAG_HSCLK_DIV},
3013 {0x009B, XCVR_DIAG_PLLDRC_CTRL}
3016 static struct cdns_torrent_vals usb_sgmii_link_cmn_vals = {
3017 .reg_pairs = usb_sgmii_link_cmn_regs,
3018 .num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs),
3021 static struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = {
3022 .reg_pairs = usb_sgmii_xcvr_diag_ln_regs,
3023 .num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs),
3026 static struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = {
3027 .reg_pairs = sgmii_usb_xcvr_diag_ln_regs,
3028 .num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs),
3031 /* PCIe and USB Unique SSC link configuration */
3032 static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = {
3033 {0x0003, PHY_PLL_CFG},
3034 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
3035 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
3036 {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0}
3039 static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = {
3040 {0x0000, XCVR_DIAG_HSCLK_SEL},
3041 {0x0001, XCVR_DIAG_HSCLK_DIV},
3042 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
3045 static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = {
3046 {0x0011, XCVR_DIAG_HSCLK_SEL},
3047 {0x0001, XCVR_DIAG_HSCLK_DIV},
3048 {0x00C9, XCVR_DIAG_PLLDRC_CTRL}
3051 static struct cdns_torrent_vals pcie_usb_link_cmn_vals = {
3052 .reg_pairs = pcie_usb_link_cmn_regs,
3053 .num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs),
3056 static struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = {
3057 .reg_pairs = pcie_usb_xcvr_diag_ln_regs,
3058 .num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs),
3061 static struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = {
3062 .reg_pairs = usb_pcie_xcvr_diag_ln_regs,
3063 .num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs),
3066 /* USB 100 MHz Ref clk, internal SSC */
3067 static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = {
3068 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3069 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3070 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3071 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3072 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3073 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3074 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3075 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3076 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3077 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3078 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3079 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3080 {0x0064, CMN_PLL0_INTDIV_M0},
3081 {0x0050, CMN_PLL0_INTDIV_M1},
3082 {0x0064, CMN_PLL1_INTDIV_M0},
3083 {0x0002, CMN_PLL0_FRACDIVH_M0},
3084 {0x0002, CMN_PLL0_FRACDIVH_M1},
3085 {0x0002, CMN_PLL1_FRACDIVH_M0},
3086 {0x0044, CMN_PLL0_HIGH_THR_M0},
3087 {0x0036, CMN_PLL0_HIGH_THR_M1},
3088 {0x0044, CMN_PLL1_HIGH_THR_M0},
3089 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3090 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3091 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3092 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3093 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3094 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3095 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3096 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3097 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3098 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3099 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3100 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3101 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3102 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3103 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3104 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3105 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3106 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3107 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3108 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3109 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3110 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3111 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3112 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3113 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3114 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3115 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
3116 {0x007F, CMN_TXPUCAL_TUNE},
3117 {0x007F, CMN_TXPDCAL_TUNE}
3120 static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = {
3121 .reg_pairs = usb_100_int_ssc_cmn_regs,
3122 .num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs),
3125 /* Single USB link configuration */
3126 static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = {
3127 {0x0000, PHY_PLL_CFG},
3128 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
3131 static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = {
3132 {0x0000, XCVR_DIAG_HSCLK_SEL},
3133 {0x0001, XCVR_DIAG_HSCLK_DIV},
3134 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
3137 static struct cdns_torrent_vals sl_usb_link_cmn_vals = {
3138 .reg_pairs = sl_usb_link_cmn_regs,
3139 .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs),
3142 static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = {
3143 .reg_pairs = sl_usb_xcvr_diag_ln_regs,
3144 .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs),
3147 /* USB PHY PCS common configuration */
3148 static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = {
3149 {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0},
3150 {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0},
3151 {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1}
3154 static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = {
3155 .reg_pairs = usb_phy_pcs_cmn_regs,
3156 .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs),
3159 /* USB 100 MHz Ref clk, no SSC */
3160 static struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = {
3161 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3162 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3163 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3164 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3165 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
3166 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3167 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
3170 static struct cdns_torrent_vals sl_usb_100_no_ssc_cmn_vals = {
3171 .reg_pairs = sl_usb_100_no_ssc_cmn_regs,
3172 .num_regs = ARRAY_SIZE(sl_usb_100_no_ssc_cmn_regs),
3175 static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = {
3176 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3177 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
3178 {0x007F, CMN_TXPUCAL_TUNE},
3179 {0x007F, CMN_TXPDCAL_TUNE}
3182 static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = {
3183 {0x02FF, TX_PSC_A0},
3184 {0x06AF, TX_PSC_A1},
3185 {0x06AE, TX_PSC_A2},
3186 {0x06AE, TX_PSC_A3},
3187 {0x2A82, TX_TXCC_CTRL},
3188 {0x0014, TX_TXCC_CPOST_MULT_01},
3189 {0x0003, XCVR_DIAG_PSC_OVRD}
3192 static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = {
3193 {0x0D1D, RX_PSC_A0},
3194 {0x0D1D, RX_PSC_A1},
3195 {0x0D00, RX_PSC_A2},
3196 {0x0500, RX_PSC_A3},
3197 {0x0013, RX_SIGDET_HL_FILT_TMR},
3198 {0x0000, RX_REE_GCSM1_CTRL},
3199 {0x0C02, RX_REE_ATTEN_THR},
3200 {0x0330, RX_REE_SMGM_CTRL1},
3201 {0x0300, RX_REE_SMGM_CTRL2},
3202 {0x0019, RX_REE_TAP1_CLIP},
3203 {0x0019, RX_REE_TAP2TON_CLIP},
3204 {0x1004, RX_DIAG_SIGDET_TUNE},
3205 {0x00F9, RX_DIAG_NQST_CTRL},
3206 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3207 {0x0002, RX_DIAG_DFE_AMP_TUNE_3},
3208 {0x0000, RX_DIAG_PI_CAP},
3209 {0x0031, RX_DIAG_PI_RATE},
3210 {0x0001, RX_DIAG_ACYA},
3211 {0x018C, RX_CDRLF_CNFG},
3212 {0x0003, RX_CDRLF_CNFG3}
3215 static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = {
3216 .reg_pairs = usb_100_no_ssc_cmn_regs,
3217 .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs),
3220 static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = {
3221 .reg_pairs = usb_100_no_ssc_tx_ln_regs,
3222 .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs),
3225 static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = {
3226 .reg_pairs = usb_100_no_ssc_rx_ln_regs,
3227 .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs),
3230 /* Single link USB, 100 MHz Ref clk, internal SSC */
3231 static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = {
3232 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3233 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3234 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3235 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3236 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3237 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3238 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3239 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3240 {0x0064, CMN_PLL0_INTDIV_M0},
3241 {0x0064, CMN_PLL1_INTDIV_M0},
3242 {0x0002, CMN_PLL0_FRACDIVH_M0},
3243 {0x0002, CMN_PLL1_FRACDIVH_M0},
3244 {0x0044, CMN_PLL0_HIGH_THR_M0},
3245 {0x0044, CMN_PLL1_HIGH_THR_M0},
3246 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3247 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3248 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3249 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3250 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3251 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3252 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3253 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3254 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3255 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3256 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3257 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3258 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3259 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3260 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3261 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
3262 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3263 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3264 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3265 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3266 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3267 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3268 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3269 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
3272 static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = {
3273 .reg_pairs = sl_usb_100_int_ssc_cmn_regs,
3274 .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs),
3277 /* PCIe and SGMII/QSGMII Unique SSC link configuration */
3278 static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = {
3279 {0x0003, PHY_PLL_CFG},
3280 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
3281 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
3282 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
3285 static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = {
3286 {0x0000, XCVR_DIAG_HSCLK_SEL},
3287 {0x0001, XCVR_DIAG_HSCLK_DIV},
3288 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
3291 static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = {
3292 {0x0011, XCVR_DIAG_HSCLK_SEL},
3293 {0x0003, XCVR_DIAG_HSCLK_DIV},
3294 {0x009B, XCVR_DIAG_PLLDRC_CTRL}
3297 static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = {
3298 .reg_pairs = pcie_sgmii_link_cmn_regs,
3299 .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs),
3302 static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = {
3303 .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs,
3304 .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs),
3307 static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = {
3308 .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs,
3309 .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs),
3312 /* SGMII 100 MHz Ref clk, no SSC */
3313 static struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = {
3314 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3315 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3316 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3317 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3318 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3321 static struct cdns_torrent_vals sl_sgmii_100_no_ssc_cmn_vals = {
3322 .reg_pairs = sl_sgmii_100_no_ssc_cmn_regs,
3323 .num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_cmn_regs),
3326 static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = {
3327 {0x007F, CMN_TXPUCAL_TUNE},
3328 {0x007F, CMN_TXPDCAL_TUNE}
3331 static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = {
3332 {0x00F3, TX_PSC_A0},
3333 {0x04A2, TX_PSC_A2},
3334 {0x04A2, TX_PSC_A3},
3335 {0x0000, TX_TXCC_CPOST_MULT_00},
3336 {0x00B3, DRV_DIAG_TX_DRV}
3339 static struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = {
3340 {0x00F3, TX_PSC_A0},
3341 {0x04A2, TX_PSC_A2},
3342 {0x04A2, TX_PSC_A3},
3343 {0x0000, TX_TXCC_CPOST_MULT_00},
3344 {0x00B3, DRV_DIAG_TX_DRV},
3345 {0x4000, XCVR_DIAG_RXCLK_CTRL},
3348 static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = {
3349 {0x091D, RX_PSC_A0},
3350 {0x0900, RX_PSC_A2},
3351 {0x0100, RX_PSC_A3},
3352 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
3353 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
3354 {0x0000, RX_DIAG_DFE_CTRL},
3355 {0x0019, RX_REE_TAP1_CLIP},
3356 {0x0019, RX_REE_TAP2TON_CLIP},
3357 {0x0098, RX_DIAG_NQST_CTRL},
3358 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3359 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
3360 {0x0000, RX_DIAG_PI_CAP},
3361 {0x0010, RX_DIAG_PI_RATE},
3362 {0x0001, RX_DIAG_ACYA},
3363 {0x018C, RX_CDRLF_CNFG},
3366 static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = {
3367 .reg_pairs = sgmii_100_no_ssc_cmn_regs,
3368 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs),
3371 static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = {
3372 .reg_pairs = sgmii_100_no_ssc_tx_ln_regs,
3373 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs),
3376 static struct cdns_torrent_vals ti_sgmii_100_no_ssc_tx_ln_vals = {
3377 .reg_pairs = ti_sgmii_100_no_ssc_tx_ln_regs,
3378 .num_regs = ARRAY_SIZE(ti_sgmii_100_no_ssc_tx_ln_regs),
3381 static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = {
3382 .reg_pairs = sgmii_100_no_ssc_rx_ln_regs,
3383 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs),
3386 /* SGMII 100 MHz Ref clk, internal SSC */
3387 static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = {
3388 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3389 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3390 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3391 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3392 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3393 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3394 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3395 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3396 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3397 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3398 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3399 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3400 {0x0064, CMN_PLL0_INTDIV_M0},
3401 {0x0050, CMN_PLL0_INTDIV_M1},
3402 {0x0064, CMN_PLL1_INTDIV_M0},
3403 {0x0002, CMN_PLL0_FRACDIVH_M0},
3404 {0x0002, CMN_PLL0_FRACDIVH_M1},
3405 {0x0002, CMN_PLL1_FRACDIVH_M0},
3406 {0x0044, CMN_PLL0_HIGH_THR_M0},
3407 {0x0036, CMN_PLL0_HIGH_THR_M1},
3408 {0x0044, CMN_PLL1_HIGH_THR_M0},
3409 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3410 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3411 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3412 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3413 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3414 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3415 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3416 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3417 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3418 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3419 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3420 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3421 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3422 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3423 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3424 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3425 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3426 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3427 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3428 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3429 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3430 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3431 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3432 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3433 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3434 {0x007F, CMN_TXPUCAL_TUNE},
3435 {0x007F, CMN_TXPDCAL_TUNE}
3438 static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = {
3439 .reg_pairs = sgmii_100_int_ssc_cmn_regs,
3440 .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs),
3443 /* QSGMII 100 MHz Ref clk, no SSC */
3444 static struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = {
3445 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3446 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3447 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3448 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3449 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3452 static struct cdns_torrent_vals sl_qsgmii_100_no_ssc_cmn_vals = {
3453 .reg_pairs = sl_qsgmii_100_no_ssc_cmn_regs,
3454 .num_regs = ARRAY_SIZE(sl_qsgmii_100_no_ssc_cmn_regs),
3457 static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = {
3458 {0x007F, CMN_TXPUCAL_TUNE},
3459 {0x007F, CMN_TXPDCAL_TUNE}
3462 static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = {
3463 {0x00F3, TX_PSC_A0},
3464 {0x04A2, TX_PSC_A2},
3465 {0x04A2, TX_PSC_A3},
3466 {0x0000, TX_TXCC_CPOST_MULT_00},
3467 {0x0011, TX_TXCC_MGNFS_MULT_100},
3468 {0x0003, DRV_DIAG_TX_DRV}
3471 static struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = {
3472 {0x00F3, TX_PSC_A0},
3473 {0x04A2, TX_PSC_A2},
3474 {0x04A2, TX_PSC_A3},
3475 {0x0000, TX_TXCC_CPOST_MULT_00},
3476 {0x0011, TX_TXCC_MGNFS_MULT_100},
3477 {0x0003, DRV_DIAG_TX_DRV},
3478 {0x4000, XCVR_DIAG_RXCLK_CTRL},
3481 static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = {
3482 {0x091D, RX_PSC_A0},
3483 {0x0900, RX_PSC_A2},
3484 {0x0100, RX_PSC_A3},
3485 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
3486 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
3487 {0x0000, RX_DIAG_DFE_CTRL},
3488 {0x0019, RX_REE_TAP1_CLIP},
3489 {0x0019, RX_REE_TAP2TON_CLIP},
3490 {0x0098, RX_DIAG_NQST_CTRL},
3491 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3492 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
3493 {0x0000, RX_DIAG_PI_CAP},
3494 {0x0010, RX_DIAG_PI_RATE},
3495 {0x0001, RX_DIAG_ACYA},
3496 {0x018C, RX_CDRLF_CNFG},
3499 static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = {
3500 .reg_pairs = qsgmii_100_no_ssc_cmn_regs,
3501 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs),
3504 static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = {
3505 .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs,
3506 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs),
3509 static struct cdns_torrent_vals ti_qsgmii_100_no_ssc_tx_ln_vals = {
3510 .reg_pairs = ti_qsgmii_100_no_ssc_tx_ln_regs,
3511 .num_regs = ARRAY_SIZE(ti_qsgmii_100_no_ssc_tx_ln_regs),
3514 static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = {
3515 .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs,
3516 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs),
3519 /* QSGMII 100 MHz Ref clk, internal SSC */
3520 static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = {
3521 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3522 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3523 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3524 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3525 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3526 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3527 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3528 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3529 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3530 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3531 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3532 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3533 {0x0064, CMN_PLL0_INTDIV_M0},
3534 {0x0050, CMN_PLL0_INTDIV_M1},
3535 {0x0064, CMN_PLL1_INTDIV_M0},
3536 {0x0002, CMN_PLL0_FRACDIVH_M0},
3537 {0x0002, CMN_PLL0_FRACDIVH_M1},
3538 {0x0002, CMN_PLL1_FRACDIVH_M0},
3539 {0x0044, CMN_PLL0_HIGH_THR_M0},
3540 {0x0036, CMN_PLL0_HIGH_THR_M1},
3541 {0x0044, CMN_PLL1_HIGH_THR_M0},
3542 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3543 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3544 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3545 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3546 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3547 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3548 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3549 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3550 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3551 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3552 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3553 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3554 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3555 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3556 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3557 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3558 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3559 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3560 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3561 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3562 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3563 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3564 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3565 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3566 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3567 {0x007F, CMN_TXPUCAL_TUNE},
3568 {0x007F, CMN_TXPDCAL_TUNE}
3571 static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = {
3572 .reg_pairs = qsgmii_100_int_ssc_cmn_regs,
3573 .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs),
3576 /* Single SGMII/QSGMII link configuration */
3577 static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = {
3578 {0x0000, PHY_PLL_CFG},
3579 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
3582 static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = {
3583 {0x0000, XCVR_DIAG_HSCLK_SEL},
3584 {0x0003, XCVR_DIAG_HSCLK_DIV},
3585 {0x0013, XCVR_DIAG_PLLDRC_CTRL}
3588 static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = {
3589 .reg_pairs = sl_sgmii_link_cmn_regs,
3590 .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs),
3593 static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
3594 .reg_pairs = sl_sgmii_xcvr_diag_ln_regs,
3595 .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
3598 /* Multi link PCIe, 100 MHz Ref clk, internal SSC */
3599 static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
3600 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3601 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3602 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3603 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3604 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3605 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3606 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3607 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3608 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3609 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3610 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3611 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3612 {0x0064, CMN_PLL0_INTDIV_M0},
3613 {0x0050, CMN_PLL0_INTDIV_M1},
3614 {0x0064, CMN_PLL1_INTDIV_M0},
3615 {0x0002, CMN_PLL0_FRACDIVH_M0},
3616 {0x0002, CMN_PLL0_FRACDIVH_M1},
3617 {0x0002, CMN_PLL1_FRACDIVH_M0},
3618 {0x0044, CMN_PLL0_HIGH_THR_M0},
3619 {0x0036, CMN_PLL0_HIGH_THR_M1},
3620 {0x0044, CMN_PLL1_HIGH_THR_M0},
3621 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3622 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3623 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3624 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3625 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3626 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3627 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3628 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3629 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3630 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3631 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3632 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3633 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3634 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3635 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3636 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3637 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3638 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3639 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3640 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3641 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3642 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3643 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3644 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3645 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
3648 static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = {
3649 .reg_pairs = pcie_100_int_ssc_cmn_regs,
3650 .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs),
3653 /* Single link PCIe, 100 MHz Ref clk, internal SSC */
3654 static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = {
3655 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3656 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3657 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3658 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3659 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3660 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3661 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3662 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3663 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3664 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3665 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3666 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3667 {0x0064, CMN_PLL0_INTDIV_M0},
3668 {0x0050, CMN_PLL0_INTDIV_M1},
3669 {0x0050, CMN_PLL1_INTDIV_M0},
3670 {0x0002, CMN_PLL0_FRACDIVH_M0},
3671 {0x0002, CMN_PLL0_FRACDIVH_M1},
3672 {0x0002, CMN_PLL1_FRACDIVH_M0},
3673 {0x0044, CMN_PLL0_HIGH_THR_M0},
3674 {0x0036, CMN_PLL0_HIGH_THR_M1},
3675 {0x0036, CMN_PLL1_HIGH_THR_M0},
3676 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3677 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3678 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3679 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3680 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3681 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3682 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3683 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3684 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3685 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3686 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3687 {0x0058, CMN_PLL1_SS_CTRL3_M0},
3688 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3689 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3690 {0x0012, CMN_PLL1_SS_CTRL4_M0},
3691 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3692 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3693 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3694 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3695 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3696 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3697 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3698 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3699 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3700 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
3703 static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = {
3704 .reg_pairs = sl_pcie_100_int_ssc_cmn_regs,
3705 .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs),
3708 /* PCIe, 100 MHz Ref clk, no SSC & external SSC */
3709 static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = {
3710 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3711 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3712 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}
3715 static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = {
3716 {0x0019, RX_REE_TAP1_CLIP},
3717 {0x0019, RX_REE_TAP2TON_CLIP},
3718 {0x0001, RX_DIAG_ACYA}
3721 static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = {
3722 .reg_pairs = pcie_100_ext_no_ssc_cmn_regs,
3723 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs),
3726 static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = {
3727 .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs,
3728 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs),
3731 static const struct cdns_torrent_data cdns_map_torrent = {
3732 .block_offset_shift = 0x2,
3733 .reg_offset_shift = 0x2,
3737 [NO_SSC] = &sl_dp_link_cmn_vals,
3743 [EXTERNAL_SSC] = NULL,
3744 [INTERNAL_SSC] = NULL,
3747 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3748 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3749 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3752 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3753 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3754 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3757 [NO_SSC] = &pcie_usb_link_cmn_vals,
3758 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3759 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3764 [NO_SSC] = &sl_sgmii_link_cmn_vals,
3767 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3768 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3769 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3772 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3773 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3774 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3779 [NO_SSC] = &sl_sgmii_link_cmn_vals,
3782 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3783 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3784 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3787 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3788 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3789 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3794 [NO_SSC] = &sl_usb_link_cmn_vals,
3795 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
3796 [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
3799 [NO_SSC] = &pcie_usb_link_cmn_vals,
3800 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3801 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3804 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3805 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3806 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3809 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3810 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3811 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3818 [NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
3824 [EXTERNAL_SSC] = NULL,
3825 [INTERNAL_SSC] = NULL,
3828 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3829 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3830 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3833 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3834 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3835 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3838 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3839 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3840 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3845 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
3848 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3849 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3850 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3853 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3854 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3855 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3860 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
3863 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3864 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3865 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3868 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3869 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3870 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3875 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
3876 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
3877 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
3880 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3881 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3882 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3885 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3886 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3887 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3890 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3891 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3892 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3899 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3900 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3901 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3904 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3905 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3906 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3909 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3910 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3911 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3914 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3915 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3916 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3924 [NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals,
3931 [NO_SSC] = &sl_dp_25_no_ssc_cmn_vals,
3938 [NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
3944 [EXTERNAL_SSC] = NULL,
3945 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
3948 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3949 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3950 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3953 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3954 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3955 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3958 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3959 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3960 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3965 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
3968 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
3969 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3970 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
3973 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
3974 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3975 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3980 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
3983 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3984 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3985 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
3988 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3989 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3990 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3995 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
3996 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
3997 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4000 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
4001 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
4002 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
4005 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4006 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4007 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4010 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4011 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4012 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4021 [NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals,
4028 [NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals,
4035 [NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals,
4041 [EXTERNAL_SSC] = NULL,
4042 [INTERNAL_SSC] = NULL,
4046 [EXTERNAL_SSC] = NULL,
4047 [INTERNAL_SSC] = NULL,
4051 [EXTERNAL_SSC] = NULL,
4052 [INTERNAL_SSC] = NULL,
4056 [EXTERNAL_SSC] = NULL,
4057 [INTERNAL_SSC] = NULL,
4062 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4065 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4066 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4067 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4070 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4071 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4072 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4077 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4080 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4081 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4082 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4085 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4086 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4087 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4092 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4093 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4094 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4097 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4098 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4099 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4102 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4103 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4104 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4107 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4108 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4109 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4118 [NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals,
4125 [NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals,
4132 [NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals,
4137 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4138 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4139 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4142 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4143 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4144 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4147 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4148 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4149 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4152 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4153 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4154 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4159 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4162 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4163 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4164 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4167 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4168 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4169 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4174 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4177 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4178 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4179 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4182 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4183 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4184 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4189 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4190 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4191 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4194 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4195 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4196 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4199 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4200 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4201 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4204 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4205 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4206 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4213 static const struct cdns_torrent_data ti_j721e_map_torrent = {
4214 .block_offset_shift = 0x0,
4215 .reg_offset_shift = 0x1,
4219 [NO_SSC] = &sl_dp_link_cmn_vals,
4225 [EXTERNAL_SSC] = NULL,
4226 [INTERNAL_SSC] = NULL,
4229 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
4230 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4231 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4234 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
4235 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4236 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4239 [NO_SSC] = &pcie_usb_link_cmn_vals,
4240 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4241 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4246 [NO_SSC] = &sl_sgmii_link_cmn_vals,
4249 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
4250 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4251 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4254 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4255 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4256 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4261 [NO_SSC] = &sl_sgmii_link_cmn_vals,
4264 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
4265 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4266 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4269 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4270 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4271 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4276 [NO_SSC] = &sl_usb_link_cmn_vals,
4277 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
4278 [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
4281 [NO_SSC] = &pcie_usb_link_cmn_vals,
4282 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4283 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4286 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4287 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4288 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4291 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4292 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4293 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4300 [NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
4306 [EXTERNAL_SSC] = NULL,
4307 [INTERNAL_SSC] = NULL,
4310 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4311 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4312 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4315 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4316 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4317 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4320 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
4321 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
4322 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
4327 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
4330 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4331 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4332 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4335 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4336 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4337 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4342 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
4345 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4346 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4347 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4350 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4351 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4352 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4357 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
4358 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
4359 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
4362 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
4363 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
4364 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
4367 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4368 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4369 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4372 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4373 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4374 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4381 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4382 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4383 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4386 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4387 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4388 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4391 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4392 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4393 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4396 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4397 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4398 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4406 [NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals,
4413 [NO_SSC] = &sl_dp_25_no_ssc_cmn_vals,
4420 [NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
4426 [EXTERNAL_SSC] = NULL,
4427 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
4430 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
4431 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
4432 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
4435 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
4436 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
4437 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
4440 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
4441 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
4442 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
4447 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
4450 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
4451 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
4452 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
4455 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
4456 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
4457 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
4462 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
4465 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4466 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4467 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
4470 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4471 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4472 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4477 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4478 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4479 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4482 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
4483 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
4484 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
4487 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4488 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4489 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4492 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4493 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4494 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4503 [NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals,
4510 [NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals,
4517 [NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals,
4523 [EXTERNAL_SSC] = NULL,
4524 [INTERNAL_SSC] = NULL,
4528 [EXTERNAL_SSC] = NULL,
4529 [INTERNAL_SSC] = NULL,
4533 [EXTERNAL_SSC] = NULL,
4534 [INTERNAL_SSC] = NULL,
4538 [EXTERNAL_SSC] = NULL,
4539 [INTERNAL_SSC] = NULL,
4544 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4547 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4548 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4549 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4552 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4553 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4554 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4559 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4562 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4563 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4564 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4567 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4568 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4569 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4574 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4575 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4576 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4579 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4580 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4581 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4584 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4585 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4586 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4589 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4590 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4591 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4600 [NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals,
4607 [NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals,
4614 [NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals,
4619 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4620 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4621 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4624 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4625 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4626 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4629 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4630 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4631 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4634 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4635 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4636 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4641 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4644 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4645 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4646 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4649 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4650 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4651 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4656 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4659 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4660 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4661 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4664 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4665 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4666 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4671 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4672 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4673 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4676 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4677 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4678 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4681 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4682 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4683 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4686 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4687 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4688 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4695 static const struct of_device_id cdns_torrent_phy_of_match[] = {
4697 .compatible = "cdns,torrent-phy",
4698 .data = &cdns_map_torrent,
4701 .compatible = "ti,j721e-serdes-10g",
4702 .data = &ti_j721e_map_torrent,
4706 MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match);
4708 static struct platform_driver cdns_torrent_phy_driver = {
4709 .probe = cdns_torrent_phy_probe,
4710 .remove_new = cdns_torrent_phy_remove,
4712 .name = "cdns-torrent-phy",
4713 .of_match_table = cdns_torrent_phy_of_match,
4716 module_platform_driver(cdns_torrent_phy_driver);
4718 MODULE_AUTHOR("Cadence Design Systems, Inc.");
4719 MODULE_DESCRIPTION("Cadence Torrent PHY driver");
4720 MODULE_LICENSE("GPL v2");