drivers/phy/cadence/phy-cadence-torrent.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Cadence Torrent SD0801 PHY driver.
   4  *
   5  * Copyright 2018 Cadence Design Systems, Inc.
   6  *
   7  */
   8
   9 #include <dt-bindings/phy/phy.h>
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_device.h>
  20 #include <linux/phy/phy.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/reset.h>
  23 #include <linux/regmap.h>
  24
  25 #define REF_CLK_19_2MHz         19200000
  26 #define REF_CLK_25MHz           25000000
  27
  28 #define MAX_NUM_LANES           4
  29 #define DEFAULT_MAX_BIT_RATE    8100 /* in Mbps */
  30
  31 #define NUM_SSC_MODE            3
  32 #define NUM_PHY_TYPE            6
  33
  34 #define POLL_TIMEOUT_US         5000
  35 #define PLL_LOCK_TIMEOUT        100000
  36
  37 #define TORRENT_COMMON_CDB_OFFSET       0x0
  38
  39 #define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset)        \
  40                                 ((0x4000 << (block_offset)) +           \
  41                                 (((ln) << 9) << (reg_offset)))
  42
  43 #define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset)        \
  44                                 ((0x8000 << (block_offset)) +           \
  45                                 (((ln) << 9) << (reg_offset)))
  46
  47 #define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset)     \
  48                                 (0xC000 << (block_offset))
  49
  50 #define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset)     \
  51                                 (0xE000 << (block_offset))
  52
  53 #define TORRENT_DPTX_PHY_OFFSET         0x0
  54
  55 /*
  56  * register offsets from DPTX PHY register block base (i.e MHDP
  57  * register base + 0x30a00)
  58  */
  59 #define PHY_AUX_CTRL                    0x04
  60 #define PHY_RESET                       0x20
  61 #define PMA_TX_ELEC_IDLE_MASK           0xF0U
  62 #define PMA_TX_ELEC_IDLE_SHIFT          4
  63 #define PHY_L00_RESET_N_MASK            0x01U
  64 #define PHY_PMA_XCVR_PLLCLK_EN          0x24
  65 #define PHY_PMA_XCVR_PLLCLK_EN_ACK      0x28
  66 #define PHY_PMA_XCVR_POWER_STATE_REQ    0x2c
  67 #define PHY_POWER_STATE_LN_0    0x0000
  68 #define PHY_POWER_STATE_LN_1    0x0008
  69 #define PHY_POWER_STATE_LN_2    0x0010
  70 #define PHY_POWER_STATE_LN_3    0x0018
  71 #define PMA_XCVR_POWER_STATE_REQ_LN_MASK        0x3FU
  72 #define PHY_PMA_XCVR_POWER_STATE_ACK    0x30
  73 #define PHY_PMA_CMN_READY               0x34
  74
  75 /*
  76  * register offsets from SD0801 PHY register block base (i.e MHDP
  77  * register base + 0x500000)
  78  */
  79 #define CMN_SSM_BANDGAP_TMR             0x0021U
  80 #define CMN_SSM_BIAS_TMR                0x0022U
  81 #define CMN_PLLSM0_PLLPRE_TMR           0x002AU
  82 #define CMN_PLLSM0_PLLLOCK_TMR          0x002CU
  83 #define CMN_PLLSM1_PLLPRE_TMR           0x0032U
  84 #define CMN_PLLSM1_PLLLOCK_TMR          0x0034U
  85 #define CMN_CDIAG_CDB_PWRI_OVRD         0x0041U
  86 #define CMN_CDIAG_XCVRC_PWRI_OVRD       0x0047U
  87 #define CMN_BGCAL_INIT_TMR              0x0064U
  88 #define CMN_BGCAL_ITER_TMR              0x0065U
  89 #define CMN_IBCAL_INIT_TMR              0x0074U
  90 #define CMN_PLL0_VCOCAL_TCTRL           0x0082U
  91 #define CMN_PLL0_VCOCAL_INIT_TMR        0x0084U
  92 #define CMN_PLL0_VCOCAL_ITER_TMR        0x0085U
  93 #define CMN_PLL0_VCOCAL_REFTIM_START    0x0086U
  94 #define CMN_PLL0_VCOCAL_PLLCNT_START    0x0088U
  95 #define CMN_PLL0_INTDIV_M0              0x0090U
  96 #define CMN_PLL0_FRACDIVL_M0            0x0091U
  97 #define CMN_PLL0_FRACDIVH_M0            0x0092U
  98 #define CMN_PLL0_HIGH_THR_M0            0x0093U
  99 #define CMN_PLL0_DSM_DIAG_M0            0x0094U
 100 #define CMN_PLL0_SS_CTRL1_M0            0x0098U
 101 #define CMN_PLL0_SS_CTRL2_M0            0x0099U
 102 #define CMN_PLL0_SS_CTRL3_M0            0x009AU
 103 #define CMN_PLL0_SS_CTRL4_M0            0x009BU
 104 #define CMN_PLL0_LOCK_REFCNT_START      0x009CU
 105 #define CMN_PLL0_LOCK_PLLCNT_START      0x009EU
 106 #define CMN_PLL0_LOCK_PLLCNT_THR        0x009FU
 107 #define CMN_PLL0_INTDIV_M1              0x00A0U
 108 #define CMN_PLL0_FRACDIVH_M1            0x00A2U
 109 #define CMN_PLL0_HIGH_THR_M1            0x00A3U
 110 #define CMN_PLL0_DSM_DIAG_M1            0x00A4U
 111 #define CMN_PLL0_SS_CTRL1_M1            0x00A8U
 112 #define CMN_PLL0_SS_CTRL2_M1            0x00A9U
 113 #define CMN_PLL0_SS_CTRL3_M1            0x00AAU
 114 #define CMN_PLL0_SS_CTRL4_M1            0x00ABU
 115 #define CMN_PLL1_VCOCAL_TCTRL           0x00C2U
 116 #define CMN_PLL1_VCOCAL_INIT_TMR        0x00C4U
 117 #define CMN_PLL1_VCOCAL_ITER_TMR        0x00C5U
 118 #define CMN_PLL1_VCOCAL_REFTIM_START    0x00C6U
 119 #define CMN_PLL1_VCOCAL_PLLCNT_START    0x00C8U
 120 #define CMN_PLL1_INTDIV_M0              0x00D0U
 121 #define CMN_PLL1_FRACDIVL_M0            0x00D1U
 122 #define CMN_PLL1_FRACDIVH_M0            0x00D2U
 123 #define CMN_PLL1_HIGH_THR_M0            0x00D3U
 124 #define CMN_PLL1_DSM_DIAG_M0            0x00D4U
 125 #define CMN_PLL1_SS_CTRL1_M0            0x00D8U
 126 #define CMN_PLL1_SS_CTRL2_M0            0x00D9U
 127 #define CMN_PLL1_SS_CTRL3_M0            0x00DAU
 128 #define CMN_PLL1_SS_CTRL4_M0            0x00DBU
 129 #define CMN_PLL1_LOCK_REFCNT_START      0x00DCU
 130 #define CMN_PLL1_LOCK_PLLCNT_START      0x00DEU
 131 #define CMN_PLL1_LOCK_PLLCNT_THR        0x00DFU
 132 #define CMN_TXPUCAL_TUNE                0x0103U
 133 #define CMN_TXPUCAL_INIT_TMR            0x0104U
 134 #define CMN_TXPUCAL_ITER_TMR            0x0105U
 135 #define CMN_TXPDCAL_TUNE                0x010BU
 136 #define CMN_TXPDCAL_INIT_TMR            0x010CU
 137 #define CMN_TXPDCAL_ITER_TMR            0x010DU
 138 #define CMN_RXCAL_INIT_TMR              0x0114U
 139 #define CMN_RXCAL_ITER_TMR              0x0115U
 140 #define CMN_SD_CAL_INIT_TMR             0x0124U
 141 #define CMN_SD_CAL_ITER_TMR             0x0125U
 142 #define CMN_SD_CAL_REFTIM_START         0x0126U
 143 #define CMN_SD_CAL_PLLCNT_START         0x0128U
 144 #define CMN_PDIAG_PLL0_CTRL_M0          0x01A0U
 145 #define CMN_PDIAG_PLL0_CLK_SEL_M0       0x01A1U
 146 #define CMN_PDIAG_PLL0_CP_PADJ_M0       0x01A4U
 147 #define CMN_PDIAG_PLL0_CP_IADJ_M0       0x01A5U
 148 #define CMN_PDIAG_PLL0_FILT_PADJ_M0     0x01A6U
 149 #define CMN_PDIAG_PLL0_CTRL_M1          0x01B0U
 150 #define CMN_PDIAG_PLL0_CLK_SEL_M1       0x01B1U
 151 #define CMN_PDIAG_PLL0_CP_PADJ_M1       0x01B4U
 152 #define CMN_PDIAG_PLL0_CP_IADJ_M1       0x01B5U
 153 #define CMN_PDIAG_PLL0_FILT_PADJ_M1     0x01B6U
 154 #define CMN_PDIAG_PLL1_CTRL_M0          0x01C0U
 155 #define CMN_PDIAG_PLL1_CLK_SEL_M0       0x01C1U
 156 #define CMN_PDIAG_PLL1_CP_PADJ_M0       0x01C4U
 157 #define CMN_PDIAG_PLL1_CP_IADJ_M0       0x01C5U
 158 #define CMN_PDIAG_PLL1_FILT_PADJ_M0     0x01C6U
 159 #define CMN_DIAG_BIAS_OVRD1             0x01E1U
 160
 161 /* PMA TX Lane registers */
 162 #define TX_TXCC_CTRL                    0x0040U
 163 #define TX_TXCC_CPOST_MULT_00           0x004CU
 164 #define TX_TXCC_CPOST_MULT_01           0x004DU
 165 #define TX_TXCC_MGNFS_MULT_000          0x0050U
 166 #define DRV_DIAG_TX_DRV                 0x00C6U
 167 #define XCVR_DIAG_PLLDRC_CTRL           0x00E5U
 168 #define XCVR_DIAG_HSCLK_SEL             0x00E6U
 169 #define XCVR_DIAG_HSCLK_DIV             0x00E7U
 170 #define XCVR_DIAG_BIDI_CTRL             0x00EAU
 171 #define XCVR_DIAG_PSC_OVRD              0x00EBU
 172 #define TX_PSC_A0                       0x0100U
 173 #define TX_PSC_A1                       0x0101U
 174 #define TX_PSC_A2                       0x0102U
 175 #define TX_PSC_A3                       0x0103U
 176 #define TX_RCVDET_ST_TMR                0x0123U
 177 #define TX_DIAG_ACYA                    0x01E7U
 178 #define TX_DIAG_ACYA_HBDC_MASK          0x0001U
 179
 180 /* PMA RX Lane registers */
 181 #define RX_PSC_A0                       0x0000U
 182 #define RX_PSC_A1                       0x0001U
 183 #define RX_PSC_A2                       0x0002U
 184 #define RX_PSC_A3                       0x0003U
 185 #define RX_PSC_CAL                      0x0006U
 186 #define RX_CDRLF_CNFG                   0x0080U
 187 #define RX_CDRLF_CNFG3                  0x0082U
 188 #define RX_SIGDET_HL_FILT_TMR           0x0090U
 189 #define RX_REE_GCSM1_CTRL               0x0108U
 190 #define RX_REE_GCSM1_EQENM_PH1          0x0109U
 191 #define RX_REE_GCSM1_EQENM_PH2          0x010AU
 192 #define RX_REE_GCSM2_CTRL               0x0110U
 193 #define RX_REE_PERGCSM_CTRL             0x0118U
 194 #define RX_REE_ATTEN_THR                0x0149U
 195 #define RX_REE_TAP1_CLIP                0x0171U
 196 #define RX_REE_TAP2TON_CLIP             0x0172U
 197 #define RX_REE_SMGM_CTRL1               0x0177U
 198 #define RX_REE_SMGM_CTRL2               0x0178U
 199 #define RX_DIAG_DFE_CTRL                0x01E0U
 200 #define RX_DIAG_DFE_AMP_TUNE_2          0x01E2U
 201 #define RX_DIAG_DFE_AMP_TUNE_3          0x01E3U
 202 #define RX_DIAG_NQST_CTRL               0x01E5U
 203 #define RX_DIAG_SIGDET_TUNE             0x01E8U
 204 #define RX_DIAG_PI_RATE                 0x01F4U
 205 #define RX_DIAG_PI_CAP                  0x01F5U
 206 #define RX_DIAG_ACYA                    0x01FFU
 207
 208 /* PHY PCS common registers */
 209 #define PHY_PLL_CFG                     0x000EU
 210 #define PHY_PIPE_USB3_GEN2_PRE_CFG0     0x0020U
 211 #define PHY_PIPE_USB3_GEN2_POST_CFG0    0x0022U
 212 #define PHY_PIPE_USB3_GEN2_POST_CFG1    0x0023U
 213
 214 /* PHY PMA common registers */
 215 #define PHY_PMA_CMN_CTRL1               0x0000U
 216 #define PHY_PMA_CMN_CTRL2               0x0001U
 217 #define PHY_PMA_PLL_RAW_CTRL            0x0003U
 218
 219 static const struct reg_field phy_pll_cfg =
 220                                 REG_FIELD(PHY_PLL_CFG, 0, 1);
 221
 222 static const struct reg_field phy_pma_cmn_ctrl_1 =
 223                                 REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0);
 224
 225 static const struct reg_field phy_pma_cmn_ctrl_2 =
 226                                 REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7);
 227
 228 static const struct reg_field phy_pma_pll_raw_ctrl =
 229                                 REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1);
 230
 231 static const struct reg_field phy_reset_ctrl =
 232                                 REG_FIELD(PHY_RESET, 8, 8);
 233
 234 enum cdns_torrent_phy_type {
 235         TYPE_NONE,
 236         TYPE_DP,
 237         TYPE_PCIE,
 238         TYPE_SGMII,
 239         TYPE_QSGMII,
 240         TYPE_USB,
 241 };
 242
 243 enum cdns_torrent_ssc_mode {
 244         NO_SSC,
 245         EXTERNAL_SSC,
 246         INTERNAL_SSC
 247 };
 248
 249 struct cdns_torrent_inst {
 250         struct phy *phy;
 251         u32 mlane;
 252         enum cdns_torrent_phy_type phy_type;
 253         u32 num_lanes;
 254         struct reset_control *lnk_rst;
 255         enum cdns_torrent_ssc_mode ssc_mode;
 256 };
 257
 258 struct cdns_torrent_phy {
 259         void __iomem *base;     /* DPTX registers base */
 260         void __iomem *sd_base; /* SD0801 registers base */
 261         u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
 262         struct reset_control *phy_rst;
 263         struct reset_control *apb_rst;
 264         struct device *dev;
 265         struct clk *clk;
 266         unsigned long ref_clk_rate;
 267         struct cdns_torrent_inst phys[MAX_NUM_LANES];
 268         int nsubnodes;
 269         const struct cdns_torrent_data *init_data;
 270         struct regmap *regmap;
 271         struct regmap *regmap_common_cdb;
 272         struct regmap *regmap_phy_pcs_common_cdb;
 273         struct regmap *regmap_phy_pma_common_cdb;
 274         struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
 275         struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
 276         struct regmap *regmap_dptx_phy_reg;
 277         struct regmap_field *phy_pll_cfg;
 278         struct regmap_field *phy_pma_cmn_ctrl_1;
 279         struct regmap_field *phy_pma_cmn_ctrl_2;
 280         struct regmap_field *phy_pma_pll_raw_ctrl;
 281         struct regmap_field *phy_reset_ctrl;
 282 };
 283
 284 enum phy_powerstate {
 285         POWERSTATE_A0 = 0,
 286         /* Powerstate A1 is unused */
 287         POWERSTATE_A2 = 2,
 288         POWERSTATE_A3 = 3,
 289 };
 290
 291 static int cdns_torrent_phy_init(struct phy *phy);
 292 static int cdns_torrent_dp_init(struct phy *phy);
 293 static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
 294                                u32 num_lanes);
 295 static
 296 int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy);
 297 static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
 298                                     struct cdns_torrent_inst *inst);
 299 static
 300 void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy);
 301 static
 302 void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
 303                                              u32 rate, bool ssc);
 304 static
 305 void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy);
 306 static
 307 void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
 308                                            u32 rate, bool ssc);
 309 static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
 310                                          unsigned int lane);
 311 static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
 312                                          u32 rate, u32 num_lanes);
 313 static int cdns_torrent_dp_configure(struct phy *phy,
 314                                      union phy_configure_opts *opts);
 315 static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
 316                                            u32 num_lanes,
 317                                            enum phy_powerstate powerstate);
 318 static int cdns_torrent_phy_on(struct phy *phy);
 319 static int cdns_torrent_phy_off(struct phy *phy);
 320
 321 static const struct phy_ops cdns_torrent_phy_ops = {
 322         .init           = cdns_torrent_phy_init,
 323         .configure      = cdns_torrent_dp_configure,
 324         .power_on       = cdns_torrent_phy_on,
 325         .power_off      = cdns_torrent_phy_off,
 326         .owner          = THIS_MODULE,
 327 };
 328
 329 struct cdns_reg_pairs {
 330         u32 val;
 331         u32 off;
 332 };
 333
 334 struct cdns_torrent_vals {
 335         struct cdns_reg_pairs *reg_pairs;
 336         u32 num_regs;
 337 };
 338
 339 struct cdns_torrent_data {
 340         u8 block_offset_shift;
 341         u8 reg_offset_shift;
 342         struct cdns_torrent_vals *link_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 343                                                [NUM_SSC_MODE];
 344         struct cdns_torrent_vals *xcvr_diag_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 345                                                 [NUM_SSC_MODE];
 346         struct cdns_torrent_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 347                                               [NUM_SSC_MODE];
 348         struct cdns_torrent_vals *cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 349                                           [NUM_SSC_MODE];
 350         struct cdns_torrent_vals *tx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 351                                             [NUM_SSC_MODE];
 352         struct cdns_torrent_vals *rx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 353                                             [NUM_SSC_MODE];
 354 };
 355
 356 struct cdns_regmap_cdb_context {
 357         struct device *dev;
 358         void __iomem *base;
 359         u8 reg_offset_shift;
 360 };
 361
 362 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
 363 {
 364         struct cdns_regmap_cdb_context *ctx = context;
 365         u32 offset = reg << ctx->reg_offset_shift;
 366
 367         writew(val, ctx->base + offset);
 368
 369         return 0;
 370 }
 371
 372 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
 373 {
 374         struct cdns_regmap_cdb_context *ctx = context;
 375         u32 offset = reg << ctx->reg_offset_shift;
 376
 377         *val = readw(ctx->base + offset);
 378         return 0;
 379 }
 380
 381 static int cdns_regmap_dptx_write(void *context, unsigned int reg,
 382                                   unsigned int val)
 383 {
 384         struct cdns_regmap_cdb_context *ctx = context;
 385         u32 offset = reg;
 386
 387         writel(val, ctx->base + offset);
 388
 389         return 0;
 390 }
 391
 392 static int cdns_regmap_dptx_read(void *context, unsigned int reg,
 393                                  unsigned int *val)
 394 {
 395         struct cdns_regmap_cdb_context *ctx = context;
 396         u32 offset = reg;
 397
 398         *val = readl(ctx->base + offset);
 399         return 0;
 400 }
 401
 402 #define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \
 403 { \
 404         .name = "torrent_tx_lane" n "_cdb", \
 405         .reg_stride = 1, \
 406         .fast_io = true, \
 407         .reg_write = cdns_regmap_write, \
 408         .reg_read = cdns_regmap_read, \
 409 }
 410
 411 #define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \
 412 { \
 413         .name = "torrent_rx_lane" n "_cdb", \
 414         .reg_stride = 1, \
 415         .fast_io = true, \
 416         .reg_write = cdns_regmap_write, \
 417         .reg_read = cdns_regmap_read, \
 418 }
 419
 420 static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = {
 421         TORRENT_TX_LANE_CDB_REGMAP_CONF("0"),
 422         TORRENT_TX_LANE_CDB_REGMAP_CONF("1"),
 423         TORRENT_TX_LANE_CDB_REGMAP_CONF("2"),
 424         TORRENT_TX_LANE_CDB_REGMAP_CONF("3"),
 425 };
 426
 427 static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = {
 428         TORRENT_RX_LANE_CDB_REGMAP_CONF("0"),
 429         TORRENT_RX_LANE_CDB_REGMAP_CONF("1"),
 430         TORRENT_RX_LANE_CDB_REGMAP_CONF("2"),
 431         TORRENT_RX_LANE_CDB_REGMAP_CONF("3"),
 432 };
 433
 434 static const struct regmap_config cdns_torrent_common_cdb_config = {
 435         .name = "torrent_common_cdb",
 436         .reg_stride = 1,
 437         .fast_io = true,
 438         .reg_write = cdns_regmap_write,
 439         .reg_read = cdns_regmap_read,
 440 };
 441
 442 static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = {
 443         .name = "torrent_phy_pcs_cmn_cdb",
 444         .reg_stride = 1,
 445         .fast_io = true,
 446         .reg_write = cdns_regmap_write,
 447         .reg_read = cdns_regmap_read,
 448 };
 449
 450 static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = {
 451         .name = "torrent_phy_pma_cmn_cdb",
 452         .reg_stride = 1,
 453         .fast_io = true,
 454         .reg_write = cdns_regmap_write,
 455         .reg_read = cdns_regmap_read,
 456 };
 457
 458 static const struct regmap_config cdns_torrent_dptx_phy_config = {
 459         .name = "torrent_dptx_phy",
 460         .reg_stride = 1,
 461         .fast_io = true,
 462         .reg_write = cdns_regmap_dptx_write,
 463         .reg_read = cdns_regmap_dptx_read,
 464 };
 465
 466 /* PHY mmr access functions */
 467
 468 static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val)
 469 {
 470         regmap_write(regmap, offset, val);
 471 }
 472
 473 static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset)
 474 {
 475         unsigned int val;
 476
 477         regmap_read(regmap, offset, &val);
 478         return val;
 479 }
 480
 481 /* DPTX mmr access functions */
 482
 483 static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val)
 484 {
 485         regmap_write(regmap, offset, val);
 486 }
 487
 488 static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset)
 489 {
 490         u32 val;
 491
 492         regmap_read(regmap, offset, &val);
 493         return val;
 494 }
 495
 496 /*
 497  * Structure used to store values of PHY registers for voltage-related
 498  * coefficients, for particular voltage swing and pre-emphasis level. Values
 499  * are shared across all physical lanes.
 500  */
 501 struct coefficients {
 502         /* Value of DRV_DIAG_TX_DRV register to use */
 503         u16 diag_tx_drv;
 504         /* Value of TX_TXCC_MGNFS_MULT_000 register to use */
 505         u16 mgnfs_mult;
 506         /* Value of TX_TXCC_CPOST_MULT_00 register to use */
 507         u16 cpost_mult;
 508 };
 509
 510 /*
 511  * Array consists of values of voltage-related registers for sd0801 PHY. A value
 512  * of 0xFFFF is a placeholder for invalid combination, and will never be used.
 513  */
 514 static const struct coefficients vltg_coeff[4][4] = {
 515         /* voltage swing 0, pre-emphasis 0->3 */
 516         {       {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A,
 517                  .cpost_mult = 0x0000},
 518                 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
 519                  .cpost_mult = 0x0014},
 520                 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012,
 521                  .cpost_mult = 0x0020},
 522                 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
 523                  .cpost_mult = 0x002A}
 524         },
 525
 526         /* voltage swing 1, pre-emphasis 0->3 */
 527         {       {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
 528                  .cpost_mult = 0x0000},
 529                 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
 530                  .cpost_mult = 0x0012},
 531                 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
 532                  .cpost_mult = 0x001F},
 533                 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
 534                  .cpost_mult = 0xFFFF}
 535         },
 536
 537         /* voltage swing 2, pre-emphasis 0->3 */
 538         {       {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
 539                  .cpost_mult = 0x0000},
 540                 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
 541                  .cpost_mult = 0x0013},
 542                 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
 543                  .cpost_mult = 0xFFFF},
 544                 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
 545                  .cpost_mult = 0xFFFF}
 546         },
 547
 548         /* voltage swing 3, pre-emphasis 0->3 */
 549         {       {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
 550                  .cpost_mult = 0x0000},
 551                 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
 552                  .cpost_mult = 0xFFFF},
 553                 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
 554                  .cpost_mult = 0xFFFF},
 555                 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
 556                  .cpost_mult = 0xFFFF}
 557         }
 558 };
 559
 560 /*
 561  * Enable or disable PLL for selected lanes.
 562  */
 563 static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
 564                                       struct phy_configure_opts_dp *dp,
 565                                       bool enable)
 566 {
 567         u32 rd_val;
 568         u32 ret;
 569         struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
 570
 571         /*
 572          * Used to determine, which bits to check for or enable in
 573          * PHY_PMA_XCVR_PLLCLK_EN register.
 574          */
 575         u32 pll_bits;
 576         /* Used to enable or disable lanes. */
 577         u32 pll_val;
 578
 579         /* Select values of registers and mask, depending on enabled lane
 580          * count.
 581          */
 582         switch (dp->lanes) {
 583         /* lane 0 */
 584         case (1):
 585                 pll_bits = 0x00000001;
 586                 break;
 587         /* lanes 0-1 */
 588         case (2):
 589                 pll_bits = 0x00000003;
 590                 break;
 591         /* lanes 0-3, all */
 592         default:
 593                 pll_bits = 0x0000000F;
 594                 break;
 595         }
 596
 597         if (enable)
 598                 pll_val = pll_bits;
 599         else
 600                 pll_val = 0x00000000;
 601
 602         cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val);
 603
 604         /* Wait for acknowledgment from PHY. */
 605         ret = regmap_read_poll_timeout(regmap,
 606                                        PHY_PMA_XCVR_PLLCLK_EN_ACK,
 607                                        rd_val,
 608                                        (rd_val & pll_bits) == pll_val,
 609                                        0, POLL_TIMEOUT_US);
 610         ndelay(100);
 611         return ret;
 612 }
 613
 614 /*
 615  * Perform register operations related to setting link rate, once powerstate is
 616  * set and PLL disable request was processed.
 617  */
 618 static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
 619                                           struct phy_configure_opts_dp *dp)
 620 {
 621         u32 ret;
 622         u32 read_val;
 623
 624         /* Disable the cmn_pll0_en before re-programming the new data rate. */
 625         regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0);
 626
 627         /*
 628          * Wait for PLL ready de-assertion.
 629          * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1
 630          */
 631         ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
 632                                              read_val,
 633                                              ((read_val >> 2) & 0x01) != 0,
 634                                              0, POLL_TIMEOUT_US);
 635         if (ret)
 636                 return ret;
 637         ndelay(200);
 638
 639         /* DP Rate Change - VCO Output settings. */
 640         if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz) {
 641                 /* PMA common configuration 19.2MHz */
 642                 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate,
 643                                                         dp->ssc);
 644                 cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
 645         } else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz) {
 646                 /* PMA common configuration 25MHz */
 647                 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate,
 648                                                       dp->ssc);
 649                 cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
 650         }
 651         cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes);
 652
 653         /* Enable the cmn_pll0_en. */
 654         regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x3);
 655
 656         /*
 657          * Wait for PLL ready assertion.
 658          * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1
 659          */
 660         ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
 661                                              read_val,
 662                                              (read_val & 0x01) != 0,
 663                                              0, POLL_TIMEOUT_US);
 664         return ret;
 665 }
 666
 667 /*
 668  * Verify, that parameters to configure PHY with are correct.
 669  */
 670 static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst,
 671                                          struct phy_configure_opts_dp *dp)
 672 {
 673         u8 i;
 674
 675         /* If changing link rate was required, verify it's supported. */
 676         if (dp->set_rate) {
 677                 switch (dp->link_rate) {
 678                 case 1620:
 679                 case 2160:
 680                 case 2430:
 681                 case 2700:
 682                 case 3240:
 683                 case 4320:
 684                 case 5400:
 685                 case 8100:
 686                         /* valid bit rate */
 687                         break;
 688                 default:
 689                         return -EINVAL;
 690                 }
 691         }
 692
 693         /* Verify lane count. */
 694         switch (dp->lanes) {
 695         case 1:
 696         case 2:
 697         case 4:
 698                 /* valid lane count. */
 699                 break;
 700         default:
 701                 return -EINVAL;
 702         }
 703
 704         /* Check against actual number of PHY's lanes. */
 705         if (dp->lanes > inst->num_lanes)
 706                 return -EINVAL;
 707
 708         /*
 709          * If changing voltages is required, check swing and pre-emphasis
 710          * levels, per-lane.
 711          */
 712         if (dp->set_voltages) {
 713                 /* Lane count verified previously. */
 714                 for (i = 0; i < dp->lanes; i++) {
 715                         if (dp->voltage[i] > 3 || dp->pre[i] > 3)
 716                                 return -EINVAL;
 717
 718                         /* Sum of voltage swing and pre-emphasis levels cannot
 719                          * exceed 3.
 720                          */
 721                         if (dp->voltage[i] + dp->pre[i] > 3)
 722                                 return -EINVAL;
 723                 }
 724         }
 725
 726         return 0;
 727 }
 728
 729 /* Set power state A0 and PLL clock enable to 0 on enabled lanes. */
 730 static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
 731                                        u32 num_lanes)
 732 {
 733         struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
 734         u32 pwr_state = cdns_torrent_dp_read(regmap,
 735                                              PHY_PMA_XCVR_POWER_STATE_REQ);
 736         u32 pll_clk_en = cdns_torrent_dp_read(regmap,
 737                                               PHY_PMA_XCVR_PLLCLK_EN);
 738
 739         /* Lane 0 is always enabled. */
 740         pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
 741                        PHY_POWER_STATE_LN_0);
 742         pll_clk_en &= ~0x01U;
 743
 744         if (num_lanes > 1) {
 745                 /* lane 1 */
 746                 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
 747                                PHY_POWER_STATE_LN_1);
 748                 pll_clk_en &= ~(0x01U << 1);
 749         }
 750
 751         if (num_lanes > 2) {
 752                 /* lanes 2 and 3 */
 753                 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
 754                                PHY_POWER_STATE_LN_2);
 755                 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
 756                                PHY_POWER_STATE_LN_3);
 757                 pll_clk_en &= ~(0x01U << 2);
 758                 pll_clk_en &= ~(0x01U << 3);
 759         }
 760
 761         cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
 762         cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);
 763 }
 764
 765 /* Configure lane count as required. */
 766 static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
 767                                      struct phy_configure_opts_dp *dp)
 768 {
 769         u32 value;
 770         u32 ret;
 771         struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
 772         u8 lane_mask = (1 << dp->lanes) - 1;
 773
 774         value = cdns_torrent_dp_read(regmap, PHY_RESET);
 775         /* clear pma_tx_elec_idle_ln_* bits. */
 776         value &= ~PMA_TX_ELEC_IDLE_MASK;
 777         /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */
 778         value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) &
 779                  PMA_TX_ELEC_IDLE_MASK;
 780         cdns_torrent_dp_write(regmap, PHY_RESET, value);
 781
 782         /* reset the link by asserting phy_l00_reset_n low */
 783         cdns_torrent_dp_write(regmap, PHY_RESET,
 784                               value & (~PHY_L00_RESET_N_MASK));
 785
 786         /*
 787          * Assert lane reset on unused lanes and lane 0 so they remain in reset
 788          * and powered down when re-enabling the link
 789          */
 790         value = (value & 0x0000FFF0) | (0x0000000E & lane_mask);
 791         cdns_torrent_dp_write(regmap, PHY_RESET, value);
 792
 793         cdns_torrent_dp_set_a0_pll(cdns_phy, dp->lanes);
 794
 795         /* release phy_l0*_reset_n based on used laneCount */
 796         value = (value & 0x0000FFF0) | (0x0000000F & lane_mask);
 797         cdns_torrent_dp_write(regmap, PHY_RESET, value);
 798
 799         /* Wait, until PHY gets ready after releasing PHY reset signal. */
 800         ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
 801         if (ret)
 802                 return ret;
 803
 804         ndelay(100);
 805
 806         /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
 807         cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
 808
 809         ret = cdns_torrent_dp_run(cdns_phy, dp->lanes);
 810
 811         return ret;
 812 }
 813
 814 /* Configure link rate as required. */
 815 static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy,
 816                                     struct phy_configure_opts_dp *dp)
 817 {
 818         u32 ret;
 819
 820         ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
 821                                               POWERSTATE_A3);
 822         if (ret)
 823                 return ret;
 824         ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, false);
 825         if (ret)
 826                 return ret;
 827         ndelay(200);
 828
 829         ret = cdns_torrent_dp_configure_rate(cdns_phy, dp);
 830         if (ret)
 831                 return ret;
 832         ndelay(200);
 833
 834         ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, true);
 835         if (ret)
 836                 return ret;
 837         ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
 838                                               POWERSTATE_A2);
 839         if (ret)
 840                 return ret;
 841         ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
 842                                               POWERSTATE_A0);
 843         if (ret)
 844                 return ret;
 845         ndelay(900);
 846
 847         return ret;
 848 }
 849
 850 /* Configure voltage swing and pre-emphasis for all enabled lanes. */
 851 static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy,
 852                                          struct phy_configure_opts_dp *dp)
 853 {
 854         u8 lane;
 855         u16 val;
 856
 857         for (lane = 0; lane < dp->lanes; lane++) {
 858                 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
 859                                             TX_DIAG_ACYA);
 860                 /*
 861                  * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the
 862                  * current state of the analog TX driver.
 863                  */
 864                 val |= TX_DIAG_ACYA_HBDC_MASK;
 865                 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
 866                                        TX_DIAG_ACYA, val);
 867
 868                 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
 869                                        TX_TXCC_CTRL, 0x08A4);
 870                 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv;
 871                 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
 872                                        DRV_DIAG_TX_DRV, val);
 873                 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult;
 874                 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
 875                                        TX_TXCC_MGNFS_MULT_000,
 876                                        val);
 877                 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult;
 878                 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
 879                                        TX_TXCC_CPOST_MULT_00,
 880                                        val);
 881
 882                 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
 883                                             TX_DIAG_ACYA);
 884                 /*
 885                  * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of
 886                  * analog TX driver to reflect the new programmed one.
 887                  */
 888                 val &= ~TX_DIAG_ACYA_HBDC_MASK;
 889                 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
 890                                        TX_DIAG_ACYA, val);
 891         }
 892 };
 893
 894 static int cdns_torrent_dp_configure(struct phy *phy,
 895                                      union phy_configure_opts *opts)
 896 {
 897         struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
 898         struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
 899         int ret;
 900
 901         ret = cdns_torrent_dp_verify_config(inst, &opts->dp);
 902         if (ret) {
 903                 dev_err(&phy->dev, "invalid params for phy configure\n");
 904                 return ret;
 905         }
 906
 907         if (opts->dp.set_lanes) {
 908                 ret = cdns_torrent_dp_set_lanes(cdns_phy, &opts->dp);
 909                 if (ret) {
 910                         dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n");
 911                         return ret;
 912                 }
 913         }
 914
 915         if (opts->dp.set_rate) {
 916                 ret = cdns_torrent_dp_set_rate(cdns_phy, &opts->dp);
 917                 if (ret) {
 918                         dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n");
 919                         return ret;
 920                 }
 921         }
 922
 923         if (opts->dp.set_voltages)
 924                 cdns_torrent_dp_set_voltages(cdns_phy, &opts->dp);
 925
 926         return ret;
 927 }
 928
 929 static int cdns_torrent_dp_init(struct phy *phy)
 930 {
 931         unsigned char lane_bits;
 932         int ret;
 933         struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
 934         struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
 935         struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
 936
 937         switch (cdns_phy->ref_clk_rate) {
 938         case REF_CLK_19_2MHz:
 939         case REF_CLK_25MHz:
 940                 /* Valid Ref Clock Rate */
 941                 break;
 942         default:
 943                 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
 944                 return -EINVAL;
 945         }
 946
 947         cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
 948
 949         /* PHY PMA registers configuration function */
 950         cdns_torrent_dp_pma_cfg(cdns_phy, inst);
 951
 952         /*
 953          * Set lines power state to A0
 954          * Set lines pll clk enable to 0
 955          */
 956         cdns_torrent_dp_set_a0_pll(cdns_phy, inst->num_lanes);
 957
 958         /*
 959          * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on
 960          * used lanes
 961          */
 962         lane_bits = (1 << inst->num_lanes) - 1;
 963         cdns_torrent_dp_write(regmap, PHY_RESET,
 964                               ((0xF & ~lane_bits) << 4) | (0xF & lane_bits));
 965
 966         /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
 967         cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
 968
 969         /* PHY PMA registers configuration functions */
 970         /* Initialize PHY with max supported link rate, without SSC. */
 971         if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
 972                 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
 973                                                         cdns_phy->max_bit_rate,
 974                                                         false);
 975         else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
 976                 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
 977                                                       cdns_phy->max_bit_rate,
 978                                                       false);
 979         cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate,
 980                                      inst->num_lanes);
 981
 982         /* take out of reset */
 983         regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1);
 984
 985         cdns_torrent_phy_on(phy);
 986
 987         ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
 988         if (ret)
 989                 return ret;
 990
 991         ret = cdns_torrent_dp_run(cdns_phy, inst->num_lanes);
 992
 993         return ret;
 994 }
 995
 996 static
 997 int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
 998 {
 999         unsigned int reg;
1000         int ret;
1001         struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1002
1003         ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,
1004                                        reg & 1, 0, POLL_TIMEOUT_US);
1005         if (ret == -ETIMEDOUT) {
1006                 dev_err(cdns_phy->dev,
1007                         "timeout waiting for PMA common ready\n");
1008                 return -ETIMEDOUT;
1009         }
1010
1011         return 0;
1012 }
1013
1014 static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy,
1015                                     struct cdns_torrent_inst *inst)
1016 {
1017         unsigned int i;
1018
1019         if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
1020                 /* PMA common configuration 19.2MHz */
1021                 cdns_torrent_dp_pma_cmn_cfg_19_2mhz(cdns_phy);
1022         else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
1023                 /* PMA common configuration 25MHz */
1024                 cdns_torrent_dp_pma_cmn_cfg_25mhz(cdns_phy);
1025
1026         /* PMA lane configuration to deal with multi-link operation */
1027         for (i = 0; i < inst->num_lanes; i++)
1028                 cdns_torrent_dp_pma_lane_cfg(cdns_phy, i);
1029 }
1030
1031 static
1032 void cdns_torrent_dp_pma_cmn_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy)
1033 {
1034         struct regmap *regmap = cdns_phy->regmap_common_cdb;
1035
1036         /* refclock registers - assumes 19.2 MHz refclock */
1037         cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0014);
1038         cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0027);
1039         cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00A1);
1040         cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0027);
1041         cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00A1);
1042         cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x0060);
1043         cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x0060);
1044         cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0014);
1045         cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x0018);
1046         cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0005);
1047         cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x0018);
1048         cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0005);
1049         cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x0240);
1050         cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0005);
1051         cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
1052         cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
1053         cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000B);
1054         cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x0137);
1055
1056         /* PLL registers */
1057         cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
1058         cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
1059         cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
1060         cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
1061         cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
1062         cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
1063         cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
1064         cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
1065         cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00C0);
1066         cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
1067         cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00C0);
1068         cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
1069         cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0260);
1070         cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
1071         cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0260);
1072         cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
1073 }
1074
1075 /*
1076  * Set registers responsible for enabling and configuring SSC, with second and
1077  * third register values provided by parameters.
1078  */
1079 static
1080 void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy,
1081                                         u32 ctrl2_val, u32 ctrl3_val)
1082 {
1083         struct regmap *regmap = cdns_phy->regmap_common_cdb;
1084
1085         cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
1086         cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
1087         cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val);
1088         cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
1089         cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
1090         cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
1091         cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val);
1092         cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
1093 }
1094
1095 static
1096 void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
1097                                              u32 rate, bool ssc)
1098 {
1099         struct regmap *regmap = cdns_phy->regmap_common_cdb;
1100
1101         /* Assumes 19.2 MHz refclock */
1102         switch (rate) {
1103         /* Setting VCO for 10.8GHz */
1104         case 2700:
1105         case 5400:
1106                 cdns_torrent_phy_write(regmap,
1107                                        CMN_PLL0_INTDIV_M0, 0x0119);
1108                 cdns_torrent_phy_write(regmap,
1109                                        CMN_PLL0_FRACDIVL_M0, 0x4000);
1110                 cdns_torrent_phy_write(regmap,
1111                                        CMN_PLL0_FRACDIVH_M0, 0x0002);
1112                 cdns_torrent_phy_write(regmap,
1113                                        CMN_PLL0_HIGH_THR_M0, 0x00BC);
1114                 cdns_torrent_phy_write(regmap,
1115                                        CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
1116                 cdns_torrent_phy_write(regmap,
1117                                        CMN_PLL1_INTDIV_M0, 0x0119);
1118                 cdns_torrent_phy_write(regmap,
1119                                        CMN_PLL1_FRACDIVL_M0, 0x4000);
1120                 cdns_torrent_phy_write(regmap,
1121                                        CMN_PLL1_FRACDIVH_M0, 0x0002);
1122                 cdns_torrent_phy_write(regmap,
1123                                        CMN_PLL1_HIGH_THR_M0, 0x00BC);
1124                 cdns_torrent_phy_write(regmap,
1125                                        CMN_PDIAG_PLL1_CTRL_M0, 0x0012);
1126                 if (ssc)
1127                         cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A,
1128                                                            0x006A);
1129                 break;
1130         /* Setting VCO for 9.72GHz */
1131         case 1620:
1132         case 2430:
1133         case 3240:
1134                 cdns_torrent_phy_write(regmap,
1135                                        CMN_PLL0_INTDIV_M0, 0x01FA);
1136                 cdns_torrent_phy_write(regmap,
1137                                        CMN_PLL0_FRACDIVL_M0, 0x4000);
1138                 cdns_torrent_phy_write(regmap,
1139                                        CMN_PLL0_FRACDIVH_M0, 0x0002);
1140                 cdns_torrent_phy_write(regmap,
1141                                        CMN_PLL0_HIGH_THR_M0, 0x0152);
1142                 cdns_torrent_phy_write(regmap,
1143                                        CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1144                 cdns_torrent_phy_write(regmap,
1145                                        CMN_PLL1_INTDIV_M0, 0x01FA);
1146                 cdns_torrent_phy_write(regmap,
1147                                        CMN_PLL1_FRACDIVL_M0, 0x4000);
1148                 cdns_torrent_phy_write(regmap,
1149                                        CMN_PLL1_FRACDIVH_M0, 0x0002);
1150                 cdns_torrent_phy_write(regmap,
1151                                        CMN_PLL1_HIGH_THR_M0, 0x0152);
1152                 cdns_torrent_phy_write(regmap,
1153                                        CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1154                 if (ssc)
1155                         cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD,
1156                                                            0x0069);
1157                 break;
1158         /* Setting VCO for 8.64GHz */
1159         case 2160:
1160         case 4320:
1161                 cdns_torrent_phy_write(regmap,
1162                                        CMN_PLL0_INTDIV_M0, 0x01C2);
1163                 cdns_torrent_phy_write(regmap,
1164                                        CMN_PLL0_FRACDIVL_M0, 0x0000);
1165                 cdns_torrent_phy_write(regmap,
1166                                        CMN_PLL0_FRACDIVH_M0, 0x0002);
1167                 cdns_torrent_phy_write(regmap,
1168                                        CMN_PLL0_HIGH_THR_M0, 0x012C);
1169                 cdns_torrent_phy_write(regmap,
1170                                        CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1171                 cdns_torrent_phy_write(regmap,
1172                                        CMN_PLL1_INTDIV_M0, 0x01C2);
1173                 cdns_torrent_phy_write(regmap,
1174                                        CMN_PLL1_FRACDIVL_M0, 0x0000);
1175                 cdns_torrent_phy_write(regmap,
1176                                        CMN_PLL1_FRACDIVH_M0, 0x0002);
1177                 cdns_torrent_phy_write(regmap,
1178                                        CMN_PLL1_HIGH_THR_M0, 0x012C);
1179                 cdns_torrent_phy_write(regmap,
1180                                        CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1181                 if (ssc)
1182                         cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536,
1183                                                            0x0069);
1184                 break;
1185         /* Setting VCO for 8.1GHz */
1186         case 8100:
1187                 cdns_torrent_phy_write(regmap,
1188                                        CMN_PLL0_INTDIV_M0, 0x01A5);
1189                 cdns_torrent_phy_write(regmap,
1190                                        CMN_PLL0_FRACDIVL_M0, 0xE000);
1191                 cdns_torrent_phy_write(regmap,
1192                                        CMN_PLL0_FRACDIVH_M0, 0x0002);
1193                 cdns_torrent_phy_write(regmap,
1194                                        CMN_PLL0_HIGH_THR_M0, 0x011A);
1195                 cdns_torrent_phy_write(regmap,
1196                                        CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1197                 cdns_torrent_phy_write(regmap,
1198                                        CMN_PLL1_INTDIV_M0, 0x01A5);
1199                 cdns_torrent_phy_write(regmap,
1200                                        CMN_PLL1_FRACDIVL_M0, 0xE000);
1201                 cdns_torrent_phy_write(regmap,
1202                                        CMN_PLL1_FRACDIVH_M0, 0x0002);
1203                 cdns_torrent_phy_write(regmap,
1204                                        CMN_PLL1_HIGH_THR_M0, 0x011A);
1205                 cdns_torrent_phy_write(regmap,
1206                                        CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1207                 if (ssc)
1208                         cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7,
1209                                                            0x006A);
1210                 break;
1211         }
1212
1213         if (ssc) {
1214                 cdns_torrent_phy_write(regmap,
1215                                        CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);
1216                 cdns_torrent_phy_write(regmap,
1217                                        CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
1218                 cdns_torrent_phy_write(regmap,
1219                                        CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);
1220                 cdns_torrent_phy_write(regmap,
1221                                        CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
1222         } else {
1223                 cdns_torrent_phy_write(regmap,
1224                                        CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);
1225                 cdns_torrent_phy_write(regmap,
1226                                        CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);
1227                 /* Set reset register values to disable SSC */
1228                 cdns_torrent_phy_write(regmap,
1229                                        CMN_PLL0_SS_CTRL1_M0, 0x0002);
1230                 cdns_torrent_phy_write(regmap,
1231                                        CMN_PLL0_SS_CTRL2_M0, 0x0000);
1232                 cdns_torrent_phy_write(regmap,
1233                                        CMN_PLL0_SS_CTRL3_M0, 0x0000);
1234                 cdns_torrent_phy_write(regmap,
1235                                        CMN_PLL0_SS_CTRL4_M0, 0x0000);
1236                 cdns_torrent_phy_write(regmap,
1237                                        CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
1238                 cdns_torrent_phy_write(regmap,
1239                                        CMN_PLL1_SS_CTRL1_M0, 0x0002);
1240                 cdns_torrent_phy_write(regmap,
1241                                        CMN_PLL1_SS_CTRL2_M0, 0x0000);
1242                 cdns_torrent_phy_write(regmap,
1243                                        CMN_PLL1_SS_CTRL3_M0, 0x0000);
1244                 cdns_torrent_phy_write(regmap,
1245                                        CMN_PLL1_SS_CTRL4_M0, 0x0000);
1246                 cdns_torrent_phy_write(regmap,
1247                                        CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
1248         }
1249
1250         cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099);
1251         cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099);
1252         cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099);
1253         cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
1254 }
1255
1256 static
1257 void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy)
1258 {
1259         struct regmap *regmap = cdns_phy->regmap_common_cdb;
1260
1261         /* refclock registers - assumes 25 MHz refclock */
1262         cdns_torrent_phy_write(regmap, CMN_SSM_BIAS_TMR, 0x0019);
1263         cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLPRE_TMR, 0x0032);
1264         cdns_torrent_phy_write(regmap, CMN_PLLSM0_PLLLOCK_TMR, 0x00D1);
1265         cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLPRE_TMR, 0x0032);
1266         cdns_torrent_phy_write(regmap, CMN_PLLSM1_PLLLOCK_TMR, 0x00D1);
1267         cdns_torrent_phy_write(regmap, CMN_BGCAL_INIT_TMR, 0x007D);
1268         cdns_torrent_phy_write(regmap, CMN_BGCAL_ITER_TMR, 0x007D);
1269         cdns_torrent_phy_write(regmap, CMN_IBCAL_INIT_TMR, 0x0019);
1270         cdns_torrent_phy_write(regmap, CMN_TXPUCAL_INIT_TMR, 0x001E);
1271         cdns_torrent_phy_write(regmap, CMN_TXPUCAL_ITER_TMR, 0x0006);
1272         cdns_torrent_phy_write(regmap, CMN_TXPDCAL_INIT_TMR, 0x001E);
1273         cdns_torrent_phy_write(regmap, CMN_TXPDCAL_ITER_TMR, 0x0006);
1274         cdns_torrent_phy_write(regmap, CMN_RXCAL_INIT_TMR, 0x02EE);
1275         cdns_torrent_phy_write(regmap, CMN_RXCAL_ITER_TMR, 0x0006);
1276         cdns_torrent_phy_write(regmap, CMN_SD_CAL_INIT_TMR, 0x0002);
1277         cdns_torrent_phy_write(regmap, CMN_SD_CAL_ITER_TMR, 0x0002);
1278         cdns_torrent_phy_write(regmap, CMN_SD_CAL_REFTIM_START, 0x000E);
1279         cdns_torrent_phy_write(regmap, CMN_SD_CAL_PLLCNT_START, 0x012B);
1280
1281         /* PLL registers */
1282         cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
1283         cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
1284         cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
1285         cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
1286         cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
1287         cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
1288         cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
1289         cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
1290         cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_INIT_TMR, 0x00FA);
1291         cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_ITER_TMR, 0x0004);
1292         cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_INIT_TMR, 0x00FA);
1293         cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_ITER_TMR, 0x0004);
1294         cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_REFTIM_START, 0x0317);
1295         cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_TCTRL, 0x0003);
1296         cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_REFTIM_START, 0x0317);
1297         cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_TCTRL, 0x0003);
1298 }
1299
1300 /*
1301  * Set registers responsible for enabling and configuring SSC, with second
1302  * register value provided by a parameter.
1303  */
1304 static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy,
1305                                              u32 ctrl2_val)
1306 {
1307         struct regmap *regmap = cdns_phy->regmap_common_cdb;
1308
1309         cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
1310         cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
1311         cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F);
1312         cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
1313         cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
1314         cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
1315         cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F);
1316         cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
1317 }
1318
1319 static
1320 void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
1321                                            u32 rate, bool ssc)
1322 {
1323         struct regmap *regmap = cdns_phy->regmap_common_cdb;
1324
1325         /* Assumes 25 MHz refclock */
1326         switch (rate) {
1327         /* Setting VCO for 10.8GHz */
1328         case 2700:
1329         case 5400:
1330                 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0);
1331                 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
1332                 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1333                 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120);
1334                 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0);
1335                 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
1336                 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1337                 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120);
1338                 if (ssc)
1339                         cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423);
1340                 break;
1341         /* Setting VCO for 9.72GHz */
1342         case 1620:
1343         case 2430:
1344         case 3240:
1345                 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184);
1346                 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD);
1347                 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1348                 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104);
1349                 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184);
1350                 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD);
1351                 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1352                 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104);
1353                 if (ssc)
1354                         cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9);
1355                 break;
1356         /* Setting VCO for 8.64GHz */
1357         case 2160:
1358         case 4320:
1359                 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159);
1360                 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A);
1361                 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1362                 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7);
1363                 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159);
1364                 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A);
1365                 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1366                 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7);
1367                 if (ssc)
1368                         cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F);
1369                 break;
1370         /* Setting VCO for 8.1GHz */
1371         case 8100:
1372                 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144);
1373                 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
1374                 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
1375                 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8);
1376                 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144);
1377                 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
1378                 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
1379                 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8);
1380                 if (ssc)
1381                         cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A);
1382                 break;
1383         }
1384
1385         cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
1386         cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
1387
1388         if (ssc) {
1389                 cdns_torrent_phy_write(regmap,
1390                                        CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315);
1391                 cdns_torrent_phy_write(regmap,
1392                                        CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
1393                 cdns_torrent_phy_write(regmap,
1394                                        CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315);
1395                 cdns_torrent_phy_write(regmap,
1396                                        CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
1397         } else {
1398                 cdns_torrent_phy_write(regmap,
1399                                        CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317);
1400                 cdns_torrent_phy_write(regmap,
1401                                        CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317);
1402                 /* Set reset register values to disable SSC */
1403                 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
1404                 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
1405                 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
1406                 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
1407                 cdns_torrent_phy_write(regmap,
1408                                        CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
1409                 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
1410                 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
1411                 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
1412                 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
1413                 cdns_torrent_phy_write(regmap,
1414                                        CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
1415         }
1416
1417         cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7);
1418         cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7);
1419         cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7);
1420         cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
1421 }
1422
1423 static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
1424                                          u32 rate, u32 num_lanes)
1425 {
1426         unsigned int clk_sel_val = 0;
1427         unsigned int hsclk_div_val = 0;
1428         unsigned int i;
1429
1430         /* 16'h0000 for single DP link configuration */
1431         regmap_field_write(cdns_phy->phy_pll_cfg, 0x0);
1432
1433         switch (rate) {
1434         case 1620:
1435                 clk_sel_val = 0x0f01;
1436                 hsclk_div_val = 2;
1437                 break;
1438         case 2160:
1439         case 2430:
1440         case 2700:
1441                 clk_sel_val = 0x0701;
1442                 hsclk_div_val = 1;
1443                 break;
1444         case 3240:
1445                 clk_sel_val = 0x0b00;
1446                 hsclk_div_val = 2;
1447                 break;
1448         case 4320:
1449         case 5400:
1450                 clk_sel_val = 0x0301;
1451                 hsclk_div_val = 0;
1452                 break;
1453         case 8100:
1454                 clk_sel_val = 0x0200;
1455                 hsclk_div_val = 0;
1456                 break;
1457         }
1458
1459         cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1460                                CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
1461         cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1462                                CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
1463
1464         /* PMA lane configuration to deal with multi-link operation */
1465         for (i = 0; i < num_lanes; i++)
1466                 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i],
1467                                        XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
1468 }
1469
1470 static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
1471                                          unsigned int lane)
1472 {
1473         /* Per lane, refclock-dependent receiver detection setting */
1474         if (cdns_phy->ref_clk_rate == REF_CLK_19_2MHz)
1475                 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1476                                        TX_RCVDET_ST_TMR, 0x0780);
1477         else if (cdns_phy->ref_clk_rate == REF_CLK_25MHz)
1478                 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1479                                        TX_RCVDET_ST_TMR, 0x09C4);
1480
1481         /* Writing Tx/Rx Power State Controllers registers */
1482         cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1483                                TX_PSC_A0, 0x00FB);
1484         cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1485                                TX_PSC_A2, 0x04AA);
1486         cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1487                                TX_PSC_A3, 0x04AA);
1488         cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1489                                RX_PSC_A0, 0x0000);
1490         cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1491                                RX_PSC_A2, 0x0000);
1492         cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1493                                RX_PSC_A3, 0x0000);
1494
1495         cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1496                                RX_PSC_CAL, 0x0000);
1497
1498         cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1499                                RX_REE_GCSM1_CTRL, 0x0000);
1500         cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1501                                RX_REE_GCSM2_CTRL, 0x0000);
1502         cdns_torrent_phy_write(cdns_phy->regmap_rx_lane_cdb[lane],
1503                                RX_REE_PERGCSM_CTRL, 0x0000);
1504
1505         cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1506                                XCVR_DIAG_BIDI_CTRL, 0x000F);
1507         cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1508                                XCVR_DIAG_PLLDRC_CTRL, 0x0001);
1509         cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1510                                XCVR_DIAG_HSCLK_SEL, 0x0000);
1511 }
1512
1513 static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
1514                                            u32 num_lanes,
1515                                            enum phy_powerstate powerstate)
1516 {
1517         /* Register value for power state for a single byte. */
1518         u32 value_part;
1519         u32 value;
1520         u32 mask;
1521         u32 read_val;
1522         u32 ret;
1523         struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1524
1525         switch (powerstate) {
1526         case (POWERSTATE_A0):
1527                 value_part = 0x01U;
1528                 break;
1529         case (POWERSTATE_A2):
1530                 value_part = 0x04U;
1531                 break;
1532         default:
1533                 /* Powerstate A3 */
1534                 value_part = 0x08U;
1535                 break;
1536         }
1537
1538         /* Select values of registers and mask, depending on enabled
1539          * lane count.
1540          */
1541         switch (num_lanes) {
1542         /* lane 0 */
1543         case (1):
1544                 value = value_part;
1545                 mask = 0x0000003FU;
1546                 break;
1547         /* lanes 0-1 */
1548         case (2):
1549                 value = (value_part
1550                          | (value_part << 8));
1551                 mask = 0x00003F3FU;
1552                 break;
1553         /* lanes 0-3, all */
1554         default:
1555                 value = (value_part
1556                          | (value_part << 8)
1557                          | (value_part << 16)
1558                          | (value_part << 24));
1559                 mask = 0x3F3F3F3FU;
1560                 break;
1561         }
1562
1563         /* Set power state A<n>. */
1564         cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);
1565         /* Wait, until PHY acknowledges power state completion. */
1566         ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,
1567                                        read_val, (read_val & mask) == value, 0,
1568                                        POLL_TIMEOUT_US);
1569         cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
1570         ndelay(100);
1571
1572         return ret;
1573 }
1574
1575 static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
1576 {
1577         unsigned int read_val;
1578         int ret;
1579         struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1580
1581         /*
1582          * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
1583          * master lane
1584          */
1585         ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
1586                                        read_val, read_val & 1,
1587                                        0, POLL_TIMEOUT_US);
1588         if (ret == -ETIMEDOUT) {
1589                 dev_err(cdns_phy->dev,
1590                         "timeout waiting for link PLL clock enable ack\n");
1591                 return ret;
1592         }
1593
1594         ndelay(100);
1595
1596         ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
1597                                               POWERSTATE_A2);
1598         if (ret)
1599                 return ret;
1600
1601         ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
1602                                               POWERSTATE_A0);
1603
1604         return ret;
1605 }
1606
1607 static int cdns_torrent_phy_on(struct phy *phy)
1608 {
1609         struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1610         struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1611         u32 read_val;
1612         int ret;
1613
1614         if (cdns_phy->nsubnodes == 1) {
1615                 /* Take the PHY lane group out of reset */
1616                 reset_control_deassert(inst->lnk_rst);
1617
1618                 /* Take the PHY out of reset */
1619                 ret = reset_control_deassert(cdns_phy->phy_rst);
1620                 if (ret)
1621                         return ret;
1622         }
1623
1624         /*
1625          * Wait for cmn_ready assertion
1626          * PHY_PMA_CMN_CTRL1[0] == 1
1627          */
1628         ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
1629                                              read_val, read_val, 1000,
1630                                              PLL_LOCK_TIMEOUT);
1631         if (ret) {
1632                 dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
1633                 return ret;
1634         }
1635
1636         mdelay(10);
1637
1638         return 0;
1639 }
1640
1641 static int cdns_torrent_phy_off(struct phy *phy)
1642 {
1643         struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1644         struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1645         int ret;
1646
1647         if (cdns_phy->nsubnodes != 1)
1648                 return 0;
1649
1650         ret = reset_control_assert(cdns_phy->phy_rst);
1651         if (ret)
1652                 return ret;
1653
1654         return reset_control_assert(inst->lnk_rst);
1655 }
1656
1657 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
1658                                        u32 block_offset,
1659                                        u8 reg_offset_shift,
1660                                        const struct regmap_config *config)
1661 {
1662         struct cdns_regmap_cdb_context *ctx;
1663
1664         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1665         if (!ctx)
1666                 return ERR_PTR(-ENOMEM);
1667
1668         ctx->dev = dev;
1669         ctx->base = base + block_offset;
1670         ctx->reg_offset_shift = reg_offset_shift;
1671
1672         return devm_regmap_init(dev, NULL, ctx, config);
1673 }
1674
1675 static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy)
1676 {
1677         struct device *dev = cdns_phy->dev;
1678         struct regmap_field *field;
1679         struct regmap *regmap;
1680
1681         regmap = cdns_phy->regmap_dptx_phy_reg;
1682         field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl);
1683         if (IS_ERR(field)) {
1684                 dev_err(dev, "PHY_RESET reg field init failed\n");
1685                 return PTR_ERR(field);
1686         }
1687         cdns_phy->phy_reset_ctrl = field;
1688
1689         return 0;
1690 }
1691
1692 static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy)
1693 {
1694         struct device *dev = cdns_phy->dev;
1695         struct regmap_field *field;
1696         struct regmap *regmap;
1697
1698         regmap = cdns_phy->regmap_phy_pcs_common_cdb;
1699         field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg);
1700         if (IS_ERR(field)) {
1701                 dev_err(dev, "PHY_PLL_CFG reg field init failed\n");
1702                 return PTR_ERR(field);
1703         }
1704         cdns_phy->phy_pll_cfg = field;
1705
1706         regmap = cdns_phy->regmap_phy_pma_common_cdb;
1707         field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1);
1708         if (IS_ERR(field)) {
1709                 dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n");
1710                 return PTR_ERR(field);
1711         }
1712         cdns_phy->phy_pma_cmn_ctrl_1 = field;
1713
1714         regmap = cdns_phy->regmap_phy_pma_common_cdb;
1715         field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2);
1716         if (IS_ERR(field)) {
1717                 dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n");
1718                 return PTR_ERR(field);
1719         }
1720         cdns_phy->phy_pma_cmn_ctrl_2 = field;
1721
1722         regmap = cdns_phy->regmap_phy_pma_common_cdb;
1723         field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl);
1724         if (IS_ERR(field)) {
1725                 dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n");
1726                 return PTR_ERR(field);
1727         }
1728         cdns_phy->phy_pma_pll_raw_ctrl = field;
1729
1730         return 0;
1731 }
1732
1733 static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy)
1734 {
1735         void __iomem *base = cdns_phy->base;
1736         struct device *dev = cdns_phy->dev;
1737         struct regmap *regmap;
1738         u8 reg_offset_shift;
1739         u32 block_offset;
1740
1741         reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
1742
1743         block_offset = TORRENT_DPTX_PHY_OFFSET;
1744         regmap = cdns_regmap_init(dev, base, block_offset,
1745                                   reg_offset_shift,
1746                                   &cdns_torrent_dptx_phy_config);
1747         if (IS_ERR(regmap)) {
1748                 dev_err(dev, "Failed to init DPTX PHY regmap\n");
1749                 return PTR_ERR(regmap);
1750         }
1751         cdns_phy->regmap_dptx_phy_reg = regmap;
1752
1753         return 0;
1754 }
1755
1756 static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy)
1757 {
1758         void __iomem *sd_base = cdns_phy->sd_base;
1759         u8 block_offset_shift, reg_offset_shift;
1760         struct device *dev = cdns_phy->dev;
1761         struct regmap *regmap;
1762         u32 block_offset;
1763         int i;
1764
1765         block_offset_shift = cdns_phy->init_data->block_offset_shift;
1766         reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
1767
1768         for (i = 0; i < MAX_NUM_LANES; i++) {
1769                 block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift,
1770                                                           reg_offset_shift);
1771                 regmap = cdns_regmap_init(dev, sd_base, block_offset,
1772                                           reg_offset_shift,
1773                                           &cdns_torrent_tx_lane_cdb_config[i]);
1774                 if (IS_ERR(regmap)) {
1775                         dev_err(dev, "Failed to init tx lane CDB regmap\n");
1776                         return PTR_ERR(regmap);
1777                 }
1778                 cdns_phy->regmap_tx_lane_cdb[i] = regmap;
1779
1780                 block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift,
1781                                                           reg_offset_shift);
1782                 regmap = cdns_regmap_init(dev, sd_base, block_offset,
1783                                           reg_offset_shift,
1784                                           &cdns_torrent_rx_lane_cdb_config[i]);
1785                 if (IS_ERR(regmap)) {
1786                         dev_err(dev, "Failed to init rx lane CDB regmap\n");
1787                         return PTR_ERR(regmap);
1788                 }
1789                 cdns_phy->regmap_rx_lane_cdb[i] = regmap;
1790         }
1791
1792         block_offset = TORRENT_COMMON_CDB_OFFSET;
1793         regmap = cdns_regmap_init(dev, sd_base, block_offset,
1794                                   reg_offset_shift,
1795                                   &cdns_torrent_common_cdb_config);
1796         if (IS_ERR(regmap)) {
1797                 dev_err(dev, "Failed to init common CDB regmap\n");
1798                 return PTR_ERR(regmap);
1799         }
1800         cdns_phy->regmap_common_cdb = regmap;
1801
1802         block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift);
1803         regmap = cdns_regmap_init(dev, sd_base, block_offset,
1804                                   reg_offset_shift,
1805                                   &cdns_torrent_phy_pcs_cmn_cdb_config);
1806         if (IS_ERR(regmap)) {
1807                 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
1808                 return PTR_ERR(regmap);
1809         }
1810         cdns_phy->regmap_phy_pcs_common_cdb = regmap;
1811
1812         block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift);
1813         regmap = cdns_regmap_init(dev, sd_base, block_offset,
1814                                   reg_offset_shift,
1815                                   &cdns_torrent_phy_pma_cmn_cdb_config);
1816         if (IS_ERR(regmap)) {
1817                 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
1818                 return PTR_ERR(regmap);
1819         }
1820         cdns_phy->regmap_phy_pma_common_cdb = regmap;
1821
1822         return 0;
1823 }
1824
1825 static int cdns_torrent_phy_init(struct phy *phy)
1826 {
1827         struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1828         const struct cdns_torrent_data *init_data = cdns_phy->init_data;
1829         struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
1830         struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
1831         struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1832         enum cdns_torrent_phy_type phy_type = inst->phy_type;
1833         enum cdns_torrent_ssc_mode ssc = inst->ssc_mode;
1834         struct cdns_torrent_vals *pcs_cmn_vals;
1835         struct cdns_reg_pairs *reg_pairs;
1836         struct regmap *regmap;
1837         u32 num_regs;
1838         int i, j;
1839
1840         if (cdns_phy->nsubnodes > 1)
1841                 return 0;
1842
1843         if (phy_type == TYPE_DP)
1844                 return cdns_torrent_dp_init(phy);
1845
1846         /**
1847          * Spread spectrum generation is not required or supported
1848          * for SGMII/QSGMII
1849          */
1850         if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII)
1851                 ssc = NO_SSC;
1852
1853         /* PHY configuration specific registers for single link */
1854         link_cmn_vals = init_data->link_cmn_vals[phy_type][TYPE_NONE][ssc];
1855         if (link_cmn_vals) {
1856                 reg_pairs = link_cmn_vals->reg_pairs;
1857                 num_regs = link_cmn_vals->num_regs;
1858                 regmap = cdns_phy->regmap_common_cdb;
1859
1860                 /**
1861                  * First array value in link_cmn_vals must be of
1862                  * PHY_PLL_CFG register
1863                  */
1864                 regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val);
1865
1866                 for (i = 1; i < num_regs; i++)
1867                         regmap_write(regmap, reg_pairs[i].off,
1868                                      reg_pairs[i].val);
1869         }
1870
1871         xcvr_diag_vals = init_data->xcvr_diag_vals[phy_type][TYPE_NONE][ssc];
1872         if (xcvr_diag_vals) {
1873                 reg_pairs = xcvr_diag_vals->reg_pairs;
1874                 num_regs = xcvr_diag_vals->num_regs;
1875                 for (i = 0; i < inst->num_lanes; i++) {
1876                         regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
1877                         for (j = 0; j < num_regs; j++)
1878                                 regmap_write(regmap, reg_pairs[j].off,
1879                                              reg_pairs[j].val);
1880                 }
1881         }
1882
1883         /* PHY PCS common registers configurations */
1884         pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
1885         if (pcs_cmn_vals) {
1886                 reg_pairs = pcs_cmn_vals->reg_pairs;
1887                 num_regs = pcs_cmn_vals->num_regs;
1888                 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
1889                 for (i = 0; i < num_regs; i++)
1890                         regmap_write(regmap, reg_pairs[i].off,
1891                                      reg_pairs[i].val);
1892         }
1893
1894         /* PMA common registers configurations */
1895         cmn_vals = init_data->cmn_vals[phy_type][TYPE_NONE][ssc];
1896         if (cmn_vals) {
1897                 reg_pairs = cmn_vals->reg_pairs;
1898                 num_regs = cmn_vals->num_regs;
1899                 regmap = cdns_phy->regmap_common_cdb;
1900                 for (i = 0; i < num_regs; i++)
1901                         regmap_write(regmap, reg_pairs[i].off,
1902                                      reg_pairs[i].val);
1903         }
1904
1905         /* PMA TX lane registers configurations */
1906         tx_ln_vals = init_data->tx_ln_vals[phy_type][TYPE_NONE][ssc];
1907         if (tx_ln_vals) {
1908                 reg_pairs = tx_ln_vals->reg_pairs;
1909                 num_regs = tx_ln_vals->num_regs;
1910                 for (i = 0; i < inst->num_lanes; i++) {
1911                         regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
1912                         for (j = 0; j < num_regs; j++)
1913                                 regmap_write(regmap, reg_pairs[j].off,
1914                                              reg_pairs[j].val);
1915                 }
1916         }
1917
1918         /* PMA RX lane registers configurations */
1919         rx_ln_vals = init_data->rx_ln_vals[phy_type][TYPE_NONE][ssc];
1920         if (rx_ln_vals) {
1921                 reg_pairs = rx_ln_vals->reg_pairs;
1922                 num_regs = rx_ln_vals->num_regs;
1923                 for (i = 0; i < inst->num_lanes; i++) {
1924                         regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane];
1925                         for (j = 0; j < num_regs; j++)
1926                                 regmap_write(regmap, reg_pairs[j].off,
1927                                              reg_pairs[j].val);
1928                 }
1929         }
1930
1931         return 0;
1932 }
1933
1934 static
1935 int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
1936 {
1937         const struct cdns_torrent_data *init_data = cdns_phy->init_data;
1938         struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
1939         struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
1940         enum cdns_torrent_phy_type phy_t1, phy_t2, tmp_phy_type;
1941         struct cdns_torrent_vals *pcs_cmn_vals;
1942         int i, j, node, mlane, num_lanes, ret;
1943         struct cdns_reg_pairs *reg_pairs;
1944         enum cdns_torrent_ssc_mode ssc;
1945         struct regmap *regmap;
1946         u32 num_regs;
1947
1948         /* Maximum 2 links (subnodes) are supported */
1949         if (cdns_phy->nsubnodes != 2)
1950                 return -EINVAL;
1951
1952         phy_t1 = cdns_phy->phys[0].phy_type;
1953         phy_t2 = cdns_phy->phys[1].phy_type;
1954
1955         /**
1956          * First configure the PHY for first link with phy_t1. Get the array
1957          * values as [phy_t1][phy_t2][ssc].
1958          */
1959         for (node = 0; node < cdns_phy->nsubnodes; node++) {
1960                 if (node == 1) {
1961                         /**
1962                          * If first link with phy_t1 is configured, then
1963                          * configure the PHY for second link with phy_t2.
1964                          * Get the array values as [phy_t2][phy_t1][ssc].
1965                          */
1966                         tmp_phy_type = phy_t1;
1967                         phy_t1 = phy_t2;
1968                         phy_t2 = tmp_phy_type;
1969                 }
1970
1971                 mlane = cdns_phy->phys[node].mlane;
1972                 ssc = cdns_phy->phys[node].ssc_mode;
1973                 num_lanes = cdns_phy->phys[node].num_lanes;
1974
1975                 /**
1976                  * PHY configuration specific registers:
1977                  * link_cmn_vals depend on combination of PHY types being
1978                  * configured and are common for both PHY types, so array
1979                  * values should be same for [phy_t1][phy_t2][ssc] and
1980                  * [phy_t2][phy_t1][ssc].
1981                  * xcvr_diag_vals also depend on combination of PHY types
1982                  * being configured, but these can be different for particular
1983                  * PHY type and are per lane.
1984                  */
1985                 link_cmn_vals = init_data->link_cmn_vals[phy_t1][phy_t2][ssc];
1986                 if (link_cmn_vals) {
1987                         reg_pairs = link_cmn_vals->reg_pairs;
1988                         num_regs = link_cmn_vals->num_regs;
1989                         regmap = cdns_phy->regmap_common_cdb;
1990
1991                         /**
1992                          * First array value in link_cmn_vals must be of
1993                          * PHY_PLL_CFG register
1994                          */
1995                         regmap_field_write(cdns_phy->phy_pll_cfg,
1996                                            reg_pairs[0].val);
1997
1998                         for (i = 1; i < num_regs; i++)
1999                                 regmap_write(regmap, reg_pairs[i].off,
2000                                              reg_pairs[i].val);
2001                 }
2002
2003                 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_t1][phy_t2][ssc];
2004                 if (xcvr_diag_vals) {
2005                         reg_pairs = xcvr_diag_vals->reg_pairs;
2006                         num_regs = xcvr_diag_vals->num_regs;
2007                         for (i = 0; i < num_lanes; i++) {
2008                                 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
2009                                 for (j = 0; j < num_regs; j++)
2010                                         regmap_write(regmap, reg_pairs[j].off,
2011                                                      reg_pairs[j].val);
2012                         }
2013                 }
2014
2015                 /* PHY PCS common registers configurations */
2016                 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc];
2017                 if (pcs_cmn_vals) {
2018                         reg_pairs = pcs_cmn_vals->reg_pairs;
2019                         num_regs = pcs_cmn_vals->num_regs;
2020                         regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2021                         for (i = 0; i < num_regs; i++)
2022                                 regmap_write(regmap, reg_pairs[i].off,
2023                                              reg_pairs[i].val);
2024                 }
2025
2026                 /* PMA common registers configurations */
2027                 cmn_vals = init_data->cmn_vals[phy_t1][phy_t2][ssc];
2028                 if (cmn_vals) {
2029                         reg_pairs = cmn_vals->reg_pairs;
2030                         num_regs = cmn_vals->num_regs;
2031                         regmap = cdns_phy->regmap_common_cdb;
2032                         for (i = 0; i < num_regs; i++)
2033                                 regmap_write(regmap, reg_pairs[i].off,
2034                                              reg_pairs[i].val);
2035                 }
2036
2037                 /* PMA TX lane registers configurations */
2038                 tx_ln_vals = init_data->tx_ln_vals[phy_t1][phy_t2][ssc];
2039                 if (tx_ln_vals) {
2040                         reg_pairs = tx_ln_vals->reg_pairs;
2041                         num_regs = tx_ln_vals->num_regs;
2042                         for (i = 0; i < num_lanes; i++) {
2043                                 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
2044                                 for (j = 0; j < num_regs; j++)
2045                                         regmap_write(regmap, reg_pairs[j].off,
2046                                                      reg_pairs[j].val);
2047                         }
2048                 }
2049
2050                 /* PMA RX lane registers configurations */
2051                 rx_ln_vals = init_data->rx_ln_vals[phy_t1][phy_t2][ssc];
2052                 if (rx_ln_vals) {
2053                         reg_pairs = rx_ln_vals->reg_pairs;
2054                         num_regs = rx_ln_vals->num_regs;
2055                         for (i = 0; i < num_lanes; i++) {
2056                                 regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane];
2057                                 for (j = 0; j < num_regs; j++)
2058                                         regmap_write(regmap, reg_pairs[j].off,
2059                                                      reg_pairs[j].val);
2060                         }
2061                 }
2062
2063                 reset_control_deassert(cdns_phy->phys[node].lnk_rst);
2064         }
2065
2066         /* Take the PHY out of reset */
2067         ret = reset_control_deassert(cdns_phy->phy_rst);
2068         if (ret)
2069                 return ret;
2070
2071         return 0;
2072 }
2073
2074 static int cdns_torrent_phy_probe(struct platform_device *pdev)
2075 {
2076         struct cdns_torrent_phy *cdns_phy;
2077         struct device *dev = &pdev->dev;
2078         struct phy_provider *phy_provider;
2079         const struct cdns_torrent_data *data;
2080         struct device_node *child;
2081         int ret, subnodes, node = 0, i;
2082         u32 total_num_lanes = 0;
2083         u8 init_dp_regmap = 0;
2084         u32 phy_type;
2085
2086         /* Get init data for this PHY */
2087         data = of_device_get_match_data(dev);
2088         if (!data)
2089                 return -EINVAL;
2090
2091         cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
2092         if (!cdns_phy)
2093                 return -ENOMEM;
2094
2095         dev_set_drvdata(dev, cdns_phy);
2096         cdns_phy->dev = dev;
2097         cdns_phy->init_data = data;
2098
2099         cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0);
2100         if (IS_ERR(cdns_phy->phy_rst)) {
2101                 dev_err(dev, "%s: failed to get reset\n",
2102                         dev->of_node->full_name);
2103                 return PTR_ERR(cdns_phy->phy_rst);
2104         }
2105
2106         cdns_phy->apb_rst = devm_reset_control_get_optional(dev, "torrent_apb");
2107         if (IS_ERR(cdns_phy->apb_rst)) {
2108                 dev_err(dev, "%s: failed to get apb reset\n",
2109                         dev->of_node->full_name);
2110                 return PTR_ERR(cdns_phy->apb_rst);
2111         }
2112
2113         cdns_phy->clk = devm_clk_get(dev, "refclk");
2114         if (IS_ERR(cdns_phy->clk)) {
2115                 dev_err(dev, "phy ref clock not found\n");
2116                 return PTR_ERR(cdns_phy->clk);
2117         }
2118
2119         cdns_phy->sd_base = devm_platform_ioremap_resource(pdev, 0);
2120         if (IS_ERR(cdns_phy->sd_base))
2121                 return PTR_ERR(cdns_phy->sd_base);
2122
2123         subnodes = of_get_available_child_count(dev->of_node);
2124         if (subnodes == 0) {
2125                 dev_err(dev, "No available link subnodes found\n");
2126                 return -EINVAL;
2127         }
2128
2129         ret = cdns_torrent_regmap_init(cdns_phy);
2130         if (ret)
2131                 return ret;
2132
2133         ret = cdns_torrent_regfield_init(cdns_phy);
2134         if (ret)
2135                 return ret;
2136
2137         ret = clk_prepare_enable(cdns_phy->clk);
2138         if (ret) {
2139                 dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
2140                 return ret;
2141         }
2142
2143         cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk);
2144         if (!(cdns_phy->ref_clk_rate)) {
2145                 dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
2146                 clk_disable_unprepare(cdns_phy->clk);
2147                 return -EINVAL;
2148         }
2149
2150         /* Enable APB */
2151         reset_control_deassert(cdns_phy->apb_rst);
2152
2153         for_each_available_child_of_node(dev->of_node, child) {
2154                 struct phy *gphy;
2155
2156                 /* PHY subnode name must be 'phy'. */
2157                 if (!(of_node_name_eq(child, "phy")))
2158                         continue;
2159
2160                 cdns_phy->phys[node].lnk_rst =
2161                                 of_reset_control_array_get_exclusive(child);
2162                 if (IS_ERR(cdns_phy->phys[node].lnk_rst)) {
2163                         dev_err(dev, "%s: failed to get reset\n",
2164                                 child->full_name);
2165                         ret = PTR_ERR(cdns_phy->phys[node].lnk_rst);
2166                         goto put_lnk_rst;
2167                 }
2168
2169                 if (of_property_read_u32(child, "reg",
2170                                          &cdns_phy->phys[node].mlane)) {
2171                         dev_err(dev, "%s: No \"reg\"-property.\n",
2172                                 child->full_name);
2173                         ret = -EINVAL;
2174                         goto put_child;
2175                 }
2176
2177                 if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) {
2178                         dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n",
2179                                 child->full_name);
2180                         ret = -EINVAL;
2181                         goto put_child;
2182                 }
2183
2184                 switch (phy_type) {
2185                 case PHY_TYPE_PCIE:
2186                         cdns_phy->phys[node].phy_type = TYPE_PCIE;
2187                         break;
2188                 case PHY_TYPE_DP:
2189                         cdns_phy->phys[node].phy_type = TYPE_DP;
2190                         break;
2191                 case PHY_TYPE_SGMII:
2192                         cdns_phy->phys[node].phy_type = TYPE_SGMII;
2193                         break;
2194                 case PHY_TYPE_QSGMII:
2195                         cdns_phy->phys[node].phy_type = TYPE_QSGMII;
2196                         break;
2197                 case PHY_TYPE_USB3:
2198                         cdns_phy->phys[node].phy_type = TYPE_USB;
2199                         break;
2200                 default:
2201                         dev_err(dev, "Unsupported protocol\n");
2202                         ret = -EINVAL;
2203                         goto put_child;
2204                 }
2205
2206                 if (of_property_read_u32(child, "cdns,num-lanes",
2207                                          &cdns_phy->phys[node].num_lanes)) {
2208                         dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n",
2209                                 child->full_name);
2210                         ret = -EINVAL;
2211                         goto put_child;
2212                 }
2213
2214                 total_num_lanes += cdns_phy->phys[node].num_lanes;
2215
2216                 /* Get SSC mode */
2217                 cdns_phy->phys[node].ssc_mode = NO_SSC;
2218                 of_property_read_u32(child, "cdns,ssc-mode",
2219                                      &cdns_phy->phys[node].ssc_mode);
2220
2221                 gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops);
2222                 if (IS_ERR(gphy)) {
2223                         ret = PTR_ERR(gphy);
2224                         goto put_child;
2225                 }
2226
2227                 if (cdns_phy->phys[node].phy_type == TYPE_DP) {
2228                         switch (cdns_phy->phys[node].num_lanes) {
2229                         case 1:
2230                         case 2:
2231                         case 4:
2232                         /* valid number of lanes */
2233                                 break;
2234                         default:
2235                                 dev_err(dev, "unsupported number of lanes: %d\n",
2236                                         cdns_phy->phys[node].num_lanes);
2237                                 ret = -EINVAL;
2238                                 goto put_child;
2239                         }
2240
2241                         cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE;
2242                         of_property_read_u32(child, "cdns,max-bit-rate",
2243                                              &cdns_phy->max_bit_rate);
2244
2245                         switch (cdns_phy->max_bit_rate) {
2246                         case 1620:
2247                         case 2160:
2248                         case 2430:
2249                         case 2700:
2250                         case 3240:
2251                         case 4320:
2252                         case 5400:
2253                         case 8100:
2254                         /* valid bit rate */
2255                                 break;
2256                         default:
2257                                 dev_err(dev, "unsupported max bit rate: %dMbps\n",
2258                                         cdns_phy->max_bit_rate);
2259                                 ret = -EINVAL;
2260                                 goto put_child;
2261                         }
2262
2263                         /* DPTX registers */
2264                         cdns_phy->base = devm_platform_ioremap_resource(pdev, 1);
2265                         if (IS_ERR(cdns_phy->base)) {
2266                                 ret = PTR_ERR(cdns_phy->base);
2267                                 goto put_child;
2268                         }
2269
2270                         if (!init_dp_regmap) {
2271                                 ret = cdns_torrent_dp_regmap_init(cdns_phy);
2272                                 if (ret)
2273                                         goto put_child;
2274
2275                                 ret = cdns_torrent_dp_regfield_init(cdns_phy);
2276                                 if (ret)
2277                                         goto put_child;
2278
2279                                 init_dp_regmap++;
2280                         }
2281
2282                         dev_info(dev, "%d lanes, max bit rate %d.%03d Gbps\n",
2283                                  cdns_phy->phys[node].num_lanes,
2284                                  cdns_phy->max_bit_rate / 1000,
2285                                  cdns_phy->max_bit_rate % 1000);
2286
2287                         gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes;
2288                         gphy->attrs.max_link_rate = cdns_phy->max_bit_rate;
2289                         gphy->attrs.mode = PHY_MODE_DP;
2290                 }
2291
2292                 cdns_phy->phys[node].phy = gphy;
2293                 phy_set_drvdata(gphy, &cdns_phy->phys[node]);
2294
2295                 node++;
2296         }
2297         cdns_phy->nsubnodes = node;
2298
2299         if (total_num_lanes > MAX_NUM_LANES) {
2300                 dev_err(dev, "Invalid lane configuration\n");
2301                 goto put_lnk_rst;
2302         }
2303
2304         if (cdns_phy->nsubnodes > 1) {
2305                 ret = cdns_torrent_phy_configure_multilink(cdns_phy);
2306                 if (ret)
2307                         goto put_lnk_rst;
2308         }
2309
2310         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2311         if (IS_ERR(phy_provider)) {
2312                 ret = PTR_ERR(phy_provider);
2313                 goto put_lnk_rst;
2314         }
2315
2316         return 0;
2317
2318 put_child:
2319         node++;
2320 put_lnk_rst:
2321         for (i = 0; i < node; i++)
2322                 reset_control_put(cdns_phy->phys[i].lnk_rst);
2323         of_node_put(child);
2324         reset_control_assert(cdns_phy->apb_rst);
2325         clk_disable_unprepare(cdns_phy->clk);
2326         return ret;
2327 }
2328
2329 static int cdns_torrent_phy_remove(struct platform_device *pdev)
2330 {
2331         struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev);
2332         int i;
2333
2334         reset_control_assert(cdns_phy->phy_rst);
2335         reset_control_assert(cdns_phy->apb_rst);
2336         for (i = 0; i < cdns_phy->nsubnodes; i++) {
2337                 reset_control_assert(cdns_phy->phys[i].lnk_rst);
2338                 reset_control_put(cdns_phy->phys[i].lnk_rst);
2339         }
2340
2341         clk_disable_unprepare(cdns_phy->clk);
2342
2343         return 0;
2344 }
2345
2346 /* USB and SGMII/QSGMII link configuration */
2347 static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {
2348         {0x0002, PHY_PLL_CFG},
2349         {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0},
2350         {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
2351 };
2352
2353 static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = {
2354         {0x0000, XCVR_DIAG_HSCLK_SEL},
2355         {0x0001, XCVR_DIAG_HSCLK_DIV},
2356         {0x0041, XCVR_DIAG_PLLDRC_CTRL}
2357 };
2358
2359 static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = {
2360         {0x0011, XCVR_DIAG_HSCLK_SEL},
2361         {0x0003, XCVR_DIAG_HSCLK_DIV},
2362         {0x009B, XCVR_DIAG_PLLDRC_CTRL}
2363 };
2364
2365 static struct cdns_torrent_vals usb_sgmii_link_cmn_vals = {
2366         .reg_pairs = usb_sgmii_link_cmn_regs,
2367         .num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs),
2368 };
2369
2370 static struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = {
2371         .reg_pairs = usb_sgmii_xcvr_diag_ln_regs,
2372         .num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs),
2373 };
2374
2375 static struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = {
2376         .reg_pairs = sgmii_usb_xcvr_diag_ln_regs,
2377         .num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs),
2378 };
2379
2380 /* PCIe and USB Unique SSC link configuration */
2381 static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = {
2382         {0x0003, PHY_PLL_CFG},
2383         {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
2384         {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
2385         {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0}
2386 };
2387
2388 static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = {
2389         {0x0000, XCVR_DIAG_HSCLK_SEL},
2390         {0x0001, XCVR_DIAG_HSCLK_DIV},
2391         {0x0012, XCVR_DIAG_PLLDRC_CTRL}
2392 };
2393
2394 static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = {
2395         {0x0011, XCVR_DIAG_HSCLK_SEL},
2396         {0x0001, XCVR_DIAG_HSCLK_DIV},
2397         {0x00C9, XCVR_DIAG_PLLDRC_CTRL}
2398 };
2399
2400 static struct cdns_torrent_vals pcie_usb_link_cmn_vals = {
2401         .reg_pairs = pcie_usb_link_cmn_regs,
2402         .num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs),
2403 };
2404
2405 static struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = {
2406         .reg_pairs = pcie_usb_xcvr_diag_ln_regs,
2407         .num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs),
2408 };
2409
2410 static struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = {
2411         .reg_pairs = usb_pcie_xcvr_diag_ln_regs,
2412         .num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs),
2413 };
2414
2415 /* USB 100 MHz Ref clk, internal SSC */
2416 static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = {
2417         {0x0004, CMN_PLL0_DSM_DIAG_M0},
2418         {0x0004, CMN_PLL0_DSM_DIAG_M1},
2419         {0x0004, CMN_PLL1_DSM_DIAG_M0},
2420         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
2421         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
2422         {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
2423         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
2424         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
2425         {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
2426         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
2427         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
2428         {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
2429         {0x0064, CMN_PLL0_INTDIV_M0},
2430         {0x0050, CMN_PLL0_INTDIV_M1},
2431         {0x0064, CMN_PLL1_INTDIV_M0},
2432         {0x0002, CMN_PLL0_FRACDIVH_M0},
2433         {0x0002, CMN_PLL0_FRACDIVH_M1},
2434         {0x0002, CMN_PLL1_FRACDIVH_M0},
2435         {0x0044, CMN_PLL0_HIGH_THR_M0},
2436         {0x0036, CMN_PLL0_HIGH_THR_M1},
2437         {0x0044, CMN_PLL1_HIGH_THR_M0},
2438         {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
2439         {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
2440         {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
2441         {0x0001, CMN_PLL0_SS_CTRL1_M0},
2442         {0x0001, CMN_PLL0_SS_CTRL1_M1},
2443         {0x0001, CMN_PLL1_SS_CTRL1_M0},
2444         {0x011B, CMN_PLL0_SS_CTRL2_M0},
2445         {0x011B, CMN_PLL0_SS_CTRL2_M1},
2446         {0x011B, CMN_PLL1_SS_CTRL2_M0},
2447         {0x006E, CMN_PLL0_SS_CTRL3_M0},
2448         {0x0058, CMN_PLL0_SS_CTRL3_M1},
2449         {0x006E, CMN_PLL1_SS_CTRL3_M0},
2450         {0x000E, CMN_PLL0_SS_CTRL4_M0},
2451         {0x0012, CMN_PLL0_SS_CTRL4_M1},
2452         {0x000E, CMN_PLL1_SS_CTRL4_M0},
2453         {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
2454         {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
2455         {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
2456         {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
2457         {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2458         {0x0003, CMN_PLL1_VCOCAL_TCTRL},
2459         {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
2460         {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
2461         {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
2462         {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
2463         {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
2464         {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
2465         {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
2466         {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
2467 };
2468
2469 static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = {
2470         .reg_pairs = usb_100_int_ssc_cmn_regs,
2471         .num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs),
2472 };
2473
2474 /* Single USB link configuration */
2475 static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = {
2476         {0x0000, PHY_PLL_CFG},
2477         {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
2478 };
2479
2480 static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = {
2481         {0x0000, XCVR_DIAG_HSCLK_SEL},
2482         {0x0001, XCVR_DIAG_HSCLK_DIV},
2483         {0x0041, XCVR_DIAG_PLLDRC_CTRL}
2484 };
2485
2486 static struct cdns_torrent_vals sl_usb_link_cmn_vals = {
2487         .reg_pairs = sl_usb_link_cmn_regs,
2488         .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs),
2489 };
2490
2491 static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = {
2492         .reg_pairs = sl_usb_xcvr_diag_ln_regs,
2493         .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs),
2494 };
2495
2496 /* USB PHY PCS common configuration */
2497 static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = {
2498         {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0},
2499         {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0},
2500         {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1}
2501 };
2502
2503 static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = {
2504         .reg_pairs = usb_phy_pcs_cmn_regs,
2505         .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs),
2506 };
2507
2508 /* USB 100 MHz Ref clk, no SSC */
2509 static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = {
2510         {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2511         {0x0003, CMN_PLL1_VCOCAL_TCTRL},
2512         {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
2513         {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
2514 };
2515
2516 static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = {
2517         {0x02FF, TX_PSC_A0},
2518         {0x06AF, TX_PSC_A1},
2519         {0x06AE, TX_PSC_A2},
2520         {0x06AE, TX_PSC_A3},
2521         {0x2A82, TX_TXCC_CTRL},
2522         {0x0014, TX_TXCC_CPOST_MULT_01},
2523         {0x0003, XCVR_DIAG_PSC_OVRD}
2524 };
2525
2526 static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = {
2527         {0x0D1D, RX_PSC_A0},
2528         {0x0D1D, RX_PSC_A1},
2529         {0x0D00, RX_PSC_A2},
2530         {0x0500, RX_PSC_A3},
2531         {0x0013, RX_SIGDET_HL_FILT_TMR},
2532         {0x0000, RX_REE_GCSM1_CTRL},
2533         {0x0C02, RX_REE_ATTEN_THR},
2534         {0x0330, RX_REE_SMGM_CTRL1},
2535         {0x0300, RX_REE_SMGM_CTRL2},
2536         {0x0019, RX_REE_TAP1_CLIP},
2537         {0x0019, RX_REE_TAP2TON_CLIP},
2538         {0x1004, RX_DIAG_SIGDET_TUNE},
2539         {0x00F9, RX_DIAG_NQST_CTRL},
2540         {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
2541         {0x0002, RX_DIAG_DFE_AMP_TUNE_3},
2542         {0x0000, RX_DIAG_PI_CAP},
2543         {0x0031, RX_DIAG_PI_RATE},
2544         {0x0001, RX_DIAG_ACYA},
2545         {0x018C, RX_CDRLF_CNFG},
2546         {0x0003, RX_CDRLF_CNFG3}
2547 };
2548
2549 static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = {
2550         .reg_pairs = usb_100_no_ssc_cmn_regs,
2551         .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs),
2552 };
2553
2554 static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = {
2555         .reg_pairs = usb_100_no_ssc_tx_ln_regs,
2556         .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs),
2557 };
2558
2559 static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = {
2560         .reg_pairs = usb_100_no_ssc_rx_ln_regs,
2561         .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs),
2562 };
2563
2564 /* Single link USB, 100 MHz Ref clk, internal SSC */
2565 static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = {
2566         {0x0004, CMN_PLL0_DSM_DIAG_M0},
2567         {0x0004, CMN_PLL1_DSM_DIAG_M0},
2568         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
2569         {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
2570         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
2571         {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
2572         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
2573         {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
2574         {0x0064, CMN_PLL0_INTDIV_M0},
2575         {0x0064, CMN_PLL1_INTDIV_M0},
2576         {0x0002, CMN_PLL0_FRACDIVH_M0},
2577         {0x0002, CMN_PLL1_FRACDIVH_M0},
2578         {0x0044, CMN_PLL0_HIGH_THR_M0},
2579         {0x0044, CMN_PLL1_HIGH_THR_M0},
2580         {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
2581         {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
2582         {0x0001, CMN_PLL0_SS_CTRL1_M0},
2583         {0x0001, CMN_PLL1_SS_CTRL1_M0},
2584         {0x011B, CMN_PLL0_SS_CTRL2_M0},
2585         {0x011B, CMN_PLL1_SS_CTRL2_M0},
2586         {0x006E, CMN_PLL0_SS_CTRL3_M0},
2587         {0x006E, CMN_PLL1_SS_CTRL3_M0},
2588         {0x000E, CMN_PLL0_SS_CTRL4_M0},
2589         {0x000E, CMN_PLL1_SS_CTRL4_M0},
2590         {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
2591         {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
2592         {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
2593         {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
2594         {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2595         {0x0003, CMN_PLL1_VCOCAL_TCTRL},
2596         {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
2597         {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
2598         {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
2599         {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
2600         {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
2601         {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
2602         {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
2603         {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
2604 };
2605
2606 static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = {
2607         .reg_pairs = sl_usb_100_int_ssc_cmn_regs,
2608         .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs),
2609 };
2610
2611 /* PCIe and SGMII/QSGMII Unique SSC link configuration */
2612 static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = {
2613         {0x0003, PHY_PLL_CFG},
2614         {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
2615         {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
2616         {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
2617 };
2618
2619 static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = {
2620         {0x0000, XCVR_DIAG_HSCLK_SEL},
2621         {0x0001, XCVR_DIAG_HSCLK_DIV},
2622         {0x0012, XCVR_DIAG_PLLDRC_CTRL}
2623 };
2624
2625 static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = {
2626         {0x0011, XCVR_DIAG_HSCLK_SEL},
2627         {0x0003, XCVR_DIAG_HSCLK_DIV},
2628         {0x009B, XCVR_DIAG_PLLDRC_CTRL}
2629 };
2630
2631 static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = {
2632         .reg_pairs = pcie_sgmii_link_cmn_regs,
2633         .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs),
2634 };
2635
2636 static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = {
2637         .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs,
2638         .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs),
2639 };
2640
2641 static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = {
2642         .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs,
2643         .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs),
2644 };
2645
2646 /* SGMII 100 MHz Ref clk, no SSC */
2647 static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = {
2648         {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2649         {0x0003, CMN_PLL1_VCOCAL_TCTRL},
2650         {0x3700, CMN_DIAG_BIAS_OVRD1},
2651         {0x0008, CMN_TXPUCAL_TUNE},
2652         {0x0008, CMN_TXPDCAL_TUNE}
2653 };
2654
2655 static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = {
2656         {0x00F3, TX_PSC_A0},
2657         {0x04A2, TX_PSC_A2},
2658         {0x04A2, TX_PSC_A3},
2659         {0x0000, TX_TXCC_CPOST_MULT_00},
2660         {0x00B3, DRV_DIAG_TX_DRV}
2661 };
2662
2663 static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = {
2664         {0x091D, RX_PSC_A0},
2665         {0x0900, RX_PSC_A2},
2666         {0x0100, RX_PSC_A3},
2667         {0x03C7, RX_REE_GCSM1_EQENM_PH1},
2668         {0x01C7, RX_REE_GCSM1_EQENM_PH2},
2669         {0x0000, RX_DIAG_DFE_CTRL},
2670         {0x0019, RX_REE_TAP1_CLIP},
2671         {0x0019, RX_REE_TAP2TON_CLIP},
2672         {0x0098, RX_DIAG_NQST_CTRL},
2673         {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
2674         {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
2675         {0x0000, RX_DIAG_PI_CAP},
2676         {0x0010, RX_DIAG_PI_RATE},
2677         {0x0001, RX_DIAG_ACYA},
2678         {0x018C, RX_CDRLF_CNFG},
2679 };
2680
2681 static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = {
2682         .reg_pairs = sgmii_100_no_ssc_cmn_regs,
2683         .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs),
2684 };
2685
2686 static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = {
2687         .reg_pairs = sgmii_100_no_ssc_tx_ln_regs,
2688         .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs),
2689 };
2690
2691 static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = {
2692         .reg_pairs = sgmii_100_no_ssc_rx_ln_regs,
2693         .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs),
2694 };
2695
2696 /* SGMII 100 MHz Ref clk, internal SSC */
2697 static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = {
2698         {0x0004, CMN_PLL0_DSM_DIAG_M0},
2699         {0x0004, CMN_PLL0_DSM_DIAG_M1},
2700         {0x0004, CMN_PLL1_DSM_DIAG_M0},
2701         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
2702         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
2703         {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
2704         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
2705         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
2706         {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
2707         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
2708         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
2709         {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
2710         {0x0064, CMN_PLL0_INTDIV_M0},
2711         {0x0050, CMN_PLL0_INTDIV_M1},
2712         {0x0064, CMN_PLL1_INTDIV_M0},
2713         {0x0002, CMN_PLL0_FRACDIVH_M0},
2714         {0x0002, CMN_PLL0_FRACDIVH_M1},
2715         {0x0002, CMN_PLL1_FRACDIVH_M0},
2716         {0x0044, CMN_PLL0_HIGH_THR_M0},
2717         {0x0036, CMN_PLL0_HIGH_THR_M1},
2718         {0x0044, CMN_PLL1_HIGH_THR_M0},
2719         {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
2720         {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
2721         {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
2722         {0x0001, CMN_PLL0_SS_CTRL1_M0},
2723         {0x0001, CMN_PLL0_SS_CTRL1_M1},
2724         {0x0001, CMN_PLL1_SS_CTRL1_M0},
2725         {0x011B, CMN_PLL0_SS_CTRL2_M0},
2726         {0x011B, CMN_PLL0_SS_CTRL2_M1},
2727         {0x011B, CMN_PLL1_SS_CTRL2_M0},
2728         {0x006E, CMN_PLL0_SS_CTRL3_M0},
2729         {0x0058, CMN_PLL0_SS_CTRL3_M1},
2730         {0x006E, CMN_PLL1_SS_CTRL3_M0},
2731         {0x000E, CMN_PLL0_SS_CTRL4_M0},
2732         {0x0012, CMN_PLL0_SS_CTRL4_M1},
2733         {0x000E, CMN_PLL1_SS_CTRL4_M0},
2734         {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
2735         {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
2736         {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
2737         {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
2738         {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2739         {0x0003, CMN_PLL1_VCOCAL_TCTRL},
2740         {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
2741         {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
2742         {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
2743         {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
2744         {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
2745         {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
2746         {0x3700, CMN_DIAG_BIAS_OVRD1},
2747         {0x0008, CMN_TXPUCAL_TUNE},
2748         {0x0008, CMN_TXPDCAL_TUNE}
2749 };
2750
2751 static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = {
2752         .reg_pairs = sgmii_100_int_ssc_cmn_regs,
2753         .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs),
2754 };
2755
2756 /* QSGMII 100 MHz Ref clk, no SSC */
2757 static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = {
2758         {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2759         {0x0003, CMN_PLL1_VCOCAL_TCTRL}
2760 };
2761
2762 static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = {
2763         {0x00F3, TX_PSC_A0},
2764         {0x04A2, TX_PSC_A2},
2765         {0x04A2, TX_PSC_A3},
2766         {0x0000, TX_TXCC_CPOST_MULT_00},
2767         {0x0003, DRV_DIAG_TX_DRV}
2768 };
2769
2770 static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = {
2771         {0x091D, RX_PSC_A0},
2772         {0x0900, RX_PSC_A2},
2773         {0x0100, RX_PSC_A3},
2774         {0x03C7, RX_REE_GCSM1_EQENM_PH1},
2775         {0x01C7, RX_REE_GCSM1_EQENM_PH2},
2776         {0x0000, RX_DIAG_DFE_CTRL},
2777         {0x0019, RX_REE_TAP1_CLIP},
2778         {0x0019, RX_REE_TAP2TON_CLIP},
2779         {0x0098, RX_DIAG_NQST_CTRL},
2780         {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
2781         {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
2782         {0x0000, RX_DIAG_PI_CAP},
2783         {0x0010, RX_DIAG_PI_RATE},
2784         {0x0001, RX_DIAG_ACYA},
2785         {0x018C, RX_CDRLF_CNFG},
2786 };
2787
2788 static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = {
2789         .reg_pairs = qsgmii_100_no_ssc_cmn_regs,
2790         .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs),
2791 };
2792
2793 static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = {
2794         .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs,
2795         .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs),
2796 };
2797
2798 static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = {
2799         .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs,
2800         .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs),
2801 };
2802
2803 /* QSGMII 100 MHz Ref clk, internal SSC */
2804 static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = {
2805         {0x0004, CMN_PLL0_DSM_DIAG_M0},
2806         {0x0004, CMN_PLL0_DSM_DIAG_M1},
2807         {0x0004, CMN_PLL1_DSM_DIAG_M0},
2808         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
2809         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
2810         {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
2811         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
2812         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
2813         {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
2814         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
2815         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
2816         {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
2817         {0x0064, CMN_PLL0_INTDIV_M0},
2818         {0x0050, CMN_PLL0_INTDIV_M1},
2819         {0x0064, CMN_PLL1_INTDIV_M0},
2820         {0x0002, CMN_PLL0_FRACDIVH_M0},
2821         {0x0002, CMN_PLL0_FRACDIVH_M1},
2822         {0x0002, CMN_PLL1_FRACDIVH_M0},
2823         {0x0044, CMN_PLL0_HIGH_THR_M0},
2824         {0x0036, CMN_PLL0_HIGH_THR_M1},
2825         {0x0044, CMN_PLL1_HIGH_THR_M0},
2826         {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
2827         {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
2828         {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
2829         {0x0001, CMN_PLL0_SS_CTRL1_M0},
2830         {0x0001, CMN_PLL0_SS_CTRL1_M1},
2831         {0x0001, CMN_PLL1_SS_CTRL1_M0},
2832         {0x011B, CMN_PLL0_SS_CTRL2_M0},
2833         {0x011B, CMN_PLL0_SS_CTRL2_M1},
2834         {0x011B, CMN_PLL1_SS_CTRL2_M0},
2835         {0x006E, CMN_PLL0_SS_CTRL3_M0},
2836         {0x0058, CMN_PLL0_SS_CTRL3_M1},
2837         {0x006E, CMN_PLL1_SS_CTRL3_M0},
2838         {0x000E, CMN_PLL0_SS_CTRL4_M0},
2839         {0x0012, CMN_PLL0_SS_CTRL4_M1},
2840         {0x000E, CMN_PLL1_SS_CTRL4_M0},
2841         {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
2842         {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
2843         {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
2844         {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
2845         {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2846         {0x0003, CMN_PLL1_VCOCAL_TCTRL},
2847         {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
2848         {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
2849         {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
2850         {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
2851         {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
2852         {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
2853 };
2854
2855 static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = {
2856         .reg_pairs = qsgmii_100_int_ssc_cmn_regs,
2857         .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs),
2858 };
2859
2860 /* Single SGMII/QSGMII link configuration */
2861 static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = {
2862         {0x0000, PHY_PLL_CFG},
2863         {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
2864 };
2865
2866 static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = {
2867         {0x0000, XCVR_DIAG_HSCLK_SEL},
2868         {0x0003, XCVR_DIAG_HSCLK_DIV},
2869         {0x0013, XCVR_DIAG_PLLDRC_CTRL}
2870 };
2871
2872 static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = {
2873         .reg_pairs = sl_sgmii_link_cmn_regs,
2874         .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs),
2875 };
2876
2877 static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
2878         .reg_pairs = sl_sgmii_xcvr_diag_ln_regs,
2879         .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
2880 };
2881
2882 /* Multi link PCIe, 100 MHz Ref clk, internal SSC */
2883 static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
2884         {0x0004, CMN_PLL0_DSM_DIAG_M0},
2885         {0x0004, CMN_PLL0_DSM_DIAG_M1},
2886         {0x0004, CMN_PLL1_DSM_DIAG_M0},
2887         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
2888         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
2889         {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
2890         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
2891         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
2892         {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
2893         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
2894         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
2895         {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
2896         {0x0064, CMN_PLL0_INTDIV_M0},
2897         {0x0050, CMN_PLL0_INTDIV_M1},
2898         {0x0064, CMN_PLL1_INTDIV_M0},
2899         {0x0002, CMN_PLL0_FRACDIVH_M0},
2900         {0x0002, CMN_PLL0_FRACDIVH_M1},
2901         {0x0002, CMN_PLL1_FRACDIVH_M0},
2902         {0x0044, CMN_PLL0_HIGH_THR_M0},
2903         {0x0036, CMN_PLL0_HIGH_THR_M1},
2904         {0x0044, CMN_PLL1_HIGH_THR_M0},
2905         {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
2906         {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
2907         {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
2908         {0x0001, CMN_PLL0_SS_CTRL1_M0},
2909         {0x0001, CMN_PLL0_SS_CTRL1_M1},
2910         {0x0001, CMN_PLL1_SS_CTRL1_M0},
2911         {0x011B, CMN_PLL0_SS_CTRL2_M0},
2912         {0x011B, CMN_PLL0_SS_CTRL2_M1},
2913         {0x011B, CMN_PLL1_SS_CTRL2_M0},
2914         {0x006E, CMN_PLL0_SS_CTRL3_M0},
2915         {0x0058, CMN_PLL0_SS_CTRL3_M1},
2916         {0x006E, CMN_PLL1_SS_CTRL3_M0},
2917         {0x000E, CMN_PLL0_SS_CTRL4_M0},
2918         {0x0012, CMN_PLL0_SS_CTRL4_M1},
2919         {0x000E, CMN_PLL1_SS_CTRL4_M0},
2920         {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
2921         {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
2922         {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
2923         {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
2924         {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2925         {0x0003, CMN_PLL1_VCOCAL_TCTRL},
2926         {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
2927         {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
2928         {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
2929         {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
2930         {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
2931         {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
2932 };
2933
2934 static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = {
2935         .reg_pairs = pcie_100_int_ssc_cmn_regs,
2936         .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs),
2937 };
2938
2939 /* Single link PCIe, 100 MHz Ref clk, internal SSC */
2940 static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = {
2941         {0x0004, CMN_PLL0_DSM_DIAG_M0},
2942         {0x0004, CMN_PLL0_DSM_DIAG_M1},
2943         {0x0004, CMN_PLL1_DSM_DIAG_M0},
2944         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
2945         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
2946         {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
2947         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
2948         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
2949         {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
2950         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
2951         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
2952         {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
2953         {0x0064, CMN_PLL0_INTDIV_M0},
2954         {0x0050, CMN_PLL0_INTDIV_M1},
2955         {0x0050, CMN_PLL1_INTDIV_M0},
2956         {0x0002, CMN_PLL0_FRACDIVH_M0},
2957         {0x0002, CMN_PLL0_FRACDIVH_M1},
2958         {0x0002, CMN_PLL1_FRACDIVH_M0},
2959         {0x0044, CMN_PLL0_HIGH_THR_M0},
2960         {0x0036, CMN_PLL0_HIGH_THR_M1},
2961         {0x0036, CMN_PLL1_HIGH_THR_M0},
2962         {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
2963         {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
2964         {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
2965         {0x0001, CMN_PLL0_SS_CTRL1_M0},
2966         {0x0001, CMN_PLL0_SS_CTRL1_M1},
2967         {0x0001, CMN_PLL1_SS_CTRL1_M0},
2968         {0x011B, CMN_PLL0_SS_CTRL2_M0},
2969         {0x011B, CMN_PLL0_SS_CTRL2_M1},
2970         {0x011B, CMN_PLL1_SS_CTRL2_M0},
2971         {0x006E, CMN_PLL0_SS_CTRL3_M0},
2972         {0x0058, CMN_PLL0_SS_CTRL3_M1},
2973         {0x0058, CMN_PLL1_SS_CTRL3_M0},
2974         {0x000E, CMN_PLL0_SS_CTRL4_M0},
2975         {0x0012, CMN_PLL0_SS_CTRL4_M1},
2976         {0x0012, CMN_PLL1_SS_CTRL4_M0},
2977         {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
2978         {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
2979         {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
2980         {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
2981         {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2982         {0x0003, CMN_PLL1_VCOCAL_TCTRL},
2983         {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
2984         {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
2985         {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
2986         {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
2987         {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
2988         {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
2989 };
2990
2991 static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = {
2992         .reg_pairs = sl_pcie_100_int_ssc_cmn_regs,
2993         .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs),
2994 };
2995
2996 /* PCIe, 100 MHz Ref clk, no SSC & external SSC */
2997 static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = {
2998         {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2999         {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3000 };
3001
3002 static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = {
3003         {0x0019, RX_REE_TAP1_CLIP},
3004         {0x0019, RX_REE_TAP2TON_CLIP},
3005         {0x0001, RX_DIAG_ACYA}
3006 };
3007
3008 static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = {
3009         .reg_pairs = pcie_100_ext_no_ssc_cmn_regs,
3010         .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs),
3011 };
3012
3013 static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = {
3014         .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs,
3015         .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs),
3016 };
3017
3018 static const struct cdns_torrent_data cdns_map_torrent = {
3019         .block_offset_shift = 0x2,
3020         .reg_offset_shift = 0x2,
3021         .link_cmn_vals = {
3022                 [TYPE_PCIE] = {
3023                         [TYPE_NONE] = {
3024                                 [NO_SSC] = NULL,
3025                                 [EXTERNAL_SSC] = NULL,
3026                                 [INTERNAL_SSC] = NULL,
3027                         },
3028                         [TYPE_SGMII] = {
3029                                 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3030                                 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3031                                 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3032                         },
3033                         [TYPE_QSGMII] = {
3034                                 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3035                                 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3036                                 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3037                         },
3038                         [TYPE_USB] = {
3039                                 [NO_SSC] = &pcie_usb_link_cmn_vals,
3040                                 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3041                                 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3042                         },
3043                 },
3044                 [TYPE_SGMII] = {
3045                         [TYPE_NONE] = {
3046                                 [NO_SSC] = &sl_sgmii_link_cmn_vals,
3047                         },
3048                         [TYPE_PCIE] = {
3049                                 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3050                                 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3051                                 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3052                         },
3053                         [TYPE_USB] = {
3054                                 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3055                                 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3056                                 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3057                         },
3058                 },
3059                 [TYPE_QSGMII] = {
3060                         [TYPE_NONE] = {
3061                                 [NO_SSC] = &sl_sgmii_link_cmn_vals,
3062                         },
3063                         [TYPE_PCIE] = {
3064                                 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3065                                 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3066                                 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3067                         },
3068                         [TYPE_USB] = {
3069                                 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3070                                 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3071                                 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3072                         },
3073                 },
3074                 [TYPE_USB] = {
3075                         [TYPE_NONE] = {
3076                                 [NO_SSC] = &sl_usb_link_cmn_vals,
3077                                 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
3078                                 [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
3079                         },
3080                         [TYPE_PCIE] = {
3081                                 [NO_SSC] = &pcie_usb_link_cmn_vals,
3082                                 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3083                                 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3084                         },
3085                         [TYPE_SGMII] = {
3086                                 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3087                                 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3088                                 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3089                         },
3090                         [TYPE_QSGMII] = {
3091                                 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3092                                 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3093                                 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3094                         },
3095                 },
3096         },
3097         .xcvr_diag_vals = {
3098                 [TYPE_PCIE] = {
3099                         [TYPE_NONE] = {
3100                                 [NO_SSC] = NULL,
3101                                 [EXTERNAL_SSC] = NULL,
3102                                 [INTERNAL_SSC] = NULL,
3103                         },
3104                         [TYPE_SGMII] = {
3105                                 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3106                                 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3107                                 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3108                         },
3109                         [TYPE_QSGMII] = {
3110                                 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3111                                 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3112                                 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3113                         },
3114                         [TYPE_USB] = {
3115                                 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3116                                 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3117                                 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3118                         },
3119                 },
3120                 [TYPE_SGMII] = {
3121                         [TYPE_NONE] = {
3122                                 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
3123                         },
3124                         [TYPE_PCIE] = {
3125                                 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3126                                 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3127                                 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3128                         },
3129                         [TYPE_USB] = {
3130                                 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3131                                 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3132                                 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3133                         },
3134                 },
3135                 [TYPE_QSGMII] = {
3136                         [TYPE_NONE] = {
3137                                 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
3138                         },
3139                         [TYPE_PCIE] = {
3140                                 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3141                                 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3142                                 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3143                         },
3144                         [TYPE_USB] = {
3145                                 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3146                                 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3147                                 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3148                         },
3149                 },
3150                 [TYPE_USB] = {
3151                         [TYPE_NONE] = {
3152                                 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
3153                                 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
3154                                 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
3155                         },
3156                         [TYPE_PCIE] = {
3157                                 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3158                                 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3159                                 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3160                         },
3161                         [TYPE_SGMII] = {
3162                                 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3163                                 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3164                                 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3165                         },
3166                         [TYPE_QSGMII] = {
3167                                 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3168                                 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3169                                 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3170                         },
3171                 },
3172         },
3173         .pcs_cmn_vals = {
3174                 [TYPE_USB] = {
3175                         [TYPE_NONE] = {
3176                                 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3177                                 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3178                                 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3179                         },
3180                         [TYPE_PCIE] = {
3181                                 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3182                                 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3183                                 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3184                         },
3185                         [TYPE_SGMII] = {
3186                                 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3187                                 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3188                                 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3189                         },
3190                         [TYPE_QSGMII] = {
3191                                 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3192                                 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3193                                 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3194                         },
3195                 },
3196         },
3197         .cmn_vals = {
3198                 [TYPE_PCIE] = {
3199                         [TYPE_NONE] = {
3200                                 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3201                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3202                                 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
3203                         },
3204                         [TYPE_SGMII] = {
3205                                 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3206                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3207                                 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3208                         },
3209                         [TYPE_QSGMII] = {
3210                                 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3211                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3212                                 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3213                         },
3214                         [TYPE_USB] = {
3215                                 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3216                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3217                                 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3218                         },
3219                 },
3220                 [TYPE_SGMII] = {
3221                         [TYPE_NONE] = {
3222                                 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
3223                         },
3224                         [TYPE_PCIE] = {
3225                                 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
3226                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3227                                 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
3228                         },
3229                         [TYPE_USB] = {
3230                                 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
3231                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3232                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3233                         },
3234                 },
3235                 [TYPE_QSGMII] = {
3236                         [TYPE_NONE] = {
3237                                 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3238                         },
3239                         [TYPE_PCIE] = {
3240                                 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3241                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3242                                 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
3243                         },
3244                         [TYPE_USB] = {
3245                                 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3246                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3247                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3248                         },
3249                 },
3250                 [TYPE_USB] = {
3251                         [TYPE_NONE] = {
3252                                 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
3253                                 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
3254                                 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
3255                         },
3256                         [TYPE_PCIE] = {
3257                                 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
3258                                 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
3259                                 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
3260                         },
3261                         [TYPE_SGMII] = {
3262                                 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
3263                                 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
3264                                 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
3265                         },
3266                         [TYPE_QSGMII] = {
3267                                 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
3268                                 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
3269                                 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
3270                         },
3271                 },
3272         },
3273         .tx_ln_vals = {
3274                 [TYPE_PCIE] = {
3275                         [TYPE_NONE] = {
3276                                 [NO_SSC] = NULL,
3277                                 [EXTERNAL_SSC] = NULL,
3278                                 [INTERNAL_SSC] = NULL,
3279                         },
3280                         [TYPE_SGMII] = {
3281                                 [NO_SSC] = NULL,
3282                                 [EXTERNAL_SSC] = NULL,
3283                                 [INTERNAL_SSC] = NULL,
3284                         },
3285                         [TYPE_QSGMII] = {
3286                                 [NO_SSC] = NULL,
3287                                 [EXTERNAL_SSC] = NULL,
3288                                 [INTERNAL_SSC] = NULL,
3289                         },
3290                         [TYPE_USB] = {
3291                                 [NO_SSC] = NULL,
3292                                 [EXTERNAL_SSC] = NULL,
3293                                 [INTERNAL_SSC] = NULL,
3294                         },
3295                 },
3296                 [TYPE_SGMII] = {
3297                         [TYPE_NONE] = {
3298                                 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3299                         },
3300                         [TYPE_PCIE] = {
3301                                 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3302                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3303                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3304                         },
3305                         [TYPE_USB] = {
3306                                 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3307                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3308                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3309                         },
3310                 },
3311                 [TYPE_QSGMII] = {
3312                         [TYPE_NONE] = {
3313                                 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3314                         },
3315                         [TYPE_PCIE] = {
3316                                 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3317                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3318                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3319                         },
3320                         [TYPE_USB] = {
3321                                 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3322                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3323                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3324                         },
3325                 },
3326                 [TYPE_USB] = {
3327                         [TYPE_NONE] = {
3328                                 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
3329                                 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3330                                 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3331                         },
3332                         [TYPE_PCIE] = {
3333                                 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
3334                                 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3335                                 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3336                         },
3337                         [TYPE_SGMII] = {
3338                                 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
3339                                 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3340                                 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3341                         },
3342                         [TYPE_QSGMII] = {
3343                                 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
3344                                 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3345                                 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3346                         },
3347                 },
3348         },
3349         .rx_ln_vals = {
3350                 [TYPE_PCIE] = {
3351                         [TYPE_NONE] = {
3352                                 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3353                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3354                                 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3355                         },
3356                         [TYPE_SGMII] = {
3357                                 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3358                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3359                                 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3360                         },
3361                         [TYPE_QSGMII] = {
3362                                 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3363                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3364                                 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3365                         },
3366                         [TYPE_USB] = {
3367                                 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3368                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3369                                 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3370                         },
3371                 },
3372                 [TYPE_SGMII] = {
3373                         [TYPE_NONE] = {
3374                                 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3375                         },
3376                         [TYPE_PCIE] = {
3377                                 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3378                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3379                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3380                         },
3381                         [TYPE_USB] = {
3382                                 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3383                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3384                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3385                         },
3386                 },
3387                 [TYPE_QSGMII] = {
3388                         [TYPE_NONE] = {
3389                                 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3390                         },
3391                         [TYPE_PCIE] = {
3392                                 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3393                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3394                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3395                         },
3396                         [TYPE_USB] = {
3397                                 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3398                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3399                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3400                         },
3401                 },
3402                 [TYPE_USB] = {
3403                         [TYPE_NONE] = {
3404                                 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
3405                                 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3406                                 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3407                         },
3408                         [TYPE_PCIE] = {
3409                                 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
3410                                 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3411                                 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3412                         },
3413                         [TYPE_SGMII] = {
3414                                 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
3415                                 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3416                                 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3417                         },
3418                         [TYPE_QSGMII] = {
3419                                 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
3420                                 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3421                                 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3422                         },
3423                 },
3424         },
3425 };
3426
3427 static const struct cdns_torrent_data ti_j721e_map_torrent = {
3428         .block_offset_shift = 0x0,
3429         .reg_offset_shift = 0x1,
3430         .link_cmn_vals = {
3431                 [TYPE_PCIE] = {
3432                         [TYPE_NONE] = {
3433                                 [NO_SSC] = NULL,
3434                                 [EXTERNAL_SSC] = NULL,
3435                                 [INTERNAL_SSC] = NULL,
3436                         },
3437                         [TYPE_SGMII] = {
3438                                 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3439                                 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3440                                 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3441                         },
3442                         [TYPE_QSGMII] = {
3443                                 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3444                                 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3445                                 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3446                         },
3447                         [TYPE_USB] = {
3448                                 [NO_SSC] = &pcie_usb_link_cmn_vals,
3449                                 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3450                                 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3451                         },
3452                 },
3453                 [TYPE_SGMII] = {
3454                         [TYPE_NONE] = {
3455                                 [NO_SSC] = &sl_sgmii_link_cmn_vals,
3456                         },
3457                         [TYPE_PCIE] = {
3458                                 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3459                                 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3460                                 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3461                         },
3462                         [TYPE_USB] = {
3463                                 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3464                                 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3465                                 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3466                         },
3467                 },
3468                 [TYPE_QSGMII] = {
3469                         [TYPE_NONE] = {
3470                                 [NO_SSC] = &sl_sgmii_link_cmn_vals,
3471                         },
3472                         [TYPE_PCIE] = {
3473                                 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3474                                 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3475                                 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3476                         },
3477                         [TYPE_USB] = {
3478                                 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3479                                 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3480                                 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3481                         },
3482                 },
3483                 [TYPE_USB] = {
3484                         [TYPE_NONE] = {
3485                                 [NO_SSC] = &sl_usb_link_cmn_vals,
3486                                 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
3487                                 [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
3488                         },
3489                         [TYPE_PCIE] = {
3490                                 [NO_SSC] = &pcie_usb_link_cmn_vals,
3491                                 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3492                                 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3493                         },
3494                         [TYPE_SGMII] = {
3495                                 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3496                                 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3497                                 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3498                         },
3499                         [TYPE_QSGMII] = {
3500                                 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3501                                 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3502                                 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3503                         },
3504                 },
3505         },
3506         .xcvr_diag_vals = {
3507                 [TYPE_PCIE] = {
3508                         [TYPE_NONE] = {
3509                                 [NO_SSC] = NULL,
3510                                 [EXTERNAL_SSC] = NULL,
3511                                 [INTERNAL_SSC] = NULL,
3512                         },
3513                         [TYPE_SGMII] = {
3514                                 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3515                                 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3516                                 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3517                         },
3518                         [TYPE_QSGMII] = {
3519                                 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3520                                 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3521                                 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3522                         },
3523                         [TYPE_USB] = {
3524                                 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3525                                 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3526                                 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3527                         },
3528                 },
3529                 [TYPE_SGMII] = {
3530                         [TYPE_NONE] = {
3531                                 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
3532                         },
3533                         [TYPE_PCIE] = {
3534                                 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3535                                 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3536                                 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3537                         },
3538                         [TYPE_USB] = {
3539                                 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3540                                 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3541                                 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3542                         },
3543                 },
3544                 [TYPE_QSGMII] = {
3545                         [TYPE_NONE] = {
3546                                 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
3547                         },
3548                         [TYPE_PCIE] = {
3549                                 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3550                                 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3551                                 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3552                         },
3553                         [TYPE_USB] = {
3554                                 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3555                                 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3556                                 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3557                         },
3558                 },
3559                 [TYPE_USB] = {
3560                         [TYPE_NONE] = {
3561                                 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
3562                                 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
3563                                 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
3564                         },
3565                         [TYPE_PCIE] = {
3566                                 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3567                                 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3568                                 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3569                         },
3570                         [TYPE_SGMII] = {
3571                                 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3572                                 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3573                                 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3574                         },
3575                         [TYPE_QSGMII] = {
3576                                 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3577                                 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3578                                 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3579                         },
3580                 },
3581         },
3582         .pcs_cmn_vals = {
3583                 [TYPE_USB] = {
3584                         [TYPE_NONE] = {
3585                                 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3586                                 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3587                                 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3588                         },
3589                         [TYPE_PCIE] = {
3590                                 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3591                                 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3592                                 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3593                         },
3594                         [TYPE_SGMII] = {
3595                                 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3596                                 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3597                                 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3598                         },
3599                         [TYPE_QSGMII] = {
3600                                 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3601                                 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3602                                 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3603                         },
3604                 },
3605         },
3606         .cmn_vals = {
3607                 [TYPE_PCIE] = {
3608                         [TYPE_NONE] = {
3609                                 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3610                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3611                                 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
3612                         },
3613                         [TYPE_SGMII] = {
3614                                 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3615                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3616                                 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3617                         },
3618                         [TYPE_QSGMII] = {
3619                                 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3620                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3621                                 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3622                         },
3623                         [TYPE_USB] = {
3624                                 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3625                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3626                                 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3627                         },
3628                 },
3629                 [TYPE_SGMII] = {
3630                         [TYPE_NONE] = {
3631                                 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
3632                         },
3633                         [TYPE_PCIE] = {
3634                                 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
3635                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3636                                 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
3637                         },
3638                         [TYPE_USB] = {
3639                                 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
3640                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3641                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3642                         },
3643                 },
3644                 [TYPE_QSGMII] = {
3645                         [TYPE_NONE] = {
3646                                 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3647                         },
3648                         [TYPE_PCIE] = {
3649                                 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3650                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3651                                 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
3652                         },
3653                         [TYPE_USB] = {
3654                                 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3655                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3656                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3657                         },
3658                 },
3659                 [TYPE_USB] = {
3660                         [TYPE_NONE] = {
3661                                 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
3662                                 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
3663                                 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
3664                         },
3665                         [TYPE_PCIE] = {
3666                                 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
3667                                 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
3668                                 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
3669                         },
3670                         [TYPE_SGMII] = {
3671                                 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
3672                                 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
3673                                 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
3674                         },
3675                         [TYPE_QSGMII] = {
3676                                 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
3677                                 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
3678                                 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
3679                         },
3680                 },
3681         },
3682         .tx_ln_vals = {
3683                 [TYPE_PCIE] = {
3684                         [TYPE_NONE] = {
3685                                 [NO_SSC] = NULL,
3686                                 [EXTERNAL_SSC] = NULL,
3687                                 [INTERNAL_SSC] = NULL,
3688                         },
3689                         [TYPE_SGMII] = {
3690                                 [NO_SSC] = NULL,
3691                                 [EXTERNAL_SSC] = NULL,
3692                                 [INTERNAL_SSC] = NULL,
3693                         },
3694                         [TYPE_QSGMII] = {
3695                                 [NO_SSC] = NULL,
3696                                 [EXTERNAL_SSC] = NULL,
3697                                 [INTERNAL_SSC] = NULL,
3698                         },
3699                         [TYPE_USB] = {
3700                                 [NO_SSC] = NULL,
3701                                 [EXTERNAL_SSC] = NULL,
3702                                 [INTERNAL_SSC] = NULL,
3703                         },
3704                 },
3705                 [TYPE_SGMII] = {
3706                         [TYPE_NONE] = {
3707                                 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3708                         },
3709                         [TYPE_PCIE] = {
3710                                 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3711                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3712                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3713                         },
3714                         [TYPE_USB] = {
3715                                 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3716                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3717                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
3718                         },
3719                 },
3720                 [TYPE_QSGMII] = {
3721                         [TYPE_NONE] = {
3722                                 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3723                         },
3724                         [TYPE_PCIE] = {
3725                                 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3726                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3727                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3728                         },
3729                         [TYPE_USB] = {
3730                                 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3731                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3732                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
3733                         },
3734                 },
3735                 [TYPE_USB] = {
3736                         [TYPE_NONE] = {
3737                                 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
3738                                 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3739                                 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3740                         },
3741                         [TYPE_PCIE] = {
3742                                 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
3743                                 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3744                                 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3745                         },
3746                         [TYPE_SGMII] = {
3747                                 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
3748                                 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3749                                 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3750                         },
3751                         [TYPE_QSGMII] = {
3752                                 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
3753                                 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3754                                 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
3755                         },
3756                 },
3757         },
3758         .rx_ln_vals = {
3759                 [TYPE_PCIE] = {
3760                         [TYPE_NONE] = {
3761                                 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3762                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3763                                 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3764                         },
3765                         [TYPE_SGMII] = {
3766                                 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3767                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3768                                 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3769                         },
3770                         [TYPE_QSGMII] = {
3771                                 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3772                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3773                                 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3774                         },
3775                         [TYPE_USB] = {
3776                                 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3777                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3778                                 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
3779                         },
3780                 },
3781                 [TYPE_SGMII] = {
3782                         [TYPE_NONE] = {
3783                                 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3784                         },
3785                         [TYPE_PCIE] = {
3786                                 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3787                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3788                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3789                         },
3790                         [TYPE_USB] = {
3791                                 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3792                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3793                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
3794                         },
3795                 },
3796                 [TYPE_QSGMII] = {
3797                         [TYPE_NONE] = {
3798                                 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3799                         },
3800                         [TYPE_PCIE] = {
3801                                 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3802                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3803                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3804                         },
3805                         [TYPE_USB] = {
3806                                 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3807                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3808                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
3809                         },
3810                 },
3811                 [TYPE_USB] = {
3812                         [TYPE_NONE] = {
3813                                 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
3814                                 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3815                                 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3816                         },
3817                         [TYPE_PCIE] = {
3818                                 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
3819                                 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3820                                 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3821                         },
3822                         [TYPE_SGMII] = {
3823                                 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
3824                                 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3825                                 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3826                         },
3827                         [TYPE_QSGMII] = {
3828                                 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
3829                                 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3830                                 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
3831                         },
3832                 },
3833         },
3834 };
3835
3836 static const struct of_device_id cdns_torrent_phy_of_match[] = {
3837         {
3838                 .compatible = "cdns,torrent-phy",
3839                 .data = &cdns_map_torrent,
3840         },
3841         {
3842                 .compatible = "ti,j721e-serdes-10g",
3843                 .data = &ti_j721e_map_torrent,
3844         },
3845         {}
3846 };
3847 MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match);
3848
3849 static struct platform_driver cdns_torrent_phy_driver = {
3850         .probe  = cdns_torrent_phy_probe,
3851         .remove = cdns_torrent_phy_remove,
3852         .driver = {
3853                 .name   = "cdns-torrent-phy",
3854                 .of_match_table = cdns_torrent_phy_of_match,
3855         }
3856 };
3857 module_platform_driver(cdns_torrent_phy_driver);
3858
3859 MODULE_AUTHOR("Cadence Design Systems, Inc.");
3860 MODULE_DESCRIPTION("Cadence Torrent PHY driver");
3861 MODULE_LICENSE("GPL v2");