1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence Torrent SD0801 PHY driver.
5 * Copyright 2018 Cadence Design Systems, Inc.
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/phy/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/reset.h>
25 #include <linux/regmap.h>
27 #define REF_CLK_19_2MHZ 19200000
28 #define REF_CLK_25MHZ 25000000
29 #define REF_CLK_100MHZ 100000000
31 #define MAX_NUM_LANES 4
32 #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */
34 #define NUM_SSC_MODE 3
36 #define NUM_PHY_TYPE 6
38 #define POLL_TIMEOUT_US 5000
39 #define PLL_LOCK_TIMEOUT 100000
41 #define TORRENT_COMMON_CDB_OFFSET 0x0
43 #define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
44 ((0x4000 << (block_offset)) + \
45 (((ln) << 9) << (reg_offset)))
47 #define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
48 ((0x8000 << (block_offset)) + \
49 (((ln) << 9) << (reg_offset)))
51 #define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \
52 (0xC000 << (block_offset))
54 #define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
55 ((0xD000 << (block_offset)) + \
56 (((ln) << 8) << (reg_offset)))
58 #define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \
59 (0xE000 << (block_offset))
61 #define TORRENT_DPTX_PHY_OFFSET 0x0
64 * register offsets from DPTX PHY register block base (i.e MHDP
65 * register base + 0x30a00)
67 #define PHY_AUX_CTRL 0x04
68 #define PHY_RESET 0x20
69 #define PMA_TX_ELEC_IDLE_MASK 0xF0U
70 #define PMA_TX_ELEC_IDLE_SHIFT 4
71 #define PHY_L00_RESET_N_MASK 0x01U
72 #define PHY_PMA_XCVR_PLLCLK_EN 0x24
73 #define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28
74 #define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c
75 #define PHY_POWER_STATE_LN_0 0x0000
76 #define PHY_POWER_STATE_LN_1 0x0008
77 #define PHY_POWER_STATE_LN_2 0x0010
78 #define PHY_POWER_STATE_LN_3 0x0018
79 #define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU
80 #define PHY_PMA_XCVR_POWER_STATE_ACK 0x30
81 #define PHY_PMA_CMN_READY 0x34
84 * register offsets from SD0801 PHY register block base (i.e MHDP
85 * register base + 0x500000)
87 #define CMN_SSM_BANDGAP_TMR 0x0021U
88 #define CMN_SSM_BIAS_TMR 0x0022U
89 #define CMN_PLLSM0_PLLPRE_TMR 0x002AU
90 #define CMN_PLLSM0_PLLLOCK_TMR 0x002CU
91 #define CMN_PLLSM1_PLLPRE_TMR 0x0032U
92 #define CMN_PLLSM1_PLLLOCK_TMR 0x0034U
93 #define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U
94 #define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U
95 #define CMN_CDIAG_REFCLK_OVRD 0x004CU
96 #define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U
97 #define CMN_BGCAL_INIT_TMR 0x0064U
98 #define CMN_BGCAL_ITER_TMR 0x0065U
99 #define CMN_IBCAL_INIT_TMR 0x0074U
100 #define CMN_PLL0_VCOCAL_TCTRL 0x0082U
101 #define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U
102 #define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U
103 #define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U
104 #define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U
105 #define CMN_PLL0_INTDIV_M0 0x0090U
106 #define CMN_PLL0_FRACDIVL_M0 0x0091U
107 #define CMN_PLL0_FRACDIVH_M0 0x0092U
108 #define CMN_PLL0_HIGH_THR_M0 0x0093U
109 #define CMN_PLL0_DSM_DIAG_M0 0x0094U
110 #define CMN_PLL0_DSM_FBH_OVRD_M0 0x0095U
111 #define CMN_PLL0_SS_CTRL1_M0 0x0098U
112 #define CMN_PLL0_SS_CTRL2_M0 0x0099U
113 #define CMN_PLL0_SS_CTRL3_M0 0x009AU
114 #define CMN_PLL0_SS_CTRL4_M0 0x009BU
115 #define CMN_PLL0_LOCK_REFCNT_START 0x009CU
116 #define CMN_PLL0_LOCK_PLLCNT_START 0x009EU
117 #define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU
118 #define CMN_PLL0_INTDIV_M1 0x00A0U
119 #define CMN_PLL0_FRACDIVH_M1 0x00A2U
120 #define CMN_PLL0_HIGH_THR_M1 0x00A3U
121 #define CMN_PLL0_DSM_DIAG_M1 0x00A4U
122 #define CMN_PLL0_SS_CTRL1_M1 0x00A8U
123 #define CMN_PLL0_SS_CTRL2_M1 0x00A9U
124 #define CMN_PLL0_SS_CTRL3_M1 0x00AAU
125 #define CMN_PLL0_SS_CTRL4_M1 0x00ABU
126 #define CMN_PLL1_VCOCAL_TCTRL 0x00C2U
127 #define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U
128 #define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U
129 #define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U
130 #define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U
131 #define CMN_PLL1_INTDIV_M0 0x00D0U
132 #define CMN_PLL1_FRACDIVL_M0 0x00D1U
133 #define CMN_PLL1_FRACDIVH_M0 0x00D2U
134 #define CMN_PLL1_HIGH_THR_M0 0x00D3U
135 #define CMN_PLL1_DSM_DIAG_M0 0x00D4U
136 #define CMN_PLL1_DSM_FBH_OVRD_M0 0x00D5U
137 #define CMN_PLL1_DSM_FBL_OVRD_M0 0x00D6U
138 #define CMN_PLL1_SS_CTRL1_M0 0x00D8U
139 #define CMN_PLL1_SS_CTRL2_M0 0x00D9U
140 #define CMN_PLL1_SS_CTRL3_M0 0x00DAU
141 #define CMN_PLL1_SS_CTRL4_M0 0x00DBU
142 #define CMN_PLL1_LOCK_REFCNT_START 0x00DCU
143 #define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU
144 #define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU
145 #define CMN_TXPUCAL_TUNE 0x0103U
146 #define CMN_TXPUCAL_INIT_TMR 0x0104U
147 #define CMN_TXPUCAL_ITER_TMR 0x0105U
148 #define CMN_TXPDCAL_TUNE 0x010BU
149 #define CMN_TXPDCAL_INIT_TMR 0x010CU
150 #define CMN_TXPDCAL_ITER_TMR 0x010DU
151 #define CMN_RXCAL_INIT_TMR 0x0114U
152 #define CMN_RXCAL_ITER_TMR 0x0115U
153 #define CMN_SD_CAL_INIT_TMR 0x0124U
154 #define CMN_SD_CAL_ITER_TMR 0x0125U
155 #define CMN_SD_CAL_REFTIM_START 0x0126U
156 #define CMN_SD_CAL_PLLCNT_START 0x0128U
157 #define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U
158 #define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U
159 #define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U
160 #define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U
161 #define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U
162 #define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U
163 #define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01B1U
164 #define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U
165 #define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U
166 #define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U
167 #define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U
168 #define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U
169 #define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U
170 #define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U
171 #define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U
172 #define CMN_DIAG_BIAS_OVRD1 0x01E1U
174 /* PMA TX Lane registers */
175 #define TX_TXCC_CTRL 0x0040U
176 #define TX_TXCC_CPOST_MULT_00 0x004CU
177 #define TX_TXCC_CPOST_MULT_01 0x004DU
178 #define TX_TXCC_MGNFS_MULT_000 0x0050U
179 #define TX_TXCC_MGNFS_MULT_100 0x0054U
180 #define DRV_DIAG_TX_DRV 0x00C6U
181 #define XCVR_DIAG_PLLDRC_CTRL 0x00E5U
182 #define XCVR_DIAG_HSCLK_SEL 0x00E6U
183 #define XCVR_DIAG_HSCLK_DIV 0x00E7U
184 #define XCVR_DIAG_RXCLK_CTRL 0x00E9U
185 #define XCVR_DIAG_BIDI_CTRL 0x00EAU
186 #define XCVR_DIAG_PSC_OVRD 0x00EBU
187 #define TX_PSC_A0 0x0100U
188 #define TX_PSC_A1 0x0101U
189 #define TX_PSC_A2 0x0102U
190 #define TX_PSC_A3 0x0103U
191 #define TX_RCVDET_ST_TMR 0x0123U
192 #define TX_DIAG_ACYA 0x01E7U
193 #define TX_DIAG_ACYA_HBDC_MASK 0x0001U
195 /* PMA RX Lane registers */
196 #define RX_PSC_A0 0x0000U
197 #define RX_PSC_A1 0x0001U
198 #define RX_PSC_A2 0x0002U
199 #define RX_PSC_A3 0x0003U
200 #define RX_PSC_CAL 0x0006U
201 #define RX_CDRLF_CNFG 0x0080U
202 #define RX_CDRLF_CNFG3 0x0082U
203 #define RX_SIGDET_HL_FILT_TMR 0x0090U
204 #define RX_REE_GCSM1_CTRL 0x0108U
205 #define RX_REE_GCSM1_EQENM_PH1 0x0109U
206 #define RX_REE_GCSM1_EQENM_PH2 0x010AU
207 #define RX_REE_GCSM2_CTRL 0x0110U
208 #define RX_REE_PERGCSM_CTRL 0x0118U
209 #define RX_REE_ATTEN_THR 0x0149U
210 #define RX_REE_TAP1_CLIP 0x0171U
211 #define RX_REE_TAP2TON_CLIP 0x0172U
212 #define RX_REE_SMGM_CTRL1 0x0177U
213 #define RX_REE_SMGM_CTRL2 0x0178U
214 #define RX_DIAG_DFE_CTRL 0x01E0U
215 #define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U
216 #define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U
217 #define RX_DIAG_NQST_CTRL 0x01E5U
218 #define RX_DIAG_SIGDET_TUNE 0x01E8U
219 #define RX_DIAG_PI_RATE 0x01F4U
220 #define RX_DIAG_PI_CAP 0x01F5U
221 #define RX_DIAG_ACYA 0x01FFU
223 /* PHY PCS common registers */
224 #define PHY_PIPE_CMN_CTRL1 0x0000U
225 #define PHY_PLL_CFG 0x000EU
226 #define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U
227 #define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U
228 #define PHY_PIPE_USB3_GEN2_POST_CFG1 0x0023U
230 /* PHY PCS lane registers */
231 #define PHY_PCS_ISO_LINK_CTRL 0x000BU
233 /* PHY PMA common registers */
234 #define PHY_PMA_CMN_CTRL1 0x0000U
235 #define PHY_PMA_CMN_CTRL2 0x0001U
236 #define PHY_PMA_PLL_RAW_CTRL 0x0003U
238 #define CDNS_TORRENT_OUTPUT_CLOCKS 3
240 static const char * const clk_names[] = {
241 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
242 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
243 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
246 static const struct reg_field phy_pll_cfg =
247 REG_FIELD(PHY_PLL_CFG, 0, 1);
249 static const struct reg_field phy_pma_cmn_ctrl_1 =
250 REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0);
252 static const struct reg_field phy_pma_cmn_ctrl_2 =
253 REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7);
255 static const struct reg_field phy_pma_pll_raw_ctrl =
256 REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1);
258 static const struct reg_field phy_reset_ctrl =
259 REG_FIELD(PHY_RESET, 8, 8);
261 static const struct reg_field phy_pcs_iso_link_ctrl_1 =
262 REG_FIELD(PHY_PCS_ISO_LINK_CTRL, 1, 1);
264 static const struct reg_field phy_pipe_cmn_ctrl1_0 = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0);
266 static const struct reg_field cmn_cdiag_refclk_ovrd_4 =
267 REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4);
269 #define REFCLK_OUT_NUM_CMN_CONFIG 4
271 enum cdns_torrent_refclk_out_cmn {
272 CMN_CDIAG_REFCLK_DRV0_CTRL_1,
273 CMN_CDIAG_REFCLK_DRV0_CTRL_4,
274 CMN_CDIAG_REFCLK_DRV0_CTRL_5,
275 CMN_CDIAG_REFCLK_DRV0_CTRL_6,
278 static const struct reg_field refclk_out_cmn_cfg[] = {
279 [CMN_CDIAG_REFCLK_DRV0_CTRL_1] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1),
280 [CMN_CDIAG_REFCLK_DRV0_CTRL_4] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4),
281 [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5),
282 [CMN_CDIAG_REFCLK_DRV0_CTRL_6] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6),
285 static const int refclk_driver_parent_index[] = {
286 CDNS_TORRENT_DERIVED_REFCLK,
287 CDNS_TORRENT_RECEIVED_REFCLK
290 static u32 cdns_torrent_refclk_driver_mux_table[] = { 1, 0 };
292 enum cdns_torrent_phy_type {
301 enum cdns_torrent_ref_clk {
307 enum cdns_torrent_ssc_mode {
313 struct cdns_torrent_inst {
316 enum cdns_torrent_phy_type phy_type;
318 struct reset_control *lnk_rst;
319 enum cdns_torrent_ssc_mode ssc_mode;
322 struct cdns_torrent_phy {
323 void __iomem *base; /* DPTX registers base */
324 void __iomem *sd_base; /* SD0801 registers base */
325 u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
326 struct reset_control *phy_rst;
327 struct reset_control *apb_rst;
330 enum cdns_torrent_ref_clk ref_clk_rate;
331 struct cdns_torrent_inst phys[MAX_NUM_LANES];
333 const struct cdns_torrent_data *init_data;
334 struct regmap *regmap;
335 struct regmap *regmap_common_cdb;
336 struct regmap *regmap_phy_pcs_common_cdb;
337 struct regmap *regmap_phy_pma_common_cdb;
338 struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
339 struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
340 struct regmap *regmap_phy_pcs_lane_cdb[MAX_NUM_LANES];
341 struct regmap *regmap_dptx_phy_reg;
342 struct regmap_field *phy_pll_cfg;
343 struct regmap_field *phy_pipe_cmn_ctrl1_0;
344 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
345 struct regmap_field *phy_pma_cmn_ctrl_1;
346 struct regmap_field *phy_pma_cmn_ctrl_2;
347 struct regmap_field *phy_pma_pll_raw_ctrl;
348 struct regmap_field *phy_reset_ctrl;
349 struct regmap_field *phy_pcs_iso_link_ctrl_1[MAX_NUM_LANES];
350 struct clk_hw_onecell_data *clk_hw_data;
353 enum phy_powerstate {
355 /* Powerstate A1 is unused */
360 struct cdns_torrent_refclk_driver {
362 struct regmap_field *cmn_fields[REFCLK_OUT_NUM_CMN_CONFIG];
363 struct clk_init_data clk_data;
366 #define to_cdns_torrent_refclk_driver(_hw) \
367 container_of(_hw, struct cdns_torrent_refclk_driver, hw)
369 struct cdns_torrent_derived_refclk {
371 struct regmap_field *phy_pipe_cmn_ctrl1_0;
372 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
373 struct clk_init_data clk_data;
376 #define to_cdns_torrent_derived_refclk(_hw) \
377 container_of(_hw, struct cdns_torrent_derived_refclk, hw)
379 struct cdns_torrent_received_refclk {
381 struct regmap_field *phy_pipe_cmn_ctrl1_0;
382 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
383 struct clk_init_data clk_data;
386 #define to_cdns_torrent_received_refclk(_hw) \
387 container_of(_hw, struct cdns_torrent_received_refclk, hw)
389 struct cdns_reg_pairs {
394 struct cdns_torrent_vals {
395 struct cdns_reg_pairs *reg_pairs;
399 struct cdns_torrent_data {
400 u8 block_offset_shift;
402 struct cdns_torrent_vals *link_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
404 struct cdns_torrent_vals *xcvr_diag_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
406 struct cdns_torrent_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
408 struct cdns_torrent_vals *cmn_vals[NUM_REF_CLK][NUM_PHY_TYPE]
409 [NUM_PHY_TYPE][NUM_SSC_MODE];
410 struct cdns_torrent_vals *tx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE]
411 [NUM_PHY_TYPE][NUM_SSC_MODE];
412 struct cdns_torrent_vals *rx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE]
413 [NUM_PHY_TYPE][NUM_SSC_MODE];
416 struct cdns_regmap_cdb_context {
422 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
424 struct cdns_regmap_cdb_context *ctx = context;
425 u32 offset = reg << ctx->reg_offset_shift;
427 writew(val, ctx->base + offset);
432 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
434 struct cdns_regmap_cdb_context *ctx = context;
435 u32 offset = reg << ctx->reg_offset_shift;
437 *val = readw(ctx->base + offset);
441 static int cdns_regmap_dptx_write(void *context, unsigned int reg,
444 struct cdns_regmap_cdb_context *ctx = context;
447 writel(val, ctx->base + offset);
452 static int cdns_regmap_dptx_read(void *context, unsigned int reg,
455 struct cdns_regmap_cdb_context *ctx = context;
458 *val = readl(ctx->base + offset);
462 #define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \
464 .name = "torrent_tx_lane" n "_cdb", \
467 .reg_write = cdns_regmap_write, \
468 .reg_read = cdns_regmap_read, \
471 #define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \
473 .name = "torrent_rx_lane" n "_cdb", \
476 .reg_write = cdns_regmap_write, \
477 .reg_read = cdns_regmap_read, \
480 static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = {
481 TORRENT_TX_LANE_CDB_REGMAP_CONF("0"),
482 TORRENT_TX_LANE_CDB_REGMAP_CONF("1"),
483 TORRENT_TX_LANE_CDB_REGMAP_CONF("2"),
484 TORRENT_TX_LANE_CDB_REGMAP_CONF("3"),
487 static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = {
488 TORRENT_RX_LANE_CDB_REGMAP_CONF("0"),
489 TORRENT_RX_LANE_CDB_REGMAP_CONF("1"),
490 TORRENT_RX_LANE_CDB_REGMAP_CONF("2"),
491 TORRENT_RX_LANE_CDB_REGMAP_CONF("3"),
494 static const struct regmap_config cdns_torrent_common_cdb_config = {
495 .name = "torrent_common_cdb",
498 .reg_write = cdns_regmap_write,
499 .reg_read = cdns_regmap_read,
502 #define TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \
504 .name = "torrent_phy_pcs_lane" n "_cdb", \
507 .reg_write = cdns_regmap_write, \
508 .reg_read = cdns_regmap_read, \
511 static const struct regmap_config cdns_torrent_phy_pcs_lane_cdb_config[] = {
512 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("0"),
513 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("1"),
514 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("2"),
515 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("3"),
518 static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = {
519 .name = "torrent_phy_pcs_cmn_cdb",
522 .reg_write = cdns_regmap_write,
523 .reg_read = cdns_regmap_read,
526 static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = {
527 .name = "torrent_phy_pma_cmn_cdb",
530 .reg_write = cdns_regmap_write,
531 .reg_read = cdns_regmap_read,
534 static const struct regmap_config cdns_torrent_dptx_phy_config = {
535 .name = "torrent_dptx_phy",
538 .reg_write = cdns_regmap_dptx_write,
539 .reg_read = cdns_regmap_dptx_read,
542 /* PHY mmr access functions */
544 static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val)
546 regmap_write(regmap, offset, val);
549 static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset)
553 regmap_read(regmap, offset, &val);
557 /* DPTX mmr access functions */
559 static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val)
561 regmap_write(regmap, offset, val);
564 static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset)
568 regmap_read(regmap, offset, &val);
573 * Structure used to store values of PHY registers for voltage-related
574 * coefficients, for particular voltage swing and pre-emphasis level. Values
575 * are shared across all physical lanes.
577 struct coefficients {
578 /* Value of DRV_DIAG_TX_DRV register to use */
580 /* Value of TX_TXCC_MGNFS_MULT_000 register to use */
582 /* Value of TX_TXCC_CPOST_MULT_00 register to use */
587 * Array consists of values of voltage-related registers for sd0801 PHY. A value
588 * of 0xFFFF is a placeholder for invalid combination, and will never be used.
590 static const struct coefficients vltg_coeff[4][4] = {
591 /* voltage swing 0, pre-emphasis 0->3 */
592 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A,
593 .cpost_mult = 0x0000},
594 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
595 .cpost_mult = 0x0014},
596 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012,
597 .cpost_mult = 0x0020},
598 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
599 .cpost_mult = 0x002A}
602 /* voltage swing 1, pre-emphasis 0->3 */
603 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
604 .cpost_mult = 0x0000},
605 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
606 .cpost_mult = 0x0012},
607 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
608 .cpost_mult = 0x001F},
609 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
610 .cpost_mult = 0xFFFF}
613 /* voltage swing 2, pre-emphasis 0->3 */
614 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
615 .cpost_mult = 0x0000},
616 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
617 .cpost_mult = 0x0013},
618 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
619 .cpost_mult = 0xFFFF},
620 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
621 .cpost_mult = 0xFFFF}
624 /* voltage swing 3, pre-emphasis 0->3 */
625 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
626 .cpost_mult = 0x0000},
627 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
628 .cpost_mult = 0xFFFF},
629 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
630 .cpost_mult = 0xFFFF},
631 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
632 .cpost_mult = 0xFFFF}
636 static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type)
640 return "DisplayPort";
655 * Set registers responsible for enabling and configuring SSC, with second and
656 * third register values provided by parameters.
659 void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy,
660 u32 ctrl2_val, u32 ctrl3_val)
662 struct regmap *regmap = cdns_phy->regmap_common_cdb;
664 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
665 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
666 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val);
667 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
668 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
669 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
670 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val);
671 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
675 void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
678 struct regmap *regmap = cdns_phy->regmap_common_cdb;
680 /* Assumes 19.2 MHz refclock */
682 /* Setting VCO for 10.8GHz */
685 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0119);
686 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);
687 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
688 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00BC);
689 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
690 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0119);
691 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);
692 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
693 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00BC);
694 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0012);
696 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A, 0x006A);
698 /* Setting VCO for 9.72GHz */
702 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01FA);
703 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);
704 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
705 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0152);
706 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
707 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01FA);
708 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);
709 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
710 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0152);
711 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
713 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD, 0x0069);
715 /* Setting VCO for 8.64GHz */
718 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01C2);
719 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
720 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
721 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x012C);
722 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
723 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01C2);
724 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
725 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
726 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x012C);
727 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
729 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536, 0x0069);
731 /* Setting VCO for 8.1GHz */
733 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01A5);
734 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xE000);
735 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
736 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x011A);
737 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
738 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01A5);
739 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xE000);
740 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
741 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x011A);
742 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
744 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7, 0x006A);
749 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);
750 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
751 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);
752 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
754 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);
755 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);
756 /* Set reset register values to disable SSC */
757 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
758 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
759 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
760 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
761 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
762 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
763 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
764 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
765 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
766 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
769 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099);
770 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099);
771 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099);
772 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
776 * Set registers responsible for enabling and configuring SSC, with second
777 * register value provided by a parameter.
779 static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy,
782 struct regmap *regmap = cdns_phy->regmap_common_cdb;
784 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
785 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
786 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F);
787 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
788 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
789 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
790 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F);
791 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
795 void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
798 struct regmap *regmap = cdns_phy->regmap_common_cdb;
800 /* Assumes 25 MHz refclock */
802 /* Setting VCO for 10.8GHz */
805 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0);
806 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
807 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
808 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120);
809 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0);
810 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
811 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
812 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120);
814 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423);
816 /* Setting VCO for 9.72GHz */
820 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184);
821 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD);
822 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
823 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104);
824 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184);
825 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD);
826 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
827 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104);
829 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9);
831 /* Setting VCO for 8.64GHz */
834 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159);
835 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A);
836 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
837 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7);
838 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159);
839 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A);
840 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
841 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7);
843 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F);
845 /* Setting VCO for 8.1GHz */
847 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144);
848 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
849 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
850 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8);
851 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144);
852 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
853 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
854 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8);
856 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A);
860 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
861 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
864 cdns_torrent_phy_write(regmap,
865 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315);
866 cdns_torrent_phy_write(regmap,
867 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
868 cdns_torrent_phy_write(regmap,
869 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315);
870 cdns_torrent_phy_write(regmap,
871 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
873 cdns_torrent_phy_write(regmap,
874 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317);
875 cdns_torrent_phy_write(regmap,
876 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317);
877 /* Set reset register values to disable SSC */
878 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
879 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
880 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
881 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
882 cdns_torrent_phy_write(regmap,
883 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
884 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
885 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
886 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
887 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
888 cdns_torrent_phy_write(regmap,
889 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
892 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7);
893 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7);
894 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7);
895 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
899 void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy,
902 struct regmap *regmap = cdns_phy->regmap_common_cdb;
904 /* Assumes 100 MHz refclock */
906 /* Setting VCO for 10.8GHz */
909 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028);
910 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022);
911 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022);
912 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C);
914 /* Setting VCO for 9.72GHz */
918 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
919 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
920 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
921 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
922 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
923 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
924 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
925 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
926 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061);
927 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061);
928 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333);
929 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333);
930 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
931 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
932 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042);
933 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042);
934 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
935 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
937 /* Setting VCO for 8.64GHz */
940 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
941 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
942 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
943 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
944 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
945 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
946 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
947 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
948 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056);
949 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056);
950 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666);
951 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666);
952 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
953 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
954 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A);
955 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A);
956 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
957 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
959 /* Setting VCO for 8.1GHz */
961 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
962 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
963 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
964 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
965 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
966 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
967 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
968 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
969 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051);
970 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051);
971 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
972 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
973 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036);
974 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036);
975 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
976 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
982 * Enable or disable PLL for selected lanes.
984 static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
985 struct phy_configure_opts_dp *dp,
990 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
993 * Used to determine, which bits to check for or enable in
994 * PHY_PMA_XCVR_PLLCLK_EN register.
997 /* Used to enable or disable lanes. */
1000 /* Select values of registers and mask, depending on enabled lane
1003 switch (dp->lanes) {
1006 pll_bits = 0x00000001;
1010 pll_bits = 0x00000003;
1012 /* lanes 0-3, all */
1014 pll_bits = 0x0000000F;
1021 pll_val = 0x00000000;
1023 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val);
1025 /* Wait for acknowledgment from PHY. */
1026 ret = regmap_read_poll_timeout(regmap,
1027 PHY_PMA_XCVR_PLLCLK_EN_ACK,
1029 (rd_val & pll_bits) == pll_val,
1030 0, POLL_TIMEOUT_US);
1035 static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
1037 enum phy_powerstate powerstate)
1039 /* Register value for power state for a single byte. */
1045 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1047 switch (powerstate) {
1048 case (POWERSTATE_A0):
1051 case (POWERSTATE_A2):
1060 /* Select values of registers and mask, depending on enabled
1063 switch (num_lanes) {
1072 | (value_part << 8));
1075 /* lanes 0-3, all */
1079 | (value_part << 16)
1080 | (value_part << 24));
1085 /* Set power state A<n>. */
1086 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);
1087 /* Wait, until PHY acknowledges power state completion. */
1088 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,
1089 read_val, (read_val & mask) == value, 0,
1091 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
1097 static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes)
1099 unsigned int read_val;
1101 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1104 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
1107 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
1108 read_val, read_val & 1,
1109 0, POLL_TIMEOUT_US);
1110 if (ret == -ETIMEDOUT) {
1111 dev_err(cdns_phy->dev,
1112 "timeout waiting for link PLL clock enable ack\n");
1118 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
1123 ret = cdns_torrent_dp_set_power_state(cdns_phy, num_lanes,
1129 static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
1133 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1135 ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,
1136 reg & 1, 0, POLL_TIMEOUT_US);
1137 if (ret == -ETIMEDOUT) {
1138 dev_err(cdns_phy->dev,
1139 "timeout waiting for PMA common ready\n");
1146 static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
1147 u32 rate, u32 num_lanes)
1149 unsigned int clk_sel_val = 0;
1150 unsigned int hsclk_div_val = 0;
1155 clk_sel_val = 0x0f01;
1161 clk_sel_val = 0x0701;
1165 clk_sel_val = 0x0b00;
1170 clk_sel_val = 0x0301;
1174 clk_sel_val = 0x0200;
1179 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1180 CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
1181 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1182 CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
1184 /* PMA lane configuration to deal with multi-link operation */
1185 for (i = 0; i < num_lanes; i++)
1186 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[i],
1187 XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
1191 * Perform register operations related to setting link rate, once powerstate is
1192 * set and PLL disable request was processed.
1194 static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
1195 struct phy_configure_opts_dp *dp)
1199 /* Disable the cmn_pll0_en before re-programming the new data rate. */
1200 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x0);
1203 * Wait for PLL ready de-assertion.
1204 * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1
1206 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1208 ((read_val >> 2) & 0x01) != 0,
1209 0, POLL_TIMEOUT_US);
1214 /* DP Rate Change - VCO Output settings. */
1215 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
1216 /* PMA common configuration 19.2MHz */
1217 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc);
1218 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
1219 /* PMA common configuration 25MHz */
1220 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc);
1221 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
1222 /* PMA common configuration 100MHz */
1223 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, dp->link_rate, dp->ssc);
1225 cdns_torrent_dp_pma_cmn_rate(cdns_phy, dp->link_rate, dp->lanes);
1227 /* Enable the cmn_pll0_en. */
1228 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, 0x3);
1231 * Wait for PLL ready assertion.
1232 * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1
1234 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1236 (read_val & 0x01) != 0,
1237 0, POLL_TIMEOUT_US);
1242 * Verify, that parameters to configure PHY with are correct.
1244 static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst,
1245 struct phy_configure_opts_dp *dp)
1249 /* If changing link rate was required, verify it's supported. */
1251 switch (dp->link_rate) {
1260 /* valid bit rate */
1267 /* Verify lane count. */
1268 switch (dp->lanes) {
1272 /* valid lane count. */
1278 /* Check against actual number of PHY's lanes. */
1279 if (dp->lanes > inst->num_lanes)
1283 * If changing voltages is required, check swing and pre-emphasis
1286 if (dp->set_voltages) {
1287 /* Lane count verified previously. */
1288 for (i = 0; i < dp->lanes; i++) {
1289 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
1292 /* Sum of voltage swing and pre-emphasis levels cannot
1295 if (dp->voltage[i] + dp->pre[i] > 3)
1303 /* Set power state A0 and PLL clock enable to 0 on enabled lanes. */
1304 static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
1307 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1308 u32 pwr_state = cdns_torrent_dp_read(regmap,
1309 PHY_PMA_XCVR_POWER_STATE_REQ);
1310 u32 pll_clk_en = cdns_torrent_dp_read(regmap,
1311 PHY_PMA_XCVR_PLLCLK_EN);
1313 /* Lane 0 is always enabled. */
1314 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
1315 PHY_POWER_STATE_LN_0);
1316 pll_clk_en &= ~0x01U;
1318 if (num_lanes > 1) {
1320 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
1321 PHY_POWER_STATE_LN_1);
1322 pll_clk_en &= ~(0x01U << 1);
1325 if (num_lanes > 2) {
1327 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
1328 PHY_POWER_STATE_LN_2);
1329 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
1330 PHY_POWER_STATE_LN_3);
1331 pll_clk_en &= ~(0x01U << 2);
1332 pll_clk_en &= ~(0x01U << 3);
1335 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
1336 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);
1339 /* Configure lane count as required. */
1340 static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
1341 struct phy_configure_opts_dp *dp)
1345 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1346 u8 lane_mask = (1 << dp->lanes) - 1;
1348 value = cdns_torrent_dp_read(regmap, PHY_RESET);
1349 /* clear pma_tx_elec_idle_ln_* bits. */
1350 value &= ~PMA_TX_ELEC_IDLE_MASK;
1351 /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */
1352 value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) &
1353 PMA_TX_ELEC_IDLE_MASK;
1354 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1356 /* reset the link by asserting phy_l00_reset_n low */
1357 cdns_torrent_dp_write(regmap, PHY_RESET,
1358 value & (~PHY_L00_RESET_N_MASK));
1361 * Assert lane reset on unused lanes and lane 0 so they remain in reset
1362 * and powered down when re-enabling the link
1364 value = (value & 0x0000FFF0) | (0x0000000E & lane_mask);
1365 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1367 cdns_torrent_dp_set_a0_pll(cdns_phy, dp->lanes);
1369 /* release phy_l0*_reset_n based on used laneCount */
1370 value = (value & 0x0000FFF0) | (0x0000000F & lane_mask);
1371 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1373 /* Wait, until PHY gets ready after releasing PHY reset signal. */
1374 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
1380 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
1381 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
1383 ret = cdns_torrent_dp_run(cdns_phy, dp->lanes);
1388 /* Configure link rate as required. */
1389 static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy,
1390 struct phy_configure_opts_dp *dp)
1394 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
1398 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, false);
1403 ret = cdns_torrent_dp_configure_rate(cdns_phy, dp);
1408 ret = cdns_torrent_dp_set_pll_en(cdns_phy, dp, true);
1411 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
1415 ret = cdns_torrent_dp_set_power_state(cdns_phy, dp->lanes,
1424 /* Configure voltage swing and pre-emphasis for all enabled lanes. */
1425 static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy,
1426 struct phy_configure_opts_dp *dp)
1431 for (lane = 0; lane < dp->lanes; lane++) {
1432 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
1435 * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the
1436 * current state of the analog TX driver.
1438 val |= TX_DIAG_ACYA_HBDC_MASK;
1439 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1442 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1443 TX_TXCC_CTRL, 0x08A4);
1444 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv;
1445 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1446 DRV_DIAG_TX_DRV, val);
1447 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult;
1448 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1449 TX_TXCC_MGNFS_MULT_000,
1451 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult;
1452 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1453 TX_TXCC_CPOST_MULT_00,
1456 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[lane],
1459 * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of
1460 * analog TX driver to reflect the new programmed one.
1462 val &= ~TX_DIAG_ACYA_HBDC_MASK;
1463 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[lane],
1468 static int cdns_torrent_dp_configure(struct phy *phy,
1469 union phy_configure_opts *opts)
1471 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1472 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1475 ret = cdns_torrent_dp_verify_config(inst, &opts->dp);
1477 dev_err(&phy->dev, "invalid params for phy configure\n");
1481 if (opts->dp.set_lanes) {
1482 ret = cdns_torrent_dp_set_lanes(cdns_phy, &opts->dp);
1484 dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n");
1489 if (opts->dp.set_rate) {
1490 ret = cdns_torrent_dp_set_rate(cdns_phy, &opts->dp);
1492 dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n");
1497 if (opts->dp.set_voltages)
1498 cdns_torrent_dp_set_voltages(cdns_phy, &opts->dp);
1503 static int cdns_torrent_phy_on(struct phy *phy)
1505 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1506 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1510 if (cdns_phy->nsubnodes == 1) {
1511 /* Take the PHY lane group out of reset */
1512 reset_control_deassert(inst->lnk_rst);
1514 /* Take the PHY out of reset */
1515 ret = reset_control_deassert(cdns_phy->phy_rst);
1521 * Wait for cmn_ready assertion
1522 * PHY_PMA_CMN_CTRL1[0] == 1
1524 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
1525 read_val, read_val, 1000,
1528 dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
1532 if (inst->phy_type == TYPE_PCIE || inst->phy_type == TYPE_USB) {
1533 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pcs_iso_link_ctrl_1[inst->mlane],
1534 read_val, !read_val, 1000,
1536 if (ret == -ETIMEDOUT) {
1537 dev_err(cdns_phy->dev, "Timeout waiting for PHY status ready\n");
1545 static int cdns_torrent_phy_off(struct phy *phy)
1547 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1548 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1551 if (cdns_phy->nsubnodes != 1)
1554 ret = reset_control_assert(cdns_phy->phy_rst);
1558 return reset_control_assert(inst->lnk_rst);
1561 static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy,
1562 struct cdns_torrent_inst *inst)
1564 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1565 unsigned char lane_bits;
1567 cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
1570 * Set lines power state to A0
1571 * Set lines pll clk enable to 0
1573 cdns_torrent_dp_set_a0_pll(cdns_phy, inst->num_lanes);
1576 * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on
1579 lane_bits = (1 << inst->num_lanes) - 1;
1580 cdns_torrent_dp_write(regmap, PHY_RESET,
1581 ((0xF & ~lane_bits) << 4) | (0xF & lane_bits));
1583 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
1584 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, 0x0001);
1587 * PHY PMA registers configuration functions
1588 * Initialize PHY with max supported link rate, without SSC.
1590 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
1591 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
1592 cdns_phy->max_bit_rate,
1594 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
1595 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
1596 cdns_phy->max_bit_rate,
1598 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
1599 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy,
1600 cdns_phy->max_bit_rate,
1603 cdns_torrent_dp_pma_cmn_rate(cdns_phy, cdns_phy->max_bit_rate,
1606 /* take out of reset */
1607 regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1);
1610 static int cdns_torrent_dp_start(struct cdns_torrent_phy *cdns_phy,
1611 struct cdns_torrent_inst *inst,
1616 cdns_torrent_phy_on(phy);
1618 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
1622 ret = cdns_torrent_dp_run(cdns_phy, inst->num_lanes);
1627 static int cdns_torrent_dp_init(struct phy *phy)
1629 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1630 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1632 switch (cdns_phy->ref_clk_rate) {
1636 /* Valid Ref Clock Rate */
1639 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
1643 cdns_torrent_dp_common_init(cdns_phy, inst);
1645 return cdns_torrent_dp_start(cdns_phy, inst, phy);
1648 static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
1650 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1652 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 1);
1653 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 1);
1658 static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw)
1660 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1662 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 0);
1663 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 0);
1666 static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw)
1668 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1671 regmap_field_read(derived_refclk->cmn_cdiag_refclk_ovrd_4, &val);
1676 static const struct clk_ops cdns_torrent_derived_refclk_ops = {
1677 .enable = cdns_torrent_derived_refclk_enable,
1678 .disable = cdns_torrent_derived_refclk_disable,
1679 .is_enabled = cdns_torrent_derived_refclk_is_enabled,
1682 static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy)
1684 struct cdns_torrent_derived_refclk *derived_refclk;
1685 struct device *dev = cdns_phy->dev;
1686 struct clk_init_data *init;
1687 const char *parent_name;
1693 derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL);
1694 if (!derived_refclk)
1697 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
1698 clk_names[CDNS_TORRENT_DERIVED_REFCLK]);
1700 clk = devm_clk_get_optional(dev, "phy_en_refclk");
1702 dev_err(dev, "No parent clock for derived_refclk\n");
1703 return PTR_ERR(clk);
1706 init = &derived_refclk->clk_data;
1709 parent_name = __clk_get_name(clk);
1710 init->parent_names = &parent_name;
1711 init->num_parents = 1;
1713 init->ops = &cdns_torrent_derived_refclk_ops;
1715 init->name = clk_name;
1717 derived_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0;
1718 derived_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4;
1720 derived_refclk->hw.init = init;
1722 hw = &derived_refclk->hw;
1723 ret = devm_clk_hw_register(dev, hw);
1727 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_DERIVED_REFCLK] = hw;
1732 static int cdns_torrent_received_refclk_enable(struct clk_hw *hw)
1734 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1736 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 1);
1741 static void cdns_torrent_received_refclk_disable(struct clk_hw *hw)
1743 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1745 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 0);
1748 static int cdns_torrent_received_refclk_is_enabled(struct clk_hw *hw)
1750 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1753 regmap_field_read(received_refclk->phy_pipe_cmn_ctrl1_0, &val);
1754 regmap_field_read(received_refclk->cmn_cdiag_refclk_ovrd_4, &cmn_val);
1756 return val && !cmn_val;
1759 static const struct clk_ops cdns_torrent_received_refclk_ops = {
1760 .enable = cdns_torrent_received_refclk_enable,
1761 .disable = cdns_torrent_received_refclk_disable,
1762 .is_enabled = cdns_torrent_received_refclk_is_enabled,
1765 static int cdns_torrent_received_refclk_register(struct cdns_torrent_phy *cdns_phy)
1767 struct cdns_torrent_received_refclk *received_refclk;
1768 struct device *dev = cdns_phy->dev;
1769 struct clk_init_data *init;
1770 const char *parent_name;
1776 received_refclk = devm_kzalloc(dev, sizeof(*received_refclk), GFP_KERNEL);
1777 if (!received_refclk)
1780 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
1781 clk_names[CDNS_TORRENT_RECEIVED_REFCLK]);
1783 clk = devm_clk_get_optional(dev, "phy_en_refclk");
1785 dev_err(dev, "No parent clock for received_refclk\n");
1786 return PTR_ERR(clk);
1789 init = &received_refclk->clk_data;
1792 parent_name = __clk_get_name(clk);
1793 init->parent_names = &parent_name;
1794 init->num_parents = 1;
1796 init->ops = &cdns_torrent_received_refclk_ops;
1798 init->name = clk_name;
1800 received_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0;
1801 received_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4;
1803 received_refclk->hw.init = init;
1805 hw = &received_refclk->hw;
1806 ret = devm_clk_hw_register(dev, hw);
1810 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_RECEIVED_REFCLK] = hw;
1815 static int cdns_torrent_refclk_driver_enable(struct clk_hw *hw)
1817 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1819 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0);
1820 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1);
1821 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0);
1826 static void cdns_torrent_refclk_driver_disable(struct clk_hw *hw)
1828 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1830 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 1);
1833 static int cdns_torrent_refclk_driver_is_enabled(struct clk_hw *hw)
1835 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1838 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], &val);
1843 static u8 cdns_torrent_refclk_driver_get_parent(struct clk_hw *hw)
1845 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1848 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], &val);
1849 return clk_mux_val_to_index(hw, cdns_torrent_refclk_driver_mux_table, 0, val);
1852 static int cdns_torrent_refclk_driver_set_parent(struct clk_hw *hw, u8 index)
1854 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1857 val = cdns_torrent_refclk_driver_mux_table[index];
1858 return regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], val);
1861 static const struct clk_ops cdns_torrent_refclk_driver_ops = {
1862 .enable = cdns_torrent_refclk_driver_enable,
1863 .disable = cdns_torrent_refclk_driver_disable,
1864 .is_enabled = cdns_torrent_refclk_driver_is_enabled,
1865 .set_parent = cdns_torrent_refclk_driver_set_parent,
1866 .get_parent = cdns_torrent_refclk_driver_get_parent,
1869 static int cdns_torrent_refclk_driver_register(struct cdns_torrent_phy *cdns_phy)
1871 struct cdns_torrent_refclk_driver *refclk_driver;
1872 struct device *dev = cdns_phy->dev;
1873 struct regmap_field *field;
1874 struct clk_init_data *init;
1875 const char **parent_names;
1876 unsigned int num_parents;
1877 struct regmap *regmap;
1882 refclk_driver = devm_kzalloc(dev, sizeof(*refclk_driver), GFP_KERNEL);
1886 num_parents = ARRAY_SIZE(refclk_driver_parent_index);
1887 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL);
1891 for (i = 0; i < num_parents; i++) {
1892 hw = cdns_phy->clk_hw_data->hws[refclk_driver_parent_index[i]];
1893 if (IS_ERR_OR_NULL(hw)) {
1894 dev_err(dev, "No parent clock for refclk driver clock\n");
1895 return IS_ERR(hw) ? PTR_ERR(hw) : -ENOENT;
1897 parent_names[i] = clk_hw_get_name(hw);
1900 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
1901 clk_names[CDNS_TORRENT_REFCLK_DRIVER]);
1903 init = &refclk_driver->clk_data;
1905 init->ops = &cdns_torrent_refclk_driver_ops;
1906 init->flags = CLK_SET_RATE_NO_REPARENT;
1907 init->parent_names = parent_names;
1908 init->num_parents = num_parents;
1909 init->name = clk_name;
1911 regmap = cdns_phy->regmap_common_cdb;
1913 for (i = 0; i < REFCLK_OUT_NUM_CMN_CONFIG; i++) {
1914 field = devm_regmap_field_alloc(dev, regmap, refclk_out_cmn_cfg[i]);
1915 if (IS_ERR(field)) {
1916 dev_err(dev, "Refclk driver CMN reg field init failed\n");
1917 return PTR_ERR(field);
1919 refclk_driver->cmn_fields[i] = field;
1922 /* Enable Derived reference clock as default */
1923 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1);
1925 refclk_driver->hw.init = init;
1927 hw = &refclk_driver->hw;
1928 ret = devm_clk_hw_register(dev, hw);
1932 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_REFCLK_DRIVER] = hw;
1937 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
1939 u8 reg_offset_shift,
1940 const struct regmap_config *config)
1942 struct cdns_regmap_cdb_context *ctx;
1944 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1946 return ERR_PTR(-ENOMEM);
1949 ctx->base = base + block_offset;
1950 ctx->reg_offset_shift = reg_offset_shift;
1952 return devm_regmap_init(dev, NULL, ctx, config);
1955 static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy)
1957 struct device *dev = cdns_phy->dev;
1958 struct regmap_field *field;
1959 struct regmap *regmap;
1961 regmap = cdns_phy->regmap_dptx_phy_reg;
1962 field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl);
1963 if (IS_ERR(field)) {
1964 dev_err(dev, "PHY_RESET reg field init failed\n");
1965 return PTR_ERR(field);
1967 cdns_phy->phy_reset_ctrl = field;
1972 static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy)
1974 struct device *dev = cdns_phy->dev;
1975 struct regmap_field *field;
1976 struct regmap *regmap;
1979 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
1980 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg);
1981 if (IS_ERR(field)) {
1982 dev_err(dev, "PHY_PLL_CFG reg field init failed\n");
1983 return PTR_ERR(field);
1985 cdns_phy->phy_pll_cfg = field;
1987 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
1988 field = devm_regmap_field_alloc(dev, regmap, phy_pipe_cmn_ctrl1_0);
1989 if (IS_ERR(field)) {
1990 dev_err(dev, "phy_pipe_cmn_ctrl1_0 reg field init failed\n");
1991 return PTR_ERR(field);
1993 cdns_phy->phy_pipe_cmn_ctrl1_0 = field;
1995 regmap = cdns_phy->regmap_common_cdb;
1996 field = devm_regmap_field_alloc(dev, regmap, cmn_cdiag_refclk_ovrd_4);
1997 if (IS_ERR(field)) {
1998 dev_err(dev, "cmn_cdiag_refclk_ovrd_4 reg field init failed\n");
1999 return PTR_ERR(field);
2001 cdns_phy->cmn_cdiag_refclk_ovrd_4 = field;
2003 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2004 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1);
2005 if (IS_ERR(field)) {
2006 dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n");
2007 return PTR_ERR(field);
2009 cdns_phy->phy_pma_cmn_ctrl_1 = field;
2011 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2012 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2);
2013 if (IS_ERR(field)) {
2014 dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n");
2015 return PTR_ERR(field);
2017 cdns_phy->phy_pma_cmn_ctrl_2 = field;
2019 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2020 field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl);
2021 if (IS_ERR(field)) {
2022 dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n");
2023 return PTR_ERR(field);
2025 cdns_phy->phy_pma_pll_raw_ctrl = field;
2027 for (i = 0; i < MAX_NUM_LANES; i++) {
2028 regmap = cdns_phy->regmap_phy_pcs_lane_cdb[i];
2029 field = devm_regmap_field_alloc(dev, regmap, phy_pcs_iso_link_ctrl_1);
2030 if (IS_ERR(field)) {
2031 dev_err(dev, "PHY_PCS_ISO_LINK_CTRL reg field init for ln %d failed\n", i);
2032 return PTR_ERR(field);
2034 cdns_phy->phy_pcs_iso_link_ctrl_1[i] = field;
2040 static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy)
2042 void __iomem *base = cdns_phy->base;
2043 struct device *dev = cdns_phy->dev;
2044 struct regmap *regmap;
2045 u8 reg_offset_shift;
2048 reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
2050 block_offset = TORRENT_DPTX_PHY_OFFSET;
2051 regmap = cdns_regmap_init(dev, base, block_offset,
2053 &cdns_torrent_dptx_phy_config);
2054 if (IS_ERR(regmap)) {
2055 dev_err(dev, "Failed to init DPTX PHY regmap\n");
2056 return PTR_ERR(regmap);
2058 cdns_phy->regmap_dptx_phy_reg = regmap;
2063 static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy)
2065 void __iomem *sd_base = cdns_phy->sd_base;
2066 u8 block_offset_shift, reg_offset_shift;
2067 struct device *dev = cdns_phy->dev;
2068 struct regmap *regmap;
2072 block_offset_shift = cdns_phy->init_data->block_offset_shift;
2073 reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
2075 for (i = 0; i < MAX_NUM_LANES; i++) {
2076 block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift,
2078 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2080 &cdns_torrent_tx_lane_cdb_config[i]);
2081 if (IS_ERR(regmap)) {
2082 dev_err(dev, "Failed to init tx lane CDB regmap\n");
2083 return PTR_ERR(regmap);
2085 cdns_phy->regmap_tx_lane_cdb[i] = regmap;
2087 block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift,
2089 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2091 &cdns_torrent_rx_lane_cdb_config[i]);
2092 if (IS_ERR(regmap)) {
2093 dev_err(dev, "Failed to init rx lane CDB regmap\n");
2094 return PTR_ERR(regmap);
2096 cdns_phy->regmap_rx_lane_cdb[i] = regmap;
2098 block_offset = TORRENT_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift,
2100 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2102 &cdns_torrent_phy_pcs_lane_cdb_config[i]);
2103 if (IS_ERR(regmap)) {
2104 dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n");
2105 return PTR_ERR(regmap);
2107 cdns_phy->regmap_phy_pcs_lane_cdb[i] = regmap;
2110 block_offset = TORRENT_COMMON_CDB_OFFSET;
2111 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2113 &cdns_torrent_common_cdb_config);
2114 if (IS_ERR(regmap)) {
2115 dev_err(dev, "Failed to init common CDB regmap\n");
2116 return PTR_ERR(regmap);
2118 cdns_phy->regmap_common_cdb = regmap;
2120 block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift);
2121 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2123 &cdns_torrent_phy_pcs_cmn_cdb_config);
2124 if (IS_ERR(regmap)) {
2125 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
2126 return PTR_ERR(regmap);
2128 cdns_phy->regmap_phy_pcs_common_cdb = regmap;
2130 block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift);
2131 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2133 &cdns_torrent_phy_pma_cmn_cdb_config);
2134 if (IS_ERR(regmap)) {
2135 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
2136 return PTR_ERR(regmap);
2138 cdns_phy->regmap_phy_pma_common_cdb = regmap;
2143 static int cdns_torrent_phy_init(struct phy *phy)
2145 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
2146 const struct cdns_torrent_data *init_data = cdns_phy->init_data;
2147 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
2148 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
2149 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
2150 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
2151 enum cdns_torrent_phy_type phy_type = inst->phy_type;
2152 enum cdns_torrent_ssc_mode ssc = inst->ssc_mode;
2153 struct cdns_torrent_vals *pcs_cmn_vals;
2154 struct cdns_reg_pairs *reg_pairs;
2155 struct regmap *regmap;
2159 if (cdns_phy->nsubnodes > 1)
2163 * Spread spectrum generation is not required or supported
2166 if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII)
2169 /* PHY configuration specific registers for single link */
2170 link_cmn_vals = init_data->link_cmn_vals[phy_type][TYPE_NONE][ssc];
2171 if (link_cmn_vals) {
2172 reg_pairs = link_cmn_vals->reg_pairs;
2173 num_regs = link_cmn_vals->num_regs;
2174 regmap = cdns_phy->regmap_common_cdb;
2177 * First array value in link_cmn_vals must be of
2178 * PHY_PLL_CFG register
2180 regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val);
2182 for (i = 1; i < num_regs; i++)
2183 regmap_write(regmap, reg_pairs[i].off,
2187 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_type][TYPE_NONE][ssc];
2188 if (xcvr_diag_vals) {
2189 reg_pairs = xcvr_diag_vals->reg_pairs;
2190 num_regs = xcvr_diag_vals->num_regs;
2191 for (i = 0; i < inst->num_lanes; i++) {
2192 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
2193 for (j = 0; j < num_regs; j++)
2194 regmap_write(regmap, reg_pairs[j].off,
2199 /* PHY PCS common registers configurations */
2200 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
2202 reg_pairs = pcs_cmn_vals->reg_pairs;
2203 num_regs = pcs_cmn_vals->num_regs;
2204 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2205 for (i = 0; i < num_regs; i++)
2206 regmap_write(regmap, reg_pairs[i].off,
2210 /* PMA common registers configurations */
2211 cmn_vals = init_data->cmn_vals[ref_clk][phy_type][TYPE_NONE][ssc];
2213 reg_pairs = cmn_vals->reg_pairs;
2214 num_regs = cmn_vals->num_regs;
2215 regmap = cdns_phy->regmap_common_cdb;
2216 for (i = 0; i < num_regs; i++)
2217 regmap_write(regmap, reg_pairs[i].off,
2221 /* PMA TX lane registers configurations */
2222 tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc];
2224 reg_pairs = tx_ln_vals->reg_pairs;
2225 num_regs = tx_ln_vals->num_regs;
2226 for (i = 0; i < inst->num_lanes; i++) {
2227 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
2228 for (j = 0; j < num_regs; j++)
2229 regmap_write(regmap, reg_pairs[j].off,
2234 /* PMA RX lane registers configurations */
2235 rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc];
2237 reg_pairs = rx_ln_vals->reg_pairs;
2238 num_regs = rx_ln_vals->num_regs;
2239 for (i = 0; i < inst->num_lanes; i++) {
2240 regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane];
2241 for (j = 0; j < num_regs; j++)
2242 regmap_write(regmap, reg_pairs[j].off,
2247 if (phy_type == TYPE_DP)
2248 return cdns_torrent_dp_init(phy);
2253 static const struct phy_ops cdns_torrent_phy_ops = {
2254 .init = cdns_torrent_phy_init,
2255 .configure = cdns_torrent_dp_configure,
2256 .power_on = cdns_torrent_phy_on,
2257 .power_off = cdns_torrent_phy_off,
2258 .owner = THIS_MODULE,
2261 static int cdns_torrent_noop_phy_on(struct phy *phy)
2263 /* Give 5ms to 10ms delay for the PIPE clock to be stable */
2264 usleep_range(5000, 10000);
2269 static const struct phy_ops noop_ops = {
2270 .power_on = cdns_torrent_noop_phy_on,
2271 .owner = THIS_MODULE,
2275 int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
2277 const struct cdns_torrent_data *init_data = cdns_phy->init_data;
2278 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
2279 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
2280 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
2281 enum cdns_torrent_phy_type phy_t1, phy_t2, tmp_phy_type;
2282 struct cdns_torrent_vals *pcs_cmn_vals;
2283 int i, j, node, mlane, num_lanes, ret;
2284 struct cdns_reg_pairs *reg_pairs;
2285 enum cdns_torrent_ssc_mode ssc;
2286 struct regmap *regmap;
2289 /* Maximum 2 links (subnodes) are supported */
2290 if (cdns_phy->nsubnodes != 2)
2293 phy_t1 = cdns_phy->phys[0].phy_type;
2294 phy_t2 = cdns_phy->phys[1].phy_type;
2297 * First configure the PHY for first link with phy_t1. Get the array
2298 * values as [phy_t1][phy_t2][ssc].
2300 for (node = 0; node < cdns_phy->nsubnodes; node++) {
2303 * If first link with phy_t1 is configured, then
2304 * configure the PHY for second link with phy_t2.
2305 * Get the array values as [phy_t2][phy_t1][ssc].
2307 tmp_phy_type = phy_t1;
2309 phy_t2 = tmp_phy_type;
2312 mlane = cdns_phy->phys[node].mlane;
2313 ssc = cdns_phy->phys[node].ssc_mode;
2314 num_lanes = cdns_phy->phys[node].num_lanes;
2317 * PHY configuration specific registers:
2318 * link_cmn_vals depend on combination of PHY types being
2319 * configured and are common for both PHY types, so array
2320 * values should be same for [phy_t1][phy_t2][ssc] and
2321 * [phy_t2][phy_t1][ssc].
2322 * xcvr_diag_vals also depend on combination of PHY types
2323 * being configured, but these can be different for particular
2324 * PHY type and are per lane.
2326 link_cmn_vals = init_data->link_cmn_vals[phy_t1][phy_t2][ssc];
2327 if (link_cmn_vals) {
2328 reg_pairs = link_cmn_vals->reg_pairs;
2329 num_regs = link_cmn_vals->num_regs;
2330 regmap = cdns_phy->regmap_common_cdb;
2333 * First array value in link_cmn_vals must be of
2334 * PHY_PLL_CFG register
2336 regmap_field_write(cdns_phy->phy_pll_cfg,
2339 for (i = 1; i < num_regs; i++)
2340 regmap_write(regmap, reg_pairs[i].off,
2344 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_t1][phy_t2][ssc];
2345 if (xcvr_diag_vals) {
2346 reg_pairs = xcvr_diag_vals->reg_pairs;
2347 num_regs = xcvr_diag_vals->num_regs;
2348 for (i = 0; i < num_lanes; i++) {
2349 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
2350 for (j = 0; j < num_regs; j++)
2351 regmap_write(regmap, reg_pairs[j].off,
2356 /* PHY PCS common registers configurations */
2357 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc];
2359 reg_pairs = pcs_cmn_vals->reg_pairs;
2360 num_regs = pcs_cmn_vals->num_regs;
2361 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2362 for (i = 0; i < num_regs; i++)
2363 regmap_write(regmap, reg_pairs[i].off,
2367 /* PMA common registers configurations */
2368 cmn_vals = init_data->cmn_vals[ref_clk][phy_t1][phy_t2][ssc];
2370 reg_pairs = cmn_vals->reg_pairs;
2371 num_regs = cmn_vals->num_regs;
2372 regmap = cdns_phy->regmap_common_cdb;
2373 for (i = 0; i < num_regs; i++)
2374 regmap_write(regmap, reg_pairs[i].off,
2378 /* PMA TX lane registers configurations */
2379 tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_t1][phy_t2][ssc];
2381 reg_pairs = tx_ln_vals->reg_pairs;
2382 num_regs = tx_ln_vals->num_regs;
2383 for (i = 0; i < num_lanes; i++) {
2384 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
2385 for (j = 0; j < num_regs; j++)
2386 regmap_write(regmap, reg_pairs[j].off,
2391 /* PMA RX lane registers configurations */
2392 rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_t1][phy_t2][ssc];
2394 reg_pairs = rx_ln_vals->reg_pairs;
2395 num_regs = rx_ln_vals->num_regs;
2396 for (i = 0; i < num_lanes; i++) {
2397 regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane];
2398 for (j = 0; j < num_regs; j++)
2399 regmap_write(regmap, reg_pairs[j].off,
2404 reset_control_deassert(cdns_phy->phys[node].lnk_rst);
2407 /* Take the PHY out of reset */
2408 ret = reset_control_deassert(cdns_phy->phy_rst);
2415 static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy)
2417 struct device *dev = cdns_phy->dev;
2419 of_clk_del_provider(dev->of_node);
2422 static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy)
2424 struct device *dev = cdns_phy->dev;
2425 struct device_node *node = dev->of_node;
2426 struct clk_hw_onecell_data *data;
2429 data = devm_kzalloc(dev, struct_size(data, hws, CDNS_TORRENT_OUTPUT_CLOCKS), GFP_KERNEL);
2433 data->num = CDNS_TORRENT_OUTPUT_CLOCKS;
2434 cdns_phy->clk_hw_data = data;
2436 ret = cdns_torrent_derived_refclk_register(cdns_phy);
2438 dev_err(dev, "failed to register derived refclk\n");
2442 ret = cdns_torrent_received_refclk_register(cdns_phy);
2444 dev_err(dev, "failed to register received refclk\n");
2448 ret = cdns_torrent_refclk_driver_register(cdns_phy);
2450 dev_err(dev, "failed to register refclk driver\n");
2454 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data);
2456 dev_err(dev, "Failed to add clock provider: %s\n", node->name);
2463 static int cdns_torrent_reset(struct cdns_torrent_phy *cdns_phy)
2465 struct device *dev = cdns_phy->dev;
2467 cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0);
2468 if (IS_ERR(cdns_phy->phy_rst)) {
2469 dev_err(dev, "%s: failed to get reset\n",
2470 dev->of_node->full_name);
2471 return PTR_ERR(cdns_phy->phy_rst);
2474 cdns_phy->apb_rst = devm_reset_control_get_optional_exclusive(dev, "torrent_apb");
2475 if (IS_ERR(cdns_phy->apb_rst)) {
2476 dev_err(dev, "%s: failed to get apb reset\n",
2477 dev->of_node->full_name);
2478 return PTR_ERR(cdns_phy->apb_rst);
2484 static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy)
2486 struct device *dev = cdns_phy->dev;
2487 unsigned long ref_clk_rate;
2490 cdns_phy->clk = devm_clk_get(dev, "refclk");
2491 if (IS_ERR(cdns_phy->clk)) {
2492 dev_err(dev, "phy ref clock not found\n");
2493 return PTR_ERR(cdns_phy->clk);
2496 ret = clk_prepare_enable(cdns_phy->clk);
2498 dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
2502 ref_clk_rate = clk_get_rate(cdns_phy->clk);
2503 if (!ref_clk_rate) {
2504 dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
2505 clk_disable_unprepare(cdns_phy->clk);
2509 switch (ref_clk_rate) {
2510 case REF_CLK_19_2MHZ:
2511 cdns_phy->ref_clk_rate = CLK_19_2_MHZ;
2514 cdns_phy->ref_clk_rate = CLK_25_MHZ;
2516 case REF_CLK_100MHZ:
2517 cdns_phy->ref_clk_rate = CLK_100_MHZ;
2520 dev_err(cdns_phy->dev, "Invalid Ref Clock Rate\n");
2521 clk_disable_unprepare(cdns_phy->clk);
2528 static int cdns_torrent_phy_probe(struct platform_device *pdev)
2530 struct cdns_torrent_phy *cdns_phy;
2531 struct device *dev = &pdev->dev;
2532 struct phy_provider *phy_provider;
2533 const struct cdns_torrent_data *data;
2534 struct device_node *child;
2535 int ret, subnodes, node = 0, i;
2536 u32 total_num_lanes = 0;
2537 int already_configured;
2538 u8 init_dp_regmap = 0;
2541 /* Get init data for this PHY */
2542 data = of_device_get_match_data(dev);
2546 cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
2550 dev_set_drvdata(dev, cdns_phy);
2551 cdns_phy->dev = dev;
2552 cdns_phy->init_data = data;
2554 cdns_phy->sd_base = devm_platform_ioremap_resource(pdev, 0);
2555 if (IS_ERR(cdns_phy->sd_base))
2556 return PTR_ERR(cdns_phy->sd_base);
2558 subnodes = of_get_available_child_count(dev->of_node);
2559 if (subnodes == 0) {
2560 dev_err(dev, "No available link subnodes found\n");
2564 ret = cdns_torrent_regmap_init(cdns_phy);
2568 ret = cdns_torrent_regfield_init(cdns_phy);
2572 ret = cdns_torrent_clk_register(cdns_phy);
2576 regmap_field_read(cdns_phy->phy_pma_cmn_ctrl_1, &already_configured);
2578 if (!already_configured) {
2579 ret = cdns_torrent_reset(cdns_phy);
2583 ret = cdns_torrent_clk(cdns_phy);
2588 reset_control_deassert(cdns_phy->apb_rst);
2591 for_each_available_child_of_node(dev->of_node, child) {
2594 /* PHY subnode name must be 'phy'. */
2595 if (!(of_node_name_eq(child, "phy")))
2598 cdns_phy->phys[node].lnk_rst =
2599 of_reset_control_array_get_exclusive(child);
2600 if (IS_ERR(cdns_phy->phys[node].lnk_rst)) {
2601 dev_err(dev, "%s: failed to get reset\n",
2603 ret = PTR_ERR(cdns_phy->phys[node].lnk_rst);
2607 if (of_property_read_u32(child, "reg",
2608 &cdns_phy->phys[node].mlane)) {
2609 dev_err(dev, "%s: No \"reg\"-property.\n",
2615 if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) {
2616 dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n",
2624 cdns_phy->phys[node].phy_type = TYPE_PCIE;
2627 cdns_phy->phys[node].phy_type = TYPE_DP;
2629 case PHY_TYPE_SGMII:
2630 cdns_phy->phys[node].phy_type = TYPE_SGMII;
2632 case PHY_TYPE_QSGMII:
2633 cdns_phy->phys[node].phy_type = TYPE_QSGMII;
2636 cdns_phy->phys[node].phy_type = TYPE_USB;
2639 dev_err(dev, "Unsupported protocol\n");
2644 if (of_property_read_u32(child, "cdns,num-lanes",
2645 &cdns_phy->phys[node].num_lanes)) {
2646 dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n",
2652 total_num_lanes += cdns_phy->phys[node].num_lanes;
2655 cdns_phy->phys[node].ssc_mode = NO_SSC;
2656 of_property_read_u32(child, "cdns,ssc-mode",
2657 &cdns_phy->phys[node].ssc_mode);
2659 if (!already_configured)
2660 gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops);
2662 gphy = devm_phy_create(dev, child, &noop_ops);
2664 ret = PTR_ERR(gphy);
2668 if (cdns_phy->phys[node].phy_type == TYPE_DP) {
2669 switch (cdns_phy->phys[node].num_lanes) {
2673 /* valid number of lanes */
2676 dev_err(dev, "unsupported number of lanes: %d\n",
2677 cdns_phy->phys[node].num_lanes);
2682 cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE;
2683 of_property_read_u32(child, "cdns,max-bit-rate",
2684 &cdns_phy->max_bit_rate);
2686 switch (cdns_phy->max_bit_rate) {
2695 /* valid bit rate */
2698 dev_err(dev, "unsupported max bit rate: %dMbps\n",
2699 cdns_phy->max_bit_rate);
2704 /* DPTX registers */
2705 cdns_phy->base = devm_platform_ioremap_resource(pdev, 1);
2706 if (IS_ERR(cdns_phy->base)) {
2707 ret = PTR_ERR(cdns_phy->base);
2711 if (!init_dp_regmap) {
2712 ret = cdns_torrent_dp_regmap_init(cdns_phy);
2716 ret = cdns_torrent_dp_regfield_init(cdns_phy);
2723 dev_dbg(dev, "DP max bit rate %d.%03d Gbps\n",
2724 cdns_phy->max_bit_rate / 1000,
2725 cdns_phy->max_bit_rate % 1000);
2727 gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes;
2728 gphy->attrs.max_link_rate = cdns_phy->max_bit_rate;
2729 gphy->attrs.mode = PHY_MODE_DP;
2732 cdns_phy->phys[node].phy = gphy;
2733 phy_set_drvdata(gphy, &cdns_phy->phys[node]);
2737 cdns_phy->nsubnodes = node;
2739 if (total_num_lanes > MAX_NUM_LANES) {
2740 dev_err(dev, "Invalid lane configuration\n");
2745 if (cdns_phy->nsubnodes > 1 && !already_configured) {
2746 ret = cdns_torrent_phy_configure_multilink(cdns_phy);
2751 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2752 if (IS_ERR(phy_provider)) {
2753 ret = PTR_ERR(phy_provider);
2757 if (cdns_phy->nsubnodes > 1)
2758 dev_dbg(dev, "Multi-link: %s (%d lanes) & %s (%d lanes)",
2759 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
2760 cdns_phy->phys[0].num_lanes,
2761 cdns_torrent_get_phy_type(cdns_phy->phys[1].phy_type),
2762 cdns_phy->phys[1].num_lanes);
2764 dev_dbg(dev, "Single link: %s (%d lanes)",
2765 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
2766 cdns_phy->phys[0].num_lanes);
2773 for (i = 0; i < node; i++)
2774 reset_control_put(cdns_phy->phys[i].lnk_rst);
2776 reset_control_assert(cdns_phy->apb_rst);
2777 clk_disable_unprepare(cdns_phy->clk);
2779 cdns_torrent_clk_cleanup(cdns_phy);
2783 static int cdns_torrent_phy_remove(struct platform_device *pdev)
2785 struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev);
2788 reset_control_assert(cdns_phy->phy_rst);
2789 reset_control_assert(cdns_phy->apb_rst);
2790 for (i = 0; i < cdns_phy->nsubnodes; i++) {
2791 reset_control_assert(cdns_phy->phys[i].lnk_rst);
2792 reset_control_put(cdns_phy->phys[i].lnk_rst);
2795 clk_disable_unprepare(cdns_phy->clk);
2796 cdns_torrent_clk_cleanup(cdns_phy);
2801 /* Single DisplayPort(DP) link configuration */
2802 static struct cdns_reg_pairs sl_dp_link_cmn_regs[] = {
2803 {0x0000, PHY_PLL_CFG},
2806 static struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = {
2807 {0x0000, XCVR_DIAG_HSCLK_SEL},
2808 {0x0001, XCVR_DIAG_PLLDRC_CTRL}
2811 static struct cdns_torrent_vals sl_dp_link_cmn_vals = {
2812 .reg_pairs = sl_dp_link_cmn_regs,
2813 .num_regs = ARRAY_SIZE(sl_dp_link_cmn_regs),
2816 static struct cdns_torrent_vals sl_dp_xcvr_diag_ln_vals = {
2817 .reg_pairs = sl_dp_xcvr_diag_ln_regs,
2818 .num_regs = ARRAY_SIZE(sl_dp_xcvr_diag_ln_regs),
2821 /* Single DP, 19.2 MHz Ref clk, no SSC */
2822 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = {
2823 {0x0014, CMN_SSM_BIAS_TMR},
2824 {0x0027, CMN_PLLSM0_PLLPRE_TMR},
2825 {0x00A1, CMN_PLLSM0_PLLLOCK_TMR},
2826 {0x0027, CMN_PLLSM1_PLLPRE_TMR},
2827 {0x00A1, CMN_PLLSM1_PLLLOCK_TMR},
2828 {0x0060, CMN_BGCAL_INIT_TMR},
2829 {0x0060, CMN_BGCAL_ITER_TMR},
2830 {0x0014, CMN_IBCAL_INIT_TMR},
2831 {0x0018, CMN_TXPUCAL_INIT_TMR},
2832 {0x0005, CMN_TXPUCAL_ITER_TMR},
2833 {0x0018, CMN_TXPDCAL_INIT_TMR},
2834 {0x0005, CMN_TXPDCAL_ITER_TMR},
2835 {0x0240, CMN_RXCAL_INIT_TMR},
2836 {0x0005, CMN_RXCAL_ITER_TMR},
2837 {0x0002, CMN_SD_CAL_INIT_TMR},
2838 {0x0002, CMN_SD_CAL_ITER_TMR},
2839 {0x000B, CMN_SD_CAL_REFTIM_START},
2840 {0x0137, CMN_SD_CAL_PLLCNT_START},
2841 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
2842 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
2843 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
2844 {0x0004, CMN_PLL0_DSM_DIAG_M0},
2845 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
2846 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
2847 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
2848 {0x0004, CMN_PLL1_DSM_DIAG_M0},
2849 {0x00C0, CMN_PLL0_VCOCAL_INIT_TMR},
2850 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
2851 {0x00C0, CMN_PLL1_VCOCAL_INIT_TMR},
2852 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
2853 {0x0260, CMN_PLL0_VCOCAL_REFTIM_START},
2854 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2855 {0x0260, CMN_PLL1_VCOCAL_REFTIM_START},
2856 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
2859 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = {
2860 {0x0780, TX_RCVDET_ST_TMR},
2861 {0x00FB, TX_PSC_A0},
2862 {0x04AA, TX_PSC_A2},
2863 {0x04AA, TX_PSC_A3},
2864 {0x000F, XCVR_DIAG_BIDI_CTRL}
2867 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = {
2868 {0x0000, RX_PSC_A0},
2869 {0x0000, RX_PSC_A2},
2870 {0x0000, RX_PSC_A3},
2871 {0x0000, RX_PSC_CAL},
2872 {0x0000, RX_REE_GCSM1_CTRL},
2873 {0x0000, RX_REE_GCSM2_CTRL},
2874 {0x0000, RX_REE_PERGCSM_CTRL}
2877 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_cmn_vals = {
2878 .reg_pairs = sl_dp_19_2_no_ssc_cmn_regs,
2879 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_cmn_regs),
2882 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_tx_ln_vals = {
2883 .reg_pairs = sl_dp_19_2_no_ssc_tx_ln_regs,
2884 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_tx_ln_regs),
2887 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_rx_ln_vals = {
2888 .reg_pairs = sl_dp_19_2_no_ssc_rx_ln_regs,
2889 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_rx_ln_regs),
2892 /* Single DP, 25 MHz Ref clk, no SSC */
2893 static struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = {
2894 {0x0019, CMN_SSM_BIAS_TMR},
2895 {0x0032, CMN_PLLSM0_PLLPRE_TMR},
2896 {0x00D1, CMN_PLLSM0_PLLLOCK_TMR},
2897 {0x0032, CMN_PLLSM1_PLLPRE_TMR},
2898 {0x00D1, CMN_PLLSM1_PLLLOCK_TMR},
2899 {0x007D, CMN_BGCAL_INIT_TMR},
2900 {0x007D, CMN_BGCAL_ITER_TMR},
2901 {0x0019, CMN_IBCAL_INIT_TMR},
2902 {0x001E, CMN_TXPUCAL_INIT_TMR},
2903 {0x0006, CMN_TXPUCAL_ITER_TMR},
2904 {0x001E, CMN_TXPDCAL_INIT_TMR},
2905 {0x0006, CMN_TXPDCAL_ITER_TMR},
2906 {0x02EE, CMN_RXCAL_INIT_TMR},
2907 {0x0006, CMN_RXCAL_ITER_TMR},
2908 {0x0002, CMN_SD_CAL_INIT_TMR},
2909 {0x0002, CMN_SD_CAL_ITER_TMR},
2910 {0x000E, CMN_SD_CAL_REFTIM_START},
2911 {0x012B, CMN_SD_CAL_PLLCNT_START},
2912 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
2913 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
2914 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
2915 {0x0004, CMN_PLL0_DSM_DIAG_M0},
2916 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
2917 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
2918 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
2919 {0x0004, CMN_PLL1_DSM_DIAG_M0},
2920 {0x00FA, CMN_PLL0_VCOCAL_INIT_TMR},
2921 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
2922 {0x00FA, CMN_PLL1_VCOCAL_INIT_TMR},
2923 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
2924 {0x0317, CMN_PLL0_VCOCAL_REFTIM_START},
2925 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2926 {0x0317, CMN_PLL1_VCOCAL_REFTIM_START},
2927 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
2930 static struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = {
2931 {0x09C4, TX_RCVDET_ST_TMR},
2932 {0x00FB, TX_PSC_A0},
2933 {0x04AA, TX_PSC_A2},
2934 {0x04AA, TX_PSC_A3},
2935 {0x000F, XCVR_DIAG_BIDI_CTRL}
2938 static struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = {
2939 {0x0000, RX_PSC_A0},
2940 {0x0000, RX_PSC_A2},
2941 {0x0000, RX_PSC_A3},
2942 {0x0000, RX_PSC_CAL},
2943 {0x0000, RX_REE_GCSM1_CTRL},
2944 {0x0000, RX_REE_GCSM2_CTRL},
2945 {0x0000, RX_REE_PERGCSM_CTRL}
2948 static struct cdns_torrent_vals sl_dp_25_no_ssc_cmn_vals = {
2949 .reg_pairs = sl_dp_25_no_ssc_cmn_regs,
2950 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_cmn_regs),
2953 static struct cdns_torrent_vals sl_dp_25_no_ssc_tx_ln_vals = {
2954 .reg_pairs = sl_dp_25_no_ssc_tx_ln_regs,
2955 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_tx_ln_regs),
2958 static struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = {
2959 .reg_pairs = sl_dp_25_no_ssc_rx_ln_regs,
2960 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_rx_ln_regs),
2963 /* Single DP, 100 MHz Ref clk, no SSC */
2964 static struct cdns_reg_pairs sl_dp_100_no_ssc_cmn_regs[] = {
2965 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
2966 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
2969 static struct cdns_reg_pairs sl_dp_100_no_ssc_tx_ln_regs[] = {
2970 {0x00FB, TX_PSC_A0},
2971 {0x04AA, TX_PSC_A2},
2972 {0x04AA, TX_PSC_A3},
2973 {0x000F, XCVR_DIAG_BIDI_CTRL}
2976 static struct cdns_reg_pairs sl_dp_100_no_ssc_rx_ln_regs[] = {
2977 {0x0000, RX_PSC_A0},
2978 {0x0000, RX_PSC_A2},
2979 {0x0000, RX_PSC_A3},
2980 {0x0000, RX_PSC_CAL},
2981 {0x0000, RX_REE_GCSM1_CTRL},
2982 {0x0000, RX_REE_GCSM2_CTRL},
2983 {0x0000, RX_REE_PERGCSM_CTRL}
2986 static struct cdns_torrent_vals sl_dp_100_no_ssc_cmn_vals = {
2987 .reg_pairs = sl_dp_100_no_ssc_cmn_regs,
2988 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_cmn_regs),
2991 static struct cdns_torrent_vals sl_dp_100_no_ssc_tx_ln_vals = {
2992 .reg_pairs = sl_dp_100_no_ssc_tx_ln_regs,
2993 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_tx_ln_regs),
2996 static struct cdns_torrent_vals sl_dp_100_no_ssc_rx_ln_vals = {
2997 .reg_pairs = sl_dp_100_no_ssc_rx_ln_regs,
2998 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_rx_ln_regs),
3001 /* USB and SGMII/QSGMII link configuration */
3002 static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {
3003 {0x0002, PHY_PLL_CFG},
3004 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0},
3005 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
3008 static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = {
3009 {0x0000, XCVR_DIAG_HSCLK_SEL},
3010 {0x0001, XCVR_DIAG_HSCLK_DIV},
3011 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
3014 static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = {
3015 {0x0011, XCVR_DIAG_HSCLK_SEL},
3016 {0x0003, XCVR_DIAG_HSCLK_DIV},
3017 {0x009B, XCVR_DIAG_PLLDRC_CTRL}
3020 static struct cdns_torrent_vals usb_sgmii_link_cmn_vals = {
3021 .reg_pairs = usb_sgmii_link_cmn_regs,
3022 .num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs),
3025 static struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = {
3026 .reg_pairs = usb_sgmii_xcvr_diag_ln_regs,
3027 .num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs),
3030 static struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = {
3031 .reg_pairs = sgmii_usb_xcvr_diag_ln_regs,
3032 .num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs),
3035 /* PCIe and USB Unique SSC link configuration */
3036 static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = {
3037 {0x0003, PHY_PLL_CFG},
3038 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
3039 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
3040 {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0}
3043 static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = {
3044 {0x0000, XCVR_DIAG_HSCLK_SEL},
3045 {0x0001, XCVR_DIAG_HSCLK_DIV},
3046 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
3049 static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = {
3050 {0x0011, XCVR_DIAG_HSCLK_SEL},
3051 {0x0001, XCVR_DIAG_HSCLK_DIV},
3052 {0x00C9, XCVR_DIAG_PLLDRC_CTRL}
3055 static struct cdns_torrent_vals pcie_usb_link_cmn_vals = {
3056 .reg_pairs = pcie_usb_link_cmn_regs,
3057 .num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs),
3060 static struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = {
3061 .reg_pairs = pcie_usb_xcvr_diag_ln_regs,
3062 .num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs),
3065 static struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = {
3066 .reg_pairs = usb_pcie_xcvr_diag_ln_regs,
3067 .num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs),
3070 /* USB 100 MHz Ref clk, internal SSC */
3071 static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = {
3072 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3073 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3074 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3075 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3076 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3077 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3078 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3079 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3080 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3081 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3082 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3083 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3084 {0x0064, CMN_PLL0_INTDIV_M0},
3085 {0x0050, CMN_PLL0_INTDIV_M1},
3086 {0x0064, CMN_PLL1_INTDIV_M0},
3087 {0x0002, CMN_PLL0_FRACDIVH_M0},
3088 {0x0002, CMN_PLL0_FRACDIVH_M1},
3089 {0x0002, CMN_PLL1_FRACDIVH_M0},
3090 {0x0044, CMN_PLL0_HIGH_THR_M0},
3091 {0x0036, CMN_PLL0_HIGH_THR_M1},
3092 {0x0044, CMN_PLL1_HIGH_THR_M0},
3093 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3094 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3095 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3096 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3097 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3098 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3099 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3100 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3101 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3102 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3103 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3104 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3105 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3106 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3107 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3108 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3109 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3110 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3111 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3112 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3113 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3114 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3115 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3116 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3117 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3118 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3119 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
3120 {0x007F, CMN_TXPUCAL_TUNE},
3121 {0x007F, CMN_TXPDCAL_TUNE}
3124 static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = {
3125 .reg_pairs = usb_100_int_ssc_cmn_regs,
3126 .num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs),
3129 /* Single USB link configuration */
3130 static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = {
3131 {0x0000, PHY_PLL_CFG},
3132 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
3135 static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = {
3136 {0x0000, XCVR_DIAG_HSCLK_SEL},
3137 {0x0001, XCVR_DIAG_HSCLK_DIV},
3138 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
3141 static struct cdns_torrent_vals sl_usb_link_cmn_vals = {
3142 .reg_pairs = sl_usb_link_cmn_regs,
3143 .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs),
3146 static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = {
3147 .reg_pairs = sl_usb_xcvr_diag_ln_regs,
3148 .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs),
3151 /* USB PHY PCS common configuration */
3152 static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = {
3153 {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0},
3154 {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0},
3155 {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1}
3158 static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = {
3159 .reg_pairs = usb_phy_pcs_cmn_regs,
3160 .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs),
3163 /* USB 100 MHz Ref clk, no SSC */
3164 static struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = {
3165 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3166 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3167 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3168 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3169 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
3170 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3171 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
3174 static struct cdns_torrent_vals sl_usb_100_no_ssc_cmn_vals = {
3175 .reg_pairs = sl_usb_100_no_ssc_cmn_regs,
3176 .num_regs = ARRAY_SIZE(sl_usb_100_no_ssc_cmn_regs),
3179 static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = {
3180 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3181 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
3182 {0x007F, CMN_TXPUCAL_TUNE},
3183 {0x007F, CMN_TXPDCAL_TUNE}
3186 static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = {
3187 {0x02FF, TX_PSC_A0},
3188 {0x06AF, TX_PSC_A1},
3189 {0x06AE, TX_PSC_A2},
3190 {0x06AE, TX_PSC_A3},
3191 {0x2A82, TX_TXCC_CTRL},
3192 {0x0014, TX_TXCC_CPOST_MULT_01},
3193 {0x0003, XCVR_DIAG_PSC_OVRD}
3196 static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = {
3197 {0x0D1D, RX_PSC_A0},
3198 {0x0D1D, RX_PSC_A1},
3199 {0x0D00, RX_PSC_A2},
3200 {0x0500, RX_PSC_A3},
3201 {0x0013, RX_SIGDET_HL_FILT_TMR},
3202 {0x0000, RX_REE_GCSM1_CTRL},
3203 {0x0C02, RX_REE_ATTEN_THR},
3204 {0x0330, RX_REE_SMGM_CTRL1},
3205 {0x0300, RX_REE_SMGM_CTRL2},
3206 {0x0019, RX_REE_TAP1_CLIP},
3207 {0x0019, RX_REE_TAP2TON_CLIP},
3208 {0x1004, RX_DIAG_SIGDET_TUNE},
3209 {0x00F9, RX_DIAG_NQST_CTRL},
3210 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3211 {0x0002, RX_DIAG_DFE_AMP_TUNE_3},
3212 {0x0000, RX_DIAG_PI_CAP},
3213 {0x0031, RX_DIAG_PI_RATE},
3214 {0x0001, RX_DIAG_ACYA},
3215 {0x018C, RX_CDRLF_CNFG},
3216 {0x0003, RX_CDRLF_CNFG3}
3219 static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = {
3220 .reg_pairs = usb_100_no_ssc_cmn_regs,
3221 .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs),
3224 static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = {
3225 .reg_pairs = usb_100_no_ssc_tx_ln_regs,
3226 .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs),
3229 static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = {
3230 .reg_pairs = usb_100_no_ssc_rx_ln_regs,
3231 .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs),
3234 /* Single link USB, 100 MHz Ref clk, internal SSC */
3235 static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = {
3236 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3237 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3238 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3239 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3240 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3241 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3242 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3243 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3244 {0x0064, CMN_PLL0_INTDIV_M0},
3245 {0x0064, CMN_PLL1_INTDIV_M0},
3246 {0x0002, CMN_PLL0_FRACDIVH_M0},
3247 {0x0002, CMN_PLL1_FRACDIVH_M0},
3248 {0x0044, CMN_PLL0_HIGH_THR_M0},
3249 {0x0044, CMN_PLL1_HIGH_THR_M0},
3250 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3251 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3252 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3253 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3254 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3255 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3256 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3257 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3258 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3259 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3260 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3261 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3262 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3263 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3264 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3265 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
3266 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3267 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3268 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3269 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3270 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3271 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3272 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3273 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
3276 static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = {
3277 .reg_pairs = sl_usb_100_int_ssc_cmn_regs,
3278 .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs),
3281 /* PCIe and SGMII/QSGMII Unique SSC link configuration */
3282 static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = {
3283 {0x0003, PHY_PLL_CFG},
3284 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
3285 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
3286 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
3289 static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = {
3290 {0x0000, XCVR_DIAG_HSCLK_SEL},
3291 {0x0001, XCVR_DIAG_HSCLK_DIV},
3292 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
3295 static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = {
3296 {0x0011, XCVR_DIAG_HSCLK_SEL},
3297 {0x0003, XCVR_DIAG_HSCLK_DIV},
3298 {0x009B, XCVR_DIAG_PLLDRC_CTRL}
3301 static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = {
3302 .reg_pairs = pcie_sgmii_link_cmn_regs,
3303 .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs),
3306 static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = {
3307 .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs,
3308 .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs),
3311 static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = {
3312 .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs,
3313 .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs),
3316 /* SGMII 100 MHz Ref clk, no SSC */
3317 static struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = {
3318 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3319 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3320 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3321 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3322 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3325 static struct cdns_torrent_vals sl_sgmii_100_no_ssc_cmn_vals = {
3326 .reg_pairs = sl_sgmii_100_no_ssc_cmn_regs,
3327 .num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_cmn_regs),
3330 static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = {
3331 {0x007F, CMN_TXPUCAL_TUNE},
3332 {0x007F, CMN_TXPDCAL_TUNE}
3335 static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = {
3336 {0x00F3, TX_PSC_A0},
3337 {0x04A2, TX_PSC_A2},
3338 {0x04A2, TX_PSC_A3},
3339 {0x0000, TX_TXCC_CPOST_MULT_00},
3340 {0x00B3, DRV_DIAG_TX_DRV}
3343 static struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = {
3344 {0x00F3, TX_PSC_A0},
3345 {0x04A2, TX_PSC_A2},
3346 {0x04A2, TX_PSC_A3},
3347 {0x0000, TX_TXCC_CPOST_MULT_00},
3348 {0x00B3, DRV_DIAG_TX_DRV},
3349 {0x4000, XCVR_DIAG_RXCLK_CTRL},
3352 static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = {
3353 {0x091D, RX_PSC_A0},
3354 {0x0900, RX_PSC_A2},
3355 {0x0100, RX_PSC_A3},
3356 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
3357 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
3358 {0x0000, RX_DIAG_DFE_CTRL},
3359 {0x0019, RX_REE_TAP1_CLIP},
3360 {0x0019, RX_REE_TAP2TON_CLIP},
3361 {0x0098, RX_DIAG_NQST_CTRL},
3362 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3363 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
3364 {0x0000, RX_DIAG_PI_CAP},
3365 {0x0010, RX_DIAG_PI_RATE},
3366 {0x0001, RX_DIAG_ACYA},
3367 {0x018C, RX_CDRLF_CNFG},
3370 static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = {
3371 .reg_pairs = sgmii_100_no_ssc_cmn_regs,
3372 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs),
3375 static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = {
3376 .reg_pairs = sgmii_100_no_ssc_tx_ln_regs,
3377 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs),
3380 static struct cdns_torrent_vals ti_sgmii_100_no_ssc_tx_ln_vals = {
3381 .reg_pairs = ti_sgmii_100_no_ssc_tx_ln_regs,
3382 .num_regs = ARRAY_SIZE(ti_sgmii_100_no_ssc_tx_ln_regs),
3385 static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = {
3386 .reg_pairs = sgmii_100_no_ssc_rx_ln_regs,
3387 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs),
3390 /* SGMII 100 MHz Ref clk, internal SSC */
3391 static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = {
3392 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3393 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3394 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3395 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3396 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3397 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3398 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3399 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3400 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3401 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3402 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3403 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3404 {0x0064, CMN_PLL0_INTDIV_M0},
3405 {0x0050, CMN_PLL0_INTDIV_M1},
3406 {0x0064, CMN_PLL1_INTDIV_M0},
3407 {0x0002, CMN_PLL0_FRACDIVH_M0},
3408 {0x0002, CMN_PLL0_FRACDIVH_M1},
3409 {0x0002, CMN_PLL1_FRACDIVH_M0},
3410 {0x0044, CMN_PLL0_HIGH_THR_M0},
3411 {0x0036, CMN_PLL0_HIGH_THR_M1},
3412 {0x0044, CMN_PLL1_HIGH_THR_M0},
3413 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3414 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3415 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3416 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3417 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3418 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3419 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3420 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3421 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3422 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3423 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3424 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3425 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3426 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3427 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3428 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3429 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3430 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3431 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3432 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3433 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3434 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3435 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3436 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3437 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3438 {0x007F, CMN_TXPUCAL_TUNE},
3439 {0x007F, CMN_TXPDCAL_TUNE}
3442 static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = {
3443 .reg_pairs = sgmii_100_int_ssc_cmn_regs,
3444 .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs),
3447 /* QSGMII 100 MHz Ref clk, no SSC */
3448 static struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = {
3449 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3450 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3451 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3452 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3453 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3456 static struct cdns_torrent_vals sl_qsgmii_100_no_ssc_cmn_vals = {
3457 .reg_pairs = sl_qsgmii_100_no_ssc_cmn_regs,
3458 .num_regs = ARRAY_SIZE(sl_qsgmii_100_no_ssc_cmn_regs),
3461 static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = {
3462 {0x007F, CMN_TXPUCAL_TUNE},
3463 {0x007F, CMN_TXPDCAL_TUNE}
3466 static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = {
3467 {0x00F3, TX_PSC_A0},
3468 {0x04A2, TX_PSC_A2},
3469 {0x04A2, TX_PSC_A3},
3470 {0x0000, TX_TXCC_CPOST_MULT_00},
3471 {0x0011, TX_TXCC_MGNFS_MULT_100},
3472 {0x0003, DRV_DIAG_TX_DRV}
3475 static struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = {
3476 {0x00F3, TX_PSC_A0},
3477 {0x04A2, TX_PSC_A2},
3478 {0x04A2, TX_PSC_A3},
3479 {0x0000, TX_TXCC_CPOST_MULT_00},
3480 {0x0011, TX_TXCC_MGNFS_MULT_100},
3481 {0x0003, DRV_DIAG_TX_DRV},
3482 {0x4000, XCVR_DIAG_RXCLK_CTRL},
3485 static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = {
3486 {0x091D, RX_PSC_A0},
3487 {0x0900, RX_PSC_A2},
3488 {0x0100, RX_PSC_A3},
3489 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
3490 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
3491 {0x0000, RX_DIAG_DFE_CTRL},
3492 {0x0019, RX_REE_TAP1_CLIP},
3493 {0x0019, RX_REE_TAP2TON_CLIP},
3494 {0x0098, RX_DIAG_NQST_CTRL},
3495 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3496 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
3497 {0x0000, RX_DIAG_PI_CAP},
3498 {0x0010, RX_DIAG_PI_RATE},
3499 {0x0001, RX_DIAG_ACYA},
3500 {0x018C, RX_CDRLF_CNFG},
3503 static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = {
3504 .reg_pairs = qsgmii_100_no_ssc_cmn_regs,
3505 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs),
3508 static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = {
3509 .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs,
3510 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs),
3513 static struct cdns_torrent_vals ti_qsgmii_100_no_ssc_tx_ln_vals = {
3514 .reg_pairs = ti_qsgmii_100_no_ssc_tx_ln_regs,
3515 .num_regs = ARRAY_SIZE(ti_qsgmii_100_no_ssc_tx_ln_regs),
3518 static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = {
3519 .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs,
3520 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs),
3523 /* QSGMII 100 MHz Ref clk, internal SSC */
3524 static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = {
3525 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3526 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3527 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3528 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3529 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3530 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3531 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3532 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3533 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3534 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3535 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3536 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3537 {0x0064, CMN_PLL0_INTDIV_M0},
3538 {0x0050, CMN_PLL0_INTDIV_M1},
3539 {0x0064, CMN_PLL1_INTDIV_M0},
3540 {0x0002, CMN_PLL0_FRACDIVH_M0},
3541 {0x0002, CMN_PLL0_FRACDIVH_M1},
3542 {0x0002, CMN_PLL1_FRACDIVH_M0},
3543 {0x0044, CMN_PLL0_HIGH_THR_M0},
3544 {0x0036, CMN_PLL0_HIGH_THR_M1},
3545 {0x0044, CMN_PLL1_HIGH_THR_M0},
3546 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3547 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3548 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3549 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3550 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3551 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3552 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3553 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3554 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3555 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3556 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3557 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3558 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3559 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3560 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3561 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3562 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3563 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3564 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3565 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3566 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3567 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3568 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3569 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3570 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3571 {0x007F, CMN_TXPUCAL_TUNE},
3572 {0x007F, CMN_TXPDCAL_TUNE}
3575 static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = {
3576 .reg_pairs = qsgmii_100_int_ssc_cmn_regs,
3577 .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs),
3580 /* Single SGMII/QSGMII link configuration */
3581 static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = {
3582 {0x0000, PHY_PLL_CFG},
3583 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
3586 static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = {
3587 {0x0000, XCVR_DIAG_HSCLK_SEL},
3588 {0x0003, XCVR_DIAG_HSCLK_DIV},
3589 {0x0013, XCVR_DIAG_PLLDRC_CTRL}
3592 static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = {
3593 .reg_pairs = sl_sgmii_link_cmn_regs,
3594 .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs),
3597 static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
3598 .reg_pairs = sl_sgmii_xcvr_diag_ln_regs,
3599 .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
3602 /* Multi link PCIe, 100 MHz Ref clk, internal SSC */
3603 static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
3604 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3605 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3606 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3607 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3608 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3609 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3610 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3611 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3612 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3613 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3614 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3615 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3616 {0x0064, CMN_PLL0_INTDIV_M0},
3617 {0x0050, CMN_PLL0_INTDIV_M1},
3618 {0x0064, CMN_PLL1_INTDIV_M0},
3619 {0x0002, CMN_PLL0_FRACDIVH_M0},
3620 {0x0002, CMN_PLL0_FRACDIVH_M1},
3621 {0x0002, CMN_PLL1_FRACDIVH_M0},
3622 {0x0044, CMN_PLL0_HIGH_THR_M0},
3623 {0x0036, CMN_PLL0_HIGH_THR_M1},
3624 {0x0044, CMN_PLL1_HIGH_THR_M0},
3625 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3626 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3627 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3628 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3629 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3630 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3631 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3632 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3633 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3634 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3635 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3636 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3637 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3638 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3639 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3640 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3641 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3642 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3643 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3644 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3645 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3646 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3647 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3648 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3649 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
3652 static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = {
3653 .reg_pairs = pcie_100_int_ssc_cmn_regs,
3654 .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs),
3657 /* Single link PCIe, 100 MHz Ref clk, internal SSC */
3658 static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = {
3659 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3660 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3661 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3662 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3663 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3664 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3665 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3666 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3667 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3668 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3669 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3670 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3671 {0x0064, CMN_PLL0_INTDIV_M0},
3672 {0x0050, CMN_PLL0_INTDIV_M1},
3673 {0x0050, CMN_PLL1_INTDIV_M0},
3674 {0x0002, CMN_PLL0_FRACDIVH_M0},
3675 {0x0002, CMN_PLL0_FRACDIVH_M1},
3676 {0x0002, CMN_PLL1_FRACDIVH_M0},
3677 {0x0044, CMN_PLL0_HIGH_THR_M0},
3678 {0x0036, CMN_PLL0_HIGH_THR_M1},
3679 {0x0036, CMN_PLL1_HIGH_THR_M0},
3680 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3681 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3682 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3683 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3684 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3685 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3686 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3687 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3688 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3689 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3690 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3691 {0x0058, CMN_PLL1_SS_CTRL3_M0},
3692 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3693 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3694 {0x0012, CMN_PLL1_SS_CTRL4_M0},
3695 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3696 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3697 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3698 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3699 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3700 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3701 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3702 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3703 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3704 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
3707 static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = {
3708 .reg_pairs = sl_pcie_100_int_ssc_cmn_regs,
3709 .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs),
3712 /* PCIe, 100 MHz Ref clk, no SSC & external SSC */
3713 static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = {
3714 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3715 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3716 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}
3719 static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = {
3720 {0x0019, RX_REE_TAP1_CLIP},
3721 {0x0019, RX_REE_TAP2TON_CLIP},
3722 {0x0001, RX_DIAG_ACYA}
3725 static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = {
3726 .reg_pairs = pcie_100_ext_no_ssc_cmn_regs,
3727 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs),
3730 static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = {
3731 .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs,
3732 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs),
3735 static const struct cdns_torrent_data cdns_map_torrent = {
3736 .block_offset_shift = 0x2,
3737 .reg_offset_shift = 0x2,
3741 [NO_SSC] = &sl_dp_link_cmn_vals,
3747 [EXTERNAL_SSC] = NULL,
3748 [INTERNAL_SSC] = NULL,
3751 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3752 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3753 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3756 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3757 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3758 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3761 [NO_SSC] = &pcie_usb_link_cmn_vals,
3762 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3763 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3768 [NO_SSC] = &sl_sgmii_link_cmn_vals,
3771 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3772 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3773 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3776 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3777 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3778 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3783 [NO_SSC] = &sl_sgmii_link_cmn_vals,
3786 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3787 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3788 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3791 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3792 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3793 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3798 [NO_SSC] = &sl_usb_link_cmn_vals,
3799 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
3800 [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
3803 [NO_SSC] = &pcie_usb_link_cmn_vals,
3804 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3805 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3808 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3809 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3810 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3813 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3814 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3815 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3822 [NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
3828 [EXTERNAL_SSC] = NULL,
3829 [INTERNAL_SSC] = NULL,
3832 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3833 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3834 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3837 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3838 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3839 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
3842 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3843 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3844 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
3849 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
3852 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3853 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3854 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3857 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3858 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3859 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3864 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
3867 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3868 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3869 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
3872 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3873 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3874 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
3879 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
3880 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
3881 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
3884 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3885 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3886 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
3889 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3890 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3891 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3894 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3895 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3896 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
3903 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3904 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3905 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3908 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3909 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3910 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3913 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3914 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3915 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3918 [NO_SSC] = &usb_phy_pcs_cmn_vals,
3919 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3920 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
3928 [NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals,
3935 [NO_SSC] = &sl_dp_25_no_ssc_cmn_vals,
3942 [NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
3948 [EXTERNAL_SSC] = NULL,
3949 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
3952 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3953 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3954 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3957 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3958 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3959 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3962 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
3963 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
3964 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
3969 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
3972 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
3973 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3974 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
3977 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
3978 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3979 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
3984 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
3987 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3988 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3989 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
3992 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3993 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3994 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
3999 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4000 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4001 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4004 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
4005 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
4006 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
4009 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4010 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4011 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4014 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4015 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4016 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4025 [NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals,
4032 [NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals,
4039 [NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals,
4045 [EXTERNAL_SSC] = NULL,
4046 [INTERNAL_SSC] = NULL,
4050 [EXTERNAL_SSC] = NULL,
4051 [INTERNAL_SSC] = NULL,
4055 [EXTERNAL_SSC] = NULL,
4056 [INTERNAL_SSC] = NULL,
4060 [EXTERNAL_SSC] = NULL,
4061 [INTERNAL_SSC] = NULL,
4066 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4069 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4070 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4071 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4074 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4075 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4076 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4081 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4084 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4085 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4086 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4089 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4090 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4091 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4096 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4097 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4098 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4101 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4102 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4103 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4106 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4107 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4108 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4111 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4112 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4113 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4122 [NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals,
4129 [NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals,
4136 [NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals,
4141 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4142 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4143 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4146 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4147 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4148 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4151 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4152 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4153 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4156 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4157 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4158 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4163 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4166 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4167 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4168 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4171 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4172 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4173 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4178 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4181 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4182 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4183 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4186 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4187 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4188 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4193 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4194 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4195 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4198 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4199 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4200 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4203 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4204 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4205 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4208 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4209 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4210 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4217 static const struct cdns_torrent_data ti_j721e_map_torrent = {
4218 .block_offset_shift = 0x0,
4219 .reg_offset_shift = 0x1,
4223 [NO_SSC] = &sl_dp_link_cmn_vals,
4229 [EXTERNAL_SSC] = NULL,
4230 [INTERNAL_SSC] = NULL,
4233 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
4234 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4235 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4238 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
4239 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4240 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4243 [NO_SSC] = &pcie_usb_link_cmn_vals,
4244 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4245 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4250 [NO_SSC] = &sl_sgmii_link_cmn_vals,
4253 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
4254 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4255 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4258 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4259 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4260 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4265 [NO_SSC] = &sl_sgmii_link_cmn_vals,
4268 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
4269 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4270 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4273 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4274 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4275 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4280 [NO_SSC] = &sl_usb_link_cmn_vals,
4281 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
4282 [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
4285 [NO_SSC] = &pcie_usb_link_cmn_vals,
4286 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4287 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4290 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4291 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4292 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4295 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4296 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4297 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4304 [NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
4310 [EXTERNAL_SSC] = NULL,
4311 [INTERNAL_SSC] = NULL,
4314 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4315 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4316 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4319 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4320 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4321 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4324 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
4325 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
4326 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
4331 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
4334 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4335 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4336 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4339 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4340 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4341 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4346 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
4349 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4350 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4351 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4354 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4355 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4356 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4361 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
4362 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
4363 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
4366 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
4367 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
4368 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
4371 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4372 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4373 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4376 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4377 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4378 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4385 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4386 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4387 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4390 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4391 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4392 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4395 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4396 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4397 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4400 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4401 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4402 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4410 [NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals,
4417 [NO_SSC] = &sl_dp_25_no_ssc_cmn_vals,
4424 [NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
4430 [EXTERNAL_SSC] = NULL,
4431 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
4434 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
4435 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
4436 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
4439 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
4440 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
4441 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
4444 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
4445 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
4446 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
4451 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
4454 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
4455 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
4456 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
4459 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
4460 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
4461 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
4466 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
4469 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4470 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4471 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
4474 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4475 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4476 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4481 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4482 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4483 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4486 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
4487 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
4488 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
4491 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4492 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4493 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4496 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4497 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4498 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4507 [NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals,
4514 [NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals,
4521 [NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals,
4527 [EXTERNAL_SSC] = NULL,
4528 [INTERNAL_SSC] = NULL,
4532 [EXTERNAL_SSC] = NULL,
4533 [INTERNAL_SSC] = NULL,
4537 [EXTERNAL_SSC] = NULL,
4538 [INTERNAL_SSC] = NULL,
4542 [EXTERNAL_SSC] = NULL,
4543 [INTERNAL_SSC] = NULL,
4548 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4551 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4552 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4553 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4556 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4557 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4558 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4563 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4566 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4567 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4568 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4571 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4572 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4573 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4578 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4579 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4580 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4583 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4584 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4585 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4588 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4589 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4590 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4593 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4594 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4595 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4604 [NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals,
4611 [NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals,
4618 [NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals,
4623 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4624 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4625 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4628 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4629 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4630 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4633 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4634 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4635 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4638 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4639 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4640 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4645 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4648 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4649 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4650 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4653 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4654 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4655 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4660 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4663 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4664 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4665 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4668 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4669 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4670 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4675 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4676 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4677 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4680 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4681 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4682 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4685 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4686 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4687 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4690 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4691 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4692 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4699 static const struct of_device_id cdns_torrent_phy_of_match[] = {
4701 .compatible = "cdns,torrent-phy",
4702 .data = &cdns_map_torrent,
4705 .compatible = "ti,j721e-serdes-10g",
4706 .data = &ti_j721e_map_torrent,
4710 MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match);
4712 static struct platform_driver cdns_torrent_phy_driver = {
4713 .probe = cdns_torrent_phy_probe,
4714 .remove = cdns_torrent_phy_remove,
4716 .name = "cdns-torrent-phy",
4717 .of_match_table = cdns_torrent_phy_of_match,
4720 module_platform_driver(cdns_torrent_phy_driver);
4722 MODULE_AUTHOR("Cadence Design Systems, Inc.");
4723 MODULE_DESCRIPTION("Cadence Torrent PHY driver");
4724 MODULE_LICENSE("GPL v2");