1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence Torrent SD0801 PHY driver.
5 * Copyright 2018 Cadence Design Systems, Inc.
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/delay.h>
14 #include <linux/err.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/phy/phy.h>
23 #include <linux/platform_device.h>
24 #include <linux/reset.h>
25 #include <linux/regmap.h>
27 #define REF_CLK_19_2MHZ 19200000
28 #define REF_CLK_25MHZ 25000000
29 #define REF_CLK_100MHZ 100000000
31 #define MAX_NUM_LANES 4
32 #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */
34 #define NUM_SSC_MODE 3
36 #define NUM_PHY_TYPE 6
38 #define POLL_TIMEOUT_US 5000
39 #define PLL_LOCK_TIMEOUT 100000
41 #define DP_PLL0 BIT(0)
42 #define DP_PLL1 BIT(1)
44 #define TORRENT_COMMON_CDB_OFFSET 0x0
46 #define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
47 ((0x4000 << (block_offset)) + \
48 (((ln) << 9) << (reg_offset)))
50 #define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
51 ((0x8000 << (block_offset)) + \
52 (((ln) << 9) << (reg_offset)))
54 #define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \
55 (0xC000 << (block_offset))
57 #define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \
58 ((0xD000 << (block_offset)) + \
59 (((ln) << 8) << (reg_offset)))
61 #define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \
62 (0xE000 << (block_offset))
64 #define TORRENT_DPTX_PHY_OFFSET 0x0
67 * register offsets from DPTX PHY register block base (i.e MHDP
68 * register base + 0x30a00)
70 #define PHY_AUX_CTRL 0x04
71 #define PHY_RESET 0x20
72 #define PMA_TX_ELEC_IDLE_SHIFT 4
73 #define PHY_PMA_XCVR_PLLCLK_EN 0x24
74 #define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28
75 #define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c
76 #define PHY_POWER_STATE_LN(ln) ((ln) * 8)
77 #define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU
78 #define PHY_PMA_XCVR_POWER_STATE_ACK 0x30
79 #define PHY_PMA_CMN_READY 0x34
82 * register offsets from SD0801 PHY register block base (i.e MHDP
83 * register base + 0x500000)
85 #define CMN_SSM_BANDGAP_TMR 0x0021U
86 #define CMN_SSM_BIAS_TMR 0x0022U
87 #define CMN_PLLSM0_PLLPRE_TMR 0x002AU
88 #define CMN_PLLSM0_PLLLOCK_TMR 0x002CU
89 #define CMN_PLLSM1_PLLPRE_TMR 0x0032U
90 #define CMN_PLLSM1_PLLLOCK_TMR 0x0034U
91 #define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U
92 #define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U
93 #define CMN_CDIAG_REFCLK_OVRD 0x004CU
94 #define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U
95 #define CMN_BGCAL_INIT_TMR 0x0064U
96 #define CMN_BGCAL_ITER_TMR 0x0065U
97 #define CMN_IBCAL_INIT_TMR 0x0074U
98 #define CMN_PLL0_VCOCAL_TCTRL 0x0082U
99 #define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U
100 #define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U
101 #define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U
102 #define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U
103 #define CMN_PLL0_INTDIV_M0 0x0090U
104 #define CMN_PLL0_FRACDIVL_M0 0x0091U
105 #define CMN_PLL0_FRACDIVH_M0 0x0092U
106 #define CMN_PLL0_HIGH_THR_M0 0x0093U
107 #define CMN_PLL0_DSM_DIAG_M0 0x0094U
108 #define CMN_PLL0_DSM_FBH_OVRD_M0 0x0095U
109 #define CMN_PLL0_SS_CTRL1_M0 0x0098U
110 #define CMN_PLL0_SS_CTRL2_M0 0x0099U
111 #define CMN_PLL0_SS_CTRL3_M0 0x009AU
112 #define CMN_PLL0_SS_CTRL4_M0 0x009BU
113 #define CMN_PLL0_LOCK_REFCNT_START 0x009CU
114 #define CMN_PLL0_LOCK_PLLCNT_START 0x009EU
115 #define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU
116 #define CMN_PLL0_INTDIV_M1 0x00A0U
117 #define CMN_PLL0_FRACDIVH_M1 0x00A2U
118 #define CMN_PLL0_HIGH_THR_M1 0x00A3U
119 #define CMN_PLL0_DSM_DIAG_M1 0x00A4U
120 #define CMN_PLL0_SS_CTRL1_M1 0x00A8U
121 #define CMN_PLL0_SS_CTRL2_M1 0x00A9U
122 #define CMN_PLL0_SS_CTRL3_M1 0x00AAU
123 #define CMN_PLL0_SS_CTRL4_M1 0x00ABU
124 #define CMN_PLL1_VCOCAL_TCTRL 0x00C2U
125 #define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U
126 #define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U
127 #define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U
128 #define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U
129 #define CMN_PLL1_INTDIV_M0 0x00D0U
130 #define CMN_PLL1_FRACDIVL_M0 0x00D1U
131 #define CMN_PLL1_FRACDIVH_M0 0x00D2U
132 #define CMN_PLL1_HIGH_THR_M0 0x00D3U
133 #define CMN_PLL1_DSM_DIAG_M0 0x00D4U
134 #define CMN_PLL1_DSM_FBH_OVRD_M0 0x00D5U
135 #define CMN_PLL1_DSM_FBL_OVRD_M0 0x00D6U
136 #define CMN_PLL1_SS_CTRL1_M0 0x00D8U
137 #define CMN_PLL1_SS_CTRL2_M0 0x00D9U
138 #define CMN_PLL1_SS_CTRL3_M0 0x00DAU
139 #define CMN_PLL1_SS_CTRL4_M0 0x00DBU
140 #define CMN_PLL1_LOCK_REFCNT_START 0x00DCU
141 #define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU
142 #define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU
143 #define CMN_TXPUCAL_TUNE 0x0103U
144 #define CMN_TXPUCAL_INIT_TMR 0x0104U
145 #define CMN_TXPUCAL_ITER_TMR 0x0105U
146 #define CMN_TXPDCAL_TUNE 0x010BU
147 #define CMN_TXPDCAL_INIT_TMR 0x010CU
148 #define CMN_TXPDCAL_ITER_TMR 0x010DU
149 #define CMN_RXCAL_INIT_TMR 0x0114U
150 #define CMN_RXCAL_ITER_TMR 0x0115U
151 #define CMN_SD_CAL_INIT_TMR 0x0124U
152 #define CMN_SD_CAL_ITER_TMR 0x0125U
153 #define CMN_SD_CAL_REFTIM_START 0x0126U
154 #define CMN_SD_CAL_PLLCNT_START 0x0128U
155 #define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U
156 #define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U
157 #define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U
158 #define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U
159 #define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U
160 #define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U
161 #define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01B1U
162 #define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U
163 #define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U
164 #define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U
165 #define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U
166 #define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U
167 #define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U
168 #define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U
169 #define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U
170 #define CMN_DIAG_BIAS_OVRD1 0x01E1U
172 /* PMA TX Lane registers */
173 #define TX_TXCC_CTRL 0x0040U
174 #define TX_TXCC_CPOST_MULT_00 0x004CU
175 #define TX_TXCC_CPOST_MULT_01 0x004DU
176 #define TX_TXCC_MGNFS_MULT_000 0x0050U
177 #define TX_TXCC_MGNFS_MULT_100 0x0054U
178 #define DRV_DIAG_TX_DRV 0x00C6U
179 #define XCVR_DIAG_PLLDRC_CTRL 0x00E5U
180 #define XCVR_DIAG_HSCLK_SEL 0x00E6U
181 #define XCVR_DIAG_HSCLK_DIV 0x00E7U
182 #define XCVR_DIAG_RXCLK_CTRL 0x00E9U
183 #define XCVR_DIAG_BIDI_CTRL 0x00EAU
184 #define XCVR_DIAG_PSC_OVRD 0x00EBU
185 #define TX_PSC_A0 0x0100U
186 #define TX_PSC_A1 0x0101U
187 #define TX_PSC_A2 0x0102U
188 #define TX_PSC_A3 0x0103U
189 #define TX_RCVDET_ST_TMR 0x0123U
190 #define TX_DIAG_ACYA 0x01E7U
191 #define TX_DIAG_ACYA_HBDC_MASK 0x0001U
193 /* PMA RX Lane registers */
194 #define RX_PSC_A0 0x0000U
195 #define RX_PSC_A1 0x0001U
196 #define RX_PSC_A2 0x0002U
197 #define RX_PSC_A3 0x0003U
198 #define RX_PSC_CAL 0x0006U
199 #define RX_CDRLF_CNFG 0x0080U
200 #define RX_CDRLF_CNFG3 0x0082U
201 #define RX_SIGDET_HL_FILT_TMR 0x0090U
202 #define RX_REE_GCSM1_CTRL 0x0108U
203 #define RX_REE_GCSM1_EQENM_PH1 0x0109U
204 #define RX_REE_GCSM1_EQENM_PH2 0x010AU
205 #define RX_REE_GCSM2_CTRL 0x0110U
206 #define RX_REE_PERGCSM_CTRL 0x0118U
207 #define RX_REE_ATTEN_THR 0x0149U
208 #define RX_REE_TAP1_CLIP 0x0171U
209 #define RX_REE_TAP2TON_CLIP 0x0172U
210 #define RX_REE_SMGM_CTRL1 0x0177U
211 #define RX_REE_SMGM_CTRL2 0x0178U
212 #define RX_DIAG_DFE_CTRL 0x01E0U
213 #define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U
214 #define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U
215 #define RX_DIAG_NQST_CTRL 0x01E5U
216 #define RX_DIAG_SIGDET_TUNE 0x01E8U
217 #define RX_DIAG_PI_RATE 0x01F4U
218 #define RX_DIAG_PI_CAP 0x01F5U
219 #define RX_DIAG_ACYA 0x01FFU
221 /* PHY PCS common registers */
222 #define PHY_PIPE_CMN_CTRL1 0x0000U
223 #define PHY_PLL_CFG 0x000EU
224 #define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U
225 #define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U
226 #define PHY_PIPE_USB3_GEN2_POST_CFG1 0x0023U
228 /* PHY PCS lane registers */
229 #define PHY_PCS_ISO_LINK_CTRL 0x000BU
231 /* PHY PMA common registers */
232 #define PHY_PMA_CMN_CTRL1 0x0000U
233 #define PHY_PMA_CMN_CTRL2 0x0001U
234 #define PHY_PMA_PLL_RAW_CTRL 0x0003U
236 #define CDNS_TORRENT_OUTPUT_CLOCKS 3
238 static const char * const clk_names[] = {
239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
240 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
241 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
244 static const struct reg_field phy_pll_cfg =
245 REG_FIELD(PHY_PLL_CFG, 0, 1);
247 static const struct reg_field phy_pma_cmn_ctrl_1 =
248 REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0);
250 static const struct reg_field phy_pma_cmn_ctrl_2 =
251 REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7);
253 static const struct reg_field phy_pma_pll_raw_ctrl =
254 REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1);
256 static const struct reg_field phy_reset_ctrl =
257 REG_FIELD(PHY_RESET, 8, 8);
259 static const struct reg_field phy_pcs_iso_link_ctrl_1 =
260 REG_FIELD(PHY_PCS_ISO_LINK_CTRL, 1, 1);
262 static const struct reg_field phy_pipe_cmn_ctrl1_0 = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0);
264 static const struct reg_field cmn_cdiag_refclk_ovrd_4 =
265 REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4);
267 #define REFCLK_OUT_NUM_CMN_CONFIG 4
269 enum cdns_torrent_refclk_out_cmn {
270 CMN_CDIAG_REFCLK_DRV0_CTRL_1,
271 CMN_CDIAG_REFCLK_DRV0_CTRL_4,
272 CMN_CDIAG_REFCLK_DRV0_CTRL_5,
273 CMN_CDIAG_REFCLK_DRV0_CTRL_6,
276 static const struct reg_field refclk_out_cmn_cfg[] = {
277 [CMN_CDIAG_REFCLK_DRV0_CTRL_1] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1),
278 [CMN_CDIAG_REFCLK_DRV0_CTRL_4] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4),
279 [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5),
280 [CMN_CDIAG_REFCLK_DRV0_CTRL_6] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6),
283 static const int refclk_driver_parent_index[] = {
284 CDNS_TORRENT_DERIVED_REFCLK,
285 CDNS_TORRENT_RECEIVED_REFCLK
288 static u32 cdns_torrent_refclk_driver_mux_table[] = { 1, 0 };
290 enum cdns_torrent_phy_type {
299 enum cdns_torrent_ref_clk {
305 enum cdns_torrent_ssc_mode {
311 struct cdns_torrent_inst {
314 enum cdns_torrent_phy_type phy_type;
316 struct reset_control *lnk_rst;
317 enum cdns_torrent_ssc_mode ssc_mode;
320 struct cdns_torrent_phy {
321 void __iomem *base; /* DPTX registers base */
322 void __iomem *sd_base; /* SD0801 registers base */
323 u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
325 struct reset_control *phy_rst;
326 struct reset_control *apb_rst;
329 enum cdns_torrent_ref_clk ref_clk_rate;
330 struct cdns_torrent_inst phys[MAX_NUM_LANES];
332 const struct cdns_torrent_data *init_data;
333 struct regmap *regmap_common_cdb;
334 struct regmap *regmap_phy_pcs_common_cdb;
335 struct regmap *regmap_phy_pma_common_cdb;
336 struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
337 struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
338 struct regmap *regmap_phy_pcs_lane_cdb[MAX_NUM_LANES];
339 struct regmap *regmap_dptx_phy_reg;
340 struct regmap_field *phy_pll_cfg;
341 struct regmap_field *phy_pipe_cmn_ctrl1_0;
342 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
343 struct regmap_field *phy_pma_cmn_ctrl_1;
344 struct regmap_field *phy_pma_cmn_ctrl_2;
345 struct regmap_field *phy_pma_pll_raw_ctrl;
346 struct regmap_field *phy_reset_ctrl;
347 struct regmap_field *phy_pcs_iso_link_ctrl_1[MAX_NUM_LANES];
348 struct clk_hw_onecell_data *clk_hw_data;
351 enum phy_powerstate {
353 /* Powerstate A1 is unused */
358 struct cdns_torrent_refclk_driver {
360 struct regmap_field *cmn_fields[REFCLK_OUT_NUM_CMN_CONFIG];
361 struct clk_init_data clk_data;
364 #define to_cdns_torrent_refclk_driver(_hw) \
365 container_of(_hw, struct cdns_torrent_refclk_driver, hw)
367 struct cdns_torrent_derived_refclk {
369 struct regmap_field *phy_pipe_cmn_ctrl1_0;
370 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
371 struct clk_init_data clk_data;
374 #define to_cdns_torrent_derived_refclk(_hw) \
375 container_of(_hw, struct cdns_torrent_derived_refclk, hw)
377 struct cdns_torrent_received_refclk {
379 struct regmap_field *phy_pipe_cmn_ctrl1_0;
380 struct regmap_field *cmn_cdiag_refclk_ovrd_4;
381 struct clk_init_data clk_data;
384 #define to_cdns_torrent_received_refclk(_hw) \
385 container_of(_hw, struct cdns_torrent_received_refclk, hw)
387 struct cdns_reg_pairs {
392 struct cdns_torrent_vals {
393 struct cdns_reg_pairs *reg_pairs;
397 struct cdns_torrent_data {
398 u8 block_offset_shift;
400 struct cdns_torrent_vals *link_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
402 struct cdns_torrent_vals *xcvr_diag_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
404 struct cdns_torrent_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
406 struct cdns_torrent_vals *cmn_vals[NUM_REF_CLK][NUM_PHY_TYPE]
407 [NUM_PHY_TYPE][NUM_SSC_MODE];
408 struct cdns_torrent_vals *tx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE]
409 [NUM_PHY_TYPE][NUM_SSC_MODE];
410 struct cdns_torrent_vals *rx_ln_vals[NUM_REF_CLK][NUM_PHY_TYPE]
411 [NUM_PHY_TYPE][NUM_SSC_MODE];
414 struct cdns_regmap_cdb_context {
420 static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)
422 struct cdns_regmap_cdb_context *ctx = context;
423 u32 offset = reg << ctx->reg_offset_shift;
425 writew(val, ctx->base + offset);
430 static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)
432 struct cdns_regmap_cdb_context *ctx = context;
433 u32 offset = reg << ctx->reg_offset_shift;
435 *val = readw(ctx->base + offset);
439 static int cdns_regmap_dptx_write(void *context, unsigned int reg,
442 struct cdns_regmap_cdb_context *ctx = context;
445 writel(val, ctx->base + offset);
450 static int cdns_regmap_dptx_read(void *context, unsigned int reg,
453 struct cdns_regmap_cdb_context *ctx = context;
456 *val = readl(ctx->base + offset);
460 #define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \
462 .name = "torrent_tx_lane" n "_cdb", \
465 .reg_write = cdns_regmap_write, \
466 .reg_read = cdns_regmap_read, \
469 #define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \
471 .name = "torrent_rx_lane" n "_cdb", \
474 .reg_write = cdns_regmap_write, \
475 .reg_read = cdns_regmap_read, \
478 static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = {
479 TORRENT_TX_LANE_CDB_REGMAP_CONF("0"),
480 TORRENT_TX_LANE_CDB_REGMAP_CONF("1"),
481 TORRENT_TX_LANE_CDB_REGMAP_CONF("2"),
482 TORRENT_TX_LANE_CDB_REGMAP_CONF("3"),
485 static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = {
486 TORRENT_RX_LANE_CDB_REGMAP_CONF("0"),
487 TORRENT_RX_LANE_CDB_REGMAP_CONF("1"),
488 TORRENT_RX_LANE_CDB_REGMAP_CONF("2"),
489 TORRENT_RX_LANE_CDB_REGMAP_CONF("3"),
492 static const struct regmap_config cdns_torrent_common_cdb_config = {
493 .name = "torrent_common_cdb",
496 .reg_write = cdns_regmap_write,
497 .reg_read = cdns_regmap_read,
500 #define TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \
502 .name = "torrent_phy_pcs_lane" n "_cdb", \
505 .reg_write = cdns_regmap_write, \
506 .reg_read = cdns_regmap_read, \
509 static const struct regmap_config cdns_torrent_phy_pcs_lane_cdb_config[] = {
510 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("0"),
511 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("1"),
512 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("2"),
513 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("3"),
516 static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = {
517 .name = "torrent_phy_pcs_cmn_cdb",
520 .reg_write = cdns_regmap_write,
521 .reg_read = cdns_regmap_read,
524 static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = {
525 .name = "torrent_phy_pma_cmn_cdb",
528 .reg_write = cdns_regmap_write,
529 .reg_read = cdns_regmap_read,
532 static const struct regmap_config cdns_torrent_dptx_phy_config = {
533 .name = "torrent_dptx_phy",
536 .reg_write = cdns_regmap_dptx_write,
537 .reg_read = cdns_regmap_dptx_read,
540 /* PHY mmr access functions */
542 static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val)
544 regmap_write(regmap, offset, val);
547 static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset)
551 regmap_read(regmap, offset, &val);
555 /* DPTX mmr access functions */
557 static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val)
559 regmap_write(regmap, offset, val);
562 static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset)
566 regmap_read(regmap, offset, &val);
571 * Structure used to store values of PHY registers for voltage-related
572 * coefficients, for particular voltage swing and pre-emphasis level. Values
573 * are shared across all physical lanes.
575 struct coefficients {
576 /* Value of DRV_DIAG_TX_DRV register to use */
578 /* Value of TX_TXCC_MGNFS_MULT_000 register to use */
580 /* Value of TX_TXCC_CPOST_MULT_00 register to use */
585 * Array consists of values of voltage-related registers for sd0801 PHY. A value
586 * of 0xFFFF is a placeholder for invalid combination, and will never be used.
588 static const struct coefficients vltg_coeff[4][4] = {
589 /* voltage swing 0, pre-emphasis 0->3 */
590 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A,
591 .cpost_mult = 0x0000},
592 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
593 .cpost_mult = 0x0014},
594 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012,
595 .cpost_mult = 0x0020},
596 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
597 .cpost_mult = 0x002A}
600 /* voltage swing 1, pre-emphasis 0->3 */
601 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,
602 .cpost_mult = 0x0000},
603 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
604 .cpost_mult = 0x0012},
605 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
606 .cpost_mult = 0x001F},
607 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
608 .cpost_mult = 0xFFFF}
611 /* voltage swing 2, pre-emphasis 0->3 */
612 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,
613 .cpost_mult = 0x0000},
614 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
615 .cpost_mult = 0x0013},
616 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
617 .cpost_mult = 0xFFFF},
618 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
619 .cpost_mult = 0xFFFF}
622 /* voltage swing 3, pre-emphasis 0->3 */
623 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,
624 .cpost_mult = 0x0000},
625 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
626 .cpost_mult = 0xFFFF},
627 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
628 .cpost_mult = 0xFFFF},
629 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,
630 .cpost_mult = 0xFFFF}
634 static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type)
638 return "DisplayPort";
653 * Set registers responsible for enabling and configuring SSC, with second and
654 * third register values provided by parameters.
657 void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy,
658 u32 ctrl2_val, u32 ctrl3_val)
660 struct regmap *regmap = cdns_phy->regmap_common_cdb;
662 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
663 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
664 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val);
665 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
666 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
667 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
668 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val);
669 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
673 void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,
676 struct regmap *regmap = cdns_phy->regmap_common_cdb;
678 /* Assumes 19.2 MHz refclock */
680 /* Setting VCO for 10.8GHz */
683 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0119);
684 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);
685 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
686 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00BC);
687 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
688 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0119);
689 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);
690 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
691 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00BC);
692 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0012);
694 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A, 0x006A);
696 /* Setting VCO for 9.72GHz */
700 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01FA);
701 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);
702 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
703 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0152);
704 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
705 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01FA);
706 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);
707 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
708 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0152);
709 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
711 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD, 0x0069);
713 /* Setting VCO for 8.64GHz */
716 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01C2);
717 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
718 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
719 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x012C);
720 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
721 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01C2);
722 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
723 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
724 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x012C);
725 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
727 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536, 0x0069);
729 /* Setting VCO for 8.1GHz */
731 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01A5);
732 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xE000);
733 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
734 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x011A);
735 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
736 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01A5);
737 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xE000);
738 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
739 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x011A);
740 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
742 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7, 0x006A);
747 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);
748 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
749 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);
750 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
752 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);
753 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);
754 /* Set reset register values to disable SSC */
755 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
756 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
757 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
758 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
759 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
760 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
761 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
762 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
763 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
764 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
767 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099);
768 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099);
769 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099);
770 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
774 * Set registers responsible for enabling and configuring SSC, with second
775 * register value provided by a parameter.
777 static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy,
780 struct regmap *regmap = cdns_phy->regmap_common_cdb;
782 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);
783 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);
784 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F);
785 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);
786 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);
787 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);
788 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F);
789 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);
793 void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,
796 struct regmap *regmap = cdns_phy->regmap_common_cdb;
798 /* Assumes 25 MHz refclock */
800 /* Setting VCO for 10.8GHz */
803 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0);
804 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
805 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
806 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120);
807 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0);
808 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
809 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
810 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120);
812 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423);
814 /* Setting VCO for 9.72GHz */
818 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184);
819 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD);
820 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
821 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104);
822 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184);
823 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD);
824 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
825 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104);
827 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9);
829 /* Setting VCO for 8.64GHz */
832 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159);
833 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A);
834 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
835 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7);
836 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159);
837 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A);
838 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
839 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7);
841 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F);
843 /* Setting VCO for 8.1GHz */
845 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144);
846 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);
847 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
848 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8);
849 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144);
850 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);
851 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
852 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8);
854 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A);
858 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
859 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
862 cdns_torrent_phy_write(regmap,
863 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315);
864 cdns_torrent_phy_write(regmap,
865 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
866 cdns_torrent_phy_write(regmap,
867 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315);
868 cdns_torrent_phy_write(regmap,
869 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
871 cdns_torrent_phy_write(regmap,
872 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317);
873 cdns_torrent_phy_write(regmap,
874 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317);
875 /* Set reset register values to disable SSC */
876 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);
877 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);
878 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);
879 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);
880 cdns_torrent_phy_write(regmap,
881 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
882 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);
883 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);
884 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);
885 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);
886 cdns_torrent_phy_write(regmap,
887 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
890 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7);
891 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7);
892 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7);
893 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);
897 void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy,
900 struct regmap *regmap = cdns_phy->regmap_common_cdb;
902 /* Assumes 100 MHz refclock */
904 /* Setting VCO for 10.8GHz */
907 if (cdns_phy->dp_pll & DP_PLL0)
908 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022);
910 if (cdns_phy->dp_pll & DP_PLL1) {
911 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028);
912 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022);
913 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C);
916 /* Setting VCO for 9.72GHz */
920 if (cdns_phy->dp_pll & DP_PLL0) {
921 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
922 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
923 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
924 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
925 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061);
926 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333);
927 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
928 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042);
929 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
931 if (cdns_phy->dp_pll & DP_PLL1) {
932 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
933 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
934 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
935 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
936 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061);
937 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333);
938 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
939 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042);
940 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
943 /* Setting VCO for 8.64GHz */
946 if (cdns_phy->dp_pll & DP_PLL0) {
947 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
948 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
949 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
950 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
951 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056);
952 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666);
953 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
954 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A);
955 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
957 if (cdns_phy->dp_pll & DP_PLL1) {
958 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
959 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
960 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
961 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
962 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056);
963 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666);
964 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
965 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A);
966 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
969 /* Setting VCO for 8.1GHz */
971 if (cdns_phy->dp_pll & DP_PLL0) {
972 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);
973 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);
974 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);
975 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);
976 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051);
977 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);
978 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036);
979 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
981 if (cdns_phy->dp_pll & DP_PLL1) {
982 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);
983 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);
984 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);
985 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);
986 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051);
987 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);
988 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036);
989 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
995 /* Set PLL used for DP configuration */
996 static int cdns_torrent_dp_get_pll(struct cdns_torrent_phy *cdns_phy,
997 enum cdns_torrent_phy_type phy_t2)
1002 cdns_phy->dp_pll = DP_PLL1;
1006 cdns_phy->dp_pll = DP_PLL0;
1009 cdns_phy->dp_pll = DP_PLL0 | DP_PLL1;
1012 dev_err(cdns_phy->dev, "Unsupported PHY configuration\n");
1020 * Enable or disable PLL for selected lanes.
1022 static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,
1023 struct cdns_torrent_inst *inst,
1024 struct phy_configure_opts_dp *dp,
1027 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1028 u32 rd_val, pll_ack_val;
1032 * Used to determine, which bits to check for or enable in
1033 * PHY_PMA_XCVR_PLLCLK_EN register.
1036 /* Used to enable or disable lanes. */
1039 /* Select values of registers and mask, depending on enabled lane count. */
1040 pll_val = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);
1043 pll_bits = ((1 << dp->lanes) - 1);
1044 pll_val |= pll_bits;
1045 pll_ack_val = pll_bits;
1047 pll_bits = ((1 << inst->num_lanes) - 1);
1048 pll_val &= (~pll_bits);
1052 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val);
1054 /* Wait for acknowledgment from PHY. */
1055 ret = regmap_read_poll_timeout(regmap,
1056 PHY_PMA_XCVR_PLLCLK_EN_ACK,
1058 (rd_val & pll_bits) == pll_ack_val,
1059 0, POLL_TIMEOUT_US);
1064 static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
1065 struct cdns_torrent_inst *inst,
1067 enum phy_powerstate powerstate)
1069 /* Register value for power state for a single byte. */
1075 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1077 switch (powerstate) {
1078 case (POWERSTATE_A0):
1081 case (POWERSTATE_A2):
1090 /* Select values of registers and mask, depending on enabled lane count. */
1092 for (i = 0; i < num_lanes; i++) {
1093 value |= (value_part << PHY_POWER_STATE_LN(i));
1094 mask |= (PMA_XCVR_POWER_STATE_REQ_LN_MASK << PHY_POWER_STATE_LN(i));
1097 /* Set power state A<n>. */
1098 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);
1099 /* Wait, until PHY acknowledges power state completion. */
1100 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,
1101 read_val, (read_val & mask) == value, 0,
1103 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
1109 static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,
1110 struct cdns_torrent_inst *inst, u32 num_lanes)
1112 unsigned int read_val;
1114 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1117 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the
1120 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,
1121 read_val, read_val & 1,
1122 0, POLL_TIMEOUT_US);
1123 if (ret == -ETIMEDOUT) {
1124 dev_err(cdns_phy->dev,
1125 "timeout waiting for link PLL clock enable ack\n");
1131 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes,
1136 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes,
1142 static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
1146 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1148 ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,
1149 reg & 1, 0, POLL_TIMEOUT_US);
1150 if (ret == -ETIMEDOUT) {
1151 dev_err(cdns_phy->dev,
1152 "timeout waiting for PMA common ready\n");
1159 static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,
1160 struct cdns_torrent_inst *inst,
1161 u32 rate, u32 num_lanes)
1163 unsigned int clk_sel_val = 0;
1164 unsigned int hsclk_div_val = 0;
1169 clk_sel_val = 0x0f01;
1175 clk_sel_val = 0x0701;
1179 clk_sel_val = 0x0b00;
1184 clk_sel_val = 0x0301;
1188 clk_sel_val = 0x0200;
1193 if (cdns_phy->dp_pll & DP_PLL0)
1194 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1195 CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);
1197 if (cdns_phy->dp_pll & DP_PLL1)
1198 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,
1199 CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);
1201 /* PMA lane configuration to deal with multi-link operation */
1202 for (i = 0; i < num_lanes; i++)
1203 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + i],
1204 XCVR_DIAG_HSCLK_DIV, hsclk_div_val);
1208 * Perform register operations related to setting link rate, once powerstate is
1209 * set and PLL disable request was processed.
1211 static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,
1212 struct cdns_torrent_inst *inst,
1213 struct phy_configure_opts_dp *dp)
1215 u32 read_val, field_val;
1219 * Disable the associated PLL (cmn_pll0_en or cmn_pll1_en) before
1220 * re-programming the new data rate.
1222 ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val);
1225 field_val &= ~(cdns_phy->dp_pll);
1226 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val);
1229 * Wait for PLL ready de-assertion.
1230 * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1
1231 * For PLL1 - PHY_PMA_CMN_CTRL2[3] == 1
1233 if (cdns_phy->dp_pll & DP_PLL0) {
1234 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1236 ((read_val >> 2) & 0x01) != 0,
1237 0, POLL_TIMEOUT_US);
1242 if ((cdns_phy->dp_pll & DP_PLL1) && cdns_phy->nsubnodes != 1) {
1243 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1245 ((read_val >> 3) & 0x01) != 0,
1246 0, POLL_TIMEOUT_US);
1252 /* DP Rate Change - VCO Output settings. */
1253 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
1254 /* PMA common configuration 19.2MHz */
1255 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc);
1256 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
1257 /* PMA common configuration 25MHz */
1258 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc);
1259 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
1260 /* PMA common configuration 100MHz */
1261 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, dp->link_rate, dp->ssc);
1263 cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, dp->link_rate, dp->lanes);
1265 /* Enable the associated PLL (cmn_pll0_en or cmn_pll1_en) */
1266 ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val);
1269 field_val |= cdns_phy->dp_pll;
1270 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val);
1273 * Wait for PLL ready assertion.
1274 * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1
1275 * For PLL1 - PHY_PMA_CMN_CTRL2[1] == 1
1277 if (cdns_phy->dp_pll & DP_PLL0) {
1278 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1280 (read_val & 0x01) != 0,
1281 0, POLL_TIMEOUT_US);
1286 if ((cdns_phy->dp_pll & DP_PLL1) && cdns_phy->nsubnodes != 1)
1287 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,
1289 ((read_val >> 1) & 0x01) != 0,
1290 0, POLL_TIMEOUT_US);
1296 * Verify, that parameters to configure PHY with are correct.
1298 static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst,
1299 struct phy_configure_opts_dp *dp)
1303 /* If changing link rate was required, verify it's supported. */
1305 switch (dp->link_rate) {
1314 /* valid bit rate */
1321 /* Verify lane count. */
1322 switch (dp->lanes) {
1326 /* valid lane count. */
1332 /* Check against actual number of PHY's lanes. */
1333 if (dp->lanes > inst->num_lanes)
1337 * If changing voltages is required, check swing and pre-emphasis
1340 if (dp->set_voltages) {
1341 /* Lane count verified previously. */
1342 for (i = 0; i < dp->lanes; i++) {
1343 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
1346 /* Sum of voltage swing and pre-emphasis levels cannot
1349 if (dp->voltage[i] + dp->pre[i] > 3)
1357 /* Set power state A0 and PLL clock enable to 0 on enabled lanes. */
1358 static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
1359 struct cdns_torrent_inst *inst,
1362 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1363 u32 pwr_state = cdns_torrent_dp_read(regmap,
1364 PHY_PMA_XCVR_POWER_STATE_REQ);
1365 u32 pll_clk_en = cdns_torrent_dp_read(regmap,
1366 PHY_PMA_XCVR_PLLCLK_EN);
1369 for (i = 0; i < num_lanes; i++) {
1370 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK
1371 << PHY_POWER_STATE_LN(inst->mlane + i));
1373 pll_clk_en &= ~(0x01U << (inst->mlane + i));
1376 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
1377 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);
1380 /* Configure lane count as required. */
1381 static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,
1382 struct cdns_torrent_inst *inst,
1383 struct phy_configure_opts_dp *dp)
1387 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1388 u8 lane_mask = (1 << dp->lanes) - 1;
1389 u8 pma_tx_elec_idle_mask = 0;
1390 u32 clane = inst->mlane;
1392 lane_mask <<= clane;
1394 value = cdns_torrent_dp_read(regmap, PHY_RESET);
1395 /* clear pma_tx_elec_idle_ln_* bits. */
1396 pma_tx_elec_idle_mask = ((1 << inst->num_lanes) - 1) << clane;
1398 pma_tx_elec_idle_mask <<= PMA_TX_ELEC_IDLE_SHIFT;
1400 value &= ~pma_tx_elec_idle_mask;
1402 /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */
1403 value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) &
1404 pma_tx_elec_idle_mask;
1406 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1408 /* reset the link by asserting master lane phy_l0*_reset_n low */
1409 cdns_torrent_dp_write(regmap, PHY_RESET,
1410 value & (~(1 << clane)));
1413 * Assert lane reset on unused lanes and master lane so they remain in reset
1414 * and powered down when re-enabling the link
1416 for (i = 0; i < inst->num_lanes; i++)
1417 value &= (~(1 << (clane + i)));
1419 for (i = 1; i < inst->num_lanes; i++)
1420 value |= ((1 << (clane + i)) & lane_mask);
1422 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1424 cdns_torrent_dp_set_a0_pll(cdns_phy, inst, dp->lanes);
1426 /* release phy_l0*_reset_n based on used laneCount */
1427 for (i = 0; i < inst->num_lanes; i++)
1428 value &= (~(1 << (clane + i)));
1430 for (i = 0; i < inst->num_lanes; i++)
1431 value |= ((1 << (clane + i)) & lane_mask);
1433 cdns_torrent_dp_write(regmap, PHY_RESET, value);
1435 /* Wait, until PHY gets ready after releasing PHY reset signal. */
1436 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
1442 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
1443 value = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);
1444 value |= (1 << clane);
1445 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, value);
1447 ret = cdns_torrent_dp_run(cdns_phy, inst, dp->lanes);
1452 /* Configure link rate as required. */
1453 static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy,
1454 struct cdns_torrent_inst *inst,
1455 struct phy_configure_opts_dp *dp)
1459 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
1463 ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, false);
1468 ret = cdns_torrent_dp_configure_rate(cdns_phy, inst, dp);
1473 ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, true);
1476 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
1480 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,
1489 /* Configure voltage swing and pre-emphasis for all enabled lanes. */
1490 static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy,
1491 struct cdns_torrent_inst *inst,
1492 struct phy_configure_opts_dp *dp)
1497 for (lane = 0; lane < dp->lanes; lane++) {
1498 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1501 * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the
1502 * current state of the analog TX driver.
1504 val |= TX_DIAG_ACYA_HBDC_MASK;
1505 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1508 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1509 TX_TXCC_CTRL, 0x08A4);
1510 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv;
1511 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1512 DRV_DIAG_TX_DRV, val);
1513 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult;
1514 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1515 TX_TXCC_MGNFS_MULT_000,
1517 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult;
1518 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1519 TX_TXCC_CPOST_MULT_00,
1522 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1525 * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of
1526 * analog TX driver to reflect the new programmed one.
1528 val &= ~TX_DIAG_ACYA_HBDC_MASK;
1529 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],
1534 static int cdns_torrent_dp_configure(struct phy *phy,
1535 union phy_configure_opts *opts)
1537 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1538 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1541 ret = cdns_torrent_dp_verify_config(inst, &opts->dp);
1543 dev_err(&phy->dev, "invalid params for phy configure\n");
1547 if (opts->dp.set_lanes) {
1548 ret = cdns_torrent_dp_set_lanes(cdns_phy, inst, &opts->dp);
1550 dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n");
1555 if (opts->dp.set_rate) {
1556 ret = cdns_torrent_dp_set_rate(cdns_phy, inst, &opts->dp);
1558 dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n");
1563 if (opts->dp.set_voltages)
1564 cdns_torrent_dp_set_voltages(cdns_phy, inst, &opts->dp);
1569 static int cdns_torrent_phy_on(struct phy *phy)
1571 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1572 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1576 if (cdns_phy->nsubnodes == 1) {
1577 /* Take the PHY lane group out of reset */
1578 reset_control_deassert(inst->lnk_rst);
1580 /* Take the PHY out of reset */
1581 ret = reset_control_deassert(cdns_phy->phy_rst);
1587 * Wait for cmn_ready assertion
1588 * PHY_PMA_CMN_CTRL1[0] == 1
1590 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
1591 read_val, read_val, 1000,
1594 dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
1598 if (inst->phy_type == TYPE_PCIE || inst->phy_type == TYPE_USB) {
1599 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pcs_iso_link_ctrl_1[inst->mlane],
1600 read_val, !read_val, 1000,
1602 if (ret == -ETIMEDOUT) {
1603 dev_err(cdns_phy->dev, "Timeout waiting for PHY status ready\n");
1611 static int cdns_torrent_phy_off(struct phy *phy)
1613 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1614 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1617 if (cdns_phy->nsubnodes != 1)
1620 ret = reset_control_assert(cdns_phy->phy_rst);
1624 return reset_control_assert(inst->lnk_rst);
1627 static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy,
1628 struct cdns_torrent_inst *inst)
1630 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;
1631 unsigned char lane_bits;
1634 cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */
1637 * Set lines power state to A0
1638 * Set lines pll clk enable to 0
1640 cdns_torrent_dp_set_a0_pll(cdns_phy, inst, inst->num_lanes);
1643 * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on
1646 lane_bits = (1 << inst->num_lanes) - 1;
1648 val = cdns_torrent_dp_read(regmap, PHY_RESET);
1649 val |= (0xF & lane_bits);
1650 val &= ~(lane_bits << 4);
1651 cdns_torrent_dp_write(regmap, PHY_RESET, val);
1653 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
1654 val = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);
1656 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, val);
1659 * PHY PMA registers configuration functions
1660 * Initialize PHY with max supported link rate, without SSC.
1662 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)
1663 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,
1664 cdns_phy->max_bit_rate,
1666 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)
1667 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,
1668 cdns_phy->max_bit_rate,
1670 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)
1671 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy,
1672 cdns_phy->max_bit_rate,
1675 cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, cdns_phy->max_bit_rate,
1678 /* take out of reset */
1679 regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1);
1682 static int cdns_torrent_dp_start(struct cdns_torrent_phy *cdns_phy,
1683 struct cdns_torrent_inst *inst,
1688 ret = cdns_torrent_phy_on(phy);
1692 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
1696 ret = cdns_torrent_dp_run(cdns_phy, inst, inst->num_lanes);
1701 static int cdns_torrent_dp_init(struct phy *phy)
1703 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
1704 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
1707 switch (cdns_phy->ref_clk_rate) {
1711 /* Valid Ref Clock Rate */
1714 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
1718 ret = cdns_torrent_dp_get_pll(cdns_phy, TYPE_NONE);
1722 cdns_torrent_dp_common_init(cdns_phy, inst);
1724 return cdns_torrent_dp_start(cdns_phy, inst, phy);
1727 static int cdns_torrent_dp_multilink_init(struct cdns_torrent_phy *cdns_phy,
1728 struct cdns_torrent_inst *inst,
1731 if (cdns_phy->ref_clk_rate != CLK_100_MHZ) {
1732 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");
1736 cdns_torrent_dp_common_init(cdns_phy, inst);
1738 return cdns_torrent_dp_start(cdns_phy, inst, phy);
1741 static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)
1743 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1745 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 1);
1746 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 1);
1751 static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw)
1753 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1755 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 0);
1756 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 0);
1759 static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw)
1761 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);
1764 regmap_field_read(derived_refclk->cmn_cdiag_refclk_ovrd_4, &val);
1769 static const struct clk_ops cdns_torrent_derived_refclk_ops = {
1770 .enable = cdns_torrent_derived_refclk_enable,
1771 .disable = cdns_torrent_derived_refclk_disable,
1772 .is_enabled = cdns_torrent_derived_refclk_is_enabled,
1775 static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy)
1777 struct cdns_torrent_derived_refclk *derived_refclk;
1778 struct device *dev = cdns_phy->dev;
1779 struct clk_init_data *init;
1780 const char *parent_name;
1786 derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL);
1787 if (!derived_refclk)
1790 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
1791 clk_names[CDNS_TORRENT_DERIVED_REFCLK]);
1793 clk = devm_clk_get_optional(dev, "phy_en_refclk");
1795 dev_err(dev, "No parent clock for derived_refclk\n");
1796 return PTR_ERR(clk);
1799 init = &derived_refclk->clk_data;
1802 parent_name = __clk_get_name(clk);
1803 init->parent_names = &parent_name;
1804 init->num_parents = 1;
1806 init->ops = &cdns_torrent_derived_refclk_ops;
1808 init->name = clk_name;
1810 derived_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0;
1811 derived_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4;
1813 derived_refclk->hw.init = init;
1815 hw = &derived_refclk->hw;
1816 ret = devm_clk_hw_register(dev, hw);
1820 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_DERIVED_REFCLK] = hw;
1825 static int cdns_torrent_received_refclk_enable(struct clk_hw *hw)
1827 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1829 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 1);
1834 static void cdns_torrent_received_refclk_disable(struct clk_hw *hw)
1836 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1838 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 0);
1841 static int cdns_torrent_received_refclk_is_enabled(struct clk_hw *hw)
1843 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);
1846 regmap_field_read(received_refclk->phy_pipe_cmn_ctrl1_0, &val);
1847 regmap_field_read(received_refclk->cmn_cdiag_refclk_ovrd_4, &cmn_val);
1849 return val && !cmn_val;
1852 static const struct clk_ops cdns_torrent_received_refclk_ops = {
1853 .enable = cdns_torrent_received_refclk_enable,
1854 .disable = cdns_torrent_received_refclk_disable,
1855 .is_enabled = cdns_torrent_received_refclk_is_enabled,
1858 static int cdns_torrent_received_refclk_register(struct cdns_torrent_phy *cdns_phy)
1860 struct cdns_torrent_received_refclk *received_refclk;
1861 struct device *dev = cdns_phy->dev;
1862 struct clk_init_data *init;
1863 const char *parent_name;
1869 received_refclk = devm_kzalloc(dev, sizeof(*received_refclk), GFP_KERNEL);
1870 if (!received_refclk)
1873 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
1874 clk_names[CDNS_TORRENT_RECEIVED_REFCLK]);
1876 clk = devm_clk_get_optional(dev, "phy_en_refclk");
1878 dev_err(dev, "No parent clock for received_refclk\n");
1879 return PTR_ERR(clk);
1882 init = &received_refclk->clk_data;
1885 parent_name = __clk_get_name(clk);
1886 init->parent_names = &parent_name;
1887 init->num_parents = 1;
1889 init->ops = &cdns_torrent_received_refclk_ops;
1891 init->name = clk_name;
1893 received_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0;
1894 received_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4;
1896 received_refclk->hw.init = init;
1898 hw = &received_refclk->hw;
1899 ret = devm_clk_hw_register(dev, hw);
1903 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_RECEIVED_REFCLK] = hw;
1908 static int cdns_torrent_refclk_driver_enable(struct clk_hw *hw)
1910 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1912 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0);
1913 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1);
1914 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0);
1919 static void cdns_torrent_refclk_driver_disable(struct clk_hw *hw)
1921 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1923 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 1);
1926 static int cdns_torrent_refclk_driver_is_enabled(struct clk_hw *hw)
1928 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1931 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], &val);
1936 static u8 cdns_torrent_refclk_driver_get_parent(struct clk_hw *hw)
1938 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1941 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], &val);
1942 return clk_mux_val_to_index(hw, cdns_torrent_refclk_driver_mux_table, 0, val);
1945 static int cdns_torrent_refclk_driver_set_parent(struct clk_hw *hw, u8 index)
1947 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);
1950 val = cdns_torrent_refclk_driver_mux_table[index];
1951 return regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], val);
1954 static const struct clk_ops cdns_torrent_refclk_driver_ops = {
1955 .enable = cdns_torrent_refclk_driver_enable,
1956 .disable = cdns_torrent_refclk_driver_disable,
1957 .is_enabled = cdns_torrent_refclk_driver_is_enabled,
1958 .determine_rate = __clk_mux_determine_rate,
1959 .set_parent = cdns_torrent_refclk_driver_set_parent,
1960 .get_parent = cdns_torrent_refclk_driver_get_parent,
1963 static int cdns_torrent_refclk_driver_register(struct cdns_torrent_phy *cdns_phy)
1965 struct cdns_torrent_refclk_driver *refclk_driver;
1966 struct device *dev = cdns_phy->dev;
1967 struct regmap_field *field;
1968 struct clk_init_data *init;
1969 const char **parent_names;
1970 unsigned int num_parents;
1971 struct regmap *regmap;
1976 refclk_driver = devm_kzalloc(dev, sizeof(*refclk_driver), GFP_KERNEL);
1980 num_parents = ARRAY_SIZE(refclk_driver_parent_index);
1981 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL);
1985 for (i = 0; i < num_parents; i++) {
1986 hw = cdns_phy->clk_hw_data->hws[refclk_driver_parent_index[i]];
1987 if (IS_ERR_OR_NULL(hw)) {
1988 dev_err(dev, "No parent clock for refclk driver clock\n");
1989 return IS_ERR(hw) ? PTR_ERR(hw) : -ENOENT;
1991 parent_names[i] = clk_hw_get_name(hw);
1994 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
1995 clk_names[CDNS_TORRENT_REFCLK_DRIVER]);
1997 init = &refclk_driver->clk_data;
1999 init->ops = &cdns_torrent_refclk_driver_ops;
2000 init->flags = CLK_SET_RATE_NO_REPARENT;
2001 init->parent_names = parent_names;
2002 init->num_parents = num_parents;
2003 init->name = clk_name;
2005 regmap = cdns_phy->regmap_common_cdb;
2007 for (i = 0; i < REFCLK_OUT_NUM_CMN_CONFIG; i++) {
2008 field = devm_regmap_field_alloc(dev, regmap, refclk_out_cmn_cfg[i]);
2009 if (IS_ERR(field)) {
2010 dev_err(dev, "Refclk driver CMN reg field init failed\n");
2011 return PTR_ERR(field);
2013 refclk_driver->cmn_fields[i] = field;
2016 /* Enable Derived reference clock as default */
2017 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1);
2019 refclk_driver->hw.init = init;
2021 hw = &refclk_driver->hw;
2022 ret = devm_clk_hw_register(dev, hw);
2026 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_REFCLK_DRIVER] = hw;
2031 static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,
2033 u8 reg_offset_shift,
2034 const struct regmap_config *config)
2036 struct cdns_regmap_cdb_context *ctx;
2038 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
2040 return ERR_PTR(-ENOMEM);
2043 ctx->base = base + block_offset;
2044 ctx->reg_offset_shift = reg_offset_shift;
2046 return devm_regmap_init(dev, NULL, ctx, config);
2049 static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy)
2051 struct device *dev = cdns_phy->dev;
2052 struct regmap_field *field;
2053 struct regmap *regmap;
2055 regmap = cdns_phy->regmap_dptx_phy_reg;
2056 field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl);
2057 if (IS_ERR(field)) {
2058 dev_err(dev, "PHY_RESET reg field init failed\n");
2059 return PTR_ERR(field);
2061 cdns_phy->phy_reset_ctrl = field;
2066 static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy)
2068 struct device *dev = cdns_phy->dev;
2069 struct regmap_field *field;
2070 struct regmap *regmap;
2073 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2074 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg);
2075 if (IS_ERR(field)) {
2076 dev_err(dev, "PHY_PLL_CFG reg field init failed\n");
2077 return PTR_ERR(field);
2079 cdns_phy->phy_pll_cfg = field;
2081 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2082 field = devm_regmap_field_alloc(dev, regmap, phy_pipe_cmn_ctrl1_0);
2083 if (IS_ERR(field)) {
2084 dev_err(dev, "phy_pipe_cmn_ctrl1_0 reg field init failed\n");
2085 return PTR_ERR(field);
2087 cdns_phy->phy_pipe_cmn_ctrl1_0 = field;
2089 regmap = cdns_phy->regmap_common_cdb;
2090 field = devm_regmap_field_alloc(dev, regmap, cmn_cdiag_refclk_ovrd_4);
2091 if (IS_ERR(field)) {
2092 dev_err(dev, "cmn_cdiag_refclk_ovrd_4 reg field init failed\n");
2093 return PTR_ERR(field);
2095 cdns_phy->cmn_cdiag_refclk_ovrd_4 = field;
2097 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2098 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1);
2099 if (IS_ERR(field)) {
2100 dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n");
2101 return PTR_ERR(field);
2103 cdns_phy->phy_pma_cmn_ctrl_1 = field;
2105 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2106 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2);
2107 if (IS_ERR(field)) {
2108 dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n");
2109 return PTR_ERR(field);
2111 cdns_phy->phy_pma_cmn_ctrl_2 = field;
2113 regmap = cdns_phy->regmap_phy_pma_common_cdb;
2114 field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl);
2115 if (IS_ERR(field)) {
2116 dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n");
2117 return PTR_ERR(field);
2119 cdns_phy->phy_pma_pll_raw_ctrl = field;
2121 for (i = 0; i < MAX_NUM_LANES; i++) {
2122 regmap = cdns_phy->regmap_phy_pcs_lane_cdb[i];
2123 field = devm_regmap_field_alloc(dev, regmap, phy_pcs_iso_link_ctrl_1);
2124 if (IS_ERR(field)) {
2125 dev_err(dev, "PHY_PCS_ISO_LINK_CTRL reg field init for ln %d failed\n", i);
2126 return PTR_ERR(field);
2128 cdns_phy->phy_pcs_iso_link_ctrl_1[i] = field;
2134 static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy)
2136 void __iomem *base = cdns_phy->base;
2137 struct device *dev = cdns_phy->dev;
2138 struct regmap *regmap;
2139 u8 reg_offset_shift;
2142 reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
2144 block_offset = TORRENT_DPTX_PHY_OFFSET;
2145 regmap = cdns_regmap_init(dev, base, block_offset,
2147 &cdns_torrent_dptx_phy_config);
2148 if (IS_ERR(regmap)) {
2149 dev_err(dev, "Failed to init DPTX PHY regmap\n");
2150 return PTR_ERR(regmap);
2152 cdns_phy->regmap_dptx_phy_reg = regmap;
2157 static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy)
2159 void __iomem *sd_base = cdns_phy->sd_base;
2160 u8 block_offset_shift, reg_offset_shift;
2161 struct device *dev = cdns_phy->dev;
2162 struct regmap *regmap;
2166 block_offset_shift = cdns_phy->init_data->block_offset_shift;
2167 reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
2169 for (i = 0; i < MAX_NUM_LANES; i++) {
2170 block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift,
2172 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2174 &cdns_torrent_tx_lane_cdb_config[i]);
2175 if (IS_ERR(regmap)) {
2176 dev_err(dev, "Failed to init tx lane CDB regmap\n");
2177 return PTR_ERR(regmap);
2179 cdns_phy->regmap_tx_lane_cdb[i] = regmap;
2181 block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift,
2183 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2185 &cdns_torrent_rx_lane_cdb_config[i]);
2186 if (IS_ERR(regmap)) {
2187 dev_err(dev, "Failed to init rx lane CDB regmap\n");
2188 return PTR_ERR(regmap);
2190 cdns_phy->regmap_rx_lane_cdb[i] = regmap;
2192 block_offset = TORRENT_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift,
2194 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2196 &cdns_torrent_phy_pcs_lane_cdb_config[i]);
2197 if (IS_ERR(regmap)) {
2198 dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n");
2199 return PTR_ERR(regmap);
2201 cdns_phy->regmap_phy_pcs_lane_cdb[i] = regmap;
2204 block_offset = TORRENT_COMMON_CDB_OFFSET;
2205 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2207 &cdns_torrent_common_cdb_config);
2208 if (IS_ERR(regmap)) {
2209 dev_err(dev, "Failed to init common CDB regmap\n");
2210 return PTR_ERR(regmap);
2212 cdns_phy->regmap_common_cdb = regmap;
2214 block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift);
2215 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2217 &cdns_torrent_phy_pcs_cmn_cdb_config);
2218 if (IS_ERR(regmap)) {
2219 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
2220 return PTR_ERR(regmap);
2222 cdns_phy->regmap_phy_pcs_common_cdb = regmap;
2224 block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift);
2225 regmap = cdns_regmap_init(dev, sd_base, block_offset,
2227 &cdns_torrent_phy_pma_cmn_cdb_config);
2228 if (IS_ERR(regmap)) {
2229 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
2230 return PTR_ERR(regmap);
2232 cdns_phy->regmap_phy_pma_common_cdb = regmap;
2237 static int cdns_torrent_phy_init(struct phy *phy)
2239 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);
2240 const struct cdns_torrent_data *init_data = cdns_phy->init_data;
2241 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
2242 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
2243 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
2244 struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
2245 enum cdns_torrent_phy_type phy_type = inst->phy_type;
2246 enum cdns_torrent_ssc_mode ssc = inst->ssc_mode;
2247 struct cdns_torrent_vals *pcs_cmn_vals;
2248 struct cdns_reg_pairs *reg_pairs;
2249 struct regmap *regmap;
2253 if (cdns_phy->nsubnodes > 1) {
2254 if (phy_type == TYPE_DP)
2255 return cdns_torrent_dp_multilink_init(cdns_phy, inst, phy);
2260 * Spread spectrum generation is not required or supported
2263 if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII)
2266 /* PHY configuration specific registers for single link */
2267 link_cmn_vals = init_data->link_cmn_vals[phy_type][TYPE_NONE][ssc];
2268 if (link_cmn_vals) {
2269 reg_pairs = link_cmn_vals->reg_pairs;
2270 num_regs = link_cmn_vals->num_regs;
2271 regmap = cdns_phy->regmap_common_cdb;
2274 * First array value in link_cmn_vals must be of
2275 * PHY_PLL_CFG register
2277 regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val);
2279 for (i = 1; i < num_regs; i++)
2280 regmap_write(regmap, reg_pairs[i].off,
2284 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_type][TYPE_NONE][ssc];
2285 if (xcvr_diag_vals) {
2286 reg_pairs = xcvr_diag_vals->reg_pairs;
2287 num_regs = xcvr_diag_vals->num_regs;
2288 for (i = 0; i < inst->num_lanes; i++) {
2289 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
2290 for (j = 0; j < num_regs; j++)
2291 regmap_write(regmap, reg_pairs[j].off,
2296 /* PHY PCS common registers configurations */
2297 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
2299 reg_pairs = pcs_cmn_vals->reg_pairs;
2300 num_regs = pcs_cmn_vals->num_regs;
2301 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2302 for (i = 0; i < num_regs; i++)
2303 regmap_write(regmap, reg_pairs[i].off,
2307 /* PMA common registers configurations */
2308 cmn_vals = init_data->cmn_vals[ref_clk][phy_type][TYPE_NONE][ssc];
2310 reg_pairs = cmn_vals->reg_pairs;
2311 num_regs = cmn_vals->num_regs;
2312 regmap = cdns_phy->regmap_common_cdb;
2313 for (i = 0; i < num_regs; i++)
2314 regmap_write(regmap, reg_pairs[i].off,
2318 /* PMA TX lane registers configurations */
2319 tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc];
2321 reg_pairs = tx_ln_vals->reg_pairs;
2322 num_regs = tx_ln_vals->num_regs;
2323 for (i = 0; i < inst->num_lanes; i++) {
2324 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
2325 for (j = 0; j < num_regs; j++)
2326 regmap_write(regmap, reg_pairs[j].off,
2331 /* PMA RX lane registers configurations */
2332 rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_type][TYPE_NONE][ssc];
2334 reg_pairs = rx_ln_vals->reg_pairs;
2335 num_regs = rx_ln_vals->num_regs;
2336 for (i = 0; i < inst->num_lanes; i++) {
2337 regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane];
2338 for (j = 0; j < num_regs; j++)
2339 regmap_write(regmap, reg_pairs[j].off,
2344 if (phy_type == TYPE_DP)
2345 return cdns_torrent_dp_init(phy);
2350 static const struct phy_ops cdns_torrent_phy_ops = {
2351 .init = cdns_torrent_phy_init,
2352 .configure = cdns_torrent_dp_configure,
2353 .power_on = cdns_torrent_phy_on,
2354 .power_off = cdns_torrent_phy_off,
2355 .owner = THIS_MODULE,
2358 static int cdns_torrent_noop_phy_on(struct phy *phy)
2360 /* Give 5ms to 10ms delay for the PIPE clock to be stable */
2361 usleep_range(5000, 10000);
2366 static const struct phy_ops noop_ops = {
2367 .power_on = cdns_torrent_noop_phy_on,
2368 .owner = THIS_MODULE,
2372 int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
2374 const struct cdns_torrent_data *init_data = cdns_phy->init_data;
2375 struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
2376 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;
2377 struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
2378 enum cdns_torrent_phy_type phy_t1, phy_t2;
2379 struct cdns_torrent_vals *pcs_cmn_vals;
2380 int i, j, node, mlane, num_lanes, ret;
2381 struct cdns_reg_pairs *reg_pairs;
2382 enum cdns_torrent_ssc_mode ssc;
2383 struct regmap *regmap;
2386 /* Maximum 2 links (subnodes) are supported */
2387 if (cdns_phy->nsubnodes != 2)
2390 phy_t1 = cdns_phy->phys[0].phy_type;
2391 phy_t2 = cdns_phy->phys[1].phy_type;
2394 * First configure the PHY for first link with phy_t1. Get the array
2395 * values as [phy_t1][phy_t2][ssc].
2397 for (node = 0; node < cdns_phy->nsubnodes; node++) {
2400 * If first link with phy_t1 is configured, then
2401 * configure the PHY for second link with phy_t2.
2402 * Get the array values as [phy_t2][phy_t1][ssc].
2404 swap(phy_t1, phy_t2);
2407 mlane = cdns_phy->phys[node].mlane;
2408 ssc = cdns_phy->phys[node].ssc_mode;
2409 num_lanes = cdns_phy->phys[node].num_lanes;
2412 * PHY configuration specific registers:
2413 * link_cmn_vals depend on combination of PHY types being
2414 * configured and are common for both PHY types, so array
2415 * values should be same for [phy_t1][phy_t2][ssc] and
2416 * [phy_t2][phy_t1][ssc].
2417 * xcvr_diag_vals also depend on combination of PHY types
2418 * being configured, but these can be different for particular
2419 * PHY type and are per lane.
2421 link_cmn_vals = init_data->link_cmn_vals[phy_t1][phy_t2][ssc];
2422 if (link_cmn_vals) {
2423 reg_pairs = link_cmn_vals->reg_pairs;
2424 num_regs = link_cmn_vals->num_regs;
2425 regmap = cdns_phy->regmap_common_cdb;
2428 * First array value in link_cmn_vals must be of
2429 * PHY_PLL_CFG register
2431 regmap_field_write(cdns_phy->phy_pll_cfg,
2434 for (i = 1; i < num_regs; i++)
2435 regmap_write(regmap, reg_pairs[i].off,
2439 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_t1][phy_t2][ssc];
2440 if (xcvr_diag_vals) {
2441 reg_pairs = xcvr_diag_vals->reg_pairs;
2442 num_regs = xcvr_diag_vals->num_regs;
2443 for (i = 0; i < num_lanes; i++) {
2444 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
2445 for (j = 0; j < num_regs; j++)
2446 regmap_write(regmap, reg_pairs[j].off,
2451 /* PHY PCS common registers configurations */
2452 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc];
2454 reg_pairs = pcs_cmn_vals->reg_pairs;
2455 num_regs = pcs_cmn_vals->num_regs;
2456 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
2457 for (i = 0; i < num_regs; i++)
2458 regmap_write(regmap, reg_pairs[i].off,
2462 /* PMA common registers configurations */
2463 cmn_vals = init_data->cmn_vals[ref_clk][phy_t1][phy_t2][ssc];
2465 reg_pairs = cmn_vals->reg_pairs;
2466 num_regs = cmn_vals->num_regs;
2467 regmap = cdns_phy->regmap_common_cdb;
2468 for (i = 0; i < num_regs; i++)
2469 regmap_write(regmap, reg_pairs[i].off,
2473 /* PMA TX lane registers configurations */
2474 tx_ln_vals = init_data->tx_ln_vals[ref_clk][phy_t1][phy_t2][ssc];
2476 reg_pairs = tx_ln_vals->reg_pairs;
2477 num_regs = tx_ln_vals->num_regs;
2478 for (i = 0; i < num_lanes; i++) {
2479 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
2480 for (j = 0; j < num_regs; j++)
2481 regmap_write(regmap, reg_pairs[j].off,
2486 /* PMA RX lane registers configurations */
2487 rx_ln_vals = init_data->rx_ln_vals[ref_clk][phy_t1][phy_t2][ssc];
2489 reg_pairs = rx_ln_vals->reg_pairs;
2490 num_regs = rx_ln_vals->num_regs;
2491 for (i = 0; i < num_lanes; i++) {
2492 regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane];
2493 for (j = 0; j < num_regs; j++)
2494 regmap_write(regmap, reg_pairs[j].off,
2499 if (phy_t1 == TYPE_DP) {
2500 ret = cdns_torrent_dp_get_pll(cdns_phy, phy_t2);
2505 reset_control_deassert(cdns_phy->phys[node].lnk_rst);
2508 /* Take the PHY out of reset */
2509 ret = reset_control_deassert(cdns_phy->phy_rst);
2516 static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy)
2518 struct device *dev = cdns_phy->dev;
2520 of_clk_del_provider(dev->of_node);
2523 static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy)
2525 struct device *dev = cdns_phy->dev;
2526 struct device_node *node = dev->of_node;
2527 struct clk_hw_onecell_data *data;
2530 data = devm_kzalloc(dev, struct_size(data, hws, CDNS_TORRENT_OUTPUT_CLOCKS), GFP_KERNEL);
2534 data->num = CDNS_TORRENT_OUTPUT_CLOCKS;
2535 cdns_phy->clk_hw_data = data;
2537 ret = cdns_torrent_derived_refclk_register(cdns_phy);
2539 dev_err(dev, "failed to register derived refclk\n");
2543 ret = cdns_torrent_received_refclk_register(cdns_phy);
2545 dev_err(dev, "failed to register received refclk\n");
2549 ret = cdns_torrent_refclk_driver_register(cdns_phy);
2551 dev_err(dev, "failed to register refclk driver\n");
2555 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data);
2557 dev_err(dev, "Failed to add clock provider: %s\n", node->name);
2564 static int cdns_torrent_reset(struct cdns_torrent_phy *cdns_phy)
2566 struct device *dev = cdns_phy->dev;
2568 cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0);
2569 if (IS_ERR(cdns_phy->phy_rst)) {
2570 dev_err(dev, "%s: failed to get reset\n",
2571 dev->of_node->full_name);
2572 return PTR_ERR(cdns_phy->phy_rst);
2575 cdns_phy->apb_rst = devm_reset_control_get_optional_exclusive(dev, "torrent_apb");
2576 if (IS_ERR(cdns_phy->apb_rst)) {
2577 dev_err(dev, "%s: failed to get apb reset\n",
2578 dev->of_node->full_name);
2579 return PTR_ERR(cdns_phy->apb_rst);
2585 static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy)
2587 struct device *dev = cdns_phy->dev;
2588 unsigned long ref_clk_rate;
2591 cdns_phy->clk = devm_clk_get(dev, "refclk");
2592 if (IS_ERR(cdns_phy->clk)) {
2593 dev_err(dev, "phy ref clock not found\n");
2594 return PTR_ERR(cdns_phy->clk);
2597 ret = clk_prepare_enable(cdns_phy->clk);
2599 dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
2603 ref_clk_rate = clk_get_rate(cdns_phy->clk);
2604 if (!ref_clk_rate) {
2605 dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
2606 clk_disable_unprepare(cdns_phy->clk);
2610 switch (ref_clk_rate) {
2611 case REF_CLK_19_2MHZ:
2612 cdns_phy->ref_clk_rate = CLK_19_2_MHZ;
2615 cdns_phy->ref_clk_rate = CLK_25_MHZ;
2617 case REF_CLK_100MHZ:
2618 cdns_phy->ref_clk_rate = CLK_100_MHZ;
2621 dev_err(cdns_phy->dev, "Invalid Ref Clock Rate\n");
2622 clk_disable_unprepare(cdns_phy->clk);
2629 static int cdns_torrent_phy_probe(struct platform_device *pdev)
2631 struct cdns_torrent_phy *cdns_phy;
2632 struct device *dev = &pdev->dev;
2633 struct phy_provider *phy_provider;
2634 const struct cdns_torrent_data *data;
2635 struct device_node *child;
2636 int ret, subnodes, node = 0, i;
2637 u32 total_num_lanes = 0;
2638 int already_configured;
2639 u8 init_dp_regmap = 0;
2642 /* Get init data for this PHY */
2643 data = of_device_get_match_data(dev);
2647 cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
2651 dev_set_drvdata(dev, cdns_phy);
2652 cdns_phy->dev = dev;
2653 cdns_phy->init_data = data;
2655 cdns_phy->sd_base = devm_platform_ioremap_resource(pdev, 0);
2656 if (IS_ERR(cdns_phy->sd_base))
2657 return PTR_ERR(cdns_phy->sd_base);
2659 subnodes = of_get_available_child_count(dev->of_node);
2660 if (subnodes == 0) {
2661 dev_err(dev, "No available link subnodes found\n");
2665 ret = cdns_torrent_regmap_init(cdns_phy);
2669 ret = cdns_torrent_regfield_init(cdns_phy);
2673 ret = cdns_torrent_clk_register(cdns_phy);
2677 regmap_field_read(cdns_phy->phy_pma_cmn_ctrl_1, &already_configured);
2679 if (!already_configured) {
2680 ret = cdns_torrent_reset(cdns_phy);
2684 ret = cdns_torrent_clk(cdns_phy);
2689 reset_control_deassert(cdns_phy->apb_rst);
2692 for_each_available_child_of_node(dev->of_node, child) {
2695 /* PHY subnode name must be 'phy'. */
2696 if (!(of_node_name_eq(child, "phy")))
2699 cdns_phy->phys[node].lnk_rst =
2700 of_reset_control_array_get_exclusive(child);
2701 if (IS_ERR(cdns_phy->phys[node].lnk_rst)) {
2702 dev_err(dev, "%s: failed to get reset\n",
2704 ret = PTR_ERR(cdns_phy->phys[node].lnk_rst);
2708 if (of_property_read_u32(child, "reg",
2709 &cdns_phy->phys[node].mlane)) {
2710 dev_err(dev, "%s: No \"reg\"-property.\n",
2716 if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) {
2717 dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n",
2725 cdns_phy->phys[node].phy_type = TYPE_PCIE;
2728 cdns_phy->phys[node].phy_type = TYPE_DP;
2730 case PHY_TYPE_SGMII:
2731 cdns_phy->phys[node].phy_type = TYPE_SGMII;
2733 case PHY_TYPE_QSGMII:
2734 cdns_phy->phys[node].phy_type = TYPE_QSGMII;
2737 cdns_phy->phys[node].phy_type = TYPE_USB;
2740 dev_err(dev, "Unsupported protocol\n");
2745 if (of_property_read_u32(child, "cdns,num-lanes",
2746 &cdns_phy->phys[node].num_lanes)) {
2747 dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n",
2753 total_num_lanes += cdns_phy->phys[node].num_lanes;
2756 cdns_phy->phys[node].ssc_mode = NO_SSC;
2757 of_property_read_u32(child, "cdns,ssc-mode",
2758 &cdns_phy->phys[node].ssc_mode);
2760 if (!already_configured)
2761 gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops);
2763 gphy = devm_phy_create(dev, child, &noop_ops);
2765 ret = PTR_ERR(gphy);
2769 if (cdns_phy->phys[node].phy_type == TYPE_DP) {
2770 switch (cdns_phy->phys[node].num_lanes) {
2774 /* valid number of lanes */
2777 dev_err(dev, "unsupported number of lanes: %d\n",
2778 cdns_phy->phys[node].num_lanes);
2783 cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE;
2784 of_property_read_u32(child, "cdns,max-bit-rate",
2785 &cdns_phy->max_bit_rate);
2787 switch (cdns_phy->max_bit_rate) {
2796 /* valid bit rate */
2799 dev_err(dev, "unsupported max bit rate: %dMbps\n",
2800 cdns_phy->max_bit_rate);
2805 /* DPTX registers */
2806 cdns_phy->base = devm_platform_ioremap_resource(pdev, 1);
2807 if (IS_ERR(cdns_phy->base)) {
2808 ret = PTR_ERR(cdns_phy->base);
2812 if (!init_dp_regmap) {
2813 ret = cdns_torrent_dp_regmap_init(cdns_phy);
2817 ret = cdns_torrent_dp_regfield_init(cdns_phy);
2824 dev_dbg(dev, "DP max bit rate %d.%03d Gbps\n",
2825 cdns_phy->max_bit_rate / 1000,
2826 cdns_phy->max_bit_rate % 1000);
2828 gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes;
2829 gphy->attrs.max_link_rate = cdns_phy->max_bit_rate;
2830 gphy->attrs.mode = PHY_MODE_DP;
2833 cdns_phy->phys[node].phy = gphy;
2834 phy_set_drvdata(gphy, &cdns_phy->phys[node]);
2838 cdns_phy->nsubnodes = node;
2840 if (total_num_lanes > MAX_NUM_LANES) {
2841 dev_err(dev, "Invalid lane configuration\n");
2846 if (cdns_phy->nsubnodes > 1 && !already_configured) {
2847 ret = cdns_torrent_phy_configure_multilink(cdns_phy);
2852 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2853 if (IS_ERR(phy_provider)) {
2854 ret = PTR_ERR(phy_provider);
2858 if (cdns_phy->nsubnodes > 1)
2859 dev_dbg(dev, "Multi-link: %s (%d lanes) & %s (%d lanes)",
2860 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
2861 cdns_phy->phys[0].num_lanes,
2862 cdns_torrent_get_phy_type(cdns_phy->phys[1].phy_type),
2863 cdns_phy->phys[1].num_lanes);
2865 dev_dbg(dev, "Single link: %s (%d lanes)",
2866 cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),
2867 cdns_phy->phys[0].num_lanes);
2874 for (i = 0; i < node; i++)
2875 reset_control_put(cdns_phy->phys[i].lnk_rst);
2877 reset_control_assert(cdns_phy->apb_rst);
2878 clk_disable_unprepare(cdns_phy->clk);
2880 cdns_torrent_clk_cleanup(cdns_phy);
2884 static void cdns_torrent_phy_remove(struct platform_device *pdev)
2886 struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev);
2889 reset_control_assert(cdns_phy->phy_rst);
2890 reset_control_assert(cdns_phy->apb_rst);
2891 for (i = 0; i < cdns_phy->nsubnodes; i++) {
2892 reset_control_assert(cdns_phy->phys[i].lnk_rst);
2893 reset_control_put(cdns_phy->phys[i].lnk_rst);
2896 clk_disable_unprepare(cdns_phy->clk);
2897 cdns_torrent_clk_cleanup(cdns_phy);
2900 /* USB and DP link configuration */
2901 static struct cdns_reg_pairs usb_dp_link_cmn_regs[] = {
2902 {0x0002, PHY_PLL_CFG},
2903 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
2906 static struct cdns_reg_pairs usb_dp_xcvr_diag_ln_regs[] = {
2907 {0x0000, XCVR_DIAG_HSCLK_SEL},
2908 {0x0001, XCVR_DIAG_HSCLK_DIV},
2909 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
2912 static struct cdns_reg_pairs dp_usb_xcvr_diag_ln_regs[] = {
2913 {0x0001, XCVR_DIAG_HSCLK_SEL},
2914 {0x0009, XCVR_DIAG_PLLDRC_CTRL}
2917 static struct cdns_torrent_vals usb_dp_link_cmn_vals = {
2918 .reg_pairs = usb_dp_link_cmn_regs,
2919 .num_regs = ARRAY_SIZE(usb_dp_link_cmn_regs),
2922 static struct cdns_torrent_vals usb_dp_xcvr_diag_ln_vals = {
2923 .reg_pairs = usb_dp_xcvr_diag_ln_regs,
2924 .num_regs = ARRAY_SIZE(usb_dp_xcvr_diag_ln_regs),
2927 static struct cdns_torrent_vals dp_usb_xcvr_diag_ln_vals = {
2928 .reg_pairs = dp_usb_xcvr_diag_ln_regs,
2929 .num_regs = ARRAY_SIZE(dp_usb_xcvr_diag_ln_regs),
2932 /* PCIe and DP link configuration */
2933 static struct cdns_reg_pairs pcie_dp_link_cmn_regs[] = {
2934 {0x0003, PHY_PLL_CFG},
2935 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
2936 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}
2939 static struct cdns_reg_pairs pcie_dp_xcvr_diag_ln_regs[] = {
2940 {0x0000, XCVR_DIAG_HSCLK_SEL},
2941 {0x0001, XCVR_DIAG_HSCLK_DIV},
2942 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
2945 static struct cdns_reg_pairs dp_pcie_xcvr_diag_ln_regs[] = {
2946 {0x0001, XCVR_DIAG_HSCLK_SEL},
2947 {0x0009, XCVR_DIAG_PLLDRC_CTRL}
2950 static struct cdns_torrent_vals pcie_dp_link_cmn_vals = {
2951 .reg_pairs = pcie_dp_link_cmn_regs,
2952 .num_regs = ARRAY_SIZE(pcie_dp_link_cmn_regs),
2955 static struct cdns_torrent_vals pcie_dp_xcvr_diag_ln_vals = {
2956 .reg_pairs = pcie_dp_xcvr_diag_ln_regs,
2957 .num_regs = ARRAY_SIZE(pcie_dp_xcvr_diag_ln_regs),
2960 static struct cdns_torrent_vals dp_pcie_xcvr_diag_ln_vals = {
2961 .reg_pairs = dp_pcie_xcvr_diag_ln_regs,
2962 .num_regs = ARRAY_SIZE(dp_pcie_xcvr_diag_ln_regs),
2965 /* DP Multilink, 100 MHz Ref clk, no SSC */
2966 static struct cdns_reg_pairs dp_100_no_ssc_cmn_regs[] = {
2967 {0x007F, CMN_TXPUCAL_TUNE},
2968 {0x007F, CMN_TXPDCAL_TUNE}
2971 static struct cdns_reg_pairs dp_100_no_ssc_tx_ln_regs[] = {
2972 {0x00FB, TX_PSC_A0},
2973 {0x04AA, TX_PSC_A2},
2974 {0x04AA, TX_PSC_A3},
2975 {0x000F, XCVR_DIAG_BIDI_CTRL}
2978 static struct cdns_reg_pairs dp_100_no_ssc_rx_ln_regs[] = {
2979 {0x0000, RX_PSC_A0},
2980 {0x0000, RX_PSC_A2},
2981 {0x0000, RX_PSC_A3},
2982 {0x0000, RX_PSC_CAL},
2983 {0x0000, RX_REE_GCSM1_CTRL},
2984 {0x0000, RX_REE_GCSM2_CTRL},
2985 {0x0000, RX_REE_PERGCSM_CTRL}
2988 static struct cdns_torrent_vals dp_100_no_ssc_cmn_vals = {
2989 .reg_pairs = dp_100_no_ssc_cmn_regs,
2990 .num_regs = ARRAY_SIZE(dp_100_no_ssc_cmn_regs),
2993 static struct cdns_torrent_vals dp_100_no_ssc_tx_ln_vals = {
2994 .reg_pairs = dp_100_no_ssc_tx_ln_regs,
2995 .num_regs = ARRAY_SIZE(dp_100_no_ssc_tx_ln_regs),
2998 static struct cdns_torrent_vals dp_100_no_ssc_rx_ln_vals = {
2999 .reg_pairs = dp_100_no_ssc_rx_ln_regs,
3000 .num_regs = ARRAY_SIZE(dp_100_no_ssc_rx_ln_regs),
3003 /* Single DisplayPort(DP) link configuration */
3004 static struct cdns_reg_pairs sl_dp_link_cmn_regs[] = {
3005 {0x0000, PHY_PLL_CFG},
3008 static struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = {
3009 {0x0000, XCVR_DIAG_HSCLK_SEL},
3010 {0x0001, XCVR_DIAG_PLLDRC_CTRL}
3013 static struct cdns_torrent_vals sl_dp_link_cmn_vals = {
3014 .reg_pairs = sl_dp_link_cmn_regs,
3015 .num_regs = ARRAY_SIZE(sl_dp_link_cmn_regs),
3018 static struct cdns_torrent_vals sl_dp_xcvr_diag_ln_vals = {
3019 .reg_pairs = sl_dp_xcvr_diag_ln_regs,
3020 .num_regs = ARRAY_SIZE(sl_dp_xcvr_diag_ln_regs),
3023 /* Single DP, 19.2 MHz Ref clk, no SSC */
3024 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = {
3025 {0x0014, CMN_SSM_BIAS_TMR},
3026 {0x0027, CMN_PLLSM0_PLLPRE_TMR},
3027 {0x00A1, CMN_PLLSM0_PLLLOCK_TMR},
3028 {0x0027, CMN_PLLSM1_PLLPRE_TMR},
3029 {0x00A1, CMN_PLLSM1_PLLLOCK_TMR},
3030 {0x0060, CMN_BGCAL_INIT_TMR},
3031 {0x0060, CMN_BGCAL_ITER_TMR},
3032 {0x0014, CMN_IBCAL_INIT_TMR},
3033 {0x0018, CMN_TXPUCAL_INIT_TMR},
3034 {0x0005, CMN_TXPUCAL_ITER_TMR},
3035 {0x0018, CMN_TXPDCAL_INIT_TMR},
3036 {0x0005, CMN_TXPDCAL_ITER_TMR},
3037 {0x0240, CMN_RXCAL_INIT_TMR},
3038 {0x0005, CMN_RXCAL_ITER_TMR},
3039 {0x0002, CMN_SD_CAL_INIT_TMR},
3040 {0x0002, CMN_SD_CAL_ITER_TMR},
3041 {0x000B, CMN_SD_CAL_REFTIM_START},
3042 {0x0137, CMN_SD_CAL_PLLCNT_START},
3043 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3044 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3045 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3046 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3047 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3048 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3049 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3050 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3051 {0x00C0, CMN_PLL0_VCOCAL_INIT_TMR},
3052 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
3053 {0x00C0, CMN_PLL1_VCOCAL_INIT_TMR},
3054 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
3055 {0x0260, CMN_PLL0_VCOCAL_REFTIM_START},
3056 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3057 {0x0260, CMN_PLL1_VCOCAL_REFTIM_START},
3058 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3061 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = {
3062 {0x0780, TX_RCVDET_ST_TMR},
3063 {0x00FB, TX_PSC_A0},
3064 {0x04AA, TX_PSC_A2},
3065 {0x04AA, TX_PSC_A3},
3066 {0x000F, XCVR_DIAG_BIDI_CTRL}
3069 static struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = {
3070 {0x0000, RX_PSC_A0},
3071 {0x0000, RX_PSC_A2},
3072 {0x0000, RX_PSC_A3},
3073 {0x0000, RX_PSC_CAL},
3074 {0x0000, RX_REE_GCSM1_CTRL},
3075 {0x0000, RX_REE_GCSM2_CTRL},
3076 {0x0000, RX_REE_PERGCSM_CTRL}
3079 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_cmn_vals = {
3080 .reg_pairs = sl_dp_19_2_no_ssc_cmn_regs,
3081 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_cmn_regs),
3084 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_tx_ln_vals = {
3085 .reg_pairs = sl_dp_19_2_no_ssc_tx_ln_regs,
3086 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_tx_ln_regs),
3089 static struct cdns_torrent_vals sl_dp_19_2_no_ssc_rx_ln_vals = {
3090 .reg_pairs = sl_dp_19_2_no_ssc_rx_ln_regs,
3091 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_rx_ln_regs),
3094 /* Single DP, 25 MHz Ref clk, no SSC */
3095 static struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = {
3096 {0x0019, CMN_SSM_BIAS_TMR},
3097 {0x0032, CMN_PLLSM0_PLLPRE_TMR},
3098 {0x00D1, CMN_PLLSM0_PLLLOCK_TMR},
3099 {0x0032, CMN_PLLSM1_PLLPRE_TMR},
3100 {0x00D1, CMN_PLLSM1_PLLLOCK_TMR},
3101 {0x007D, CMN_BGCAL_INIT_TMR},
3102 {0x007D, CMN_BGCAL_ITER_TMR},
3103 {0x0019, CMN_IBCAL_INIT_TMR},
3104 {0x001E, CMN_TXPUCAL_INIT_TMR},
3105 {0x0006, CMN_TXPUCAL_ITER_TMR},
3106 {0x001E, CMN_TXPDCAL_INIT_TMR},
3107 {0x0006, CMN_TXPDCAL_ITER_TMR},
3108 {0x02EE, CMN_RXCAL_INIT_TMR},
3109 {0x0006, CMN_RXCAL_ITER_TMR},
3110 {0x0002, CMN_SD_CAL_INIT_TMR},
3111 {0x0002, CMN_SD_CAL_ITER_TMR},
3112 {0x000E, CMN_SD_CAL_REFTIM_START},
3113 {0x012B, CMN_SD_CAL_PLLCNT_START},
3114 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3115 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3116 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3117 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3118 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3119 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3120 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3121 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3122 {0x00FA, CMN_PLL0_VCOCAL_INIT_TMR},
3123 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR},
3124 {0x00FA, CMN_PLL1_VCOCAL_INIT_TMR},
3125 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR},
3126 {0x0317, CMN_PLL0_VCOCAL_REFTIM_START},
3127 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3128 {0x0317, CMN_PLL1_VCOCAL_REFTIM_START},
3129 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3132 static struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = {
3133 {0x09C4, TX_RCVDET_ST_TMR},
3134 {0x00FB, TX_PSC_A0},
3135 {0x04AA, TX_PSC_A2},
3136 {0x04AA, TX_PSC_A3},
3137 {0x000F, XCVR_DIAG_BIDI_CTRL}
3140 static struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = {
3141 {0x0000, RX_PSC_A0},
3142 {0x0000, RX_PSC_A2},
3143 {0x0000, RX_PSC_A3},
3144 {0x0000, RX_PSC_CAL},
3145 {0x0000, RX_REE_GCSM1_CTRL},
3146 {0x0000, RX_REE_GCSM2_CTRL},
3147 {0x0000, RX_REE_PERGCSM_CTRL}
3150 static struct cdns_torrent_vals sl_dp_25_no_ssc_cmn_vals = {
3151 .reg_pairs = sl_dp_25_no_ssc_cmn_regs,
3152 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_cmn_regs),
3155 static struct cdns_torrent_vals sl_dp_25_no_ssc_tx_ln_vals = {
3156 .reg_pairs = sl_dp_25_no_ssc_tx_ln_regs,
3157 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_tx_ln_regs),
3160 static struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = {
3161 .reg_pairs = sl_dp_25_no_ssc_rx_ln_regs,
3162 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_rx_ln_regs),
3165 /* Single DP, 100 MHz Ref clk, no SSC */
3166 static struct cdns_reg_pairs sl_dp_100_no_ssc_cmn_regs[] = {
3167 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3168 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3171 static struct cdns_reg_pairs sl_dp_100_no_ssc_tx_ln_regs[] = {
3172 {0x00FB, TX_PSC_A0},
3173 {0x04AA, TX_PSC_A2},
3174 {0x04AA, TX_PSC_A3},
3175 {0x000F, XCVR_DIAG_BIDI_CTRL}
3178 static struct cdns_reg_pairs sl_dp_100_no_ssc_rx_ln_regs[] = {
3179 {0x0000, RX_PSC_A0},
3180 {0x0000, RX_PSC_A2},
3181 {0x0000, RX_PSC_A3},
3182 {0x0000, RX_PSC_CAL},
3183 {0x0000, RX_REE_GCSM1_CTRL},
3184 {0x0000, RX_REE_GCSM2_CTRL},
3185 {0x0000, RX_REE_PERGCSM_CTRL}
3188 static struct cdns_torrent_vals sl_dp_100_no_ssc_cmn_vals = {
3189 .reg_pairs = sl_dp_100_no_ssc_cmn_regs,
3190 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_cmn_regs),
3193 static struct cdns_torrent_vals sl_dp_100_no_ssc_tx_ln_vals = {
3194 .reg_pairs = sl_dp_100_no_ssc_tx_ln_regs,
3195 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_tx_ln_regs),
3198 static struct cdns_torrent_vals sl_dp_100_no_ssc_rx_ln_vals = {
3199 .reg_pairs = sl_dp_100_no_ssc_rx_ln_regs,
3200 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_rx_ln_regs),
3203 /* USB and SGMII/QSGMII link configuration */
3204 static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {
3205 {0x0002, PHY_PLL_CFG},
3206 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0},
3207 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
3210 static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = {
3211 {0x0000, XCVR_DIAG_HSCLK_SEL},
3212 {0x0001, XCVR_DIAG_HSCLK_DIV},
3213 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
3216 static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = {
3217 {0x0011, XCVR_DIAG_HSCLK_SEL},
3218 {0x0003, XCVR_DIAG_HSCLK_DIV},
3219 {0x009B, XCVR_DIAG_PLLDRC_CTRL}
3222 static struct cdns_torrent_vals usb_sgmii_link_cmn_vals = {
3223 .reg_pairs = usb_sgmii_link_cmn_regs,
3224 .num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs),
3227 static struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = {
3228 .reg_pairs = usb_sgmii_xcvr_diag_ln_regs,
3229 .num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs),
3232 static struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = {
3233 .reg_pairs = sgmii_usb_xcvr_diag_ln_regs,
3234 .num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs),
3237 /* PCIe and USB Unique SSC link configuration */
3238 static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = {
3239 {0x0003, PHY_PLL_CFG},
3240 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
3241 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
3242 {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0}
3245 static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = {
3246 {0x0000, XCVR_DIAG_HSCLK_SEL},
3247 {0x0001, XCVR_DIAG_HSCLK_DIV},
3248 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
3251 static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = {
3252 {0x0011, XCVR_DIAG_HSCLK_SEL},
3253 {0x0001, XCVR_DIAG_HSCLK_DIV},
3254 {0x00C9, XCVR_DIAG_PLLDRC_CTRL}
3257 static struct cdns_torrent_vals pcie_usb_link_cmn_vals = {
3258 .reg_pairs = pcie_usb_link_cmn_regs,
3259 .num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs),
3262 static struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = {
3263 .reg_pairs = pcie_usb_xcvr_diag_ln_regs,
3264 .num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs),
3267 static struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = {
3268 .reg_pairs = usb_pcie_xcvr_diag_ln_regs,
3269 .num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs),
3272 /* USB 100 MHz Ref clk, internal SSC */
3273 static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = {
3274 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3275 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3276 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3277 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3278 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3279 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3280 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3281 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3282 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3283 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3284 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3285 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3286 {0x0064, CMN_PLL0_INTDIV_M0},
3287 {0x0050, CMN_PLL0_INTDIV_M1},
3288 {0x0064, CMN_PLL1_INTDIV_M0},
3289 {0x0002, CMN_PLL0_FRACDIVH_M0},
3290 {0x0002, CMN_PLL0_FRACDIVH_M1},
3291 {0x0002, CMN_PLL1_FRACDIVH_M0},
3292 {0x0044, CMN_PLL0_HIGH_THR_M0},
3293 {0x0036, CMN_PLL0_HIGH_THR_M1},
3294 {0x0044, CMN_PLL1_HIGH_THR_M0},
3295 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3296 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3297 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3298 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3299 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3300 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3301 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3302 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3303 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3304 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3305 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3306 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3307 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3308 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3309 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3310 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3311 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3312 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3313 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3314 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3315 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3316 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3317 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3318 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3319 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3320 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3321 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
3322 {0x007F, CMN_TXPUCAL_TUNE},
3323 {0x007F, CMN_TXPDCAL_TUNE}
3326 static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = {
3327 .reg_pairs = usb_100_int_ssc_cmn_regs,
3328 .num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs),
3331 /* Single USB link configuration */
3332 static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = {
3333 {0x0000, PHY_PLL_CFG},
3334 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
3337 static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = {
3338 {0x0000, XCVR_DIAG_HSCLK_SEL},
3339 {0x0001, XCVR_DIAG_HSCLK_DIV},
3340 {0x0041, XCVR_DIAG_PLLDRC_CTRL}
3343 static struct cdns_torrent_vals sl_usb_link_cmn_vals = {
3344 .reg_pairs = sl_usb_link_cmn_regs,
3345 .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs),
3348 static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = {
3349 .reg_pairs = sl_usb_xcvr_diag_ln_regs,
3350 .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs),
3353 /* USB PHY PCS common configuration */
3354 static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = {
3355 {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0},
3356 {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0},
3357 {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1}
3360 static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = {
3361 .reg_pairs = usb_phy_pcs_cmn_regs,
3362 .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs),
3365 /* USB 100 MHz Ref clk, no SSC */
3366 static struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = {
3367 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3368 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3369 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3370 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3371 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
3372 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3373 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
3376 static struct cdns_torrent_vals sl_usb_100_no_ssc_cmn_vals = {
3377 .reg_pairs = sl_usb_100_no_ssc_cmn_regs,
3378 .num_regs = ARRAY_SIZE(sl_usb_100_no_ssc_cmn_regs),
3381 static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = {
3382 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3383 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
3384 {0x007F, CMN_TXPUCAL_TUNE},
3385 {0x007F, CMN_TXPDCAL_TUNE}
3388 static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = {
3389 {0x02FF, TX_PSC_A0},
3390 {0x06AF, TX_PSC_A1},
3391 {0x06AE, TX_PSC_A2},
3392 {0x06AE, TX_PSC_A3},
3393 {0x2A82, TX_TXCC_CTRL},
3394 {0x0014, TX_TXCC_CPOST_MULT_01},
3395 {0x0003, XCVR_DIAG_PSC_OVRD}
3398 static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = {
3399 {0x0D1D, RX_PSC_A0},
3400 {0x0D1D, RX_PSC_A1},
3401 {0x0D00, RX_PSC_A2},
3402 {0x0500, RX_PSC_A3},
3403 {0x0013, RX_SIGDET_HL_FILT_TMR},
3404 {0x0000, RX_REE_GCSM1_CTRL},
3405 {0x0C02, RX_REE_ATTEN_THR},
3406 {0x0330, RX_REE_SMGM_CTRL1},
3407 {0x0300, RX_REE_SMGM_CTRL2},
3408 {0x0019, RX_REE_TAP1_CLIP},
3409 {0x0019, RX_REE_TAP2TON_CLIP},
3410 {0x1004, RX_DIAG_SIGDET_TUNE},
3411 {0x00F9, RX_DIAG_NQST_CTRL},
3412 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3413 {0x0002, RX_DIAG_DFE_AMP_TUNE_3},
3414 {0x0000, RX_DIAG_PI_CAP},
3415 {0x0031, RX_DIAG_PI_RATE},
3416 {0x0001, RX_DIAG_ACYA},
3417 {0x018C, RX_CDRLF_CNFG},
3418 {0x0003, RX_CDRLF_CNFG3}
3421 static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = {
3422 .reg_pairs = usb_100_no_ssc_cmn_regs,
3423 .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs),
3426 static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = {
3427 .reg_pairs = usb_100_no_ssc_tx_ln_regs,
3428 .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs),
3431 static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = {
3432 .reg_pairs = usb_100_no_ssc_rx_ln_regs,
3433 .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs),
3436 /* Single link USB, 100 MHz Ref clk, internal SSC */
3437 static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = {
3438 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3439 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3440 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3441 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3442 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3443 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3444 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3445 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3446 {0x0064, CMN_PLL0_INTDIV_M0},
3447 {0x0064, CMN_PLL1_INTDIV_M0},
3448 {0x0002, CMN_PLL0_FRACDIVH_M0},
3449 {0x0002, CMN_PLL1_FRACDIVH_M0},
3450 {0x0044, CMN_PLL0_HIGH_THR_M0},
3451 {0x0044, CMN_PLL1_HIGH_THR_M0},
3452 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3453 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3454 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3455 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3456 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3457 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3458 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3459 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3460 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3461 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3462 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3463 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3464 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3465 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3466 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3467 {0x0003, CMN_PLL1_VCOCAL_TCTRL},
3468 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3469 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3470 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3471 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3472 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3473 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3474 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
3475 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
3478 static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = {
3479 .reg_pairs = sl_usb_100_int_ssc_cmn_regs,
3480 .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs),
3483 /* PCIe and SGMII/QSGMII Unique SSC link configuration */
3484 static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = {
3485 {0x0003, PHY_PLL_CFG},
3486 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
3487 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
3488 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
3491 static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = {
3492 {0x0000, XCVR_DIAG_HSCLK_SEL},
3493 {0x0001, XCVR_DIAG_HSCLK_DIV},
3494 {0x0012, XCVR_DIAG_PLLDRC_CTRL}
3497 static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = {
3498 {0x0011, XCVR_DIAG_HSCLK_SEL},
3499 {0x0003, XCVR_DIAG_HSCLK_DIV},
3500 {0x009B, XCVR_DIAG_PLLDRC_CTRL}
3503 static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = {
3504 .reg_pairs = pcie_sgmii_link_cmn_regs,
3505 .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs),
3508 static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = {
3509 .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs,
3510 .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs),
3513 static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = {
3514 .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs,
3515 .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs),
3518 /* SGMII 100 MHz Ref clk, no SSC */
3519 static struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = {
3520 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3521 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3522 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3523 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3524 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3527 static struct cdns_torrent_vals sl_sgmii_100_no_ssc_cmn_vals = {
3528 .reg_pairs = sl_sgmii_100_no_ssc_cmn_regs,
3529 .num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_cmn_regs),
3532 static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = {
3533 {0x007F, CMN_TXPUCAL_TUNE},
3534 {0x007F, CMN_TXPDCAL_TUNE}
3537 static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = {
3538 {0x00F3, TX_PSC_A0},
3539 {0x04A2, TX_PSC_A2},
3540 {0x04A2, TX_PSC_A3},
3541 {0x0000, TX_TXCC_CPOST_MULT_00},
3542 {0x00B3, DRV_DIAG_TX_DRV}
3545 static struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = {
3546 {0x00F3, TX_PSC_A0},
3547 {0x04A2, TX_PSC_A2},
3548 {0x04A2, TX_PSC_A3},
3549 {0x0000, TX_TXCC_CPOST_MULT_00},
3550 {0x00B3, DRV_DIAG_TX_DRV},
3551 {0x4000, XCVR_DIAG_RXCLK_CTRL},
3554 static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = {
3555 {0x091D, RX_PSC_A0},
3556 {0x0900, RX_PSC_A2},
3557 {0x0100, RX_PSC_A3},
3558 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
3559 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
3560 {0x0000, RX_DIAG_DFE_CTRL},
3561 {0x0019, RX_REE_TAP1_CLIP},
3562 {0x0019, RX_REE_TAP2TON_CLIP},
3563 {0x0098, RX_DIAG_NQST_CTRL},
3564 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3565 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
3566 {0x0000, RX_DIAG_PI_CAP},
3567 {0x0010, RX_DIAG_PI_RATE},
3568 {0x0001, RX_DIAG_ACYA},
3569 {0x018C, RX_CDRLF_CNFG},
3572 static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = {
3573 .reg_pairs = sgmii_100_no_ssc_cmn_regs,
3574 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs),
3577 static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = {
3578 .reg_pairs = sgmii_100_no_ssc_tx_ln_regs,
3579 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs),
3582 static struct cdns_torrent_vals ti_sgmii_100_no_ssc_tx_ln_vals = {
3583 .reg_pairs = ti_sgmii_100_no_ssc_tx_ln_regs,
3584 .num_regs = ARRAY_SIZE(ti_sgmii_100_no_ssc_tx_ln_regs),
3587 static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = {
3588 .reg_pairs = sgmii_100_no_ssc_rx_ln_regs,
3589 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs),
3592 /* SGMII 100 MHz Ref clk, internal SSC */
3593 static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = {
3594 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3595 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3596 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3597 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3598 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3599 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3600 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3601 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3602 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3603 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3604 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3605 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3606 {0x0064, CMN_PLL0_INTDIV_M0},
3607 {0x0050, CMN_PLL0_INTDIV_M1},
3608 {0x0064, CMN_PLL1_INTDIV_M0},
3609 {0x0002, CMN_PLL0_FRACDIVH_M0},
3610 {0x0002, CMN_PLL0_FRACDIVH_M1},
3611 {0x0002, CMN_PLL1_FRACDIVH_M0},
3612 {0x0044, CMN_PLL0_HIGH_THR_M0},
3613 {0x0036, CMN_PLL0_HIGH_THR_M1},
3614 {0x0044, CMN_PLL1_HIGH_THR_M0},
3615 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3616 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3617 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3618 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3619 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3620 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3621 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3622 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3623 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3624 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3625 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3626 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3627 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3628 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3629 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3630 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3631 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3632 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3633 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3634 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3635 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3636 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3637 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3638 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3639 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3640 {0x007F, CMN_TXPUCAL_TUNE},
3641 {0x007F, CMN_TXPDCAL_TUNE}
3644 static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = {
3645 .reg_pairs = sgmii_100_int_ssc_cmn_regs,
3646 .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs),
3649 /* QSGMII 100 MHz Ref clk, no SSC */
3650 static struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = {
3651 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3652 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3653 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
3654 {0x0003, CMN_PLL0_VCOCAL_TCTRL},
3655 {0x0003, CMN_PLL1_VCOCAL_TCTRL}
3658 static struct cdns_torrent_vals sl_qsgmii_100_no_ssc_cmn_vals = {
3659 .reg_pairs = sl_qsgmii_100_no_ssc_cmn_regs,
3660 .num_regs = ARRAY_SIZE(sl_qsgmii_100_no_ssc_cmn_regs),
3663 static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = {
3664 {0x007F, CMN_TXPUCAL_TUNE},
3665 {0x007F, CMN_TXPDCAL_TUNE}
3668 static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = {
3669 {0x00F3, TX_PSC_A0},
3670 {0x04A2, TX_PSC_A2},
3671 {0x04A2, TX_PSC_A3},
3672 {0x0000, TX_TXCC_CPOST_MULT_00},
3673 {0x0011, TX_TXCC_MGNFS_MULT_100},
3674 {0x0003, DRV_DIAG_TX_DRV}
3677 static struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = {
3678 {0x00F3, TX_PSC_A0},
3679 {0x04A2, TX_PSC_A2},
3680 {0x04A2, TX_PSC_A3},
3681 {0x0000, TX_TXCC_CPOST_MULT_00},
3682 {0x0011, TX_TXCC_MGNFS_MULT_100},
3683 {0x0003, DRV_DIAG_TX_DRV},
3684 {0x4000, XCVR_DIAG_RXCLK_CTRL},
3687 static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = {
3688 {0x091D, RX_PSC_A0},
3689 {0x0900, RX_PSC_A2},
3690 {0x0100, RX_PSC_A3},
3691 {0x03C7, RX_REE_GCSM1_EQENM_PH1},
3692 {0x01C7, RX_REE_GCSM1_EQENM_PH2},
3693 {0x0000, RX_DIAG_DFE_CTRL},
3694 {0x0019, RX_REE_TAP1_CLIP},
3695 {0x0019, RX_REE_TAP2TON_CLIP},
3696 {0x0098, RX_DIAG_NQST_CTRL},
3697 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
3698 {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
3699 {0x0000, RX_DIAG_PI_CAP},
3700 {0x0010, RX_DIAG_PI_RATE},
3701 {0x0001, RX_DIAG_ACYA},
3702 {0x018C, RX_CDRLF_CNFG},
3705 static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = {
3706 .reg_pairs = qsgmii_100_no_ssc_cmn_regs,
3707 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs),
3710 static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = {
3711 .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs,
3712 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs),
3715 static struct cdns_torrent_vals ti_qsgmii_100_no_ssc_tx_ln_vals = {
3716 .reg_pairs = ti_qsgmii_100_no_ssc_tx_ln_regs,
3717 .num_regs = ARRAY_SIZE(ti_qsgmii_100_no_ssc_tx_ln_regs),
3720 static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = {
3721 .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs,
3722 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs),
3725 /* QSGMII 100 MHz Ref clk, internal SSC */
3726 static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = {
3727 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3728 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3729 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3730 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3731 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3732 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3733 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3734 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3735 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3736 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3737 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3738 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3739 {0x0064, CMN_PLL0_INTDIV_M0},
3740 {0x0050, CMN_PLL0_INTDIV_M1},
3741 {0x0064, CMN_PLL1_INTDIV_M0},
3742 {0x0002, CMN_PLL0_FRACDIVH_M0},
3743 {0x0002, CMN_PLL0_FRACDIVH_M1},
3744 {0x0002, CMN_PLL1_FRACDIVH_M0},
3745 {0x0044, CMN_PLL0_HIGH_THR_M0},
3746 {0x0036, CMN_PLL0_HIGH_THR_M1},
3747 {0x0044, CMN_PLL1_HIGH_THR_M0},
3748 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3749 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3750 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3751 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3752 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3753 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3754 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3755 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3756 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3757 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3758 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3759 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3760 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3761 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3762 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3763 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3764 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3765 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3766 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3767 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3768 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3769 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3770 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3771 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3772 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
3773 {0x007F, CMN_TXPUCAL_TUNE},
3774 {0x007F, CMN_TXPDCAL_TUNE}
3777 static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = {
3778 .reg_pairs = qsgmii_100_int_ssc_cmn_regs,
3779 .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs),
3782 /* Single SGMII/QSGMII link configuration */
3783 static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = {
3784 {0x0000, PHY_PLL_CFG},
3785 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
3788 static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = {
3789 {0x0000, XCVR_DIAG_HSCLK_SEL},
3790 {0x0003, XCVR_DIAG_HSCLK_DIV},
3791 {0x0013, XCVR_DIAG_PLLDRC_CTRL}
3794 static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = {
3795 .reg_pairs = sl_sgmii_link_cmn_regs,
3796 .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs),
3799 static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
3800 .reg_pairs = sl_sgmii_xcvr_diag_ln_regs,
3801 .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
3804 /* Multi link PCIe, 100 MHz Ref clk, internal SSC */
3805 static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
3806 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3807 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3808 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3809 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3810 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3811 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3812 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3813 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3814 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3815 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3816 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3817 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3818 {0x0064, CMN_PLL0_INTDIV_M0},
3819 {0x0050, CMN_PLL0_INTDIV_M1},
3820 {0x0064, CMN_PLL1_INTDIV_M0},
3821 {0x0002, CMN_PLL0_FRACDIVH_M0},
3822 {0x0002, CMN_PLL0_FRACDIVH_M1},
3823 {0x0002, CMN_PLL1_FRACDIVH_M0},
3824 {0x0044, CMN_PLL0_HIGH_THR_M0},
3825 {0x0036, CMN_PLL0_HIGH_THR_M1},
3826 {0x0044, CMN_PLL1_HIGH_THR_M0},
3827 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3828 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3829 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3830 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3831 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3832 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3833 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3834 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3835 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3836 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3837 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3838 {0x006E, CMN_PLL1_SS_CTRL3_M0},
3839 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3840 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3841 {0x000E, CMN_PLL1_SS_CTRL4_M0},
3842 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3843 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3844 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3845 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3846 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3847 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3848 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3849 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3850 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3851 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
3854 static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = {
3855 .reg_pairs = pcie_100_int_ssc_cmn_regs,
3856 .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs),
3859 /* Single link PCIe, 100 MHz Ref clk, internal SSC */
3860 static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = {
3861 {0x0004, CMN_PLL0_DSM_DIAG_M0},
3862 {0x0004, CMN_PLL0_DSM_DIAG_M1},
3863 {0x0004, CMN_PLL1_DSM_DIAG_M0},
3864 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
3865 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
3866 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
3867 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
3868 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
3869 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
3870 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
3871 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
3872 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
3873 {0x0064, CMN_PLL0_INTDIV_M0},
3874 {0x0050, CMN_PLL0_INTDIV_M1},
3875 {0x0050, CMN_PLL1_INTDIV_M0},
3876 {0x0002, CMN_PLL0_FRACDIVH_M0},
3877 {0x0002, CMN_PLL0_FRACDIVH_M1},
3878 {0x0002, CMN_PLL1_FRACDIVH_M0},
3879 {0x0044, CMN_PLL0_HIGH_THR_M0},
3880 {0x0036, CMN_PLL0_HIGH_THR_M1},
3881 {0x0036, CMN_PLL1_HIGH_THR_M0},
3882 {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
3883 {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
3884 {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
3885 {0x0001, CMN_PLL0_SS_CTRL1_M0},
3886 {0x0001, CMN_PLL0_SS_CTRL1_M1},
3887 {0x0001, CMN_PLL1_SS_CTRL1_M0},
3888 {0x011B, CMN_PLL0_SS_CTRL2_M0},
3889 {0x011B, CMN_PLL0_SS_CTRL2_M1},
3890 {0x011B, CMN_PLL1_SS_CTRL2_M0},
3891 {0x006E, CMN_PLL0_SS_CTRL3_M0},
3892 {0x0058, CMN_PLL0_SS_CTRL3_M1},
3893 {0x0058, CMN_PLL1_SS_CTRL3_M0},
3894 {0x000E, CMN_PLL0_SS_CTRL4_M0},
3895 {0x0012, CMN_PLL0_SS_CTRL4_M1},
3896 {0x0012, CMN_PLL1_SS_CTRL4_M0},
3897 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
3898 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
3899 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
3900 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
3901 {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
3902 {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
3903 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
3904 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
3905 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
3906 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
3909 static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = {
3910 .reg_pairs = sl_pcie_100_int_ssc_cmn_regs,
3911 .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs),
3914 /* PCIe, 100 MHz Ref clk, no SSC & external SSC */
3915 static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = {
3916 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
3917 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
3918 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}
3921 static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = {
3922 {0x0019, RX_REE_TAP1_CLIP},
3923 {0x0019, RX_REE_TAP2TON_CLIP},
3924 {0x0001, RX_DIAG_ACYA}
3927 static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = {
3928 .reg_pairs = pcie_100_ext_no_ssc_cmn_regs,
3929 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs),
3932 static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = {
3933 .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs,
3934 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs),
3937 static const struct cdns_torrent_data cdns_map_torrent = {
3938 .block_offset_shift = 0x2,
3939 .reg_offset_shift = 0x2,
3943 [NO_SSC] = &sl_dp_link_cmn_vals,
3946 [NO_SSC] = &pcie_dp_link_cmn_vals,
3949 [NO_SSC] = &usb_dp_link_cmn_vals,
3955 [EXTERNAL_SSC] = NULL,
3956 [INTERNAL_SSC] = NULL,
3959 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3960 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3961 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3964 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3965 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3966 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3969 [NO_SSC] = &pcie_usb_link_cmn_vals,
3970 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3971 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
3974 [NO_SSC] = &pcie_dp_link_cmn_vals,
3979 [NO_SSC] = &sl_sgmii_link_cmn_vals,
3982 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3983 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3984 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3987 [NO_SSC] = &usb_sgmii_link_cmn_vals,
3988 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3989 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
3994 [NO_SSC] = &sl_sgmii_link_cmn_vals,
3997 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
3998 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
3999 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4002 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4003 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4004 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4009 [NO_SSC] = &sl_usb_link_cmn_vals,
4010 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
4011 [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
4014 [NO_SSC] = &pcie_usb_link_cmn_vals,
4015 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4016 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4019 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4020 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4021 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4024 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4025 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4026 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4029 [NO_SSC] = &usb_dp_link_cmn_vals,
4036 [NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
4039 [NO_SSC] = &dp_pcie_xcvr_diag_ln_vals,
4042 [NO_SSC] = &dp_usb_xcvr_diag_ln_vals,
4048 [EXTERNAL_SSC] = NULL,
4049 [INTERNAL_SSC] = NULL,
4052 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4053 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4054 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4057 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4058 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4059 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4062 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
4063 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
4064 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
4067 [NO_SSC] = &pcie_dp_xcvr_diag_ln_vals,
4072 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
4075 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4076 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4077 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4080 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4081 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4082 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4087 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
4090 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4091 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4092 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4095 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4096 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4097 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4102 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
4103 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
4104 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
4107 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
4108 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
4109 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
4112 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4113 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4114 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4117 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4118 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4119 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4122 [NO_SSC] = &usb_dp_xcvr_diag_ln_vals,
4129 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4130 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4131 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4134 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4135 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4136 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4139 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4140 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4141 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4144 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4145 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4146 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4149 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4157 [NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals,
4164 [NO_SSC] = &sl_dp_25_no_ssc_cmn_vals,
4171 [NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
4174 [NO_SSC] = &dp_100_no_ssc_cmn_vals,
4177 [NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
4183 [EXTERNAL_SSC] = NULL,
4184 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
4187 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
4188 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
4189 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
4192 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
4193 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
4194 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
4197 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
4198 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
4199 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
4207 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
4210 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
4211 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
4212 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
4215 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
4216 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
4217 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
4222 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
4225 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4226 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4227 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
4230 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4231 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4232 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4237 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4238 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4239 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4242 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
4243 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
4244 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
4247 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4248 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4249 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4252 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4253 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4254 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4257 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
4266 [NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals,
4273 [NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals,
4280 [NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals,
4283 [NO_SSC] = &dp_100_no_ssc_tx_ln_vals,
4286 [NO_SSC] = &dp_100_no_ssc_tx_ln_vals,
4292 [EXTERNAL_SSC] = NULL,
4293 [INTERNAL_SSC] = NULL,
4297 [EXTERNAL_SSC] = NULL,
4298 [INTERNAL_SSC] = NULL,
4302 [EXTERNAL_SSC] = NULL,
4303 [INTERNAL_SSC] = NULL,
4307 [EXTERNAL_SSC] = NULL,
4308 [INTERNAL_SSC] = NULL,
4316 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4319 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4320 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4321 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4324 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4325 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4326 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
4331 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4334 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4335 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4336 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4339 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4340 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4341 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
4346 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4347 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4348 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4351 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4352 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4353 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4356 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4357 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4358 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4361 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4362 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4363 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4366 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4375 [NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals,
4382 [NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals,
4389 [NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals,
4392 [NO_SSC] = &dp_100_no_ssc_rx_ln_vals,
4395 [NO_SSC] = &dp_100_no_ssc_rx_ln_vals,
4400 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4401 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4402 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4405 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4406 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4407 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4410 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4411 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4412 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4415 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4416 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4417 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4420 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4425 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4428 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4429 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4430 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4433 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4434 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4435 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4440 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4443 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4444 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4445 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4448 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4449 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4450 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4455 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4456 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4457 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4460 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4461 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4462 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4465 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4466 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4467 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4470 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4471 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4472 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
4475 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
4482 static const struct cdns_torrent_data ti_j721e_map_torrent = {
4483 .block_offset_shift = 0x0,
4484 .reg_offset_shift = 0x1,
4488 [NO_SSC] = &sl_dp_link_cmn_vals,
4491 [NO_SSC] = &pcie_dp_link_cmn_vals,
4494 [NO_SSC] = &usb_dp_link_cmn_vals,
4500 [EXTERNAL_SSC] = NULL,
4501 [INTERNAL_SSC] = NULL,
4504 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
4505 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4506 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4509 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
4510 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4511 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4514 [NO_SSC] = &pcie_usb_link_cmn_vals,
4515 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4516 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4519 [NO_SSC] = &pcie_dp_link_cmn_vals,
4524 [NO_SSC] = &sl_sgmii_link_cmn_vals,
4527 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
4528 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4529 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4532 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4533 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4534 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4539 [NO_SSC] = &sl_sgmii_link_cmn_vals,
4542 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
4543 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4544 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
4547 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4548 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4549 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4554 [NO_SSC] = &sl_usb_link_cmn_vals,
4555 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
4556 [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
4559 [NO_SSC] = &pcie_usb_link_cmn_vals,
4560 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4561 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
4564 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4565 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4566 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4569 [NO_SSC] = &usb_sgmii_link_cmn_vals,
4570 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4571 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
4574 [NO_SSC] = &usb_dp_link_cmn_vals,
4581 [NO_SSC] = &sl_dp_xcvr_diag_ln_vals,
4584 [NO_SSC] = &dp_pcie_xcvr_diag_ln_vals,
4587 [NO_SSC] = &dp_usb_xcvr_diag_ln_vals,
4593 [EXTERNAL_SSC] = NULL,
4594 [INTERNAL_SSC] = NULL,
4597 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4598 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4599 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4602 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4603 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4604 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
4607 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
4608 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
4609 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
4612 [NO_SSC] = &pcie_dp_xcvr_diag_ln_vals,
4617 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
4620 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4621 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4622 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4625 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4626 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4627 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4632 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
4635 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4636 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4637 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
4640 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4641 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4642 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
4647 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
4648 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
4649 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
4652 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
4653 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
4654 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
4657 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4658 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4659 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4662 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4663 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4664 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
4667 [NO_SSC] = &usb_dp_xcvr_diag_ln_vals,
4674 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4675 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4676 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4679 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4680 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4681 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4684 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4685 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4686 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4689 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4690 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4691 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
4694 [NO_SSC] = &usb_phy_pcs_cmn_vals,
4702 [NO_SSC] = &sl_dp_19_2_no_ssc_cmn_vals,
4709 [NO_SSC] = &sl_dp_25_no_ssc_cmn_vals,
4716 [NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
4719 [NO_SSC] = &dp_100_no_ssc_cmn_vals,
4722 [NO_SSC] = &sl_dp_100_no_ssc_cmn_vals,
4728 [EXTERNAL_SSC] = NULL,
4729 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
4732 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
4733 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
4734 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
4737 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
4738 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
4739 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
4742 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
4743 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
4744 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
4752 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
4755 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
4756 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
4757 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
4760 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
4761 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
4762 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
4767 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
4770 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4771 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4772 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
4775 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4776 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4777 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
4782 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4783 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4784 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4787 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
4788 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
4789 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
4792 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4793 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4794 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4797 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4798 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
4799 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
4802 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
4811 [NO_SSC] = &sl_dp_19_2_no_ssc_tx_ln_vals,
4818 [NO_SSC] = &sl_dp_25_no_ssc_tx_ln_vals,
4825 [NO_SSC] = &sl_dp_100_no_ssc_tx_ln_vals,
4828 [NO_SSC] = &dp_100_no_ssc_tx_ln_vals,
4831 [NO_SSC] = &dp_100_no_ssc_tx_ln_vals,
4837 [EXTERNAL_SSC] = NULL,
4838 [INTERNAL_SSC] = NULL,
4842 [EXTERNAL_SSC] = NULL,
4843 [INTERNAL_SSC] = NULL,
4847 [EXTERNAL_SSC] = NULL,
4848 [INTERNAL_SSC] = NULL,
4852 [EXTERNAL_SSC] = NULL,
4853 [INTERNAL_SSC] = NULL,
4861 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4864 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4865 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4866 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4869 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4870 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4871 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
4876 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4879 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4880 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4881 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4884 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4885 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4886 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
4891 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4892 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4893 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4896 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4897 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4898 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4901 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4902 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4903 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4906 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4907 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4908 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
4911 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
4920 [NO_SSC] = &sl_dp_19_2_no_ssc_rx_ln_vals,
4927 [NO_SSC] = &sl_dp_25_no_ssc_rx_ln_vals,
4934 [NO_SSC] = &sl_dp_100_no_ssc_rx_ln_vals,
4937 [NO_SSC] = &dp_100_no_ssc_rx_ln_vals,
4940 [NO_SSC] = &dp_100_no_ssc_rx_ln_vals,
4945 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4946 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4947 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4950 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4951 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4952 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4955 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4956 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4957 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4960 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4961 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4962 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4965 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
4970 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4973 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4974 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4975 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4978 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4979 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4980 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
4985 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4988 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4989 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4990 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4993 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4994 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
4995 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
5000 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
5001 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
5002 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
5005 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
5006 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
5007 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
5010 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
5011 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
5012 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
5015 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
5016 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
5017 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
5020 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
5027 static const struct of_device_id cdns_torrent_phy_of_match[] = {
5029 .compatible = "cdns,torrent-phy",
5030 .data = &cdns_map_torrent,
5033 .compatible = "ti,j721e-serdes-10g",
5034 .data = &ti_j721e_map_torrent,
5038 MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match);
5040 static struct platform_driver cdns_torrent_phy_driver = {
5041 .probe = cdns_torrent_phy_probe,
5042 .remove_new = cdns_torrent_phy_remove,
5044 .name = "cdns-torrent-phy",
5045 .of_match_table = cdns_torrent_phy_of_match,
5048 module_platform_driver(cdns_torrent_phy_driver);
5050 MODULE_AUTHOR("Cadence Design Systems, Inc.");
5051 MODULE_DESCRIPTION("Cadence Torrent PHY driver");
5052 MODULE_LICENSE("GPL v2");