drivers/phy/broadcom/phy-brcm-usb-init.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * phy-brcm-usb-init.c - Broadcom USB Phy chip specific init functions
   4  *
   5  * Copyright (C) 2014-2017 Broadcom
   6  */
   7
   8 /*
   9  * This module contains USB PHY initialization for power up and S3 resume
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/io.h>
  14
  15 #include <linux/soc/brcmstb/brcmstb.h>
  16 #include "phy-brcm-usb-init.h"
  17
  18 #define PHY_PORTS 2
  19 #define PHY_PORT_SELECT_0 0
  20 #define PHY_PORT_SELECT_1 0x1000
  21
  22 /* Register definitions for the USB CTRL block */
  23 #define USB_CTRL_SETUP                  0x00
  24 #define   USB_CTRL_SETUP_IOC_MASK                       0x00000010
  25 #define   USB_CTRL_SETUP_IPP_MASK                       0x00000020
  26 #define   USB_CTRL_SETUP_BABO_MASK                      0x00000001
  27 #define   USB_CTRL_SETUP_FNHW_MASK                      0x00000002
  28 #define   USB_CTRL_SETUP_FNBO_MASK                      0x00000004
  29 #define   USB_CTRL_SETUP_WABO_MASK                      0x00000008
  30 #define   USB_CTRL_SETUP_SCB_CLIENT_SWAP_MASK           0x00002000 /* option */
  31 #define   USB_CTRL_SETUP_SCB1_EN_MASK                   0x00004000 /* option */
  32 #define   USB_CTRL_SETUP_SCB2_EN_MASK                   0x00008000 /* option */
  33 #define   USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK           0X00020000 /* option */
  34 #define   USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK       0x00010000 /* option */
  35 #define   USB_CTRL_SETUP_STRAP_IPP_SEL_MASK             0x02000000 /* option */
  36 #define   USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK        0x04000000 /* option */
  37 #define   USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK 0x08000000 /* opt */
  38 #define   USB_CTRL_SETUP_OC3_DISABLE_MASK               0xc0000000 /* option */
  39 #define USB_CTRL_PLL_CTL                0x04
  40 #define   USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK          0x08000000
  41 #define   USB_CTRL_PLL_CTL_PLL_RESETB_MASK              0x40000000
  42 #define   USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK          0x80000000 /* option */
  43 #define USB_CTRL_EBRIDGE                0x0c
  44 #define   USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK           0x00020000 /* option */
  45 #define   USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK            0x00000f80 /* option */
  46 #define USB_CTRL_OBRIDGE                0x10
  47 #define   USB_CTRL_OBRIDGE_LS_KEEP_ALIVE_MASK           0x08000000
  48 #define USB_CTRL_MDIO                   0x14
  49 #define USB_CTRL_MDIO2                  0x18
  50 #define USB_CTRL_UTMI_CTL_1             0x2c
  51 #define   USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_MASK      0x00000800
  52 #define   USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_MASK   0x08000000
  53 #define USB_CTRL_USB_PM                 0x34
  54 #define   USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK          0x00800000 /* option */
  55 #define   USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK          0x00400000 /* option */
  56 #define   USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK      0x40000000 /* option */
  57 #define   USB_CTRL_USB_PM_USB_PWRDN_MASK                0x80000000 /* option */
  58 #define   USB_CTRL_USB_PM_SOFT_RESET_MASK               0x40000000 /* option */
  59 #define   USB_CTRL_USB_PM_USB20_HC_RESETB_MASK          0x30000000 /* option */
  60 #define   USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK      0x00300000 /* option */
  61 #define   USB_CTRL_USB_PM_RMTWKUP_EN_MASK               0x00000001
  62 #define USB_CTRL_USB_PM_STATUS          0x38
  63 #define USB_CTRL_USB30_CTL1             0x60
  64 #define   USB_CTRL_USB30_CTL1_PHY3_PLL_SEQ_START_MASK   0x00000010
  65 #define   USB_CTRL_USB30_CTL1_PHY3_RESETB_MASK          0x00010000
  66 #define   USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK      0x00020000 /* option */
  67 #define   USB_CTRL_USB30_CTL1_USB3_IOC_MASK             0x10000000 /* option */
  68 #define   USB_CTRL_USB30_CTL1_USB3_IPP_MASK             0x20000000 /* option */
  69 #define USB_CTRL_USB30_PCTL             0x70
  70 #define   USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK     0x00000002
  71 #define   USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_MASK   0x00008000
  72 #define   USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK  0x00020000
  73 #define USB_CTRL_USB_DEVICE_CTL1        0x90
  74 #define   USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK       0x00000003 /* option */
  75
  76 /* Register definitions for the XHCI EC block */
  77 #define USB_XHCI_EC_IRAADR 0x658
  78 #define USB_XHCI_EC_IRADAT 0x65c
  79
  80 enum brcm_family_type {
  81         BRCM_FAMILY_3390A0,
  82         BRCM_FAMILY_7250B0,
  83         BRCM_FAMILY_7271A0,
  84         BRCM_FAMILY_7364A0,
  85         BRCM_FAMILY_7366C0,
  86         BRCM_FAMILY_74371A0,
  87         BRCM_FAMILY_7439B0,
  88         BRCM_FAMILY_7445D0,
  89         BRCM_FAMILY_7260A0,
  90         BRCM_FAMILY_7278A0,
  91         BRCM_FAMILY_COUNT,
  92 };
  93
  94 #define USB_BRCM_FAMILY(chip) \
  95         [BRCM_FAMILY_##chip] = __stringify(chip)
  96
  97 static const char *family_names[BRCM_FAMILY_COUNT] = {
  98         USB_BRCM_FAMILY(3390A0),
  99         USB_BRCM_FAMILY(7250B0),
 100         USB_BRCM_FAMILY(7271A0),
 101         USB_BRCM_FAMILY(7364A0),
 102         USB_BRCM_FAMILY(7366C0),
 103         USB_BRCM_FAMILY(74371A0),
 104         USB_BRCM_FAMILY(7439B0),
 105         USB_BRCM_FAMILY(7445D0),
 106         USB_BRCM_FAMILY(7260A0),
 107         USB_BRCM_FAMILY(7278A0),
 108 };
 109
 110 enum {
 111         USB_CTRL_SETUP_SCB1_EN_SELECTOR,
 112         USB_CTRL_SETUP_SCB2_EN_SELECTOR,
 113         USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR,
 114         USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR,
 115         USB_CTRL_SETUP_OC3_DISABLE_SELECTOR,
 116         USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR,
 117         USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR,
 118         USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR,
 119         USB_CTRL_USB_PM_USB_PWRDN_SELECTOR,
 120         USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_SELECTOR,
 121         USB_CTRL_USB30_CTL1_USB3_IOC_SELECTOR,
 122         USB_CTRL_USB30_CTL1_USB3_IPP_SELECTOR,
 123         USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR,
 124         USB_CTRL_USB_PM_SOFT_RESET_SELECTOR,
 125         USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_SELECTOR,
 126         USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_SELECTOR,
 127         USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR,
 128         USB_CTRL_SETUP_ENDIAN_SELECTOR,
 129         USB_CTRL_SELECTOR_COUNT,
 130 };
 131
 132 #define USB_CTRL_MASK_FAMILY(params, reg, field)                        \
 133         (params->usb_reg_bits_map[USB_CTRL_##reg##_##field##_SELECTOR])
 134
 135 #define USB_CTRL_SET_FAMILY(params, reg, field) \
 136         usb_ctrl_set_family(params, USB_CTRL_##reg,     \
 137                         USB_CTRL_##reg##_##field##_SELECTOR)
 138 #define USB_CTRL_UNSET_FAMILY(params, reg, field)       \
 139         usb_ctrl_unset_family(params, USB_CTRL_##reg,   \
 140                 USB_CTRL_##reg##_##field##_SELECTOR)
 141
 142 #define MDIO_USB2       0
 143 #define MDIO_USB3       BIT(31)
 144
 145 #define USB_CTRL_SETUP_ENDIAN_BITS (    \
 146                 USB_CTRL_MASK(SETUP, BABO) |    \
 147                 USB_CTRL_MASK(SETUP, FNHW) |    \
 148                 USB_CTRL_MASK(SETUP, FNBO) |    \
 149                 USB_CTRL_MASK(SETUP, WABO))
 150
 151 #ifdef __LITTLE_ENDIAN
 152 #define ENDIAN_SETTINGS (                       \
 153                 USB_CTRL_MASK(SETUP, BABO) |    \
 154                 USB_CTRL_MASK(SETUP, FNHW))
 155 #else
 156 #define ENDIAN_SETTINGS (                       \
 157                 USB_CTRL_MASK(SETUP, FNHW) |    \
 158                 USB_CTRL_MASK(SETUP, FNBO) |    \
 159                 USB_CTRL_MASK(SETUP, WABO))
 160 #endif
 161
 162 struct id_to_type {
 163         u32 id;
 164         int type;
 165 };
 166
 167 static const struct id_to_type id_to_type_table[] = {
 168         { 0x33900000, BRCM_FAMILY_3390A0 },
 169         { 0x72500010, BRCM_FAMILY_7250B0 },
 170         { 0x72600000, BRCM_FAMILY_7260A0 },
 171         { 0x72550000, BRCM_FAMILY_7260A0 },
 172         { 0x72680000, BRCM_FAMILY_7271A0 },
 173         { 0x72710000, BRCM_FAMILY_7271A0 },
 174         { 0x73640000, BRCM_FAMILY_7364A0 },
 175         { 0x73660020, BRCM_FAMILY_7366C0 },
 176         { 0x07437100, BRCM_FAMILY_74371A0 },
 177         { 0x74390010, BRCM_FAMILY_7439B0 },
 178         { 0x74450030, BRCM_FAMILY_7445D0 },
 179         { 0x72780000, BRCM_FAMILY_7278A0 },
 180         { 0, BRCM_FAMILY_7271A0 }, /* default */
 181 };
 182
 183 static const u32
 184 usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = {
 185         /* 3390B0 */
 186         [BRCM_FAMILY_3390A0] = {
 187                 USB_CTRL_SETUP_SCB1_EN_MASK,
 188                 USB_CTRL_SETUP_SCB2_EN_MASK,
 189                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 190                 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
 191                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 192                 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
 193                 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
 194                 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
 195                 USB_CTRL_USB_PM_USB_PWRDN_MASK,
 196                 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
 197                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 198                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 199                 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
 200                 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
 201                 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
 202                 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
 203                 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
 204                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 205         },
 206         /* 7250b0 */
 207         [BRCM_FAMILY_7250B0] = {
 208                 USB_CTRL_SETUP_SCB1_EN_MASK,
 209                 USB_CTRL_SETUP_SCB2_EN_MASK,
 210                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 211                 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
 212                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 213                 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
 214                 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
 215                 USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
 216                 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
 217                 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
 218                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 219                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 220                 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
 221                 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
 222                 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
 223                 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
 224                 USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
 225                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 226         },
 227         /* 7271a0 */
 228         [BRCM_FAMILY_7271A0] = {
 229                 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */
 230                 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
 231                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 232                 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
 233                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 234                 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
 235                 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
 236                 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
 237                 USB_CTRL_USB_PM_USB_PWRDN_MASK,
 238                 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
 239                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 240                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 241                 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
 242                 USB_CTRL_USB_PM_SOFT_RESET_MASK,
 243                 USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK,
 244                 USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK,
 245                 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
 246                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 247         },
 248         /* 7364a0 */
 249         [BRCM_FAMILY_7364A0] = {
 250                 USB_CTRL_SETUP_SCB1_EN_MASK,
 251                 USB_CTRL_SETUP_SCB2_EN_MASK,
 252                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 253                 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
 254                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 255                 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
 256                 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
 257                 USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
 258                 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
 259                 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
 260                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 261                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 262                 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
 263                 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
 264                 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
 265                 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
 266                 USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
 267                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 268         },
 269         /* 7366c0 */
 270         [BRCM_FAMILY_7366C0] = {
 271                 USB_CTRL_SETUP_SCB1_EN_MASK,
 272                 USB_CTRL_SETUP_SCB2_EN_MASK,
 273                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 274                 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
 275                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 276                 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
 277                 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
 278                 USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK,
 279                 USB_CTRL_USB_PM_USB_PWRDN_MASK,
 280                 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
 281                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 282                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 283                 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
 284                 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
 285                 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
 286                 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
 287                 USB_CTRL_USB_PM_USB20_HC_RESETB_MASK,
 288                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 289         },
 290         /* 74371A0 */
 291         [BRCM_FAMILY_74371A0] = {
 292                 USB_CTRL_SETUP_SCB1_EN_MASK,
 293                 USB_CTRL_SETUP_SCB2_EN_MASK,
 294                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK,
 295                 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
 296                 0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */
 297                 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
 298                 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
 299                 0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */
 300                 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
 301                 USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK,
 302                 USB_CTRL_USB30_CTL1_USB3_IOC_MASK,
 303                 USB_CTRL_USB30_CTL1_USB3_IPP_MASK,
 304                 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
 305                 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
 306                 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
 307                 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
 308                 0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_MASK */
 309                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 310         },
 311         /* 7439B0 */
 312         [BRCM_FAMILY_7439B0] = {
 313                 USB_CTRL_SETUP_SCB1_EN_MASK,
 314                 USB_CTRL_SETUP_SCB2_EN_MASK,
 315                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 316                 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
 317                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 318                 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
 319                 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
 320                 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
 321                 USB_CTRL_USB_PM_USB_PWRDN_MASK,
 322                 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
 323                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 324                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 325                 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
 326                 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
 327                 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
 328                 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
 329                 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
 330                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 331         },
 332         /* 7445d0 */
 333         [BRCM_FAMILY_7445D0] = {
 334                 USB_CTRL_SETUP_SCB1_EN_MASK,
 335                 USB_CTRL_SETUP_SCB2_EN_MASK,
 336                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK,
 337                 0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */
 338                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 339                 USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK,
 340                 0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */
 341                 0, /* USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK */
 342                 0, /* USB_CTRL_USB_PM_USB_PWRDN_MASK */
 343                 USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK,
 344                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 345                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 346                 0, /* USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK */
 347                 0, /* USB_CTRL_USB_PM_SOFT_RESET_MASK */
 348                 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
 349                 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
 350                 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
 351                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 352         },
 353         /* 7260a0 */
 354         [BRCM_FAMILY_7260A0] = {
 355                 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */
 356                 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
 357                 USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK,
 358                 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
 359                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 360                 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
 361                 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
 362                 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
 363                 USB_CTRL_USB_PM_USB_PWRDN_MASK,
 364                 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
 365                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 366                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 367                 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
 368                 USB_CTRL_USB_PM_SOFT_RESET_MASK,
 369                 USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK,
 370                 USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK,
 371                 USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK,
 372                 ENDIAN_SETTINGS, /* USB_CTRL_SETUP ENDIAN bits */
 373         },
 374         /* 7278a0 */
 375         [BRCM_FAMILY_7278A0] = {
 376                 0, /* USB_CTRL_SETUP_SCB1_EN_MASK */
 377                 0, /* USB_CTRL_SETUP_SCB2_EN_MASK */
 378                 0, /*USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK */
 379                 USB_CTRL_SETUP_STRAP_IPP_SEL_MASK,
 380                 USB_CTRL_SETUP_OC3_DISABLE_MASK,
 381                 0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */
 382                 USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK,
 383                 USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK,
 384                 USB_CTRL_USB_PM_USB_PWRDN_MASK,
 385                 0, /* USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK */
 386                 0, /* USB_CTRL_USB30_CTL1_USB3_IOC_MASK */
 387                 0, /* USB_CTRL_USB30_CTL1_USB3_IPP_MASK */
 388                 USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK,
 389                 USB_CTRL_USB_PM_SOFT_RESET_MASK,
 390                 0, /* USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK */
 391                 0, /* USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK */
 392                 0, /* USB_CTRL_USB_PM_USB20_HC_RESETB_MASK */
 393                 0, /* USB_CTRL_SETUP ENDIAN bits */
 394         },
 395 };
 396
 397 static inline
 398 void usb_ctrl_unset_family(struct brcm_usb_init_params *params,
 399                            u32 reg_offset, u32 field)
 400 {
 401         u32 mask;
 402
 403         mask = params->usb_reg_bits_map[field];
 404         brcm_usb_ctrl_unset(params->regs[BRCM_REGS_CTRL] + reg_offset, mask);
 405 };
 406
 407 static inline
 408 void usb_ctrl_set_family(struct brcm_usb_init_params *params,
 409                          u32 reg_offset, u32 field)
 410 {
 411         u32 mask;
 412
 413         mask = params->usb_reg_bits_map[field];
 414         brcm_usb_ctrl_set(params->regs[BRCM_REGS_CTRL] + reg_offset, mask);
 415 };
 416
 417 static u32 brcmusb_usb_mdio_read(void __iomem *ctrl_base, u32 reg, int mode)
 418 {
 419         u32 data;
 420
 421         data = (reg << 16) | mode;
 422         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 423         data |= (1 << 24);
 424         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 425         data &= ~(1 << 24);
 426         /* wait for the 60MHz parallel to serial shifter */
 427         usleep_range(10, 20);
 428         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 429         /* wait for the 60MHz parallel to serial shifter */
 430         usleep_range(10, 20);
 431
 432         return brcm_usb_readl(USB_CTRL_REG(ctrl_base, MDIO2)) & 0xffff;
 433 }
 434
 435 static void brcmusb_usb_mdio_write(void __iomem *ctrl_base, u32 reg,
 436                                    u32 val, int mode)
 437 {
 438         u32 data;
 439
 440         data = (reg << 16) | val | mode;
 441         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 442         data |= (1 << 25);
 443         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 444         data &= ~(1 << 25);
 445
 446         /* wait for the 60MHz parallel to serial shifter */
 447         usleep_range(10, 20);
 448         brcm_usb_writel(data, USB_CTRL_REG(ctrl_base, MDIO));
 449         /* wait for the 60MHz parallel to serial shifter */
 450         usleep_range(10, 20);
 451 }
 452
 453 static void brcmusb_usb_phy_ldo_fix(void __iomem *ctrl_base)
 454 {
 455         /* first disable FSM but also leave it that way */
 456         /* to allow normal suspend/resume */
 457         USB_CTRL_UNSET(ctrl_base, UTMI_CTL_1, POWER_UP_FSM_EN);
 458         USB_CTRL_UNSET(ctrl_base, UTMI_CTL_1, POWER_UP_FSM_EN_P1);
 459
 460         /* reset USB 2.0 PLL */
 461         USB_CTRL_UNSET(ctrl_base, PLL_CTL, PLL_RESETB);
 462         /* PLL reset period */
 463         udelay(1);
 464         USB_CTRL_SET(ctrl_base, PLL_CTL, PLL_RESETB);
 465         /* Give PLL enough time to lock */
 466         usleep_range(1000, 2000);
 467 }
 468
 469 static void brcmusb_usb2_eye_fix(void __iomem *ctrl_base)
 470 {
 471         /* Increase USB 2.0 TX level to meet spec requirement */
 472         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x80a0, MDIO_USB2);
 473         brcmusb_usb_mdio_write(ctrl_base, 0x0a, 0xc6a0, MDIO_USB2);
 474 }
 475
 476 static void brcmusb_usb3_pll_fix(void __iomem *ctrl_base)
 477 {
 478         /* Set correct window for PLL lock detect */
 479         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
 480         brcmusb_usb_mdio_write(ctrl_base, 0x07, 0x1503, MDIO_USB3);
 481 }
 482
 483 static void brcmusb_usb3_enable_pipe_reset(void __iomem *ctrl_base)
 484 {
 485         u32 val;
 486
 487         /* Re-enable USB 3.0 pipe reset */
 488         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
 489         val = brcmusb_usb_mdio_read(ctrl_base, 0x0f, MDIO_USB3) | 0x200;
 490         brcmusb_usb_mdio_write(ctrl_base, 0x0f, val, MDIO_USB3);
 491 }
 492
 493 static void brcmusb_usb3_enable_sigdet(void __iomem *ctrl_base)
 494 {
 495         u32 val, ofs;
 496         int ii;
 497
 498         ofs = 0;
 499         for (ii = 0; ii < PHY_PORTS; ++ii) {
 500                 /* Set correct default for sigdet */
 501                 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8080 + ofs),
 502                                        MDIO_USB3);
 503                 val = brcmusb_usb_mdio_read(ctrl_base, 0x05, MDIO_USB3);
 504                 val = (val & ~0x800f) | 0x800d;
 505                 brcmusb_usb_mdio_write(ctrl_base, 0x05, val, MDIO_USB3);
 506                 ofs = PHY_PORT_SELECT_1;
 507         }
 508 }
 509
 510 static void brcmusb_usb3_enable_skip_align(void __iomem *ctrl_base)
 511 {
 512         u32 val, ofs;
 513         int ii;
 514
 515         ofs = 0;
 516         for (ii = 0; ii < PHY_PORTS; ++ii) {
 517                 /* Set correct default for SKIP align */
 518                 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8060 + ofs),
 519                                        MDIO_USB3);
 520                 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0x200;
 521                 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
 522                 ofs = PHY_PORT_SELECT_1;
 523         }
 524 }
 525
 526 static void brcmusb_usb3_unfreeze_aeq(void __iomem *ctrl_base)
 527 {
 528         u32 val, ofs;
 529         int ii;
 530
 531         ofs = 0;
 532         for (ii = 0; ii < PHY_PORTS; ++ii) {
 533                 /* Let EQ freeze after TSEQ */
 534                 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x80e0 + ofs),
 535                                        MDIO_USB3);
 536                 val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3);
 537                 val &= ~0x0008;
 538                 brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
 539                 ofs = PHY_PORT_SELECT_1;
 540         }
 541 }
 542
 543 static void brcmusb_usb3_pll_54mhz(struct brcm_usb_init_params *params)
 544 {
 545         u32 ofs;
 546         int ii;
 547         void __iomem *ctrl_base = params->regs[BRCM_REGS_CTRL];
 548
 549         /*
 550          * On newer B53 based SoC's, the reference clock for the
 551          * 3.0 PLL has been changed from 50MHz to 54MHz so the
 552          * PLL needs to be reprogrammed.
 553          * See SWLINUX-4006.
 554          *
 555          * On the 7364C0, the reference clock for the
 556          * 3.0 PLL has been changed from 50MHz to 54MHz to
 557          * work around a MOCA issue.
 558          * See SWLINUX-4169.
 559          */
 560         switch (params->selected_family) {
 561         case BRCM_FAMILY_3390A0:
 562         case BRCM_FAMILY_7250B0:
 563         case BRCM_FAMILY_7366C0:
 564         case BRCM_FAMILY_74371A0:
 565         case BRCM_FAMILY_7439B0:
 566         case BRCM_FAMILY_7445D0:
 567         case BRCM_FAMILY_7260A0:
 568                 return;
 569         case BRCM_FAMILY_7364A0:
 570                 if (BRCM_REV(params->family_id) < 0x20)
 571                         return;
 572                 break;
 573         }
 574
 575         /* set USB 3.0 PLL to accept 54Mhz reference clock */
 576         USB_CTRL_UNSET(ctrl_base, USB30_CTL1, PHY3_PLL_SEQ_START);
 577
 578         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8000, MDIO_USB3);
 579         brcmusb_usb_mdio_write(ctrl_base, 0x10, 0x5784, MDIO_USB3);
 580         brcmusb_usb_mdio_write(ctrl_base, 0x11, 0x01d0, MDIO_USB3);
 581         brcmusb_usb_mdio_write(ctrl_base, 0x12, 0x1DE8, MDIO_USB3);
 582         brcmusb_usb_mdio_write(ctrl_base, 0x13, 0xAA80, MDIO_USB3);
 583         brcmusb_usb_mdio_write(ctrl_base, 0x14, 0x8826, MDIO_USB3);
 584         brcmusb_usb_mdio_write(ctrl_base, 0x15, 0x0044, MDIO_USB3);
 585         brcmusb_usb_mdio_write(ctrl_base, 0x16, 0x8000, MDIO_USB3);
 586         brcmusb_usb_mdio_write(ctrl_base, 0x17, 0x0851, MDIO_USB3);
 587         brcmusb_usb_mdio_write(ctrl_base, 0x18, 0x0000, MDIO_USB3);
 588
 589         /* both ports */
 590         ofs = 0;
 591         for (ii = 0; ii < PHY_PORTS; ++ii) {
 592                 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8040 + ofs),
 593                                        MDIO_USB3);
 594                 brcmusb_usb_mdio_write(ctrl_base, 0x03, 0x0090, MDIO_USB3);
 595                 brcmusb_usb_mdio_write(ctrl_base, 0x04, 0x0134, MDIO_USB3);
 596                 brcmusb_usb_mdio_write(ctrl_base, 0x1f, (0x8020 + ofs),
 597                                        MDIO_USB3);
 598                 brcmusb_usb_mdio_write(ctrl_base, 0x01, 0x00e2, MDIO_USB3);
 599                 ofs = PHY_PORT_SELECT_1;
 600         }
 601
 602         /* restart PLL sequence */
 603         USB_CTRL_SET(ctrl_base, USB30_CTL1, PHY3_PLL_SEQ_START);
 604         /* Give PLL enough time to lock */
 605         usleep_range(1000, 2000);
 606 }
 607
 608 static void brcmusb_usb3_ssc_enable(void __iomem *ctrl_base)
 609 {
 610         u32 val;
 611
 612         /* Enable USB 3.0 TX spread spectrum */
 613         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x8040, MDIO_USB3);
 614         val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf;
 615         brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
 616
 617         /* Currently, USB 3.0 SSC is enabled via port 0 MDIO registers,
 618          * which should have been adequate. However, due to a bug in the
 619          * USB 3.0 PHY, it must be enabled via both ports (HWUSB3DVT-26).
 620          */
 621         brcmusb_usb_mdio_write(ctrl_base, 0x1f, 0x9040, MDIO_USB3);
 622         val = brcmusb_usb_mdio_read(ctrl_base, 0x01, MDIO_USB3) | 0xf;
 623         brcmusb_usb_mdio_write(ctrl_base, 0x01, val, MDIO_USB3);
 624 }
 625
 626 static void brcmusb_usb3_phy_workarounds(struct brcm_usb_init_params *params)
 627 {
 628         void __iomem *ctrl_base = params->regs[BRCM_REGS_CTRL];
 629
 630         brcmusb_usb3_pll_fix(ctrl_base);
 631         brcmusb_usb3_pll_54mhz(params);
 632         brcmusb_usb3_ssc_enable(ctrl_base);
 633         brcmusb_usb3_enable_pipe_reset(ctrl_base);
 634         brcmusb_usb3_enable_sigdet(ctrl_base);
 635         brcmusb_usb3_enable_skip_align(ctrl_base);
 636         brcmusb_usb3_unfreeze_aeq(ctrl_base);
 637 }
 638
 639 static void brcmusb_memc_fix(struct brcm_usb_init_params *params)
 640 {
 641         u32 prid;
 642
 643         if (params->selected_family != BRCM_FAMILY_7445D0)
 644                 return;
 645         /*
 646          * This is a workaround for HW7445-1869 where a DMA write ends up
 647          * doing a read pre-fetch after the end of the DMA buffer. This
 648          * causes a problem when the DMA buffer is at the end of physical
 649          * memory, causing the pre-fetch read to access non-existent memory,
 650          * and the chip bondout has MEMC2 disabled. When the pre-fetch read
 651          * tries to use the disabled MEMC2, it hangs the bus. The workaround
 652          * is to disable MEMC2 access in the usb controller which avoids
 653          * the hang.
 654          */
 655
 656         prid = params->product_id & 0xfffff000;
 657         switch (prid) {
 658         case 0x72520000:
 659         case 0x74480000:
 660         case 0x74490000:
 661         case 0x07252000:
 662         case 0x07448000:
 663         case 0x07449000:
 664                 USB_CTRL_UNSET_FAMILY(params, SETUP, SCB2_EN);
 665         }
 666 }
 667
 668 static void brcmusb_usb3_otp_fix(struct brcm_usb_init_params *params)
 669 {
 670         void __iomem *xhci_ec_base = params->regs[BRCM_REGS_XHCI_EC];
 671         u32 val;
 672
 673         if (params->family_id != 0x74371000 || !xhci_ec_base)
 674                 return;
 675         brcm_usb_writel(0xa20c, USB_XHCI_EC_REG(xhci_ec_base, IRAADR));
 676         val = brcm_usb_readl(USB_XHCI_EC_REG(xhci_ec_base, IRADAT));
 677
 678         /* set cfg_pick_ss_lock */
 679         val |= (1 << 27);
 680         brcm_usb_writel(val, USB_XHCI_EC_REG(xhci_ec_base, IRADAT));
 681
 682         /* Reset USB 3.0 PHY for workaround to take effect */
 683         USB_CTRL_UNSET(params->regs[BRCM_REGS_CTRL], USB30_CTL1, PHY3_RESETB);
 684         USB_CTRL_SET(params->regs[BRCM_REGS_CTRL], USB30_CTL1, PHY3_RESETB);
 685 }
 686
 687 static void brcmusb_xhci_soft_reset(struct brcm_usb_init_params *params,
 688                                     int on_off)
 689 {
 690         /* Assert reset */
 691         if (on_off) {
 692                 if (USB_CTRL_MASK_FAMILY(params, USB_PM, XHC_SOFT_RESETB))
 693                         USB_CTRL_UNSET_FAMILY(params, USB_PM, XHC_SOFT_RESETB);
 694                 else
 695                         USB_CTRL_UNSET_FAMILY(params,
 696                                               USB30_CTL1, XHC_SOFT_RESETB);
 697         } else { /* De-assert reset */
 698                 if (USB_CTRL_MASK_FAMILY(params, USB_PM, XHC_SOFT_RESETB))
 699                         USB_CTRL_SET_FAMILY(params, USB_PM, XHC_SOFT_RESETB);
 700                 else
 701                         USB_CTRL_SET_FAMILY(params, USB30_CTL1,
 702                                             XHC_SOFT_RESETB);
 703         }
 704 }
 705
 706 /*
 707  * Return the best map table family. The order is:
 708  *   - exact match of chip and major rev
 709  *   - exact match of chip and closest older major rev
 710  *   - default chip/rev.
 711  * NOTE: The minor rev is always ignored.
 712  */
 713 static enum brcm_family_type get_family_type(
 714         struct brcm_usb_init_params *params)
 715 {
 716         int last_type = -1;
 717         u32 last_family = 0;
 718         u32 family_no_major;
 719         unsigned int x;
 720         u32 family;
 721
 722         family = params->family_id & 0xfffffff0;
 723         family_no_major = params->family_id & 0xffffff00;
 724         for (x = 0; id_to_type_table[x].id; x++) {
 725                 if (family == id_to_type_table[x].id)
 726                         return id_to_type_table[x].type;
 727                 if (family_no_major == (id_to_type_table[x].id & 0xffffff00))
 728                         if (family > id_to_type_table[x].id &&
 729                             last_family < id_to_type_table[x].id) {
 730                                 last_family = id_to_type_table[x].id;
 731                                 last_type = id_to_type_table[x].type;
 732                         }
 733         }
 734
 735         /* If no match, return the default family */
 736         if (last_type == -1)
 737                 return id_to_type_table[x].type;
 738         return last_type;
 739 }
 740
 741 static void usb_init_ipp(struct brcm_usb_init_params *params)
 742 {
 743         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 744         u32 reg;
 745         u32 orig_reg;
 746
 747         /* Starting with the 7445d0, there are no longer separate 3.0
 748          * versions of IOC and IPP.
 749          */
 750         if (USB_CTRL_MASK_FAMILY(params, USB30_CTL1, USB3_IOC)) {
 751                 if (params->ioc)
 752                         USB_CTRL_SET_FAMILY(params, USB30_CTL1, USB3_IOC);
 753                 if (params->ipp == 1)
 754                         USB_CTRL_SET_FAMILY(params, USB30_CTL1, USB3_IPP);
 755         }
 756
 757         reg = brcm_usb_readl(USB_CTRL_REG(ctrl, SETUP));
 758         orig_reg = reg;
 759         if (USB_CTRL_MASK_FAMILY(params, SETUP, STRAP_CC_DRD_MODE_ENABLE_SEL))
 760                 /* Never use the strap, it's going away. */
 761                 reg &= ~(USB_CTRL_MASK_FAMILY(params,
 762                                               SETUP,
 763                                               STRAP_CC_DRD_MODE_ENABLE_SEL));
 764         if (USB_CTRL_MASK_FAMILY(params, SETUP, STRAP_IPP_SEL))
 765                 /* override ipp strap pin (if it exits) */
 766                 if (params->ipp != 2)
 767                         reg &= ~(USB_CTRL_MASK_FAMILY(params, SETUP,
 768                                                       STRAP_IPP_SEL));
 769
 770         /* Override the default OC and PP polarity */
 771         reg &= ~(USB_CTRL_MASK(SETUP, IPP) | USB_CTRL_MASK(SETUP, IOC));
 772         if (params->ioc)
 773                 reg |= USB_CTRL_MASK(SETUP, IOC);
 774         if (params->ipp == 1)
 775                 reg |= USB_CTRL_MASK(SETUP, IPP);
 776         brcm_usb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
 777
 778         /*
 779          * If we're changing IPP, make sure power is off long enough
 780          * to turn off any connected devices.
 781          */
 782         if ((reg ^ orig_reg) & USB_CTRL_MASK(SETUP, IPP))
 783                 msleep(50);
 784 }
 785
 786 static void usb_wake_enable(struct brcm_usb_init_params *params,
 787                           bool enable)
 788 {
 789         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 790
 791         if (enable)
 792                 USB_CTRL_SET(ctrl, USB_PM, RMTWKUP_EN);
 793         else
 794                 USB_CTRL_UNSET(ctrl, USB_PM, RMTWKUP_EN);
 795 }
 796
 797 static void usb_init_common(struct brcm_usb_init_params *params)
 798 {
 799         u32 reg;
 800         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 801
 802         /* Clear any pending wake conditions */
 803         usb_wake_enable(params, false);
 804         reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_PM_STATUS));
 805         brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_PM_STATUS));
 806
 807         /* Take USB out of power down */
 808         if (USB_CTRL_MASK_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN)) {
 809                 USB_CTRL_UNSET_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN);
 810                 /* 1 millisecond - for USB clocks to settle down */
 811                 usleep_range(1000, 2000);
 812         }
 813
 814         if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB_PWRDN)) {
 815                 USB_CTRL_UNSET_FAMILY(params, USB_PM, USB_PWRDN);
 816                 /* 1 millisecond - for USB clocks to settle down */
 817                 usleep_range(1000, 2000);
 818         }
 819
 820         if (params->selected_family != BRCM_FAMILY_74371A0 &&
 821             (BRCM_ID(params->family_id) != 0x7364))
 822                 /*
 823                  * HW7439-637: 7439a0 and its derivatives do not have large
 824                  * enough descriptor storage for this.
 825                  */
 826                 USB_CTRL_SET_FAMILY(params, SETUP, SS_EHCI64BIT_EN);
 827
 828         /* Block auto PLL suspend by USB2 PHY (Sasi) */
 829         USB_CTRL_SET(ctrl, PLL_CTL, PLL_SUSPEND_EN);
 830
 831         reg = brcm_usb_readl(USB_CTRL_REG(ctrl, SETUP));
 832         if (params->selected_family == BRCM_FAMILY_7364A0)
 833                 /* Suppress overcurrent indication from USB30 ports for A0 */
 834                 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, OC3_DISABLE);
 835
 836         brcmusb_usb_phy_ldo_fix(ctrl);
 837         brcmusb_usb2_eye_fix(ctrl);
 838
 839         /*
 840          * Make sure the the second and third memory controller
 841          * interfaces are enabled if they exist.
 842          */
 843         if (USB_CTRL_MASK_FAMILY(params, SETUP, SCB1_EN))
 844                 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, SCB1_EN);
 845         if (USB_CTRL_MASK_FAMILY(params, SETUP, SCB2_EN))
 846                 reg |= USB_CTRL_MASK_FAMILY(params, SETUP, SCB2_EN);
 847         brcm_usb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
 848
 849         brcmusb_memc_fix(params);
 850
 851         if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) {
 852                 reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
 853                 reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1,
 854                                         PORT_MODE);
 855                 reg |= params->mode;
 856                 brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
 857         }
 858         if (USB_CTRL_MASK_FAMILY(params, USB_PM, BDC_SOFT_RESETB)) {
 859                 switch (params->mode) {
 860                 case USB_CTLR_MODE_HOST:
 861                         USB_CTRL_UNSET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
 862                         break;
 863                 default:
 864                         USB_CTRL_UNSET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
 865                         USB_CTRL_SET_FAMILY(params, USB_PM, BDC_SOFT_RESETB);
 866                 break;
 867                 }
 868         }
 869         if (USB_CTRL_MASK_FAMILY(params, SETUP, CC_DRD_MODE_ENABLE)) {
 870                 if (params->mode == USB_CTLR_MODE_TYPEC_PD)
 871                         USB_CTRL_SET_FAMILY(params, SETUP, CC_DRD_MODE_ENABLE);
 872                 else
 873                         USB_CTRL_UNSET_FAMILY(params, SETUP,
 874                                               CC_DRD_MODE_ENABLE);
 875         }
 876 }
 877
 878 static void usb_init_eohci(struct brcm_usb_init_params *params)
 879 {
 880         u32 reg;
 881         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 882
 883         if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB20_HC_RESETB))
 884                 USB_CTRL_SET_FAMILY(params, USB_PM, USB20_HC_RESETB);
 885
 886         if (params->selected_family == BRCM_FAMILY_7366C0)
 887                 /*
 888                  * Don't enable this so the memory controller doesn't read
 889                  * into memory holes. NOTE: This bit is low true on 7366C0.
 890                  */
 891                 USB_CTRL_SET(ctrl, EBRIDGE, ESTOP_SCB_REQ);
 892
 893         /* Setup the endian bits */
 894         reg = brcm_usb_readl(USB_CTRL_REG(ctrl, SETUP));
 895         reg &= ~USB_CTRL_SETUP_ENDIAN_BITS;
 896         reg |= USB_CTRL_MASK_FAMILY(params, SETUP, ENDIAN);
 897         brcm_usb_writel(reg, USB_CTRL_REG(ctrl, SETUP));
 898
 899         if (params->selected_family == BRCM_FAMILY_7271A0)
 900                 /* Enable LS keep alive fix for certain keyboards */
 901                 USB_CTRL_SET(ctrl, OBRIDGE, LS_KEEP_ALIVE);
 902
 903         if (params->family_id == 0x72550000) {
 904                 /*
 905                  * Make the burst size 512 bytes to fix a hardware bug
 906                  * on the 7255a0. See HW7255-24.
 907                  */
 908                 reg = brcm_usb_readl(USB_CTRL_REG(ctrl, EBRIDGE));
 909                 reg &= ~USB_CTRL_MASK(EBRIDGE, EBR_SCB_SIZE);
 910                 reg |= 0x800;
 911                 brcm_usb_writel(reg, USB_CTRL_REG(ctrl, EBRIDGE));
 912         }
 913 }
 914
 915 static void usb_init_xhci(struct brcm_usb_init_params *params)
 916 {
 917         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 918
 919         USB_CTRL_UNSET(ctrl, USB30_PCTL, PHY3_IDDQ_OVERRIDE);
 920         /* 1 millisecond - for USB clocks to settle down */
 921         usleep_range(1000, 2000);
 922
 923         if (BRCM_ID(params->family_id) == 0x7366) {
 924                 /*
 925                  * The PHY3_SOFT_RESETB bits default to the wrong state.
 926                  */
 927                 USB_CTRL_SET(ctrl, USB30_PCTL, PHY3_SOFT_RESETB);
 928                 USB_CTRL_SET(ctrl, USB30_PCTL, PHY3_SOFT_RESETB_P1);
 929         }
 930
 931         /*
 932          * Kick start USB3 PHY
 933          * Make sure it's low to insure a rising edge.
 934          */
 935         USB_CTRL_UNSET(ctrl, USB30_CTL1, PHY3_PLL_SEQ_START);
 936         USB_CTRL_SET(ctrl, USB30_CTL1, PHY3_PLL_SEQ_START);
 937
 938         brcmusb_usb3_phy_workarounds(params);
 939         brcmusb_xhci_soft_reset(params, 0);
 940         brcmusb_usb3_otp_fix(params);
 941 }
 942
 943 static void usb_uninit_common(struct brcm_usb_init_params *params)
 944 {
 945         if (USB_CTRL_MASK_FAMILY(params, USB_PM, USB_PWRDN))
 946                 USB_CTRL_SET_FAMILY(params, USB_PM, USB_PWRDN);
 947
 948         if (USB_CTRL_MASK_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN))
 949                 USB_CTRL_SET_FAMILY(params, PLL_CTL, PLL_IDDQ_PWRDN);
 950         if (params->wake_enabled)
 951                 usb_wake_enable(params, true);
 952 }
 953
 954 static void usb_uninit_eohci(struct brcm_usb_init_params *params)
 955 {
 956 }
 957
 958 static void usb_uninit_xhci(struct brcm_usb_init_params *params)
 959 {
 960         brcmusb_xhci_soft_reset(params, 1);
 961         USB_CTRL_SET(params->regs[BRCM_REGS_CTRL], USB30_PCTL,
 962                      PHY3_IDDQ_OVERRIDE);
 963 }
 964
 965 static int usb_get_dual_select(struct brcm_usb_init_params *params)
 966 {
 967         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 968         u32 reg = 0;
 969
 970         pr_debug("%s\n", __func__);
 971         if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) {
 972                 reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
 973                 reg &= USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1,
 974                                         PORT_MODE);
 975         }
 976         return reg;
 977 }
 978
 979 static void usb_set_dual_select(struct brcm_usb_init_params *params, int mode)
 980 {
 981         void __iomem *ctrl = params->regs[BRCM_REGS_CTRL];
 982         u32 reg;
 983
 984         pr_debug("%s\n", __func__);
 985
 986         if (USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1, PORT_MODE)) {
 987                 reg = brcm_usb_readl(USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
 988                 reg &= ~USB_CTRL_MASK_FAMILY(params, USB_DEVICE_CTL1,
 989                                         PORT_MODE);
 990                 reg |= mode;
 991                 brcm_usb_writel(reg, USB_CTRL_REG(ctrl, USB_DEVICE_CTL1));
 992         }
 993 }
 994
 995 static const struct brcm_usb_init_ops bcm7445_ops = {
 996         .init_ipp = usb_init_ipp,
 997         .init_common = usb_init_common,
 998         .init_eohci = usb_init_eohci,
 999         .init_xhci = usb_init_xhci,
1000         .uninit_common = usb_uninit_common,
1001         .uninit_eohci = usb_uninit_eohci,
1002         .uninit_xhci = usb_uninit_xhci,
1003         .get_dual_select = usb_get_dual_select,
1004         .set_dual_select = usb_set_dual_select,
1005 };
1006
1007 void brcm_usb_dvr_init_7445(struct brcm_usb_init_params *params)
1008 {
1009         int fam;
1010
1011         pr_debug("%s\n", __func__);
1012
1013         fam = get_family_type(params);
1014         params->selected_family = fam;
1015         params->usb_reg_bits_map =
1016                 &usb_reg_bits_map_table[fam][0];
1017         params->family_name = family_names[fam];
1018         params->ops = &bcm7445_ops;
1019 }