drivers/phy/amlogic/phy-meson8b-usb2.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Meson8, Meson8b and GXBB USB2 PHY driver
   4  *
   5  * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/io.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/property.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/usb/of.h>
  19
  20 #define REG_CONFIG                                      0x00
  21         #define REG_CONFIG_CLK_EN                       BIT(0)
  22         #define REG_CONFIG_CLK_SEL_MASK                 GENMASK(3, 1)
  23         #define REG_CONFIG_CLK_DIV_MASK                 GENMASK(10, 4)
  24         #define REG_CONFIG_CLK_32k_ALTSEL               BIT(15)
  25         #define REG_CONFIG_TEST_TRIG                    BIT(31)
  26
  27 #define REG_CTRL                                        0x04
  28         #define REG_CTRL_SOFT_PRST                      BIT(0)
  29         #define REG_CTRL_SOFT_HRESET                    BIT(1)
  30         #define REG_CTRL_SS_SCALEDOWN_MODE_MASK         GENMASK(3, 2)
  31         #define REG_CTRL_CLK_DET_RST                    BIT(4)
  32         #define REG_CTRL_INTR_SEL                       BIT(5)
  33         #define REG_CTRL_CLK_DETECTED                   BIT(8)
  34         #define REG_CTRL_SOF_SENT_RCVD_TGL              BIT(9)
  35         #define REG_CTRL_SOF_TOGGLE_OUT                 BIT(10)
  36         #define REG_CTRL_POWER_ON_RESET                 BIT(15)
  37         #define REG_CTRL_SLEEPM                         BIT(16)
  38         #define REG_CTRL_TX_BITSTUFF_ENN_H              BIT(17)
  39         #define REG_CTRL_TX_BITSTUFF_ENN                BIT(18)
  40         #define REG_CTRL_COMMON_ON                      BIT(19)
  41         #define REG_CTRL_REF_CLK_SEL_MASK               GENMASK(21, 20)
  42         #define REG_CTRL_REF_CLK_SEL_SHIFT              20
  43         #define REG_CTRL_FSEL_MASK                      GENMASK(24, 22)
  44         #define REG_CTRL_FSEL_SHIFT                     22
  45         #define REG_CTRL_PORT_RESET                     BIT(25)
  46         #define REG_CTRL_THREAD_ID_MASK                 GENMASK(31, 26)
  47
  48 #define REG_ENDP_INTR                                   0x08
  49
  50 /* bits [31:26], [24:21] and [15:3] seem to be read-only */
  51 #define REG_ADP_BC                                      0x0c
  52         #define REG_ADP_BC_VBUS_VLD_EXT_SEL             BIT(0)
  53         #define REG_ADP_BC_VBUS_VLD_EXT                 BIT(1)
  54         #define REG_ADP_BC_OTG_DISABLE                  BIT(2)
  55         #define REG_ADP_BC_ID_PULLUP                    BIT(3)
  56         #define REG_ADP_BC_DRV_VBUS                     BIT(4)
  57         #define REG_ADP_BC_ADP_PRB_EN                   BIT(5)
  58         #define REG_ADP_BC_ADP_DISCHARGE                BIT(6)
  59         #define REG_ADP_BC_ADP_CHARGE                   BIT(7)
  60         #define REG_ADP_BC_SESS_END                     BIT(8)
  61         #define REG_ADP_BC_DEVICE_SESS_VLD              BIT(9)
  62         #define REG_ADP_BC_B_VALID                      BIT(10)
  63         #define REG_ADP_BC_A_VALID                      BIT(11)
  64         #define REG_ADP_BC_ID_DIG                       BIT(12)
  65         #define REG_ADP_BC_VBUS_VALID                   BIT(13)
  66         #define REG_ADP_BC_ADP_PROBE                    BIT(14)
  67         #define REG_ADP_BC_ADP_SENSE                    BIT(15)
  68         #define REG_ADP_BC_ACA_ENABLE                   BIT(16)
  69         #define REG_ADP_BC_DCD_ENABLE                   BIT(17)
  70         #define REG_ADP_BC_VDAT_DET_EN_B                BIT(18)
  71         #define REG_ADP_BC_VDAT_SRC_EN_B                BIT(19)
  72         #define REG_ADP_BC_CHARGE_SEL                   BIT(20)
  73         #define REG_ADP_BC_CHARGE_DETECT                BIT(21)
  74         #define REG_ADP_BC_ACA_PIN_RANGE_C              BIT(22)
  75         #define REG_ADP_BC_ACA_PIN_RANGE_B              BIT(23)
  76         #define REG_ADP_BC_ACA_PIN_RANGE_A              BIT(24)
  77         #define REG_ADP_BC_ACA_PIN_GND                  BIT(25)
  78         #define REG_ADP_BC_ACA_PIN_FLOAT                BIT(26)
  79
  80 #define REG_DBG_UART                                    0x10
  81
  82 #define REG_TEST                                        0x14
  83         #define REG_TEST_DATA_IN_MASK                   GENMASK(3, 0)
  84         #define REG_TEST_EN_MASK                        GENMASK(7, 4)
  85         #define REG_TEST_ADDR_MASK                      GENMASK(11, 8)
  86         #define REG_TEST_DATA_OUT_SEL                   BIT(12)
  87         #define REG_TEST_CLK                            BIT(13)
  88         #define REG_TEST_VA_TEST_EN_B_MASK              GENMASK(15, 14)
  89         #define REG_TEST_DATA_OUT_MASK                  GENMASK(19, 16)
  90         #define REG_TEST_DISABLE_ID_PULLUP              BIT(20)
  91
  92 #define REG_TUNE                                        0x18
  93         #define REG_TUNE_TX_RES_TUNE_MASK               GENMASK(1, 0)
  94         #define REG_TUNE_TX_HSXV_TUNE_MASK              GENMASK(3, 2)
  95         #define REG_TUNE_TX_VREF_TUNE_MASK              GENMASK(7, 4)
  96         #define REG_TUNE_TX_RISE_TUNE_MASK              GENMASK(9, 8)
  97         #define REG_TUNE_TX_PREEMP_PULSE_TUNE           BIT(10)
  98         #define REG_TUNE_TX_PREEMP_AMP_TUNE_MASK        GENMASK(12, 11)
  99         #define REG_TUNE_TX_FSLS_TUNE_MASK              GENMASK(16, 13)
 100         #define REG_TUNE_SQRX_TUNE_MASK                 GENMASK(19, 17)
 101         #define REG_TUNE_OTG_TUNE                       GENMASK(22, 20)
 102         #define REG_TUNE_COMP_DIS_TUNE                  GENMASK(25, 23)
 103         #define REG_TUNE_HOST_DM_PULLDOWN               BIT(26)
 104         #define REG_TUNE_HOST_DP_PULLDOWN               BIT(27)
 105
 106 #define RESET_COMPLETE_TIME                             500
 107 #define ACA_ENABLE_COMPLETE_TIME                        50
 108
 109 struct phy_meson8b_usb2_match_data {
 110         bool                    host_enable_aca;
 111 };
 112
 113 struct phy_meson8b_usb2_priv {
 114         struct regmap                                   *regmap;
 115         enum usb_dr_mode                                dr_mode;
 116         struct clk                                      *clk_usb_general;
 117         struct clk                                      *clk_usb;
 118         struct reset_control                            *reset;
 119         const struct phy_meson8b_usb2_match_data        *match;
 120 };
 121
 122 static const struct regmap_config phy_meson8b_usb2_regmap_conf = {
 123         .reg_bits = 8,
 124         .val_bits = 32,
 125         .reg_stride = 4,
 126         .max_register = REG_TUNE,
 127 };
 128
 129 static int phy_meson8b_usb2_power_on(struct phy *phy)
 130 {
 131         struct phy_meson8b_usb2_priv *priv = phy_get_drvdata(phy);
 132         u32 reg;
 133         int ret;
 134
 135         if (!IS_ERR_OR_NULL(priv->reset)) {
 136                 ret = reset_control_reset(priv->reset);
 137                 if (ret) {
 138                         dev_err(&phy->dev, "Failed to trigger USB reset\n");
 139                         return ret;
 140                 }
 141         }
 142
 143         ret = clk_prepare_enable(priv->clk_usb_general);
 144         if (ret) {
 145                 dev_err(&phy->dev, "Failed to enable USB general clock\n");
 146                 return ret;
 147         }
 148
 149         ret = clk_prepare_enable(priv->clk_usb);
 150         if (ret) {
 151                 dev_err(&phy->dev, "Failed to enable USB DDR clock\n");
 152                 clk_disable_unprepare(priv->clk_usb_general);
 153                 return ret;
 154         }
 155
 156         regmap_update_bits(priv->regmap, REG_CONFIG, REG_CONFIG_CLK_32k_ALTSEL,
 157                            REG_CONFIG_CLK_32k_ALTSEL);
 158
 159         regmap_update_bits(priv->regmap, REG_CTRL, REG_CTRL_REF_CLK_SEL_MASK,
 160                            0x2 << REG_CTRL_REF_CLK_SEL_SHIFT);
 161
 162         regmap_update_bits(priv->regmap, REG_CTRL, REG_CTRL_FSEL_MASK,
 163                            0x5 << REG_CTRL_FSEL_SHIFT);
 164
 165         /* reset the PHY */
 166         regmap_update_bits(priv->regmap, REG_CTRL, REG_CTRL_POWER_ON_RESET,
 167                            REG_CTRL_POWER_ON_RESET);
 168         udelay(RESET_COMPLETE_TIME);
 169         regmap_update_bits(priv->regmap, REG_CTRL, REG_CTRL_POWER_ON_RESET, 0);
 170         udelay(RESET_COMPLETE_TIME);
 171
 172         regmap_update_bits(priv->regmap, REG_CTRL, REG_CTRL_SOF_TOGGLE_OUT,
 173                            REG_CTRL_SOF_TOGGLE_OUT);
 174
 175         if (priv->dr_mode == USB_DR_MODE_HOST &&
 176             priv->match->host_enable_aca) {
 177                 regmap_update_bits(priv->regmap, REG_ADP_BC,
 178                                    REG_ADP_BC_ACA_ENABLE,
 179                                    REG_ADP_BC_ACA_ENABLE);
 180
 181                 udelay(ACA_ENABLE_COMPLETE_TIME);
 182
 183                 regmap_read(priv->regmap, REG_ADP_BC, &reg);
 184                 if (reg & REG_ADP_BC_ACA_PIN_FLOAT) {
 185                         dev_warn(&phy->dev, "USB ID detect failed!\n");
 186                         clk_disable_unprepare(priv->clk_usb);
 187                         clk_disable_unprepare(priv->clk_usb_general);
 188                         return -EINVAL;
 189                 }
 190         }
 191
 192         return 0;
 193 }
 194
 195 static int phy_meson8b_usb2_power_off(struct phy *phy)
 196 {
 197         struct phy_meson8b_usb2_priv *priv = phy_get_drvdata(phy);
 198
 199         clk_disable_unprepare(priv->clk_usb);
 200         clk_disable_unprepare(priv->clk_usb_general);
 201
 202         return 0;
 203 }
 204
 205 static const struct phy_ops phy_meson8b_usb2_ops = {
 206         .power_on       = phy_meson8b_usb2_power_on,
 207         .power_off      = phy_meson8b_usb2_power_off,
 208         .owner          = THIS_MODULE,
 209 };
 210
 211 static int phy_meson8b_usb2_probe(struct platform_device *pdev)
 212 {
 213         struct phy_meson8b_usb2_priv *priv;
 214         struct phy *phy;
 215         struct phy_provider *phy_provider;
 216         void __iomem *base;
 217
 218         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 219         if (!priv)
 220                 return -ENOMEM;
 221
 222         base = devm_platform_ioremap_resource(pdev, 0);
 223         if (IS_ERR(base))
 224                 return PTR_ERR(base);
 225
 226         priv->match = device_get_match_data(&pdev->dev);
 227         if (!priv->match)
 228                 return -ENODEV;
 229
 230         priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
 231                                              &phy_meson8b_usb2_regmap_conf);
 232         if (IS_ERR(priv->regmap))
 233                 return PTR_ERR(priv->regmap);
 234
 235         priv->clk_usb_general = devm_clk_get(&pdev->dev, "usb_general");
 236         if (IS_ERR(priv->clk_usb_general))
 237                 return PTR_ERR(priv->clk_usb_general);
 238
 239         priv->clk_usb = devm_clk_get(&pdev->dev, "usb");
 240         if (IS_ERR(priv->clk_usb))
 241                 return PTR_ERR(priv->clk_usb);
 242
 243         priv->reset = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
 244         if (PTR_ERR(priv->reset) == -EPROBE_DEFER)
 245                 return PTR_ERR(priv->reset);
 246
 247         priv->dr_mode = of_usb_get_dr_mode_by_phy(pdev->dev.of_node, -1);
 248         if (priv->dr_mode == USB_DR_MODE_UNKNOWN) {
 249                 dev_err(&pdev->dev,
 250                         "missing dual role configuration of the controller\n");
 251                 return -EINVAL;
 252         }
 253
 254         phy = devm_phy_create(&pdev->dev, NULL, &phy_meson8b_usb2_ops);
 255         if (IS_ERR(phy)) {
 256                 dev_err(&pdev->dev, "failed to create PHY\n");
 257                 return PTR_ERR(phy);
 258         }
 259
 260         phy_set_drvdata(phy, priv);
 261
 262         phy_provider =
 263                 devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
 264
 265         return PTR_ERR_OR_ZERO(phy_provider);
 266 }
 267
 268 static const struct phy_meson8b_usb2_match_data phy_meson8_usb2_match_data = {
 269         .host_enable_aca = false,
 270 };
 271
 272 static const struct phy_meson8b_usb2_match_data phy_meson8b_usb2_match_data = {
 273         .host_enable_aca = true,
 274 };
 275
 276 static const struct of_device_id phy_meson8b_usb2_of_match[] = {
 277         {
 278                 .compatible = "amlogic,meson8-usb2-phy",
 279                 .data = &phy_meson8_usb2_match_data
 280         },
 281         {
 282                 .compatible = "amlogic,meson8b-usb2-phy",
 283                 .data = &phy_meson8b_usb2_match_data
 284         },
 285         {
 286                 .compatible = "amlogic,meson-gxbb-usb2-phy",
 287                 .data = &phy_meson8b_usb2_match_data
 288         },
 289         { /* sentinel */ }
 290 };
 291 MODULE_DEVICE_TABLE(of, phy_meson8b_usb2_of_match);
 292
 293 static struct platform_driver phy_meson8b_usb2_driver = {
 294         .probe  = phy_meson8b_usb2_probe,
 295         .driver = {
 296                 .name           = "phy-meson-usb2",
 297                 .of_match_table = phy_meson8b_usb2_of_match,
 298         },
 299 };
 300 module_platform_driver(phy_meson8b_usb2_driver);
 301
 302 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
 303 MODULE_DESCRIPTION("Meson8, Meson8b and GXBB USB2 PHY driver");
 304 MODULE_LICENSE("GPL");