drivers/phy/amlogic/phy-meson-gxl-usb2.c

   1 /*
   2  * Meson GXL and GXM USB2 PHY driver
   3  *
   4  * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * You should have received a copy of the GNU General Public License
  11  * along with this program. If not, see <http://www.gnu.org/licenses/>.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/io.h>
  17 #include <linux/module.h>
  18 #include <linux/of_device.h>
  19 #include <linux/regmap.h>
  20 #include <linux/reset.h>
  21 #include <linux/phy/phy.h>
  22 #include <linux/platform_device.h>
  23
  24 /* bits [31:27] are read-only */
  25 #define U2P_R0                                                  0x0
  26         #define U2P_R0_BYPASS_SEL                               BIT(0)
  27         #define U2P_R0_BYPASS_DM_EN                             BIT(1)
  28         #define U2P_R0_BYPASS_DP_EN                             BIT(2)
  29         #define U2P_R0_TXBITSTUFF_ENH                           BIT(3)
  30         #define U2P_R0_TXBITSTUFF_EN                            BIT(4)
  31         #define U2P_R0_DM_PULLDOWN                              BIT(5)
  32         #define U2P_R0_DP_PULLDOWN                              BIT(6)
  33         #define U2P_R0_DP_VBUS_VLD_EXT_SEL                      BIT(7)
  34         #define U2P_R0_DP_VBUS_VLD_EXT                          BIT(8)
  35         #define U2P_R0_ADP_PRB_EN                               BIT(9)
  36         #define U2P_R0_ADP_DISCHARGE                            BIT(10)
  37         #define U2P_R0_ADP_CHARGE                               BIT(11)
  38         #define U2P_R0_DRV_VBUS                                 BIT(12)
  39         #define U2P_R0_ID_PULLUP                                BIT(13)
  40         #define U2P_R0_LOOPBACK_EN_B                            BIT(14)
  41         #define U2P_R0_OTG_DISABLE                              BIT(15)
  42         #define U2P_R0_COMMON_ONN                               BIT(16)
  43         #define U2P_R0_FSEL_MASK                                GENMASK(19, 17)
  44         #define U2P_R0_REF_CLK_SEL_MASK                         GENMASK(21, 20)
  45         #define U2P_R0_POWER_ON_RESET                           BIT(22)
  46         #define U2P_R0_V_ATE_TEST_EN_B_MASK                     GENMASK(24, 23)
  47         #define U2P_R0_ID_SET_ID_DQ                             BIT(25)
  48         #define U2P_R0_ATE_RESET                                BIT(26)
  49         #define U2P_R0_FSV_MINUS                                BIT(27)
  50         #define U2P_R0_FSV_PLUS                                 BIT(28)
  51         #define U2P_R0_BYPASS_DM_DATA                           BIT(29)
  52         #define U2P_R0_BYPASS_DP_DATA                           BIT(30)
  53
  54 #define U2P_R1                                                  0x4
  55         #define U2P_R1_BURN_IN_TEST                             BIT(0)
  56         #define U2P_R1_ACA_ENABLE                               BIT(1)
  57         #define U2P_R1_DCD_ENABLE                               BIT(2)
  58         #define U2P_R1_VDAT_SRC_EN_B                            BIT(3)
  59         #define U2P_R1_VDAT_DET_EN_B                            BIT(4)
  60         #define U2P_R1_CHARGES_SEL                              BIT(5)
  61         #define U2P_R1_TX_PREEMP_PULSE_TUNE                     BIT(6)
  62         #define U2P_R1_TX_PREEMP_AMP_TUNE_MASK                  GENMASK(8, 7)
  63         #define U2P_R1_TX_RES_TUNE_MASK                         GENMASK(10, 9)
  64         #define U2P_R1_TX_RISE_TUNE_MASK                        GENMASK(12, 11)
  65         #define U2P_R1_TX_VREF_TUNE_MASK                        GENMASK(16, 13)
  66         #define U2P_R1_TX_FSLS_TUNE_MASK                        GENMASK(20, 17)
  67         #define U2P_R1_TX_HSXV_TUNE_MASK                        GENMASK(22, 21)
  68         #define U2P_R1_OTG_TUNE_MASK                            GENMASK(25, 23)
  69         #define U2P_R1_SQRX_TUNE_MASK                           GENMASK(28, 26)
  70         #define U2P_R1_COMP_DIS_TUNE_MASK                       GENMASK(31, 29)
  71
  72 /* bits [31:14] are read-only */
  73 #define U2P_R2                                                  0x8
  74         #define U2P_R2_TESTDATA_IN_MASK                         GENMASK(7, 0)
  75         #define U2P_R2_TESTADDR_MASK                            GENMASK(11, 8)
  76         #define U2P_R2_TESTDATA_OUT_SEL                         BIT(12)
  77         #define U2P_R2_TESTCLK                                  BIT(13)
  78         #define U2P_R2_TESTDATA_OUT_MASK                        GENMASK(17, 14)
  79         #define U2P_R2_ACA_PIN_RANGE_C                          BIT(18)
  80         #define U2P_R2_ACA_PIN_RANGE_B                          BIT(19)
  81         #define U2P_R2_ACA_PIN_RANGE_A                          BIT(20)
  82         #define U2P_R2_ACA_PIN_GND                              BIT(21)
  83         #define U2P_R2_ACA_PIN_FLOAT                            BIT(22)
  84         #define U2P_R2_CHARGE_DETECT                            BIT(23)
  85         #define U2P_R2_DEVICE_SESSION_VALID                     BIT(24)
  86         #define U2P_R2_ADP_PROBE                                BIT(25)
  87         #define U2P_R2_ADP_SENSE                                BIT(26)
  88         #define U2P_R2_SESSION_END                              BIT(27)
  89         #define U2P_R2_VBUS_VALID                               BIT(28)
  90         #define U2P_R2_B_VALID                                  BIT(29)
  91         #define U2P_R2_A_VALID                                  BIT(30)
  92         #define U2P_R2_ID_DIG                                   BIT(31)
  93
  94 #define U2P_R3                                                  0xc
  95
  96 #define RESET_COMPLETE_TIME                             500
  97
  98 struct phy_meson_gxl_usb2_priv {
  99         struct regmap           *regmap;
 100         enum phy_mode           mode;
 101         int                     is_enabled;
 102         struct clk              *clk;
 103         struct reset_control    *reset;
 104 };
 105
 106 static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = {
 107         .reg_bits = 8,
 108         .val_bits = 32,
 109         .reg_stride = 4,
 110         .max_register = U2P_R3,
 111 };
 112
 113 static int phy_meson_gxl_usb2_init(struct phy *phy)
 114 {
 115         struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
 116         int ret;
 117
 118         ret = reset_control_reset(priv->reset);
 119         if (ret)
 120                 return ret;
 121
 122         ret = clk_prepare_enable(priv->clk);
 123         if (ret)
 124                 return ret;
 125
 126         return 0;
 127 }
 128
 129 static int phy_meson_gxl_usb2_exit(struct phy *phy)
 130 {
 131         struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
 132
 133         clk_disable_unprepare(priv->clk);
 134
 135         return 0;
 136 }
 137
 138 static int phy_meson_gxl_usb2_reset(struct phy *phy)
 139 {
 140         struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
 141
 142         if (priv->is_enabled) {
 143                 /* reset the PHY and wait until settings are stabilized */
 144                 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET,
 145                                    U2P_R0_POWER_ON_RESET);
 146                 udelay(RESET_COMPLETE_TIME);
 147                 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET,
 148                                    0);
 149                 udelay(RESET_COMPLETE_TIME);
 150         }
 151
 152         return 0;
 153 }
 154
 155 static int phy_meson_gxl_usb2_set_mode(struct phy *phy,
 156                                        enum phy_mode mode, int submode)
 157 {
 158         struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
 159
 160         switch (mode) {
 161         case PHY_MODE_USB_HOST:
 162         case PHY_MODE_USB_OTG:
 163                 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DM_PULLDOWN,
 164                                    U2P_R0_DM_PULLDOWN);
 165                 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DP_PULLDOWN,
 166                                    U2P_R0_DP_PULLDOWN);
 167                 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_ID_PULLUP, 0);
 168                 break;
 169
 170         case PHY_MODE_USB_DEVICE:
 171                 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DM_PULLDOWN,
 172                                    0);
 173                 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DP_PULLDOWN,
 174                                    0);
 175                 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_ID_PULLUP,
 176                                    U2P_R0_ID_PULLUP);
 177                 break;
 178
 179         default:
 180                 return -EINVAL;
 181         }
 182
 183         phy_meson_gxl_usb2_reset(phy);
 184
 185         priv->mode = mode;
 186
 187         return 0;
 188 }
 189
 190 static int phy_meson_gxl_usb2_power_off(struct phy *phy)
 191 {
 192         struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
 193
 194         priv->is_enabled = 0;
 195
 196         /* power off the PHY by putting it into reset mode */
 197         regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET,
 198                            U2P_R0_POWER_ON_RESET);
 199
 200         return 0;
 201 }
 202
 203 static int phy_meson_gxl_usb2_power_on(struct phy *phy)
 204 {
 205         struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
 206         int ret;
 207
 208         priv->is_enabled = 1;
 209
 210         /* power on the PHY by taking it out of reset mode */
 211         regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET, 0);
 212
 213         ret = phy_meson_gxl_usb2_set_mode(phy, priv->mode, 0);
 214         if (ret) {
 215                 phy_meson_gxl_usb2_power_off(phy);
 216
 217                 dev_err(&phy->dev, "Failed to initialize PHY with mode %d\n",
 218                         priv->mode);
 219                 return ret;
 220         }
 221
 222         return 0;
 223 }
 224
 225 static const struct phy_ops phy_meson_gxl_usb2_ops = {
 226         .init           = phy_meson_gxl_usb2_init,
 227         .exit           = phy_meson_gxl_usb2_exit,
 228         .power_on       = phy_meson_gxl_usb2_power_on,
 229         .power_off      = phy_meson_gxl_usb2_power_off,
 230         .set_mode       = phy_meson_gxl_usb2_set_mode,
 231         .reset          = phy_meson_gxl_usb2_reset,
 232         .owner          = THIS_MODULE,
 233 };
 234
 235 static int phy_meson_gxl_usb2_probe(struct platform_device *pdev)
 236 {
 237         struct device *dev = &pdev->dev;
 238         struct phy_provider *phy_provider;
 239         struct resource *res;
 240         struct phy_meson_gxl_usb2_priv *priv;
 241         struct phy *phy;
 242         void __iomem *base;
 243         int ret;
 244
 245         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 246         if (!priv)
 247                 return -ENOMEM;
 248
 249         platform_set_drvdata(pdev, priv);
 250
 251         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 252         base = devm_ioremap_resource(dev, res);
 253         if (IS_ERR(base))
 254                 return PTR_ERR(base);
 255
 256         /* start in host mode */
 257         priv->mode = PHY_MODE_USB_HOST;
 258
 259         priv->regmap = devm_regmap_init_mmio(dev, base,
 260                                              &phy_meson_gxl_usb2_regmap_conf);
 261         if (IS_ERR(priv->regmap))
 262                 return PTR_ERR(priv->regmap);
 263
 264         priv->clk = devm_clk_get_optional(dev, "phy");
 265         if (IS_ERR(priv->clk))
 266                 return PTR_ERR(priv->clk);
 267
 268         priv->reset = devm_reset_control_get_optional_shared(dev, "phy");
 269         if (IS_ERR(priv->reset))
 270                 return PTR_ERR(priv->reset);
 271
 272         phy = devm_phy_create(dev, NULL, &phy_meson_gxl_usb2_ops);
 273         if (IS_ERR(phy)) {
 274                 ret = PTR_ERR(phy);
 275                 if (ret != -EPROBE_DEFER)
 276                         dev_err(dev, "failed to create PHY\n");
 277
 278                 return ret;
 279         }
 280
 281         phy_set_drvdata(phy, priv);
 282
 283         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 284
 285         return PTR_ERR_OR_ZERO(phy_provider);
 286 }
 287
 288 static const struct of_device_id phy_meson_gxl_usb2_of_match[] = {
 289         { .compatible = "amlogic,meson-gxl-usb2-phy", },
 290         { },
 291 };
 292 MODULE_DEVICE_TABLE(of, phy_meson_gxl_usb2_of_match);
 293
 294 static struct platform_driver phy_meson_gxl_usb2_driver = {
 295         .probe  = phy_meson_gxl_usb2_probe,
 296         .driver = {
 297                 .name           = "phy-meson-gxl-usb2",
 298                 .of_match_table = phy_meson_gxl_usb2_of_match,
 299         },
 300 };
 301 module_platform_driver(phy_meson_gxl_usb2_driver);
 302
 303 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
 304 MODULE_DESCRIPTION("Meson GXL and GXM USB2 PHY driver");
 305 MODULE_LICENSE("GPL v2");