2 * APM X-Gene SoC PMU (Performance Monitor Unit)
4 * Copyright (c) 2016, Applied Micro Circuits Corporation
5 * Author: Hoan Tran <hotran@apm.com>
6 * Tai Nguyen <ttnguyen@apm.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/acpi.h>
23 #include <linux/clk.h>
24 #include <linux/cpuhotplug.h>
25 #include <linux/cpumask.h>
26 #include <linux/interrupt.h>
28 #include <linux/mfd/syscon.h>
29 #include <linux/module.h>
30 #include <linux/of_address.h>
31 #include <linux/of_fdt.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_platform.h>
34 #include <linux/perf_event.h>
35 #include <linux/platform_device.h>
36 #include <linux/regmap.h>
37 #include <linux/slab.h>
39 #define CSW_CSWCR 0x0000
40 #define CSW_CSWCR_DUALMCB_MASK BIT(0)
41 #define CSW_CSWCR_MCB0_ROUTING(x) (((x) & 0x0C) >> 2)
42 #define CSW_CSWCR_MCB1_ROUTING(x) (((x) & 0x30) >> 4)
43 #define MCBADDRMR 0x0000
44 #define MCBADDRMR_DUALMCU_MODE_MASK BIT(2)
46 #define PCPPMU_INTSTATUS_REG 0x000
47 #define PCPPMU_INTMASK_REG 0x004
48 #define PCPPMU_INTMASK 0x0000000F
49 #define PCPPMU_INTENMASK 0xFFFFFFFF
50 #define PCPPMU_INTCLRMASK 0xFFFFFFF0
51 #define PCPPMU_INT_MCU BIT(0)
52 #define PCPPMU_INT_MCB BIT(1)
53 #define PCPPMU_INT_L3C BIT(2)
54 #define PCPPMU_INT_IOB BIT(3)
56 #define PCPPMU_V3_INTMASK 0x00FF33FF
57 #define PCPPMU_V3_INTENMASK 0xFFFFFFFF
58 #define PCPPMU_V3_INTCLRMASK 0xFF00CC00
59 #define PCPPMU_V3_INT_MCU 0x000000FF
60 #define PCPPMU_V3_INT_MCB 0x00000300
61 #define PCPPMU_V3_INT_L3C 0x00FF0000
62 #define PCPPMU_V3_INT_IOB 0x00003000
64 #define PMU_MAX_COUNTERS 4
65 #define PMU_CNT_MAX_PERIOD 0xFFFFFFFFULL
66 #define PMU_V3_CNT_MAX_PERIOD 0xFFFFFFFFFFFFFFFFULL
67 #define PMU_OVERFLOW_MASK 0xF
68 #define PMU_PMCR_E BIT(0)
69 #define PMU_PMCR_P BIT(1)
71 #define PMU_PMEVCNTR0 0x000
72 #define PMU_PMEVCNTR1 0x004
73 #define PMU_PMEVCNTR2 0x008
74 #define PMU_PMEVCNTR3 0x00C
75 #define PMU_PMEVTYPER0 0x400
76 #define PMU_PMEVTYPER1 0x404
77 #define PMU_PMEVTYPER2 0x408
78 #define PMU_PMEVTYPER3 0x40C
79 #define PMU_PMAMR0 0xA00
80 #define PMU_PMAMR1 0xA04
81 #define PMU_PMCNTENSET 0xC00
82 #define PMU_PMCNTENCLR 0xC20
83 #define PMU_PMINTENSET 0xC40
84 #define PMU_PMINTENCLR 0xC60
85 #define PMU_PMOVSR 0xC80
86 #define PMU_PMCR 0xE04
88 /* PMU registers for V3 */
89 #define PMU_PMOVSCLR 0xC80
90 #define PMU_PMOVSSET 0xCC0
92 #define to_pmu_dev(p) container_of(p, struct xgene_pmu_dev, pmu)
93 #define GET_CNTR(ev) (ev->hw.idx)
94 #define GET_EVENTID(ev) (ev->hw.config & 0xFFULL)
95 #define GET_AGENTID(ev) (ev->hw.config_base & 0xFFFFFFFFUL)
96 #define GET_AGENT1ID(ev) ((ev->hw.config_base >> 32) & 0xFFFFFFFFUL)
104 struct xgene_pmu_dev {
105 struct hw_pmu_info *inf;
106 struct xgene_pmu *parent;
109 DECLARE_BITMAP(cntr_assign_mask, PMU_MAX_COUNTERS);
111 const struct attribute_group **attr_groups;
112 struct perf_event *pmu_counter_event[PMU_MAX_COUNTERS];
115 struct xgene_pmu_ops {
116 void (*mask_int)(struct xgene_pmu *pmu);
117 void (*unmask_int)(struct xgene_pmu *pmu);
118 u64 (*read_counter)(struct xgene_pmu_dev *pmu, int idx);
119 void (*write_counter)(struct xgene_pmu_dev *pmu, int idx, u64 val);
120 void (*write_evttype)(struct xgene_pmu_dev *pmu_dev, int idx, u32 val);
121 void (*write_agentmsk)(struct xgene_pmu_dev *pmu_dev, u32 val);
122 void (*write_agent1msk)(struct xgene_pmu_dev *pmu_dev, u32 val);
123 void (*enable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);
124 void (*disable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);
125 void (*enable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);
126 void (*disable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);
127 void (*reset_counters)(struct xgene_pmu_dev *pmu_dev);
128 void (*start_counters)(struct xgene_pmu_dev *pmu_dev);
129 void (*stop_counters)(struct xgene_pmu_dev *pmu_dev);
134 struct hlist_node node;
136 void __iomem *pcppmu_csr;
143 const struct xgene_pmu_ops *ops;
144 struct list_head l3cpmus;
145 struct list_head iobpmus;
146 struct list_head mcbpmus;
147 struct list_head mcpmus;
150 struct xgene_pmu_dev_ctx {
152 struct list_head next;
153 struct xgene_pmu_dev *pmu_dev;
154 struct hw_pmu_info inf;
157 struct xgene_pmu_data {
162 enum xgene_pmu_version {
168 enum xgene_pmu_dev_type {
177 * sysfs format attributes
179 static ssize_t xgene_pmu_format_show(struct device *dev,
180 struct device_attribute *attr, char *buf)
182 struct dev_ext_attribute *eattr;
184 eattr = container_of(attr, struct dev_ext_attribute, attr);
185 return sprintf(buf, "%s\n", (char *) eattr->var);
188 #define XGENE_PMU_FORMAT_ATTR(_name, _config) \
189 (&((struct dev_ext_attribute[]) { \
190 { .attr = __ATTR(_name, S_IRUGO, xgene_pmu_format_show, NULL), \
191 .var = (void *) _config, } \
194 static struct attribute *l3c_pmu_format_attrs[] = {
195 XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-7"),
196 XGENE_PMU_FORMAT_ATTR(l3c_agentid, "config1:0-9"),
200 static struct attribute *iob_pmu_format_attrs[] = {
201 XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-7"),
202 XGENE_PMU_FORMAT_ATTR(iob_agentid, "config1:0-63"),
206 static struct attribute *mcb_pmu_format_attrs[] = {
207 XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-5"),
208 XGENE_PMU_FORMAT_ATTR(mcb_agentid, "config1:0-9"),
212 static struct attribute *mc_pmu_format_attrs[] = {
213 XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-28"),
217 static const struct attribute_group l3c_pmu_format_attr_group = {
219 .attrs = l3c_pmu_format_attrs,
222 static const struct attribute_group iob_pmu_format_attr_group = {
224 .attrs = iob_pmu_format_attrs,
227 static const struct attribute_group mcb_pmu_format_attr_group = {
229 .attrs = mcb_pmu_format_attrs,
232 static const struct attribute_group mc_pmu_format_attr_group = {
234 .attrs = mc_pmu_format_attrs,
237 static struct attribute *l3c_pmu_v3_format_attrs[] = {
238 XGENE_PMU_FORMAT_ATTR(l3c_eventid, "config:0-39"),
242 static struct attribute *iob_pmu_v3_format_attrs[] = {
243 XGENE_PMU_FORMAT_ATTR(iob_eventid, "config:0-47"),
247 static struct attribute *iob_slow_pmu_v3_format_attrs[] = {
248 XGENE_PMU_FORMAT_ATTR(iob_slow_eventid, "config:0-16"),
252 static struct attribute *mcb_pmu_v3_format_attrs[] = {
253 XGENE_PMU_FORMAT_ATTR(mcb_eventid, "config:0-35"),
257 static struct attribute *mc_pmu_v3_format_attrs[] = {
258 XGENE_PMU_FORMAT_ATTR(mc_eventid, "config:0-44"),
262 static const struct attribute_group l3c_pmu_v3_format_attr_group = {
264 .attrs = l3c_pmu_v3_format_attrs,
267 static const struct attribute_group iob_pmu_v3_format_attr_group = {
269 .attrs = iob_pmu_v3_format_attrs,
272 static const struct attribute_group iob_slow_pmu_v3_format_attr_group = {
274 .attrs = iob_slow_pmu_v3_format_attrs,
277 static const struct attribute_group mcb_pmu_v3_format_attr_group = {
279 .attrs = mcb_pmu_v3_format_attrs,
282 static const struct attribute_group mc_pmu_v3_format_attr_group = {
284 .attrs = mc_pmu_v3_format_attrs,
288 * sysfs event attributes
290 static ssize_t xgene_pmu_event_show(struct device *dev,
291 struct device_attribute *attr, char *buf)
293 struct dev_ext_attribute *eattr;
295 eattr = container_of(attr, struct dev_ext_attribute, attr);
296 return sprintf(buf, "config=0x%lx\n", (unsigned long) eattr->var);
299 #define XGENE_PMU_EVENT_ATTR(_name, _config) \
300 (&((struct dev_ext_attribute[]) { \
301 { .attr = __ATTR(_name, S_IRUGO, xgene_pmu_event_show, NULL), \
302 .var = (void *) _config, } \
305 static struct attribute *l3c_pmu_events_attrs[] = {
306 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
307 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
308 XGENE_PMU_EVENT_ATTR(read-hit, 0x02),
309 XGENE_PMU_EVENT_ATTR(read-miss, 0x03),
310 XGENE_PMU_EVENT_ATTR(write-need-replacement, 0x06),
311 XGENE_PMU_EVENT_ATTR(write-not-need-replacement, 0x07),
312 XGENE_PMU_EVENT_ATTR(tq-full, 0x08),
313 XGENE_PMU_EVENT_ATTR(ackq-full, 0x09),
314 XGENE_PMU_EVENT_ATTR(wdb-full, 0x0a),
315 XGENE_PMU_EVENT_ATTR(bank-fifo-full, 0x0b),
316 XGENE_PMU_EVENT_ATTR(odb-full, 0x0c),
317 XGENE_PMU_EVENT_ATTR(wbq-full, 0x0d),
318 XGENE_PMU_EVENT_ATTR(bank-conflict-fifo-issue, 0x0e),
319 XGENE_PMU_EVENT_ATTR(bank-fifo-issue, 0x0f),
323 static struct attribute *iob_pmu_events_attrs[] = {
324 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
325 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
326 XGENE_PMU_EVENT_ATTR(axi0-read, 0x02),
327 XGENE_PMU_EVENT_ATTR(axi0-read-partial, 0x03),
328 XGENE_PMU_EVENT_ATTR(axi1-read, 0x04),
329 XGENE_PMU_EVENT_ATTR(axi1-read-partial, 0x05),
330 XGENE_PMU_EVENT_ATTR(csw-read-block, 0x06),
331 XGENE_PMU_EVENT_ATTR(csw-read-partial, 0x07),
332 XGENE_PMU_EVENT_ATTR(axi0-write, 0x10),
333 XGENE_PMU_EVENT_ATTR(axi0-write-partial, 0x11),
334 XGENE_PMU_EVENT_ATTR(axi1-write, 0x13),
335 XGENE_PMU_EVENT_ATTR(axi1-write-partial, 0x14),
336 XGENE_PMU_EVENT_ATTR(csw-inbound-dirty, 0x16),
340 static struct attribute *mcb_pmu_events_attrs[] = {
341 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
342 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
343 XGENE_PMU_EVENT_ATTR(csw-read, 0x02),
344 XGENE_PMU_EVENT_ATTR(csw-write-request, 0x03),
345 XGENE_PMU_EVENT_ATTR(mcb-csw-stall, 0x04),
346 XGENE_PMU_EVENT_ATTR(cancel-read-gack, 0x05),
350 static struct attribute *mc_pmu_events_attrs[] = {
351 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
352 XGENE_PMU_EVENT_ATTR(cycle-count-div-64, 0x01),
353 XGENE_PMU_EVENT_ATTR(act-cmd-sent, 0x02),
354 XGENE_PMU_EVENT_ATTR(pre-cmd-sent, 0x03),
355 XGENE_PMU_EVENT_ATTR(rd-cmd-sent, 0x04),
356 XGENE_PMU_EVENT_ATTR(rda-cmd-sent, 0x05),
357 XGENE_PMU_EVENT_ATTR(wr-cmd-sent, 0x06),
358 XGENE_PMU_EVENT_ATTR(wra-cmd-sent, 0x07),
359 XGENE_PMU_EVENT_ATTR(pde-cmd-sent, 0x08),
360 XGENE_PMU_EVENT_ATTR(sre-cmd-sent, 0x09),
361 XGENE_PMU_EVENT_ATTR(prea-cmd-sent, 0x0a),
362 XGENE_PMU_EVENT_ATTR(ref-cmd-sent, 0x0b),
363 XGENE_PMU_EVENT_ATTR(rd-rda-cmd-sent, 0x0c),
364 XGENE_PMU_EVENT_ATTR(wr-wra-cmd-sent, 0x0d),
365 XGENE_PMU_EVENT_ATTR(in-rd-collision, 0x0e),
366 XGENE_PMU_EVENT_ATTR(in-wr-collision, 0x0f),
367 XGENE_PMU_EVENT_ATTR(collision-queue-not-empty, 0x10),
368 XGENE_PMU_EVENT_ATTR(collision-queue-full, 0x11),
369 XGENE_PMU_EVENT_ATTR(mcu-request, 0x12),
370 XGENE_PMU_EVENT_ATTR(mcu-rd-request, 0x13),
371 XGENE_PMU_EVENT_ATTR(mcu-hp-rd-request, 0x14),
372 XGENE_PMU_EVENT_ATTR(mcu-wr-request, 0x15),
373 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-all, 0x16),
374 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-cancel, 0x17),
375 XGENE_PMU_EVENT_ATTR(mcu-rd-response, 0x18),
376 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-all, 0x19),
377 XGENE_PMU_EVENT_ATTR(mcu-rd-proceed-speculative-cancel, 0x1a),
378 XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-all, 0x1b),
379 XGENE_PMU_EVENT_ATTR(mcu-wr-proceed-cancel, 0x1c),
383 static const struct attribute_group l3c_pmu_events_attr_group = {
385 .attrs = l3c_pmu_events_attrs,
388 static const struct attribute_group iob_pmu_events_attr_group = {
390 .attrs = iob_pmu_events_attrs,
393 static const struct attribute_group mcb_pmu_events_attr_group = {
395 .attrs = mcb_pmu_events_attrs,
398 static const struct attribute_group mc_pmu_events_attr_group = {
400 .attrs = mc_pmu_events_attrs,
403 static struct attribute *l3c_pmu_v3_events_attrs[] = {
404 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
405 XGENE_PMU_EVENT_ATTR(read-hit, 0x01),
406 XGENE_PMU_EVENT_ATTR(read-miss, 0x02),
407 XGENE_PMU_EVENT_ATTR(index-flush-eviction, 0x03),
408 XGENE_PMU_EVENT_ATTR(write-caused-replacement, 0x04),
409 XGENE_PMU_EVENT_ATTR(write-not-caused-replacement, 0x05),
410 XGENE_PMU_EVENT_ATTR(clean-eviction, 0x06),
411 XGENE_PMU_EVENT_ATTR(dirty-eviction, 0x07),
412 XGENE_PMU_EVENT_ATTR(read, 0x08),
413 XGENE_PMU_EVENT_ATTR(write, 0x09),
414 XGENE_PMU_EVENT_ATTR(request, 0x0a),
415 XGENE_PMU_EVENT_ATTR(tq-bank-conflict-issue-stall, 0x0b),
416 XGENE_PMU_EVENT_ATTR(tq-full, 0x0c),
417 XGENE_PMU_EVENT_ATTR(ackq-full, 0x0d),
418 XGENE_PMU_EVENT_ATTR(wdb-full, 0x0e),
419 XGENE_PMU_EVENT_ATTR(odb-full, 0x10),
420 XGENE_PMU_EVENT_ATTR(wbq-full, 0x11),
421 XGENE_PMU_EVENT_ATTR(input-req-async-fifo-stall, 0x12),
422 XGENE_PMU_EVENT_ATTR(output-req-async-fifo-stall, 0x13),
423 XGENE_PMU_EVENT_ATTR(output-data-async-fifo-stall, 0x14),
424 XGENE_PMU_EVENT_ATTR(total-insertion, 0x15),
425 XGENE_PMU_EVENT_ATTR(sip-insertions-r-set, 0x16),
426 XGENE_PMU_EVENT_ATTR(sip-insertions-r-clear, 0x17),
427 XGENE_PMU_EVENT_ATTR(dip-insertions-r-set, 0x18),
428 XGENE_PMU_EVENT_ATTR(dip-insertions-r-clear, 0x19),
429 XGENE_PMU_EVENT_ATTR(dip-insertions-force-r-set, 0x1a),
430 XGENE_PMU_EVENT_ATTR(egression, 0x1b),
431 XGENE_PMU_EVENT_ATTR(replacement, 0x1c),
432 XGENE_PMU_EVENT_ATTR(old-replacement, 0x1d),
433 XGENE_PMU_EVENT_ATTR(young-replacement, 0x1e),
434 XGENE_PMU_EVENT_ATTR(r-set-replacement, 0x1f),
435 XGENE_PMU_EVENT_ATTR(r-clear-replacement, 0x20),
436 XGENE_PMU_EVENT_ATTR(old-r-replacement, 0x21),
437 XGENE_PMU_EVENT_ATTR(old-nr-replacement, 0x22),
438 XGENE_PMU_EVENT_ATTR(young-r-replacement, 0x23),
439 XGENE_PMU_EVENT_ATTR(young-nr-replacement, 0x24),
440 XGENE_PMU_EVENT_ATTR(bloomfilter-clearing, 0x25),
441 XGENE_PMU_EVENT_ATTR(generation-flip, 0x26),
442 XGENE_PMU_EVENT_ATTR(vcc-droop-detected, 0x27),
446 static struct attribute *iob_fast_pmu_v3_events_attrs[] = {
447 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
448 XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-all, 0x01),
449 XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-rd, 0x02),
450 XGENE_PMU_EVENT_ATTR(pa-req-buf-alloc-wr, 0x03),
451 XGENE_PMU_EVENT_ATTR(pa-all-cp-req, 0x04),
452 XGENE_PMU_EVENT_ATTR(pa-cp-blk-req, 0x05),
453 XGENE_PMU_EVENT_ATTR(pa-cp-ptl-req, 0x06),
454 XGENE_PMU_EVENT_ATTR(pa-cp-rd-req, 0x07),
455 XGENE_PMU_EVENT_ATTR(pa-cp-wr-req, 0x08),
456 XGENE_PMU_EVENT_ATTR(ba-all-req, 0x09),
457 XGENE_PMU_EVENT_ATTR(ba-rd-req, 0x0a),
458 XGENE_PMU_EVENT_ATTR(ba-wr-req, 0x0b),
459 XGENE_PMU_EVENT_ATTR(pa-rd-shared-req-issued, 0x10),
460 XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-req-issued, 0x11),
461 XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-stashable, 0x12),
462 XGENE_PMU_EVENT_ATTR(pa-wr-invalidate-req-issued-nonstashable, 0x13),
463 XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-stashable, 0x14),
464 XGENE_PMU_EVENT_ATTR(pa-wr-back-req-issued-nonstashable, 0x15),
465 XGENE_PMU_EVENT_ATTR(pa-ptl-wr-req, 0x16),
466 XGENE_PMU_EVENT_ATTR(pa-ptl-rd-req, 0x17),
467 XGENE_PMU_EVENT_ATTR(pa-wr-back-clean-data, 0x18),
468 XGENE_PMU_EVENT_ATTR(pa-wr-back-cancelled-on-SS, 0x1b),
469 XGENE_PMU_EVENT_ATTR(pa-barrier-occurrence, 0x1c),
470 XGENE_PMU_EVENT_ATTR(pa-barrier-cycles, 0x1d),
471 XGENE_PMU_EVENT_ATTR(pa-total-cp-snoops, 0x20),
472 XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop, 0x21),
473 XGENE_PMU_EVENT_ATTR(pa-rd-shared-snoop-hit, 0x22),
474 XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop, 0x23),
475 XGENE_PMU_EVENT_ATTR(pa-rd-exclusive-snoop-hit, 0x24),
476 XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop, 0x25),
477 XGENE_PMU_EVENT_ATTR(pa-rd-wr-invalid-snoop-hit, 0x26),
478 XGENE_PMU_EVENT_ATTR(pa-req-buffer-full, 0x28),
479 XGENE_PMU_EVENT_ATTR(cswlf-outbound-req-fifo-full, 0x29),
480 XGENE_PMU_EVENT_ATTR(cswlf-inbound-snoop-fifo-backpressure, 0x2a),
481 XGENE_PMU_EVENT_ATTR(cswlf-outbound-lack-fifo-full, 0x2b),
482 XGENE_PMU_EVENT_ATTR(cswlf-inbound-gack-fifo-backpressure, 0x2c),
483 XGENE_PMU_EVENT_ATTR(cswlf-outbound-data-fifo-full, 0x2d),
484 XGENE_PMU_EVENT_ATTR(cswlf-inbound-data-fifo-backpressure, 0x2e),
485 XGENE_PMU_EVENT_ATTR(cswlf-inbound-req-backpressure, 0x2f),
489 static struct attribute *iob_slow_pmu_v3_events_attrs[] = {
490 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
491 XGENE_PMU_EVENT_ATTR(pa-axi0-rd-req, 0x01),
492 XGENE_PMU_EVENT_ATTR(pa-axi0-wr-req, 0x02),
493 XGENE_PMU_EVENT_ATTR(pa-axi1-rd-req, 0x03),
494 XGENE_PMU_EVENT_ATTR(pa-axi1-wr-req, 0x04),
495 XGENE_PMU_EVENT_ATTR(ba-all-axi-req, 0x07),
496 XGENE_PMU_EVENT_ATTR(ba-axi-rd-req, 0x08),
497 XGENE_PMU_EVENT_ATTR(ba-axi-wr-req, 0x09),
498 XGENE_PMU_EVENT_ATTR(ba-free-list-empty, 0x10),
502 static struct attribute *mcb_pmu_v3_events_attrs[] = {
503 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
504 XGENE_PMU_EVENT_ATTR(req-receive, 0x01),
505 XGENE_PMU_EVENT_ATTR(rd-req-recv, 0x02),
506 XGENE_PMU_EVENT_ATTR(rd-req-recv-2, 0x03),
507 XGENE_PMU_EVENT_ATTR(wr-req-recv, 0x04),
508 XGENE_PMU_EVENT_ATTR(wr-req-recv-2, 0x05),
509 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu, 0x06),
510 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-mcu-2, 0x07),
511 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu, 0x08),
512 XGENE_PMU_EVENT_ATTR(rd-req-sent-to-spec-mcu-2, 0x09),
513 XGENE_PMU_EVENT_ATTR(glbl-ack-recv-for-rd-sent-to-spec-mcu, 0x0a),
514 XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-for-rd-sent-to-spec-mcu, 0x0b),
515 XGENE_PMU_EVENT_ATTR(glbl-ack-nogo-recv-for-rd-sent-to-spec-mcu, 0x0c),
516 XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req, 0x0d),
517 XGENE_PMU_EVENT_ATTR(glbl-ack-go-recv-any-rd-req-2, 0x0e),
518 XGENE_PMU_EVENT_ATTR(wr-req-sent-to-mcu, 0x0f),
519 XGENE_PMU_EVENT_ATTR(gack-recv, 0x10),
520 XGENE_PMU_EVENT_ATTR(rd-gack-recv, 0x11),
521 XGENE_PMU_EVENT_ATTR(wr-gack-recv, 0x12),
522 XGENE_PMU_EVENT_ATTR(cancel-rd-gack, 0x13),
523 XGENE_PMU_EVENT_ATTR(cancel-wr-gack, 0x14),
524 XGENE_PMU_EVENT_ATTR(mcb-csw-req-stall, 0x15),
525 XGENE_PMU_EVENT_ATTR(mcu-req-intf-blocked, 0x16),
526 XGENE_PMU_EVENT_ATTR(mcb-mcu-rd-intf-stall, 0x17),
527 XGENE_PMU_EVENT_ATTR(csw-rd-intf-blocked, 0x18),
528 XGENE_PMU_EVENT_ATTR(csw-local-ack-intf-blocked, 0x19),
529 XGENE_PMU_EVENT_ATTR(mcu-req-table-full, 0x1a),
530 XGENE_PMU_EVENT_ATTR(mcu-stat-table-full, 0x1b),
531 XGENE_PMU_EVENT_ATTR(mcu-wr-table-full, 0x1c),
532 XGENE_PMU_EVENT_ATTR(mcu-rdreceipt-resp, 0x1d),
533 XGENE_PMU_EVENT_ATTR(mcu-wrcomplete-resp, 0x1e),
534 XGENE_PMU_EVENT_ATTR(mcu-retryack-resp, 0x1f),
535 XGENE_PMU_EVENT_ATTR(mcu-pcrdgrant-resp, 0x20),
536 XGENE_PMU_EVENT_ATTR(mcu-req-from-lastload, 0x21),
537 XGENE_PMU_EVENT_ATTR(mcu-req-from-bypass, 0x22),
538 XGENE_PMU_EVENT_ATTR(volt-droop-detect, 0x23),
542 static struct attribute *mc_pmu_v3_events_attrs[] = {
543 XGENE_PMU_EVENT_ATTR(cycle-count, 0x00),
544 XGENE_PMU_EVENT_ATTR(act-sent, 0x01),
545 XGENE_PMU_EVENT_ATTR(pre-sent, 0x02),
546 XGENE_PMU_EVENT_ATTR(rd-sent, 0x03),
547 XGENE_PMU_EVENT_ATTR(rda-sent, 0x04),
548 XGENE_PMU_EVENT_ATTR(wr-sent, 0x05),
549 XGENE_PMU_EVENT_ATTR(wra-sent, 0x06),
550 XGENE_PMU_EVENT_ATTR(pd-entry-vld, 0x07),
551 XGENE_PMU_EVENT_ATTR(sref-entry-vld, 0x08),
552 XGENE_PMU_EVENT_ATTR(prea-sent, 0x09),
553 XGENE_PMU_EVENT_ATTR(ref-sent, 0x0a),
554 XGENE_PMU_EVENT_ATTR(rd-rda-sent, 0x0b),
555 XGENE_PMU_EVENT_ATTR(wr-wra-sent, 0x0c),
556 XGENE_PMU_EVENT_ATTR(raw-hazard, 0x0d),
557 XGENE_PMU_EVENT_ATTR(war-hazard, 0x0e),
558 XGENE_PMU_EVENT_ATTR(waw-hazard, 0x0f),
559 XGENE_PMU_EVENT_ATTR(rar-hazard, 0x10),
560 XGENE_PMU_EVENT_ATTR(raw-war-waw-hazard, 0x11),
561 XGENE_PMU_EVENT_ATTR(hprd-lprd-wr-req-vld, 0x12),
562 XGENE_PMU_EVENT_ATTR(lprd-req-vld, 0x13),
563 XGENE_PMU_EVENT_ATTR(hprd-req-vld, 0x14),
564 XGENE_PMU_EVENT_ATTR(hprd-lprd-req-vld, 0x15),
565 XGENE_PMU_EVENT_ATTR(wr-req-vld, 0x16),
566 XGENE_PMU_EVENT_ATTR(partial-wr-req-vld, 0x17),
567 XGENE_PMU_EVENT_ATTR(rd-retry, 0x18),
568 XGENE_PMU_EVENT_ATTR(wr-retry, 0x19),
569 XGENE_PMU_EVENT_ATTR(retry-gnt, 0x1a),
570 XGENE_PMU_EVENT_ATTR(rank-change, 0x1b),
571 XGENE_PMU_EVENT_ATTR(dir-change, 0x1c),
572 XGENE_PMU_EVENT_ATTR(rank-dir-change, 0x1d),
573 XGENE_PMU_EVENT_ATTR(rank-active, 0x1e),
574 XGENE_PMU_EVENT_ATTR(rank-idle, 0x1f),
575 XGENE_PMU_EVENT_ATTR(rank-pd, 0x20),
576 XGENE_PMU_EVENT_ATTR(rank-sref, 0x21),
577 XGENE_PMU_EVENT_ATTR(queue-fill-gt-thresh, 0x22),
578 XGENE_PMU_EVENT_ATTR(queue-rds-gt-thresh, 0x23),
579 XGENE_PMU_EVENT_ATTR(queue-wrs-gt-thresh, 0x24),
580 XGENE_PMU_EVENT_ATTR(phy-updt-complt, 0x25),
581 XGENE_PMU_EVENT_ATTR(tz-fail, 0x26),
582 XGENE_PMU_EVENT_ATTR(dram-errc, 0x27),
583 XGENE_PMU_EVENT_ATTR(dram-errd, 0x28),
584 XGENE_PMU_EVENT_ATTR(rd-enq, 0x29),
585 XGENE_PMU_EVENT_ATTR(wr-enq, 0x2a),
586 XGENE_PMU_EVENT_ATTR(tmac-limit-reached, 0x2b),
587 XGENE_PMU_EVENT_ATTR(tmaw-tracker-full, 0x2c),
591 static const struct attribute_group l3c_pmu_v3_events_attr_group = {
593 .attrs = l3c_pmu_v3_events_attrs,
596 static const struct attribute_group iob_fast_pmu_v3_events_attr_group = {
598 .attrs = iob_fast_pmu_v3_events_attrs,
601 static const struct attribute_group iob_slow_pmu_v3_events_attr_group = {
603 .attrs = iob_slow_pmu_v3_events_attrs,
606 static const struct attribute_group mcb_pmu_v3_events_attr_group = {
608 .attrs = mcb_pmu_v3_events_attrs,
611 static const struct attribute_group mc_pmu_v3_events_attr_group = {
613 .attrs = mc_pmu_v3_events_attrs,
617 * sysfs cpumask attributes
619 static ssize_t xgene_pmu_cpumask_show(struct device *dev,
620 struct device_attribute *attr, char *buf)
622 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(dev_get_drvdata(dev));
624 return cpumap_print_to_pagebuf(true, buf, &pmu_dev->parent->cpu);
627 static DEVICE_ATTR(cpumask, S_IRUGO, xgene_pmu_cpumask_show, NULL);
629 static struct attribute *xgene_pmu_cpumask_attrs[] = {
630 &dev_attr_cpumask.attr,
634 static const struct attribute_group pmu_cpumask_attr_group = {
635 .attrs = xgene_pmu_cpumask_attrs,
639 * Per PMU device attribute groups of PMU v1 and v2
641 static const struct attribute_group *l3c_pmu_attr_groups[] = {
642 &l3c_pmu_format_attr_group,
643 &pmu_cpumask_attr_group,
644 &l3c_pmu_events_attr_group,
648 static const struct attribute_group *iob_pmu_attr_groups[] = {
649 &iob_pmu_format_attr_group,
650 &pmu_cpumask_attr_group,
651 &iob_pmu_events_attr_group,
655 static const struct attribute_group *mcb_pmu_attr_groups[] = {
656 &mcb_pmu_format_attr_group,
657 &pmu_cpumask_attr_group,
658 &mcb_pmu_events_attr_group,
662 static const struct attribute_group *mc_pmu_attr_groups[] = {
663 &mc_pmu_format_attr_group,
664 &pmu_cpumask_attr_group,
665 &mc_pmu_events_attr_group,
670 * Per PMU device attribute groups of PMU v3
672 static const struct attribute_group *l3c_pmu_v3_attr_groups[] = {
673 &l3c_pmu_v3_format_attr_group,
674 &pmu_cpumask_attr_group,
675 &l3c_pmu_v3_events_attr_group,
679 static const struct attribute_group *iob_fast_pmu_v3_attr_groups[] = {
680 &iob_pmu_v3_format_attr_group,
681 &pmu_cpumask_attr_group,
682 &iob_fast_pmu_v3_events_attr_group,
686 static const struct attribute_group *iob_slow_pmu_v3_attr_groups[] = {
687 &iob_slow_pmu_v3_format_attr_group,
688 &pmu_cpumask_attr_group,
689 &iob_slow_pmu_v3_events_attr_group,
693 static const struct attribute_group *mcb_pmu_v3_attr_groups[] = {
694 &mcb_pmu_v3_format_attr_group,
695 &pmu_cpumask_attr_group,
696 &mcb_pmu_v3_events_attr_group,
700 static const struct attribute_group *mc_pmu_v3_attr_groups[] = {
701 &mc_pmu_v3_format_attr_group,
702 &pmu_cpumask_attr_group,
703 &mc_pmu_v3_events_attr_group,
707 static int get_next_avail_cntr(struct xgene_pmu_dev *pmu_dev)
711 cntr = find_first_zero_bit(pmu_dev->cntr_assign_mask,
712 pmu_dev->max_counters);
713 if (cntr == pmu_dev->max_counters)
715 set_bit(cntr, pmu_dev->cntr_assign_mask);
720 static void clear_avail_cntr(struct xgene_pmu_dev *pmu_dev, int cntr)
722 clear_bit(cntr, pmu_dev->cntr_assign_mask);
725 static inline void xgene_pmu_mask_int(struct xgene_pmu *xgene_pmu)
727 writel(PCPPMU_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
730 static inline void xgene_pmu_v3_mask_int(struct xgene_pmu *xgene_pmu)
732 writel(PCPPMU_V3_INTENMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
735 static inline void xgene_pmu_unmask_int(struct xgene_pmu *xgene_pmu)
737 writel(PCPPMU_INTCLRMASK, xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
740 static inline void xgene_pmu_v3_unmask_int(struct xgene_pmu *xgene_pmu)
742 writel(PCPPMU_V3_INTCLRMASK,
743 xgene_pmu->pcppmu_csr + PCPPMU_INTMASK_REG);
746 static inline u64 xgene_pmu_read_counter32(struct xgene_pmu_dev *pmu_dev,
749 return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
752 static inline u64 xgene_pmu_read_counter64(struct xgene_pmu_dev *pmu_dev,
758 * v3 has 64-bit counter registers composed by 2 32-bit registers
759 * This can be a problem if the counter increases and carries
760 * out of bit [31] between 2 reads. The extra reads would help
761 * to prevent this issue.
764 hi = xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1);
765 lo = xgene_pmu_read_counter32(pmu_dev, 2 * idx);
766 } while (hi != xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1));
768 return (((u64)hi << 32) | lo);
772 xgene_pmu_write_counter32(struct xgene_pmu_dev *pmu_dev, int idx, u64 val)
774 writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
778 xgene_pmu_write_counter64(struct xgene_pmu_dev *pmu_dev, int idx, u64 val)
782 cnt_hi = upper_32_bits(val);
783 cnt_lo = lower_32_bits(val);
785 /* v3 has 64-bit counter registers composed by 2 32-bit registers */
786 xgene_pmu_write_counter32(pmu_dev, 2 * idx, cnt_lo);
787 xgene_pmu_write_counter32(pmu_dev, 2 * idx + 1, cnt_hi);
791 xgene_pmu_write_evttype(struct xgene_pmu_dev *pmu_dev, int idx, u32 val)
793 writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx));
797 xgene_pmu_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val)
799 writel(val, pmu_dev->inf->csr + PMU_PMAMR0);
803 xgene_pmu_v3_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) { }
806 xgene_pmu_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val)
808 writel(val, pmu_dev->inf->csr + PMU_PMAMR1);
812 xgene_pmu_v3_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) { }
815 xgene_pmu_enable_counter(struct xgene_pmu_dev *pmu_dev, int idx)
819 val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET);
821 writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET);
825 xgene_pmu_disable_counter(struct xgene_pmu_dev *pmu_dev, int idx)
829 val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR);
831 writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR);
835 xgene_pmu_enable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx)
839 val = readl(pmu_dev->inf->csr + PMU_PMINTENSET);
841 writel(val, pmu_dev->inf->csr + PMU_PMINTENSET);
845 xgene_pmu_disable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx)
849 val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR);
851 writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR);
854 static inline void xgene_pmu_reset_counters(struct xgene_pmu_dev *pmu_dev)
858 val = readl(pmu_dev->inf->csr + PMU_PMCR);
860 writel(val, pmu_dev->inf->csr + PMU_PMCR);
863 static inline void xgene_pmu_start_counters(struct xgene_pmu_dev *pmu_dev)
867 val = readl(pmu_dev->inf->csr + PMU_PMCR);
869 writel(val, pmu_dev->inf->csr + PMU_PMCR);
872 static inline void xgene_pmu_stop_counters(struct xgene_pmu_dev *pmu_dev)
876 val = readl(pmu_dev->inf->csr + PMU_PMCR);
878 writel(val, pmu_dev->inf->csr + PMU_PMCR);
881 static void xgene_perf_pmu_enable(struct pmu *pmu)
883 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);
884 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
885 int enabled = bitmap_weight(pmu_dev->cntr_assign_mask,
886 pmu_dev->max_counters);
891 xgene_pmu->ops->start_counters(pmu_dev);
894 static void xgene_perf_pmu_disable(struct pmu *pmu)
896 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);
897 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
899 xgene_pmu->ops->stop_counters(pmu_dev);
902 static int xgene_perf_event_init(struct perf_event *event)
904 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
905 struct hw_perf_event *hw = &event->hw;
906 struct perf_event *sibling;
908 /* Test the event attr type check for PMU enumeration */
909 if (event->attr.type != event->pmu->type)
913 * SOC PMU counters are shared across all cores.
914 * Therefore, it does not support per-process mode.
915 * Also, it does not support event sampling mode.
917 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
920 /* SOC counters do not have usr/os/guest/host bits */
921 if (event->attr.exclude_user || event->attr.exclude_kernel ||
922 event->attr.exclude_host || event->attr.exclude_guest)
928 * Many perf core operations (eg. events rotation) operate on a
929 * single CPU context. This is obvious for CPU PMUs, where one
930 * expects the same sets of events being observed on all CPUs,
931 * but can lead to issues for off-core PMUs, where each
932 * event could be theoretically assigned to a different CPU. To
933 * mitigate this, we enforce CPU assignment to one, selected
934 * processor (the one described in the "cpumask" attribute).
936 event->cpu = cpumask_first(&pmu_dev->parent->cpu);
938 hw->config = event->attr.config;
940 * Each bit of the config1 field represents an agent from which the
941 * request of the event come. The event is counted only if it's caused
942 * by a request of an agent has the bit cleared.
943 * By default, the event is counted for all agents.
945 hw->config_base = event->attr.config1;
948 * We must NOT create groups containing mixed PMUs, although software
949 * events are acceptable
951 if (event->group_leader->pmu != event->pmu &&
952 !is_software_event(event->group_leader))
955 for_each_sibling_event(sibling, event->group_leader) {
956 if (sibling->pmu != event->pmu &&
957 !is_software_event(sibling))
964 static void xgene_perf_enable_event(struct perf_event *event)
966 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
967 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
969 xgene_pmu->ops->write_evttype(pmu_dev, GET_CNTR(event),
971 xgene_pmu->ops->write_agentmsk(pmu_dev, ~((u32)GET_AGENTID(event)));
972 if (pmu_dev->inf->type == PMU_TYPE_IOB)
973 xgene_pmu->ops->write_agent1msk(pmu_dev,
974 ~((u32)GET_AGENT1ID(event)));
976 xgene_pmu->ops->enable_counter(pmu_dev, GET_CNTR(event));
977 xgene_pmu->ops->enable_counter_int(pmu_dev, GET_CNTR(event));
980 static void xgene_perf_disable_event(struct perf_event *event)
982 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
983 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
985 xgene_pmu->ops->disable_counter(pmu_dev, GET_CNTR(event));
986 xgene_pmu->ops->disable_counter_int(pmu_dev, GET_CNTR(event));
989 static void xgene_perf_event_set_period(struct perf_event *event)
991 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
992 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
993 struct hw_perf_event *hw = &event->hw;
995 * For 32 bit counter, it has a period of 2^32. To account for the
996 * possibility of extreme interrupt latency we program for a period of
997 * half that. Hopefully, we can handle the interrupt before another 2^31
998 * events occur and the counter overtakes its previous value.
999 * For 64 bit counter, we don't expect it overflow.
1001 u64 val = 1ULL << 31;
1003 local64_set(&hw->prev_count, val);
1004 xgene_pmu->ops->write_counter(pmu_dev, hw->idx, val);
1007 static void xgene_perf_event_update(struct perf_event *event)
1009 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1010 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
1011 struct hw_perf_event *hw = &event->hw;
1012 u64 delta, prev_raw_count, new_raw_count;
1015 prev_raw_count = local64_read(&hw->prev_count);
1016 new_raw_count = xgene_pmu->ops->read_counter(pmu_dev, GET_CNTR(event));
1018 if (local64_cmpxchg(&hw->prev_count, prev_raw_count,
1019 new_raw_count) != prev_raw_count)
1022 delta = (new_raw_count - prev_raw_count) & pmu_dev->max_period;
1024 local64_add(delta, &event->count);
1027 static void xgene_perf_read(struct perf_event *event)
1029 xgene_perf_event_update(event);
1032 static void xgene_perf_start(struct perf_event *event, int flags)
1034 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1035 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
1036 struct hw_perf_event *hw = &event->hw;
1038 if (WARN_ON_ONCE(!(hw->state & PERF_HES_STOPPED)))
1041 WARN_ON_ONCE(!(hw->state & PERF_HES_UPTODATE));
1044 xgene_perf_event_set_period(event);
1046 if (flags & PERF_EF_RELOAD) {
1047 u64 prev_raw_count = local64_read(&hw->prev_count);
1049 xgene_pmu->ops->write_counter(pmu_dev, GET_CNTR(event),
1053 xgene_perf_enable_event(event);
1054 perf_event_update_userpage(event);
1057 static void xgene_perf_stop(struct perf_event *event, int flags)
1059 struct hw_perf_event *hw = &event->hw;
1062 if (hw->state & PERF_HES_UPTODATE)
1065 xgene_perf_disable_event(event);
1066 WARN_ON_ONCE(hw->state & PERF_HES_STOPPED);
1067 hw->state |= PERF_HES_STOPPED;
1069 if (hw->state & PERF_HES_UPTODATE)
1072 config = hw->config;
1073 xgene_perf_read(event);
1074 hw->state |= PERF_HES_UPTODATE;
1077 static int xgene_perf_add(struct perf_event *event, int flags)
1079 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1080 struct hw_perf_event *hw = &event->hw;
1082 hw->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1084 /* Allocate an event counter */
1085 hw->idx = get_next_avail_cntr(pmu_dev);
1089 /* Update counter event pointer for Interrupt handler */
1090 pmu_dev->pmu_counter_event[hw->idx] = event;
1092 if (flags & PERF_EF_START)
1093 xgene_perf_start(event, PERF_EF_RELOAD);
1098 static void xgene_perf_del(struct perf_event *event, int flags)
1100 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1101 struct hw_perf_event *hw = &event->hw;
1103 xgene_perf_stop(event, PERF_EF_UPDATE);
1105 /* clear the assigned counter */
1106 clear_avail_cntr(pmu_dev, GET_CNTR(event));
1108 perf_event_update_userpage(event);
1109 pmu_dev->pmu_counter_event[hw->idx] = NULL;
1112 static int xgene_init_perf(struct xgene_pmu_dev *pmu_dev, char *name)
1114 struct xgene_pmu *xgene_pmu;
1116 if (pmu_dev->parent->version == PCP_PMU_V3)
1117 pmu_dev->max_period = PMU_V3_CNT_MAX_PERIOD;
1119 pmu_dev->max_period = PMU_CNT_MAX_PERIOD;
1120 /* First version PMU supports only single event counter */
1121 xgene_pmu = pmu_dev->parent;
1122 if (xgene_pmu->version == PCP_PMU_V1)
1123 pmu_dev->max_counters = 1;
1125 pmu_dev->max_counters = PMU_MAX_COUNTERS;
1127 /* Perf driver registration */
1128 pmu_dev->pmu = (struct pmu) {
1129 .attr_groups = pmu_dev->attr_groups,
1130 .task_ctx_nr = perf_invalid_context,
1131 .pmu_enable = xgene_perf_pmu_enable,
1132 .pmu_disable = xgene_perf_pmu_disable,
1133 .event_init = xgene_perf_event_init,
1134 .add = xgene_perf_add,
1135 .del = xgene_perf_del,
1136 .start = xgene_perf_start,
1137 .stop = xgene_perf_stop,
1138 .read = xgene_perf_read,
1141 /* Hardware counter init */
1142 xgene_pmu->ops->stop_counters(pmu_dev);
1143 xgene_pmu->ops->reset_counters(pmu_dev);
1145 return perf_pmu_register(&pmu_dev->pmu, name, -1);
1149 xgene_pmu_dev_add(struct xgene_pmu *xgene_pmu, struct xgene_pmu_dev_ctx *ctx)
1151 struct device *dev = xgene_pmu->dev;
1152 struct xgene_pmu_dev *pmu;
1154 pmu = devm_kzalloc(dev, sizeof(*pmu), GFP_KERNEL);
1157 pmu->parent = xgene_pmu;
1158 pmu->inf = &ctx->inf;
1161 switch (pmu->inf->type) {
1163 if (!(xgene_pmu->l3c_active_mask & pmu->inf->enable_mask))
1165 if (xgene_pmu->version == PCP_PMU_V3)
1166 pmu->attr_groups = l3c_pmu_v3_attr_groups;
1168 pmu->attr_groups = l3c_pmu_attr_groups;
1171 if (xgene_pmu->version == PCP_PMU_V3)
1172 pmu->attr_groups = iob_fast_pmu_v3_attr_groups;
1174 pmu->attr_groups = iob_pmu_attr_groups;
1176 case PMU_TYPE_IOB_SLOW:
1177 if (xgene_pmu->version == PCP_PMU_V3)
1178 pmu->attr_groups = iob_slow_pmu_v3_attr_groups;
1181 if (!(xgene_pmu->mcb_active_mask & pmu->inf->enable_mask))
1183 if (xgene_pmu->version == PCP_PMU_V3)
1184 pmu->attr_groups = mcb_pmu_v3_attr_groups;
1186 pmu->attr_groups = mcb_pmu_attr_groups;
1189 if (!(xgene_pmu->mc_active_mask & pmu->inf->enable_mask))
1191 if (xgene_pmu->version == PCP_PMU_V3)
1192 pmu->attr_groups = mc_pmu_v3_attr_groups;
1194 pmu->attr_groups = mc_pmu_attr_groups;
1200 if (xgene_init_perf(pmu, ctx->name)) {
1201 dev_err(dev, "%s PMU: Failed to init perf driver\n", ctx->name);
1205 dev_info(dev, "%s PMU registered\n", ctx->name);
1210 static void _xgene_pmu_isr(int irq, struct xgene_pmu_dev *pmu_dev)
1212 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
1213 void __iomem *csr = pmu_dev->inf->csr;
1217 xgene_pmu->ops->stop_counters(pmu_dev);
1219 if (xgene_pmu->version == PCP_PMU_V3)
1220 pmovsr = readl(csr + PMU_PMOVSSET) & PMU_OVERFLOW_MASK;
1222 pmovsr = readl(csr + PMU_PMOVSR) & PMU_OVERFLOW_MASK;
1227 /* Clear interrupt flag */
1228 if (xgene_pmu->version == PCP_PMU_V1)
1229 writel(0x0, csr + PMU_PMOVSR);
1230 else if (xgene_pmu->version == PCP_PMU_V2)
1231 writel(pmovsr, csr + PMU_PMOVSR);
1233 writel(pmovsr, csr + PMU_PMOVSCLR);
1235 for (idx = 0; idx < PMU_MAX_COUNTERS; idx++) {
1236 struct perf_event *event = pmu_dev->pmu_counter_event[idx];
1237 int overflowed = pmovsr & BIT(idx);
1239 /* Ignore if we don't have an event. */
1240 if (!event || !overflowed)
1242 xgene_perf_event_update(event);
1243 xgene_perf_event_set_period(event);
1247 xgene_pmu->ops->start_counters(pmu_dev);
1250 static irqreturn_t xgene_pmu_isr(int irq, void *dev_id)
1252 u32 intr_mcu, intr_mcb, intr_l3c, intr_iob;
1253 struct xgene_pmu_dev_ctx *ctx;
1254 struct xgene_pmu *xgene_pmu = dev_id;
1255 unsigned long flags;
1258 raw_spin_lock_irqsave(&xgene_pmu->lock, flags);
1260 /* Get Interrupt PMU source */
1261 val = readl(xgene_pmu->pcppmu_csr + PCPPMU_INTSTATUS_REG);
1262 if (xgene_pmu->version == PCP_PMU_V3) {
1263 intr_mcu = PCPPMU_V3_INT_MCU;
1264 intr_mcb = PCPPMU_V3_INT_MCB;
1265 intr_l3c = PCPPMU_V3_INT_L3C;
1266 intr_iob = PCPPMU_V3_INT_IOB;
1268 intr_mcu = PCPPMU_INT_MCU;
1269 intr_mcb = PCPPMU_INT_MCB;
1270 intr_l3c = PCPPMU_INT_L3C;
1271 intr_iob = PCPPMU_INT_IOB;
1273 if (val & intr_mcu) {
1274 list_for_each_entry(ctx, &xgene_pmu->mcpmus, next) {
1275 _xgene_pmu_isr(irq, ctx->pmu_dev);
1278 if (val & intr_mcb) {
1279 list_for_each_entry(ctx, &xgene_pmu->mcbpmus, next) {
1280 _xgene_pmu_isr(irq, ctx->pmu_dev);
1283 if (val & intr_l3c) {
1284 list_for_each_entry(ctx, &xgene_pmu->l3cpmus, next) {
1285 _xgene_pmu_isr(irq, ctx->pmu_dev);
1288 if (val & intr_iob) {
1289 list_for_each_entry(ctx, &xgene_pmu->iobpmus, next) {
1290 _xgene_pmu_isr(irq, ctx->pmu_dev);
1294 raw_spin_unlock_irqrestore(&xgene_pmu->lock, flags);
1299 static int acpi_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1300 struct platform_device *pdev)
1302 void __iomem *csw_csr, *mcba_csr, *mcbb_csr;
1303 struct resource *res;
1306 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1307 csw_csr = devm_ioremap_resource(&pdev->dev, res);
1308 if (IS_ERR(csw_csr)) {
1309 dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n");
1310 return PTR_ERR(csw_csr);
1313 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1314 mcba_csr = devm_ioremap_resource(&pdev->dev, res);
1315 if (IS_ERR(mcba_csr)) {
1316 dev_err(&pdev->dev, "ioremap failed for MCBA CSR resource\n");
1317 return PTR_ERR(mcba_csr);
1320 res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1321 mcbb_csr = devm_ioremap_resource(&pdev->dev, res);
1322 if (IS_ERR(mcbb_csr)) {
1323 dev_err(&pdev->dev, "ioremap failed for MCBB CSR resource\n");
1324 return PTR_ERR(mcbb_csr);
1327 xgene_pmu->l3c_active_mask = 0x1;
1329 reg = readl(csw_csr + CSW_CSWCR);
1330 if (reg & CSW_CSWCR_DUALMCB_MASK) {
1331 /* Dual MCB active */
1332 xgene_pmu->mcb_active_mask = 0x3;
1333 /* Probe all active MC(s) */
1334 reg = readl(mcbb_csr + CSW_CSWCR);
1335 xgene_pmu->mc_active_mask =
1336 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5;
1338 /* Single MCB active */
1339 xgene_pmu->mcb_active_mask = 0x1;
1340 /* Probe all active MC(s) */
1341 reg = readl(mcba_csr + CSW_CSWCR);
1342 xgene_pmu->mc_active_mask =
1343 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1;
1349 static int acpi_pmu_v3_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1350 struct platform_device *pdev)
1352 void __iomem *csw_csr;
1353 struct resource *res;
1358 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1359 csw_csr = devm_ioremap_resource(&pdev->dev, res);
1360 if (IS_ERR(csw_csr)) {
1361 dev_err(&pdev->dev, "ioremap failed for CSW CSR resource\n");
1362 return PTR_ERR(csw_csr);
1365 reg = readl(csw_csr + CSW_CSWCR);
1366 mcb0routing = CSW_CSWCR_MCB0_ROUTING(reg);
1367 mcb1routing = CSW_CSWCR_MCB1_ROUTING(reg);
1368 if (reg & CSW_CSWCR_DUALMCB_MASK) {
1369 /* Dual MCB active */
1370 xgene_pmu->mcb_active_mask = 0x3;
1371 /* Probe all active L3C(s), maximum is 8 */
1372 xgene_pmu->l3c_active_mask = 0xFF;
1373 /* Probe all active MC(s), maximum is 8 */
1374 if ((mcb0routing == 0x2) && (mcb1routing == 0x2))
1375 xgene_pmu->mc_active_mask = 0xFF;
1376 else if ((mcb0routing == 0x1) && (mcb1routing == 0x1))
1377 xgene_pmu->mc_active_mask = 0x33;
1379 xgene_pmu->mc_active_mask = 0x11;
1381 /* Single MCB active */
1382 xgene_pmu->mcb_active_mask = 0x1;
1383 /* Probe all active L3C(s), maximum is 4 */
1384 xgene_pmu->l3c_active_mask = 0x0F;
1385 /* Probe all active MC(s), maximum is 4 */
1386 if (mcb0routing == 0x2)
1387 xgene_pmu->mc_active_mask = 0x0F;
1388 else if (mcb0routing == 0x1)
1389 xgene_pmu->mc_active_mask = 0x03;
1391 xgene_pmu->mc_active_mask = 0x01;
1397 static int fdt_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1398 struct platform_device *pdev)
1400 struct regmap *csw_map, *mcba_map, *mcbb_map;
1401 struct device_node *np = pdev->dev.of_node;
1404 csw_map = syscon_regmap_lookup_by_phandle(np, "regmap-csw");
1405 if (IS_ERR(csw_map)) {
1406 dev_err(&pdev->dev, "unable to get syscon regmap csw\n");
1407 return PTR_ERR(csw_map);
1410 mcba_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcba");
1411 if (IS_ERR(mcba_map)) {
1412 dev_err(&pdev->dev, "unable to get syscon regmap mcba\n");
1413 return PTR_ERR(mcba_map);
1416 mcbb_map = syscon_regmap_lookup_by_phandle(np, "regmap-mcbb");
1417 if (IS_ERR(mcbb_map)) {
1418 dev_err(&pdev->dev, "unable to get syscon regmap mcbb\n");
1419 return PTR_ERR(mcbb_map);
1422 xgene_pmu->l3c_active_mask = 0x1;
1423 if (regmap_read(csw_map, CSW_CSWCR, ®))
1426 if (reg & CSW_CSWCR_DUALMCB_MASK) {
1427 /* Dual MCB active */
1428 xgene_pmu->mcb_active_mask = 0x3;
1429 /* Probe all active MC(s) */
1430 if (regmap_read(mcbb_map, MCBADDRMR, ®))
1432 xgene_pmu->mc_active_mask =
1433 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0xF : 0x5;
1435 /* Single MCB active */
1436 xgene_pmu->mcb_active_mask = 0x1;
1437 /* Probe all active MC(s) */
1438 if (regmap_read(mcba_map, MCBADDRMR, ®))
1440 xgene_pmu->mc_active_mask =
1441 (reg & MCBADDRMR_DUALMCU_MODE_MASK) ? 0x3 : 0x1;
1447 static int xgene_pmu_probe_active_mcb_mcu_l3c(struct xgene_pmu *xgene_pmu,
1448 struct platform_device *pdev)
1450 if (has_acpi_companion(&pdev->dev)) {
1451 if (xgene_pmu->version == PCP_PMU_V3)
1452 return acpi_pmu_v3_probe_active_mcb_mcu_l3c(xgene_pmu,
1455 return acpi_pmu_probe_active_mcb_mcu_l3c(xgene_pmu,
1458 return fdt_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, pdev);
1461 static char *xgene_pmu_dev_name(struct device *dev, u32 type, int id)
1465 return devm_kasprintf(dev, GFP_KERNEL, "l3c%d", id);
1467 return devm_kasprintf(dev, GFP_KERNEL, "iob%d", id);
1468 case PMU_TYPE_IOB_SLOW:
1469 return devm_kasprintf(dev, GFP_KERNEL, "iob_slow%d", id);
1471 return devm_kasprintf(dev, GFP_KERNEL, "mcb%d", id);
1473 return devm_kasprintf(dev, GFP_KERNEL, "mc%d", id);
1475 return devm_kasprintf(dev, GFP_KERNEL, "unknown");
1479 #if defined(CONFIG_ACPI)
1480 static int acpi_pmu_dev_add_resource(struct acpi_resource *ares, void *data)
1482 struct resource *res = data;
1484 if (ares->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32)
1485 acpi_dev_resource_memory(ares, res);
1487 /* Always tell the ACPI core to skip this resource */
1492 xgene_pmu_dev_ctx *acpi_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu,
1493 struct acpi_device *adev, u32 type)
1495 struct device *dev = xgene_pmu->dev;
1496 struct list_head resource_list;
1497 struct xgene_pmu_dev_ctx *ctx;
1498 const union acpi_object *obj;
1499 struct hw_pmu_info *inf;
1500 void __iomem *dev_csr;
1501 struct resource res;
1505 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1509 INIT_LIST_HEAD(&resource_list);
1510 rc = acpi_dev_get_resources(adev, &resource_list,
1511 acpi_pmu_dev_add_resource, &res);
1512 acpi_dev_free_resource_list(&resource_list);
1514 dev_err(dev, "PMU type %d: No resource address found\n", type);
1518 dev_csr = devm_ioremap_resource(dev, &res);
1519 if (IS_ERR(dev_csr)) {
1520 dev_err(dev, "PMU type %d: Fail to map resource\n", type);
1524 /* A PMU device node without enable-bit-index is always enabled */
1525 rc = acpi_dev_get_property(adev, "enable-bit-index",
1526 ACPI_TYPE_INTEGER, &obj);
1530 enable_bit = (int) obj->integer.value;
1532 ctx->name = xgene_pmu_dev_name(dev, type, enable_bit);
1534 dev_err(dev, "PMU type %d: Fail to get device name\n", type);
1540 inf->enable_mask = 1 << enable_bit;
1545 static const struct acpi_device_id xgene_pmu_acpi_type_match[] = {
1546 {"APMC0D5D", PMU_TYPE_L3C},
1547 {"APMC0D5E", PMU_TYPE_IOB},
1548 {"APMC0D5F", PMU_TYPE_MCB},
1549 {"APMC0D60", PMU_TYPE_MC},
1550 {"APMC0D84", PMU_TYPE_L3C},
1551 {"APMC0D85", PMU_TYPE_IOB},
1552 {"APMC0D86", PMU_TYPE_IOB_SLOW},
1553 {"APMC0D87", PMU_TYPE_MCB},
1554 {"APMC0D88", PMU_TYPE_MC},
1558 static const struct acpi_device_id *xgene_pmu_acpi_match_type(
1559 const struct acpi_device_id *ids,
1560 struct acpi_device *adev)
1562 const struct acpi_device_id *match_id = NULL;
1563 const struct acpi_device_id *id;
1565 for (id = ids; id->id[0] || id->cls; id++) {
1566 if (!acpi_match_device_ids(adev, id))
1575 static acpi_status acpi_pmu_dev_add(acpi_handle handle, u32 level,
1576 void *data, void **return_value)
1578 const struct acpi_device_id *acpi_id;
1579 struct xgene_pmu *xgene_pmu = data;
1580 struct xgene_pmu_dev_ctx *ctx;
1581 struct acpi_device *adev;
1583 if (acpi_bus_get_device(handle, &adev))
1585 if (acpi_bus_get_status(adev) || !adev->status.present)
1588 acpi_id = xgene_pmu_acpi_match_type(xgene_pmu_acpi_type_match, adev);
1592 ctx = acpi_get_pmu_hw_inf(xgene_pmu, adev, (u32)acpi_id->driver_data);
1596 if (xgene_pmu_dev_add(xgene_pmu, ctx)) {
1597 /* Can't add the PMU device, skip it */
1598 devm_kfree(xgene_pmu->dev, ctx);
1602 switch (ctx->inf.type) {
1604 list_add(&ctx->next, &xgene_pmu->l3cpmus);
1607 list_add(&ctx->next, &xgene_pmu->iobpmus);
1609 case PMU_TYPE_IOB_SLOW:
1610 list_add(&ctx->next, &xgene_pmu->iobpmus);
1613 list_add(&ctx->next, &xgene_pmu->mcbpmus);
1616 list_add(&ctx->next, &xgene_pmu->mcpmus);
1622 static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1623 struct platform_device *pdev)
1625 struct device *dev = xgene_pmu->dev;
1629 handle = ACPI_HANDLE(dev);
1633 status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1634 acpi_pmu_dev_add, NULL, xgene_pmu, NULL);
1635 if (ACPI_FAILURE(status)) {
1636 dev_err(dev, "failed to probe PMU devices\n");
1643 static int acpi_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1644 struct platform_device *pdev)
1651 xgene_pmu_dev_ctx *fdt_get_pmu_hw_inf(struct xgene_pmu *xgene_pmu,
1652 struct device_node *np, u32 type)
1654 struct device *dev = xgene_pmu->dev;
1655 struct xgene_pmu_dev_ctx *ctx;
1656 struct hw_pmu_info *inf;
1657 void __iomem *dev_csr;
1658 struct resource res;
1661 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1665 if (of_address_to_resource(np, 0, &res) < 0) {
1666 dev_err(dev, "PMU type %d: No resource address found\n", type);
1670 dev_csr = devm_ioremap_resource(dev, &res);
1671 if (IS_ERR(dev_csr)) {
1672 dev_err(dev, "PMU type %d: Fail to map resource\n", type);
1676 /* A PMU device node without enable-bit-index is always enabled */
1677 if (of_property_read_u32(np, "enable-bit-index", &enable_bit))
1680 ctx->name = xgene_pmu_dev_name(dev, type, enable_bit);
1682 dev_err(dev, "PMU type %d: Fail to get device name\n", type);
1689 inf->enable_mask = 1 << enable_bit;
1694 static int fdt_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1695 struct platform_device *pdev)
1697 struct xgene_pmu_dev_ctx *ctx;
1698 struct device_node *np;
1700 for_each_child_of_node(pdev->dev.of_node, np) {
1701 if (!of_device_is_available(np))
1704 if (of_device_is_compatible(np, "apm,xgene-pmu-l3c"))
1705 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_L3C);
1706 else if (of_device_is_compatible(np, "apm,xgene-pmu-iob"))
1707 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_IOB);
1708 else if (of_device_is_compatible(np, "apm,xgene-pmu-mcb"))
1709 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MCB);
1710 else if (of_device_is_compatible(np, "apm,xgene-pmu-mc"))
1711 ctx = fdt_get_pmu_hw_inf(xgene_pmu, np, PMU_TYPE_MC);
1718 if (xgene_pmu_dev_add(xgene_pmu, ctx)) {
1719 /* Can't add the PMU device, skip it */
1720 devm_kfree(xgene_pmu->dev, ctx);
1724 switch (ctx->inf.type) {
1726 list_add(&ctx->next, &xgene_pmu->l3cpmus);
1729 list_add(&ctx->next, &xgene_pmu->iobpmus);
1731 case PMU_TYPE_IOB_SLOW:
1732 list_add(&ctx->next, &xgene_pmu->iobpmus);
1735 list_add(&ctx->next, &xgene_pmu->mcbpmus);
1738 list_add(&ctx->next, &xgene_pmu->mcpmus);
1746 static int xgene_pmu_probe_pmu_dev(struct xgene_pmu *xgene_pmu,
1747 struct platform_device *pdev)
1749 if (has_acpi_companion(&pdev->dev))
1750 return acpi_pmu_probe_pmu_dev(xgene_pmu, pdev);
1751 return fdt_pmu_probe_pmu_dev(xgene_pmu, pdev);
1754 static const struct xgene_pmu_data xgene_pmu_data = {
1758 static const struct xgene_pmu_data xgene_pmu_v2_data = {
1762 static const struct xgene_pmu_ops xgene_pmu_ops = {
1763 .mask_int = xgene_pmu_mask_int,
1764 .unmask_int = xgene_pmu_unmask_int,
1765 .read_counter = xgene_pmu_read_counter32,
1766 .write_counter = xgene_pmu_write_counter32,
1767 .write_evttype = xgene_pmu_write_evttype,
1768 .write_agentmsk = xgene_pmu_write_agentmsk,
1769 .write_agent1msk = xgene_pmu_write_agent1msk,
1770 .enable_counter = xgene_pmu_enable_counter,
1771 .disable_counter = xgene_pmu_disable_counter,
1772 .enable_counter_int = xgene_pmu_enable_counter_int,
1773 .disable_counter_int = xgene_pmu_disable_counter_int,
1774 .reset_counters = xgene_pmu_reset_counters,
1775 .start_counters = xgene_pmu_start_counters,
1776 .stop_counters = xgene_pmu_stop_counters,
1779 static const struct xgene_pmu_ops xgene_pmu_v3_ops = {
1780 .mask_int = xgene_pmu_v3_mask_int,
1781 .unmask_int = xgene_pmu_v3_unmask_int,
1782 .read_counter = xgene_pmu_read_counter64,
1783 .write_counter = xgene_pmu_write_counter64,
1784 .write_evttype = xgene_pmu_write_evttype,
1785 .write_agentmsk = xgene_pmu_v3_write_agentmsk,
1786 .write_agent1msk = xgene_pmu_v3_write_agent1msk,
1787 .enable_counter = xgene_pmu_enable_counter,
1788 .disable_counter = xgene_pmu_disable_counter,
1789 .enable_counter_int = xgene_pmu_enable_counter_int,
1790 .disable_counter_int = xgene_pmu_disable_counter_int,
1791 .reset_counters = xgene_pmu_reset_counters,
1792 .start_counters = xgene_pmu_start_counters,
1793 .stop_counters = xgene_pmu_stop_counters,
1796 static const struct of_device_id xgene_pmu_of_match[] = {
1797 { .compatible = "apm,xgene-pmu", .data = &xgene_pmu_data },
1798 { .compatible = "apm,xgene-pmu-v2", .data = &xgene_pmu_v2_data },
1801 MODULE_DEVICE_TABLE(of, xgene_pmu_of_match);
1803 static const struct acpi_device_id xgene_pmu_acpi_match[] = {
1804 {"APMC0D5B", PCP_PMU_V1},
1805 {"APMC0D5C", PCP_PMU_V2},
1806 {"APMC0D83", PCP_PMU_V3},
1809 MODULE_DEVICE_TABLE(acpi, xgene_pmu_acpi_match);
1812 static int xgene_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
1814 struct xgene_pmu *xgene_pmu = hlist_entry_safe(node, struct xgene_pmu,
1817 if (cpumask_empty(&xgene_pmu->cpu))
1818 cpumask_set_cpu(cpu, &xgene_pmu->cpu);
1820 /* Overflow interrupt also should use the same CPU */
1821 WARN_ON(irq_set_affinity(xgene_pmu->irq, &xgene_pmu->cpu));
1826 static int xgene_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
1828 struct xgene_pmu *xgene_pmu = hlist_entry_safe(node, struct xgene_pmu,
1830 struct xgene_pmu_dev_ctx *ctx;
1831 unsigned int target;
1833 if (!cpumask_test_and_clear_cpu(cpu, &xgene_pmu->cpu))
1835 target = cpumask_any_but(cpu_online_mask, cpu);
1836 if (target >= nr_cpu_ids)
1839 list_for_each_entry(ctx, &xgene_pmu->mcpmus, next) {
1840 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1842 list_for_each_entry(ctx, &xgene_pmu->mcbpmus, next) {
1843 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1845 list_for_each_entry(ctx, &xgene_pmu->l3cpmus, next) {
1846 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1848 list_for_each_entry(ctx, &xgene_pmu->iobpmus, next) {
1849 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1852 cpumask_set_cpu(target, &xgene_pmu->cpu);
1853 /* Overflow interrupt also should use the same CPU */
1854 WARN_ON(irq_set_affinity(xgene_pmu->irq, &xgene_pmu->cpu));
1859 static int xgene_pmu_probe(struct platform_device *pdev)
1861 const struct xgene_pmu_data *dev_data;
1862 const struct of_device_id *of_id;
1863 struct xgene_pmu *xgene_pmu;
1864 struct resource *res;
1868 /* Install a hook to update the reader CPU in case it goes offline */
1869 rc = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
1870 "CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE",
1871 xgene_pmu_online_cpu,
1872 xgene_pmu_offline_cpu);
1876 xgene_pmu = devm_kzalloc(&pdev->dev, sizeof(*xgene_pmu), GFP_KERNEL);
1879 xgene_pmu->dev = &pdev->dev;
1880 platform_set_drvdata(pdev, xgene_pmu);
1883 of_id = of_match_device(xgene_pmu_of_match, &pdev->dev);
1885 dev_data = (const struct xgene_pmu_data *) of_id->data;
1886 version = dev_data->id;
1890 if (ACPI_COMPANION(&pdev->dev)) {
1891 const struct acpi_device_id *acpi_id;
1893 acpi_id = acpi_match_device(xgene_pmu_acpi_match, &pdev->dev);
1895 version = (int) acpi_id->driver_data;
1901 if (version == PCP_PMU_V3)
1902 xgene_pmu->ops = &xgene_pmu_v3_ops;
1904 xgene_pmu->ops = &xgene_pmu_ops;
1906 INIT_LIST_HEAD(&xgene_pmu->l3cpmus);
1907 INIT_LIST_HEAD(&xgene_pmu->iobpmus);
1908 INIT_LIST_HEAD(&xgene_pmu->mcbpmus);
1909 INIT_LIST_HEAD(&xgene_pmu->mcpmus);
1911 xgene_pmu->version = version;
1912 dev_info(&pdev->dev, "X-Gene PMU version %d\n", xgene_pmu->version);
1914 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1915 xgene_pmu->pcppmu_csr = devm_ioremap_resource(&pdev->dev, res);
1916 if (IS_ERR(xgene_pmu->pcppmu_csr)) {
1917 dev_err(&pdev->dev, "ioremap failed for PCP PMU resource\n");
1918 return PTR_ERR(xgene_pmu->pcppmu_csr);
1921 irq = platform_get_irq(pdev, 0);
1923 dev_err(&pdev->dev, "No IRQ resource\n");
1927 rc = devm_request_irq(&pdev->dev, irq, xgene_pmu_isr,
1928 IRQF_NOBALANCING | IRQF_NO_THREAD,
1929 dev_name(&pdev->dev), xgene_pmu);
1931 dev_err(&pdev->dev, "Could not request IRQ %d\n", irq);
1935 xgene_pmu->irq = irq;
1937 raw_spin_lock_init(&xgene_pmu->lock);
1939 /* Check for active MCBs and MCUs */
1940 rc = xgene_pmu_probe_active_mcb_mcu_l3c(xgene_pmu, pdev);
1942 dev_warn(&pdev->dev, "Unknown MCB/MCU active status\n");
1943 xgene_pmu->mcb_active_mask = 0x1;
1944 xgene_pmu->mc_active_mask = 0x1;
1947 /* Add this instance to the list used by the hotplug callback */
1948 rc = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
1951 dev_err(&pdev->dev, "Error %d registering hotplug", rc);
1955 /* Walk through the tree for all PMU perf devices */
1956 rc = xgene_pmu_probe_pmu_dev(xgene_pmu, pdev);
1958 dev_err(&pdev->dev, "No PMU perf devices found!\n");
1959 goto out_unregister;
1962 /* Enable interrupt */
1963 xgene_pmu->ops->unmask_int(xgene_pmu);
1968 cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
1974 xgene_pmu_dev_cleanup(struct xgene_pmu *xgene_pmu, struct list_head *pmus)
1976 struct xgene_pmu_dev_ctx *ctx;
1978 list_for_each_entry(ctx, pmus, next) {
1979 perf_pmu_unregister(&ctx->pmu_dev->pmu);
1983 static int xgene_pmu_remove(struct platform_device *pdev)
1985 struct xgene_pmu *xgene_pmu = dev_get_drvdata(&pdev->dev);
1987 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->l3cpmus);
1988 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->iobpmus);
1989 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcbpmus);
1990 xgene_pmu_dev_cleanup(xgene_pmu, &xgene_pmu->mcpmus);
1991 cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_APM_XGENE_ONLINE,
1997 static struct platform_driver xgene_pmu_driver = {
1998 .probe = xgene_pmu_probe,
1999 .remove = xgene_pmu_remove,
2001 .name = "xgene-pmu",
2002 .of_match_table = xgene_pmu_of_match,
2003 .acpi_match_table = ACPI_PTR(xgene_pmu_acpi_match),
2007 builtin_platform_driver(xgene_pmu_driver);