1 // SPDX-License-Identifier: GPL-2.0-only
3 * HiSilicon SoC Hardware event counters support
5 * Copyright (C) 2017 HiSilicon Limited
6 * Author: Anurup M <anurup.m@huawei.com>
7 * Shaokun Zhang <zhangshaokun@hisilicon.com>
9 * This code is based on the uncore PMUs like arm-cci and arm-ccn.
11 #include <linux/bitmap.h>
12 #include <linux/bitops.h>
13 #include <linux/bug.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
18 #include <asm/cputype.h>
19 #include <asm/local64.h>
21 #include "hisi_uncore_pmu.h"
23 #define HISI_GET_EVENTID(ev) (ev->hw.config_base & 0xff)
24 #define HISI_MAX_PERIOD(nr) (GENMASK_ULL((nr) - 1, 0))
27 * PMU format attributes
29 ssize_t hisi_format_sysfs_show(struct device *dev,
30 struct device_attribute *attr, char *buf)
32 struct dev_ext_attribute *eattr;
34 eattr = container_of(attr, struct dev_ext_attribute, attr);
36 return sysfs_emit(buf, "%s\n", (char *)eattr->var);
38 EXPORT_SYMBOL_GPL(hisi_format_sysfs_show);
41 * PMU event attributes
43 ssize_t hisi_event_sysfs_show(struct device *dev,
44 struct device_attribute *attr, char *page)
46 struct dev_ext_attribute *eattr;
48 eattr = container_of(attr, struct dev_ext_attribute, attr);
50 return sysfs_emit(page, "config=0x%lx\n", (unsigned long)eattr->var);
52 EXPORT_SYMBOL_GPL(hisi_event_sysfs_show);
55 * sysfs cpumask attributes. For uncore PMU, we only have a single CPU to show
57 ssize_t hisi_cpumask_sysfs_show(struct device *dev,
58 struct device_attribute *attr, char *buf)
60 struct hisi_pmu *hisi_pmu = to_hisi_pmu(dev_get_drvdata(dev));
62 return sysfs_emit(buf, "%d\n", hisi_pmu->on_cpu);
64 EXPORT_SYMBOL_GPL(hisi_cpumask_sysfs_show);
66 static bool hisi_validate_event_group(struct perf_event *event)
68 struct perf_event *sibling, *leader = event->group_leader;
69 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
70 /* Include count for the event */
73 if (!is_software_event(leader)) {
75 * We must NOT create groups containing mixed PMUs, although
76 * software events are acceptable
78 if (leader->pmu != event->pmu)
81 /* Increment counter for the leader */
86 for_each_sibling_event(sibling, event->group_leader) {
87 if (is_software_event(sibling))
89 if (sibling->pmu != event->pmu)
91 /* Increment counter for each sibling */
95 /* The group can not count events more than the counters in the HW */
96 return counters <= hisi_pmu->num_counters;
99 int hisi_uncore_pmu_get_event_idx(struct perf_event *event)
101 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
102 unsigned long *used_mask = hisi_pmu->pmu_events.used_mask;
103 u32 num_counters = hisi_pmu->num_counters;
106 idx = find_first_zero_bit(used_mask, num_counters);
107 if (idx == num_counters)
110 set_bit(idx, used_mask);
114 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_get_event_idx);
116 ssize_t hisi_uncore_pmu_identifier_attr_show(struct device *dev,
117 struct device_attribute *attr,
120 struct hisi_pmu *hisi_pmu = to_hisi_pmu(dev_get_drvdata(dev));
122 return sysfs_emit(page, "0x%08x\n", hisi_pmu->identifier);
124 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_identifier_attr_show);
126 static void hisi_uncore_pmu_clear_event_idx(struct hisi_pmu *hisi_pmu, int idx)
128 clear_bit(idx, hisi_pmu->pmu_events.used_mask);
131 static irqreturn_t hisi_uncore_pmu_isr(int irq, void *data)
133 struct hisi_pmu *hisi_pmu = data;
134 struct perf_event *event;
135 unsigned long overflown;
138 overflown = hisi_pmu->ops->get_int_status(hisi_pmu);
143 * Find the counter index which overflowed if the bit was set
146 for_each_set_bit(idx, &overflown, hisi_pmu->num_counters) {
147 /* Write 1 to clear the IRQ status flag */
148 hisi_pmu->ops->clear_int_status(hisi_pmu, idx);
149 /* Get the corresponding event struct */
150 event = hisi_pmu->pmu_events.hw_events[idx];
154 hisi_uncore_pmu_event_update(event);
155 hisi_uncore_pmu_set_event_period(event);
161 int hisi_uncore_pmu_init_irq(struct hisi_pmu *hisi_pmu,
162 struct platform_device *pdev)
166 irq = platform_get_irq(pdev, 0);
170 ret = devm_request_irq(&pdev->dev, irq, hisi_uncore_pmu_isr,
171 IRQF_NOBALANCING | IRQF_NO_THREAD,
172 dev_name(&pdev->dev), hisi_pmu);
175 "Fail to request IRQ: %d ret: %d.\n", irq, ret);
183 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_init_irq);
185 int hisi_uncore_pmu_event_init(struct perf_event *event)
187 struct hw_perf_event *hwc = &event->hw;
188 struct hisi_pmu *hisi_pmu;
190 if (event->attr.type != event->pmu->type)
194 * We do not support sampling as the counters are all
195 * shared by all CPU cores in a CPU die(SCCL). Also we
196 * do not support attach to a task(per-process mode)
198 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
202 * The uncore counters not specific to any CPU, so cannot
209 * Validate if the events in group does not exceed the
210 * available counters in hardware.
212 if (!hisi_validate_event_group(event))
215 hisi_pmu = to_hisi_pmu(event->pmu);
216 if (event->attr.config > hisi_pmu->check_event)
219 if (hisi_pmu->on_cpu == -1)
222 * We don't assign an index until we actually place the event onto
223 * hardware. Use -1 to signify that we haven't decided where to put it
227 hwc->config_base = event->attr.config;
229 /* Enforce to use the same CPU for all events in this PMU */
230 event->cpu = hisi_pmu->on_cpu;
234 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_event_init);
237 * Set the counter to count the event that we're interested in,
238 * and enable interrupt and counter.
240 static void hisi_uncore_pmu_enable_event(struct perf_event *event)
242 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
243 struct hw_perf_event *hwc = &event->hw;
245 hisi_pmu->ops->write_evtype(hisi_pmu, hwc->idx,
246 HISI_GET_EVENTID(event));
248 if (hisi_pmu->ops->enable_filter)
249 hisi_pmu->ops->enable_filter(event);
251 hisi_pmu->ops->enable_counter_int(hisi_pmu, hwc);
252 hisi_pmu->ops->enable_counter(hisi_pmu, hwc);
256 * Disable counter and interrupt.
258 static void hisi_uncore_pmu_disable_event(struct perf_event *event)
260 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
261 struct hw_perf_event *hwc = &event->hw;
263 hisi_pmu->ops->disable_counter(hisi_pmu, hwc);
264 hisi_pmu->ops->disable_counter_int(hisi_pmu, hwc);
266 if (hisi_pmu->ops->disable_filter)
267 hisi_pmu->ops->disable_filter(event);
270 void hisi_uncore_pmu_set_event_period(struct perf_event *event)
272 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
273 struct hw_perf_event *hwc = &event->hw;
276 * The HiSilicon PMU counters support 32 bits or 48 bits, depending on
277 * the PMU. We reduce it to 2^(counter_bits - 1) to account for the
278 * extreme interrupt latency. So we could hopefully handle the overflow
279 * interrupt before another 2^(counter_bits - 1) events occur and the
280 * counter overtakes its previous value.
282 u64 val = BIT_ULL(hisi_pmu->counter_bits - 1);
284 local64_set(&hwc->prev_count, val);
285 /* Write start value to the hardware event counter */
286 hisi_pmu->ops->write_counter(hisi_pmu, hwc, val);
288 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_set_event_period);
290 void hisi_uncore_pmu_event_update(struct perf_event *event)
292 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
293 struct hw_perf_event *hwc = &event->hw;
294 u64 delta, prev_raw_count, new_raw_count;
297 /* Read the count from the counter register */
298 new_raw_count = hisi_pmu->ops->read_counter(hisi_pmu, hwc);
299 prev_raw_count = local64_read(&hwc->prev_count);
300 } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
301 new_raw_count) != prev_raw_count);
305 delta = (new_raw_count - prev_raw_count) &
306 HISI_MAX_PERIOD(hisi_pmu->counter_bits);
307 local64_add(delta, &event->count);
309 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_event_update);
311 void hisi_uncore_pmu_start(struct perf_event *event, int flags)
313 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
314 struct hw_perf_event *hwc = &event->hw;
316 if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
319 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
321 hisi_uncore_pmu_set_event_period(event);
323 if (flags & PERF_EF_RELOAD) {
324 u64 prev_raw_count = local64_read(&hwc->prev_count);
326 hisi_pmu->ops->write_counter(hisi_pmu, hwc, prev_raw_count);
329 hisi_uncore_pmu_enable_event(event);
330 perf_event_update_userpage(event);
332 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_start);
334 void hisi_uncore_pmu_stop(struct perf_event *event, int flags)
336 struct hw_perf_event *hwc = &event->hw;
338 hisi_uncore_pmu_disable_event(event);
339 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
340 hwc->state |= PERF_HES_STOPPED;
342 if (hwc->state & PERF_HES_UPTODATE)
345 /* Read hardware counter and update the perf counter statistics */
346 hisi_uncore_pmu_event_update(event);
347 hwc->state |= PERF_HES_UPTODATE;
349 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_stop);
351 int hisi_uncore_pmu_add(struct perf_event *event, int flags)
353 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
354 struct hw_perf_event *hwc = &event->hw;
357 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
359 /* Get an available counter index for counting */
360 idx = hisi_pmu->ops->get_event_idx(event);
365 hisi_pmu->pmu_events.hw_events[idx] = event;
367 if (flags & PERF_EF_START)
368 hisi_uncore_pmu_start(event, PERF_EF_RELOAD);
372 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_add);
374 void hisi_uncore_pmu_del(struct perf_event *event, int flags)
376 struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
377 struct hw_perf_event *hwc = &event->hw;
379 hisi_uncore_pmu_stop(event, PERF_EF_UPDATE);
380 hisi_uncore_pmu_clear_event_idx(hisi_pmu, hwc->idx);
381 perf_event_update_userpage(event);
382 hisi_pmu->pmu_events.hw_events[hwc->idx] = NULL;
384 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_del);
386 void hisi_uncore_pmu_read(struct perf_event *event)
388 /* Read hardware counter and update the perf counter statistics */
389 hisi_uncore_pmu_event_update(event);
391 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_read);
393 void hisi_uncore_pmu_enable(struct pmu *pmu)
395 struct hisi_pmu *hisi_pmu = to_hisi_pmu(pmu);
396 int enabled = bitmap_weight(hisi_pmu->pmu_events.used_mask,
397 hisi_pmu->num_counters);
402 hisi_pmu->ops->start_counters(hisi_pmu);
404 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_enable);
406 void hisi_uncore_pmu_disable(struct pmu *pmu)
408 struct hisi_pmu *hisi_pmu = to_hisi_pmu(pmu);
410 hisi_pmu->ops->stop_counters(hisi_pmu);
412 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_disable);
416 * The Super CPU Cluster (SCCL) and CPU Cluster (CCL) IDs can be
417 * determined from the MPIDR_EL1, but the encoding varies by CPU:
419 * - For MT variants of TSV110:
420 * SCCL is Aff2[7:3], CCL is Aff2[2:0]
422 * - For other MT parts:
423 * SCCL is Aff3[7:0], CCL is Aff2[7:0]
425 * - For non-MT parts:
426 * SCCL is Aff2[7:0], CCL is Aff1[7:0]
428 static void hisi_read_sccl_and_ccl_id(int *scclp, int *cclp)
430 u64 mpidr = read_cpuid_mpidr();
431 int aff3 = MPIDR_AFFINITY_LEVEL(mpidr, 3);
432 int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
433 int aff1 = MPIDR_AFFINITY_LEVEL(mpidr, 1);
434 bool mt = mpidr & MPIDR_MT_BITMASK;
437 if (mt && read_cpuid_part_number() == HISI_CPU_PART_TSV110) {
455 * Check whether the CPU is associated with this uncore PMU
457 static bool hisi_pmu_cpu_is_associated_pmu(struct hisi_pmu *hisi_pmu)
461 if (hisi_pmu->ccl_id == -1) {
462 /* If CCL_ID is -1, the PMU only shares the same SCCL */
463 hisi_read_sccl_and_ccl_id(&sccl_id, NULL);
465 return sccl_id == hisi_pmu->sccl_id;
468 hisi_read_sccl_and_ccl_id(&sccl_id, &ccl_id);
470 return sccl_id == hisi_pmu->sccl_id && ccl_id == hisi_pmu->ccl_id;
473 int hisi_uncore_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
475 struct hisi_pmu *hisi_pmu = hlist_entry_safe(node, struct hisi_pmu,
478 if (!hisi_pmu_cpu_is_associated_pmu(hisi_pmu))
481 cpumask_set_cpu(cpu, &hisi_pmu->associated_cpus);
483 /* If another CPU is already managing this PMU, simply return. */
484 if (hisi_pmu->on_cpu != -1)
487 /* Use this CPU in cpumask for event counting */
488 hisi_pmu->on_cpu = cpu;
490 /* Overflow interrupt also should use the same CPU */
491 WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(cpu)));
495 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_online_cpu);
497 int hisi_uncore_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
499 struct hisi_pmu *hisi_pmu = hlist_entry_safe(node, struct hisi_pmu,
501 cpumask_t pmu_online_cpus;
504 if (!cpumask_test_and_clear_cpu(cpu, &hisi_pmu->associated_cpus))
507 /* Nothing to do if this CPU doesn't own the PMU */
508 if (hisi_pmu->on_cpu != cpu)
511 /* Give up ownership of the PMU */
512 hisi_pmu->on_cpu = -1;
514 /* Choose a new CPU to migrate ownership of the PMU to */
515 cpumask_and(&pmu_online_cpus, &hisi_pmu->associated_cpus,
517 target = cpumask_any_but(&pmu_online_cpus, cpu);
518 if (target >= nr_cpu_ids)
521 perf_pmu_migrate_context(&hisi_pmu->pmu, cpu, target);
522 /* Use this CPU for event counting */
523 hisi_pmu->on_cpu = target;
524 WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(target)));
528 EXPORT_SYMBOL_GPL(hisi_uncore_pmu_offline_cpu);
530 MODULE_LICENSE("GPL v2");