drivers/perf/fsl_imx8_ddr_perf.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2017 NXP
   4  * Copyright 2016 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <linux/bitfield.h>
   8 #include <linux/init.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/io.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_device.h>
  15 #include <linux/of_irq.h>
  16 #include <linux/perf_event.h>
  17 #include <linux/slab.h>
  18
  19 #define COUNTER_CNTL            0x0
  20 #define COUNTER_READ            0x20
  21
  22 #define COUNTER_DPCR1           0x30
  23
  24 #define CNTL_OVER               0x1
  25 #define CNTL_CLEAR              0x2
  26 #define CNTL_EN                 0x4
  27 #define CNTL_EN_MASK            0xFFFFFFFB
  28 #define CNTL_CLEAR_MASK         0xFFFFFFFD
  29 #define CNTL_OVER_MASK          0xFFFFFFFE
  30
  31 #define CNTL_CSV_SHIFT          24
  32 #define CNTL_CSV_MASK           (0xFF << CNTL_CSV_SHIFT)
  33
  34 #define EVENT_CYCLES_ID         0
  35 #define EVENT_CYCLES_COUNTER    0
  36 #define NUM_COUNTERS            4
  37
  38 #define AXI_MASKING_REVERT      0xffff0000      /* AXI_MASKING(MSB 16bits) + AXI_ID(LSB 16bits) */
  39
  40 #define to_ddr_pmu(p)           container_of(p, struct ddr_pmu, pmu)
  41
  42 #define DDR_PERF_DEV_NAME       "imx8_ddr"
  43 #define DDR_CPUHP_CB_NAME       DDR_PERF_DEV_NAME "_perf_pmu"
  44
  45 static DEFINE_IDA(ddr_ida);
  46
  47 /* DDR Perf hardware feature */
  48 #define DDR_CAP_AXI_ID_FILTER                   0x1     /* support AXI ID filter */
  49 #define DDR_CAP_AXI_ID_FILTER_ENHANCED          0x3     /* support enhanced AXI ID filter */
  50
  51 struct fsl_ddr_devtype_data {
  52         unsigned int quirks;    /* quirks needed for different DDR Perf core */
  53         const char *identifier; /* system PMU identifier for userspace */
  54 };
  55
  56 static const struct fsl_ddr_devtype_data imx8_devtype_data;
  57
  58 static const struct fsl_ddr_devtype_data imx8m_devtype_data = {
  59         .quirks = DDR_CAP_AXI_ID_FILTER,
  60 };
  61
  62 static const struct fsl_ddr_devtype_data imx8mq_devtype_data = {
  63         .quirks = DDR_CAP_AXI_ID_FILTER,
  64         .identifier = "i.MX8MQ",
  65 };
  66
  67 static const struct fsl_ddr_devtype_data imx8mm_devtype_data = {
  68         .quirks = DDR_CAP_AXI_ID_FILTER,
  69         .identifier = "i.MX8MM",
  70 };
  71
  72 static const struct fsl_ddr_devtype_data imx8mn_devtype_data = {
  73         .quirks = DDR_CAP_AXI_ID_FILTER,
  74         .identifier = "i.MX8MN",
  75 };
  76
  77 static const struct fsl_ddr_devtype_data imx8mp_devtype_data = {
  78         .quirks = DDR_CAP_AXI_ID_FILTER_ENHANCED,
  79         .identifier = "i.MX8MP",
  80 };
  81
  82 static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
  83         { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
  84         { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
  85         { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
  86         { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
  87         { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
  88         { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
  89         { /* sentinel */ }
  90 };
  91 MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids);
  92
  93 struct ddr_pmu {
  94         struct pmu pmu;
  95         void __iomem *base;
  96         unsigned int cpu;
  97         struct  hlist_node node;
  98         struct  device *dev;
  99         struct perf_event *events[NUM_COUNTERS];
 100         int active_events;
 101         enum cpuhp_state cpuhp_state;
 102         const struct fsl_ddr_devtype_data *devtype_data;
 103         int irq;
 104         int id;
 105 };
 106
 107 static ssize_t ddr_perf_identifier_show(struct device *dev,
 108                                         struct device_attribute *attr,
 109                                         char *page)
 110 {
 111         struct ddr_pmu *pmu = dev_get_drvdata(dev);
 112
 113         return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier);
 114 }
 115
 116 static umode_t ddr_perf_identifier_attr_visible(struct kobject *kobj,
 117                                                 struct attribute *attr,
 118                                                 int n)
 119 {
 120         struct device *dev = kobj_to_dev(kobj);
 121         struct ddr_pmu *pmu = dev_get_drvdata(dev);
 122
 123         if (!pmu->devtype_data->identifier)
 124                 return 0;
 125         return attr->mode;
 126 };
 127
 128 static struct device_attribute ddr_perf_identifier_attr =
 129         __ATTR(identifier, 0444, ddr_perf_identifier_show, NULL);
 130
 131 static struct attribute *ddr_perf_identifier_attrs[] = {
 132         &ddr_perf_identifier_attr.attr,
 133         NULL,
 134 };
 135
 136 static const struct attribute_group ddr_perf_identifier_attr_group = {
 137         .attrs = ddr_perf_identifier_attrs,
 138         .is_visible = ddr_perf_identifier_attr_visible,
 139 };
 140
 141 enum ddr_perf_filter_capabilities {
 142         PERF_CAP_AXI_ID_FILTER = 0,
 143         PERF_CAP_AXI_ID_FILTER_ENHANCED,
 144         PERF_CAP_AXI_ID_FEAT_MAX,
 145 };
 146
 147 static u32 ddr_perf_filter_cap_get(struct ddr_pmu *pmu, int cap)
 148 {
 149         u32 quirks = pmu->devtype_data->quirks;
 150
 151         switch (cap) {
 152         case PERF_CAP_AXI_ID_FILTER:
 153                 return !!(quirks & DDR_CAP_AXI_ID_FILTER);
 154         case PERF_CAP_AXI_ID_FILTER_ENHANCED:
 155                 quirks &= DDR_CAP_AXI_ID_FILTER_ENHANCED;
 156                 return quirks == DDR_CAP_AXI_ID_FILTER_ENHANCED;
 157         default:
 158                 WARN(1, "unknown filter cap %d\n", cap);
 159         }
 160
 161         return 0;
 162 }
 163
 164 static ssize_t ddr_perf_filter_cap_show(struct device *dev,
 165                                         struct device_attribute *attr,
 166                                         char *buf)
 167 {
 168         struct ddr_pmu *pmu = dev_get_drvdata(dev);
 169         struct dev_ext_attribute *ea =
 170                 container_of(attr, struct dev_ext_attribute, attr);
 171         int cap = (long)ea->var;
 172
 173         return sysfs_emit(buf, "%u\n", ddr_perf_filter_cap_get(pmu, cap));
 174 }
 175
 176 #define PERF_EXT_ATTR_ENTRY(_name, _func, _var)                         \
 177         (&((struct dev_ext_attribute) {                                 \
 178                 __ATTR(_name, 0444, _func, NULL), (void *)_var          \
 179         }).attr.attr)
 180
 181 #define PERF_FILTER_EXT_ATTR_ENTRY(_name, _var)                         \
 182         PERF_EXT_ATTR_ENTRY(_name, ddr_perf_filter_cap_show, _var)
 183
 184 static struct attribute *ddr_perf_filter_cap_attr[] = {
 185         PERF_FILTER_EXT_ATTR_ENTRY(filter, PERF_CAP_AXI_ID_FILTER),
 186         PERF_FILTER_EXT_ATTR_ENTRY(enhanced_filter, PERF_CAP_AXI_ID_FILTER_ENHANCED),
 187         NULL,
 188 };
 189
 190 static const struct attribute_group ddr_perf_filter_cap_attr_group = {
 191         .name = "caps",
 192         .attrs = ddr_perf_filter_cap_attr,
 193 };
 194
 195 static ssize_t ddr_perf_cpumask_show(struct device *dev,
 196                                 struct device_attribute *attr, char *buf)
 197 {
 198         struct ddr_pmu *pmu = dev_get_drvdata(dev);
 199
 200         return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu));
 201 }
 202
 203 static struct device_attribute ddr_perf_cpumask_attr =
 204         __ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL);
 205
 206 static struct attribute *ddr_perf_cpumask_attrs[] = {
 207         &ddr_perf_cpumask_attr.attr,
 208         NULL,
 209 };
 210
 211 static const struct attribute_group ddr_perf_cpumask_attr_group = {
 212         .attrs = ddr_perf_cpumask_attrs,
 213 };
 214
 215 static ssize_t
 216 ddr_pmu_event_show(struct device *dev, struct device_attribute *attr,
 217                    char *page)
 218 {
 219         struct perf_pmu_events_attr *pmu_attr;
 220
 221         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
 222         return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id);
 223 }
 224
 225 #define IMX8_DDR_PMU_EVENT_ATTR(_name, _id)                             \
 226         (&((struct perf_pmu_events_attr[]) {                            \
 227                 { .attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\
 228                   .id = _id, }                                          \
 229         })[0].attr.attr)
 230
 231 static struct attribute *ddr_perf_events_attrs[] = {
 232         IMX8_DDR_PMU_EVENT_ATTR(cycles, EVENT_CYCLES_ID),
 233         IMX8_DDR_PMU_EVENT_ATTR(selfresh, 0x01),
 234         IMX8_DDR_PMU_EVENT_ATTR(read-accesses, 0x04),
 235         IMX8_DDR_PMU_EVENT_ATTR(write-accesses, 0x05),
 236         IMX8_DDR_PMU_EVENT_ATTR(read-queue-depth, 0x08),
 237         IMX8_DDR_PMU_EVENT_ATTR(write-queue-depth, 0x09),
 238         IMX8_DDR_PMU_EVENT_ATTR(lp-read-credit-cnt, 0x10),
 239         IMX8_DDR_PMU_EVENT_ATTR(hp-read-credit-cnt, 0x11),
 240         IMX8_DDR_PMU_EVENT_ATTR(write-credit-cnt, 0x12),
 241         IMX8_DDR_PMU_EVENT_ATTR(read-command, 0x20),
 242         IMX8_DDR_PMU_EVENT_ATTR(write-command, 0x21),
 243         IMX8_DDR_PMU_EVENT_ATTR(read-modify-write-command, 0x22),
 244         IMX8_DDR_PMU_EVENT_ATTR(hp-read, 0x23),
 245         IMX8_DDR_PMU_EVENT_ATTR(hp-req-nocredit, 0x24),
 246         IMX8_DDR_PMU_EVENT_ATTR(hp-xact-credit, 0x25),
 247         IMX8_DDR_PMU_EVENT_ATTR(lp-req-nocredit, 0x26),
 248         IMX8_DDR_PMU_EVENT_ATTR(lp-xact-credit, 0x27),
 249         IMX8_DDR_PMU_EVENT_ATTR(wr-xact-credit, 0x29),
 250         IMX8_DDR_PMU_EVENT_ATTR(read-cycles, 0x2a),
 251         IMX8_DDR_PMU_EVENT_ATTR(write-cycles, 0x2b),
 252         IMX8_DDR_PMU_EVENT_ATTR(read-write-transition, 0x30),
 253         IMX8_DDR_PMU_EVENT_ATTR(precharge, 0x31),
 254         IMX8_DDR_PMU_EVENT_ATTR(activate, 0x32),
 255         IMX8_DDR_PMU_EVENT_ATTR(load-mode, 0x33),
 256         IMX8_DDR_PMU_EVENT_ATTR(perf-mwr, 0x34),
 257         IMX8_DDR_PMU_EVENT_ATTR(read, 0x35),
 258         IMX8_DDR_PMU_EVENT_ATTR(read-activate, 0x36),
 259         IMX8_DDR_PMU_EVENT_ATTR(refresh, 0x37),
 260         IMX8_DDR_PMU_EVENT_ATTR(write, 0x38),
 261         IMX8_DDR_PMU_EVENT_ATTR(raw-hazard, 0x39),
 262         IMX8_DDR_PMU_EVENT_ATTR(axid-read, 0x41),
 263         IMX8_DDR_PMU_EVENT_ATTR(axid-write, 0x42),
 264         NULL,
 265 };
 266
 267 static const struct attribute_group ddr_perf_events_attr_group = {
 268         .name = "events",
 269         .attrs = ddr_perf_events_attrs,
 270 };
 271
 272 PMU_FORMAT_ATTR(event, "config:0-7");
 273 PMU_FORMAT_ATTR(axi_id, "config1:0-15");
 274 PMU_FORMAT_ATTR(axi_mask, "config1:16-31");
 275
 276 static struct attribute *ddr_perf_format_attrs[] = {
 277         &format_attr_event.attr,
 278         &format_attr_axi_id.attr,
 279         &format_attr_axi_mask.attr,
 280         NULL,
 281 };
 282
 283 static const struct attribute_group ddr_perf_format_attr_group = {
 284         .name = "format",
 285         .attrs = ddr_perf_format_attrs,
 286 };
 287
 288 static const struct attribute_group *attr_groups[] = {
 289         &ddr_perf_events_attr_group,
 290         &ddr_perf_format_attr_group,
 291         &ddr_perf_cpumask_attr_group,
 292         &ddr_perf_filter_cap_attr_group,
 293         &ddr_perf_identifier_attr_group,
 294         NULL,
 295 };
 296
 297 static bool ddr_perf_is_filtered(struct perf_event *event)
 298 {
 299         return event->attr.config == 0x41 || event->attr.config == 0x42;
 300 }
 301
 302 static u32 ddr_perf_filter_val(struct perf_event *event)
 303 {
 304         return event->attr.config1;
 305 }
 306
 307 static bool ddr_perf_filters_compatible(struct perf_event *a,
 308                                         struct perf_event *b)
 309 {
 310         if (!ddr_perf_is_filtered(a))
 311                 return true;
 312         if (!ddr_perf_is_filtered(b))
 313                 return true;
 314         return ddr_perf_filter_val(a) == ddr_perf_filter_val(b);
 315 }
 316
 317 static bool ddr_perf_is_enhanced_filtered(struct perf_event *event)
 318 {
 319         unsigned int filt;
 320         struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
 321
 322         filt = pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER_ENHANCED;
 323         return (filt == DDR_CAP_AXI_ID_FILTER_ENHANCED) &&
 324                 ddr_perf_is_filtered(event);
 325 }
 326
 327 static u32 ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event)
 328 {
 329         int i;
 330
 331         /*
 332          * Always map cycle event to counter 0
 333          * Cycles counter is dedicated for cycle event
 334          * can't used for the other events
 335          */
 336         if (event == EVENT_CYCLES_ID) {
 337                 if (pmu->events[EVENT_CYCLES_COUNTER] == NULL)
 338                         return EVENT_CYCLES_COUNTER;
 339                 else
 340                         return -ENOENT;
 341         }
 342
 343         for (i = 1; i < NUM_COUNTERS; i++) {
 344                 if (pmu->events[i] == NULL)
 345                         return i;
 346         }
 347
 348         return -ENOENT;
 349 }
 350
 351 static void ddr_perf_free_counter(struct ddr_pmu *pmu, int counter)
 352 {
 353         pmu->events[counter] = NULL;
 354 }
 355
 356 static u32 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter)
 357 {
 358         struct perf_event *event = pmu->events[counter];
 359         void __iomem *base = pmu->base;
 360
 361         /*
 362          * return bytes instead of bursts from ddr transaction for
 363          * axid-read and axid-write event if PMU core supports enhanced
 364          * filter.
 365          */
 366         base += ddr_perf_is_enhanced_filtered(event) ? COUNTER_DPCR1 :
 367                                                        COUNTER_READ;
 368         return readl_relaxed(base + counter * 4);
 369 }
 370
 371 static int ddr_perf_event_init(struct perf_event *event)
 372 {
 373         struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
 374         struct hw_perf_event *hwc = &event->hw;
 375         struct perf_event *sibling;
 376
 377         if (event->attr.type != event->pmu->type)
 378                 return -ENOENT;
 379
 380         if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
 381                 return -EOPNOTSUPP;
 382
 383         if (event->cpu < 0) {
 384                 dev_warn(pmu->dev, "Can't provide per-task data!\n");
 385                 return -EOPNOTSUPP;
 386         }
 387
 388         /*
 389          * We must NOT create groups containing mixed PMUs, although software
 390          * events are acceptable (for example to create a CCN group
 391          * periodically read when a hrtimer aka cpu-clock leader triggers).
 392          */
 393         if (event->group_leader->pmu != event->pmu &&
 394                         !is_software_event(event->group_leader))
 395                 return -EINVAL;
 396
 397         if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) {
 398                 if (!ddr_perf_filters_compatible(event, event->group_leader))
 399                         return -EINVAL;
 400                 for_each_sibling_event(sibling, event->group_leader) {
 401                         if (!ddr_perf_filters_compatible(event, sibling))
 402                                 return -EINVAL;
 403                 }
 404         }
 405
 406         for_each_sibling_event(sibling, event->group_leader) {
 407                 if (sibling->pmu != event->pmu &&
 408                                 !is_software_event(sibling))
 409                         return -EINVAL;
 410         }
 411
 412         event->cpu = pmu->cpu;
 413         hwc->idx = -1;
 414
 415         return 0;
 416 }
 417
 418 static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config,
 419                                   int counter, bool enable)
 420 {
 421         u8 reg = counter * 4 + COUNTER_CNTL;
 422         int val;
 423
 424         if (enable) {
 425                 /*
 426                  * cycle counter is special which should firstly write 0 then
 427                  * write 1 into CLEAR bit to clear it. Other counters only
 428                  * need write 0 into CLEAR bit and it turns out to be 1 by
 429                  * hardware. Below enable flow is harmless for all counters.
 430                  */
 431                 writel(0, pmu->base + reg);
 432                 val = CNTL_EN | CNTL_CLEAR;
 433                 val |= FIELD_PREP(CNTL_CSV_MASK, config);
 434                 writel(val, pmu->base + reg);
 435         } else {
 436                 /* Disable counter */
 437                 val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK;
 438                 writel(val, pmu->base + reg);
 439         }
 440 }
 441
 442 static bool ddr_perf_counter_overflow(struct ddr_pmu *pmu, int counter)
 443 {
 444         int val;
 445
 446         val = readl_relaxed(pmu->base + counter * 4 + COUNTER_CNTL);
 447
 448         return val & CNTL_OVER;
 449 }
 450
 451 static void ddr_perf_counter_clear(struct ddr_pmu *pmu, int counter)
 452 {
 453         u8 reg = counter * 4 + COUNTER_CNTL;
 454         int val;
 455
 456         val = readl_relaxed(pmu->base + reg);
 457         val &= ~CNTL_CLEAR;
 458         writel(val, pmu->base + reg);
 459
 460         val |= CNTL_CLEAR;
 461         writel(val, pmu->base + reg);
 462 }
 463
 464 static void ddr_perf_event_update(struct perf_event *event)
 465 {
 466         struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
 467         struct hw_perf_event *hwc = &event->hw;
 468         u64 new_raw_count;
 469         int counter = hwc->idx;
 470         int ret;
 471
 472         new_raw_count = ddr_perf_read_counter(pmu, counter);
 473         local64_add(new_raw_count, &event->count);
 474
 475         /*
 476          * For legacy SoCs: event counter continue counting when overflow,
 477          *                  no need to clear the counter.
 478          * For new SoCs: event counter stop counting when overflow, need
 479          *               clear counter to let it count again.
 480          */
 481         if (counter != EVENT_CYCLES_COUNTER) {
 482                 ret = ddr_perf_counter_overflow(pmu, counter);
 483                 if (ret)
 484                         dev_warn_ratelimited(pmu->dev,  "events lost due to counter overflow (config 0x%llx)\n",
 485                                              event->attr.config);
 486         }
 487
 488         /* clear counter every time for both cycle counter and event counter */
 489         ddr_perf_counter_clear(pmu, counter);
 490 }
 491
 492 static void ddr_perf_event_start(struct perf_event *event, int flags)
 493 {
 494         struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
 495         struct hw_perf_event *hwc = &event->hw;
 496         int counter = hwc->idx;
 497
 498         local64_set(&hwc->prev_count, 0);
 499
 500         ddr_perf_counter_enable(pmu, event->attr.config, counter, true);
 501
 502         hwc->state = 0;
 503 }
 504
 505 static int ddr_perf_event_add(struct perf_event *event, int flags)
 506 {
 507         struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
 508         struct hw_perf_event *hwc = &event->hw;
 509         int counter;
 510         int cfg = event->attr.config;
 511         int cfg1 = event->attr.config1;
 512
 513         if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) {
 514                 int i;
 515
 516                 for (i = 1; i < NUM_COUNTERS; i++) {
 517                         if (pmu->events[i] &&
 518                             !ddr_perf_filters_compatible(event, pmu->events[i]))
 519                                 return -EINVAL;
 520                 }
 521
 522                 if (ddr_perf_is_filtered(event)) {
 523                         /* revert axi id masking(axi_mask) value */
 524                         cfg1 ^= AXI_MASKING_REVERT;
 525                         writel(cfg1, pmu->base + COUNTER_DPCR1);
 526                 }
 527         }
 528
 529         counter = ddr_perf_alloc_counter(pmu, cfg);
 530         if (counter < 0) {
 531                 dev_dbg(pmu->dev, "There are not enough counters\n");
 532                 return -EOPNOTSUPP;
 533         }
 534
 535         pmu->events[counter] = event;
 536         pmu->active_events++;
 537         hwc->idx = counter;
 538
 539         hwc->state |= PERF_HES_STOPPED;
 540
 541         if (flags & PERF_EF_START)
 542                 ddr_perf_event_start(event, flags);
 543
 544         return 0;
 545 }
 546
 547 static void ddr_perf_event_stop(struct perf_event *event, int flags)
 548 {
 549         struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
 550         struct hw_perf_event *hwc = &event->hw;
 551         int counter = hwc->idx;
 552
 553         ddr_perf_counter_enable(pmu, event->attr.config, counter, false);
 554         ddr_perf_event_update(event);
 555
 556         hwc->state |= PERF_HES_STOPPED;
 557 }
 558
 559 static void ddr_perf_event_del(struct perf_event *event, int flags)
 560 {
 561         struct ddr_pmu *pmu = to_ddr_pmu(event->pmu);
 562         struct hw_perf_event *hwc = &event->hw;
 563         int counter = hwc->idx;
 564
 565         ddr_perf_event_stop(event, PERF_EF_UPDATE);
 566
 567         ddr_perf_free_counter(pmu, counter);
 568         pmu->active_events--;
 569         hwc->idx = -1;
 570 }
 571
 572 static void ddr_perf_pmu_enable(struct pmu *pmu)
 573 {
 574         struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
 575
 576         /* enable cycle counter if cycle is not active event list */
 577         if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL)
 578                 ddr_perf_counter_enable(ddr_pmu,
 579                                       EVENT_CYCLES_ID,
 580                                       EVENT_CYCLES_COUNTER,
 581                                       true);
 582 }
 583
 584 static void ddr_perf_pmu_disable(struct pmu *pmu)
 585 {
 586         struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
 587
 588         if (ddr_pmu->events[EVENT_CYCLES_COUNTER] == NULL)
 589                 ddr_perf_counter_enable(ddr_pmu,
 590                                       EVENT_CYCLES_ID,
 591                                       EVENT_CYCLES_COUNTER,
 592                                       false);
 593 }
 594
 595 static int ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base,
 596                          struct device *dev)
 597 {
 598         *pmu = (struct ddr_pmu) {
 599                 .pmu = (struct pmu) {
 600                         .module       = THIS_MODULE,
 601                         .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
 602                         .task_ctx_nr = perf_invalid_context,
 603                         .attr_groups = attr_groups,
 604                         .event_init  = ddr_perf_event_init,
 605                         .add         = ddr_perf_event_add,
 606                         .del         = ddr_perf_event_del,
 607                         .start       = ddr_perf_event_start,
 608                         .stop        = ddr_perf_event_stop,
 609                         .read        = ddr_perf_event_update,
 610                         .pmu_enable  = ddr_perf_pmu_enable,
 611                         .pmu_disable = ddr_perf_pmu_disable,
 612                 },
 613                 .base = base,
 614                 .dev = dev,
 615         };
 616
 617         pmu->id = ida_simple_get(&ddr_ida, 0, 0, GFP_KERNEL);
 618         return pmu->id;
 619 }
 620
 621 static irqreturn_t ddr_perf_irq_handler(int irq, void *p)
 622 {
 623         int i;
 624         struct ddr_pmu *pmu = (struct ddr_pmu *) p;
 625         struct perf_event *event;
 626
 627         /* all counter will stop if cycle counter disabled */
 628         ddr_perf_counter_enable(pmu,
 629                               EVENT_CYCLES_ID,
 630                               EVENT_CYCLES_COUNTER,
 631                               false);
 632         /*
 633          * When the cycle counter overflows, all counters are stopped,
 634          * and an IRQ is raised. If any other counter overflows, it
 635          * continues counting, and no IRQ is raised. But for new SoCs,
 636          * such as i.MX8MP, event counter would stop when overflow, so
 637          * we need use cycle counter to stop overflow of event counter.
 638          *
 639          * Cycles occur at least 4 times as often as other events, so we
 640          * can update all events on a cycle counter overflow and not
 641          * lose events.
 642          *
 643          */
 644         for (i = 0; i < NUM_COUNTERS; i++) {
 645
 646                 if (!pmu->events[i])
 647                         continue;
 648
 649                 event = pmu->events[i];
 650
 651                 ddr_perf_event_update(event);
 652         }
 653
 654         ddr_perf_counter_enable(pmu,
 655                               EVENT_CYCLES_ID,
 656                               EVENT_CYCLES_COUNTER,
 657                               true);
 658
 659         return IRQ_HANDLED;
 660 }
 661
 662 static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node)
 663 {
 664         struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu, node);
 665         int target;
 666
 667         if (cpu != pmu->cpu)
 668                 return 0;
 669
 670         target = cpumask_any_but(cpu_online_mask, cpu);
 671         if (target >= nr_cpu_ids)
 672                 return 0;
 673
 674         perf_pmu_migrate_context(&pmu->pmu, cpu, target);
 675         pmu->cpu = target;
 676
 677         WARN_ON(irq_set_affinity_hint(pmu->irq, cpumask_of(pmu->cpu)));
 678
 679         return 0;
 680 }
 681
 682 static int ddr_perf_probe(struct platform_device *pdev)
 683 {
 684         struct ddr_pmu *pmu;
 685         struct device_node *np;
 686         void __iomem *base;
 687         char *name;
 688         int num;
 689         int ret;
 690         int irq;
 691
 692         base = devm_platform_ioremap_resource(pdev, 0);
 693         if (IS_ERR(base))
 694                 return PTR_ERR(base);
 695
 696         np = pdev->dev.of_node;
 697
 698         pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL);
 699         if (!pmu)
 700                 return -ENOMEM;
 701
 702         num = ddr_perf_init(pmu, base, &pdev->dev);
 703
 704         platform_set_drvdata(pdev, pmu);
 705
 706         name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d",
 707                               num);
 708         if (!name)
 709                 return -ENOMEM;
 710
 711         pmu->devtype_data = of_device_get_match_data(&pdev->dev);
 712
 713         pmu->cpu = raw_smp_processor_id();
 714         ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
 715                                       DDR_CPUHP_CB_NAME,
 716                                       NULL,
 717                                       ddr_perf_offline_cpu);
 718
 719         if (ret < 0) {
 720                 dev_err(&pdev->dev, "cpuhp_setup_state_multi failed\n");
 721                 goto cpuhp_state_err;
 722         }
 723
 724         pmu->cpuhp_state = ret;
 725
 726         /* Register the pmu instance for cpu hotplug */
 727         ret = cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node);
 728         if (ret) {
 729                 dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
 730                 goto cpuhp_instance_err;
 731         }
 732
 733         /* Request irq */
 734         irq = of_irq_get(np, 0);
 735         if (irq < 0) {
 736                 dev_err(&pdev->dev, "Failed to get irq: %d", irq);
 737                 ret = irq;
 738                 goto ddr_perf_err;
 739         }
 740
 741         ret = devm_request_irq(&pdev->dev, irq,
 742                                         ddr_perf_irq_handler,
 743                                         IRQF_NOBALANCING | IRQF_NO_THREAD,
 744                                         DDR_CPUHP_CB_NAME,
 745                                         pmu);
 746         if (ret < 0) {
 747                 dev_err(&pdev->dev, "Request irq failed: %d", ret);
 748                 goto ddr_perf_err;
 749         }
 750
 751         pmu->irq = irq;
 752         ret = irq_set_affinity_hint(pmu->irq, cpumask_of(pmu->cpu));
 753         if (ret) {
 754                 dev_err(pmu->dev, "Failed to set interrupt affinity!\n");
 755                 goto ddr_perf_err;
 756         }
 757
 758         ret = perf_pmu_register(&pmu->pmu, name, -1);
 759         if (ret)
 760                 goto ddr_perf_err;
 761
 762         return 0;
 763
 764 ddr_perf_err:
 765         cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
 766 cpuhp_instance_err:
 767         cpuhp_remove_multi_state(pmu->cpuhp_state);
 768 cpuhp_state_err:
 769         ida_simple_remove(&ddr_ida, pmu->id);
 770         dev_warn(&pdev->dev, "i.MX8 DDR Perf PMU failed (%d), disabled\n", ret);
 771         return ret;
 772 }
 773
 774 static int ddr_perf_remove(struct platform_device *pdev)
 775 {
 776         struct ddr_pmu *pmu = platform_get_drvdata(pdev);
 777
 778         cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node);
 779         cpuhp_remove_multi_state(pmu->cpuhp_state);
 780         irq_set_affinity_hint(pmu->irq, NULL);
 781
 782         perf_pmu_unregister(&pmu->pmu);
 783
 784         ida_simple_remove(&ddr_ida, pmu->id);
 785         return 0;
 786 }
 787
 788 static struct platform_driver imx_ddr_pmu_driver = {
 789         .driver         = {
 790                 .name   = "imx-ddr-pmu",
 791                 .of_match_table = imx_ddr_pmu_dt_ids,
 792                 .suppress_bind_attrs = true,
 793         },
 794         .probe          = ddr_perf_probe,
 795         .remove         = ddr_perf_remove,
 796 };
 797
 798 module_platform_driver(imx_ddr_pmu_driver);
 799 MODULE_LICENSE("GPL v2");