1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARMv8 PMUv3 Performance Events handling code.
5 * Copyright (C) 2012 ARM Limited
6 * Author: Will Deacon <will.deacon@arm.com>
8 * This code is based heavily on the ARMv7 perf event code.
11 #include <asm/irq_regs.h>
12 #include <asm/perf_event.h>
15 #include <clocksource/arm_arch_timer.h>
17 #include <linux/acpi.h>
18 #include <linux/clocksource.h>
20 #include <linux/perf/arm_pmu.h>
21 #include <linux/perf/arm_pmuv3.h>
22 #include <linux/platform_device.h>
23 #include <linux/sched_clock.h>
24 #include <linux/smp.h>
25 #include <linux/nmi.h>
27 #include <asm/arm_pmuv3.h>
29 /* ARMv8 Cortex-A53 specific event types. */
30 #define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2
32 /* ARMv8 Cavium ThunderX specific event types. */
33 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST 0xE9
34 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS 0xEA
35 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS 0xEB
36 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS 0xEC
37 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS 0xED
40 * ARMv8 Architectural defined events, not all of these may
41 * be supported on any given implementation. Unsupported events will
42 * be disabled at run-time based on the PMCEID registers.
44 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
45 PERF_MAP_ALL_UNSUPPORTED,
46 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
47 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
48 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
49 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
50 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
51 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
52 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
53 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
56 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
57 [PERF_COUNT_HW_CACHE_OP_MAX]
58 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
59 PERF_CACHE_MAP_ALL_UNSUPPORTED,
61 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
62 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
64 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
65 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
67 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
68 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
70 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
71 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
73 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,
74 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,
76 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
77 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
80 static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
81 [PERF_COUNT_HW_CACHE_OP_MAX]
82 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
83 PERF_CACHE_MAP_ALL_UNSUPPORTED,
85 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
87 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
88 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
91 static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
92 [PERF_COUNT_HW_CACHE_OP_MAX]
93 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
94 PERF_CACHE_MAP_ALL_UNSUPPORTED,
96 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
97 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
98 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
99 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
101 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
102 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
104 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
105 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
108 static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
109 [PERF_COUNT_HW_CACHE_OP_MAX]
110 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
111 PERF_CACHE_MAP_ALL_UNSUPPORTED,
113 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
114 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
117 static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
118 [PERF_COUNT_HW_CACHE_OP_MAX]
119 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
120 PERF_CACHE_MAP_ALL_UNSUPPORTED,
122 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
123 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
124 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
125 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
126 [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
127 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
129 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
130 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
132 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
133 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
134 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
135 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
138 static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
139 [PERF_COUNT_HW_CACHE_OP_MAX]
140 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
141 PERF_CACHE_MAP_ALL_UNSUPPORTED,
143 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
144 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
145 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
146 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
148 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
149 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
150 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
151 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
153 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
154 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
158 armv8pmu_events_sysfs_show(struct device *dev,
159 struct device_attribute *attr, char *page)
161 struct perf_pmu_events_attr *pmu_attr;
163 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
165 return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
168 #define ARMV8_EVENT_ATTR(name, config) \
169 PMU_EVENT_ATTR_ID(name, armv8pmu_events_sysfs_show, config)
171 static struct attribute *armv8_pmuv3_event_attrs[] = {
172 ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR),
173 ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL),
174 ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL),
175 ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL),
176 ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE),
177 ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL),
178 ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED),
179 ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED),
180 ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED),
181 ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN),
182 ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN),
183 ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED),
184 ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED),
185 ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED),
186 ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED),
187 ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED),
188 ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED),
189 ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES),
190 ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED),
191 ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS),
192 ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE),
193 ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB),
194 ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE),
195 ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL),
196 ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB),
197 ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS),
198 ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR),
199 ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC),
200 ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED),
201 ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES),
202 /* Don't expose the chain event in /sys, since it's useless in isolation */
203 ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE),
204 ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE),
205 ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED),
206 ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED),
207 ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND),
208 ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND),
209 ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB),
210 ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB),
211 ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE),
212 ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL),
213 ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE),
214 ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL),
215 ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE),
216 ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB),
217 ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL),
218 ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL),
219 ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB),
220 ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB),
221 ARMV8_EVENT_ATTR(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS),
222 ARMV8_EVENT_ATTR(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE),
223 ARMV8_EVENT_ATTR(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS),
224 ARMV8_EVENT_ATTR(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK),
225 ARMV8_EVENT_ATTR(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK),
226 ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
227 ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
228 ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
229 ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
230 ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
231 ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC),
232 ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL),
233 ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND),
234 ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND),
235 ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT),
236 ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),
237 ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),
238 ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),
239 ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),
240 ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES),
241 ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM),
242 ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS),
243 ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),
244 ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),
245 ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),
246 ARMV8_EVENT_ATTR(trb_wrap, ARMV8_PMUV3_PERFCTR_TRB_WRAP),
247 ARMV8_EVENT_ATTR(trb_trig, ARMV8_PMUV3_PERFCTR_TRB_TRIG),
248 ARMV8_EVENT_ATTR(trcextout0, ARMV8_PMUV3_PERFCTR_TRCEXTOUT0),
249 ARMV8_EVENT_ATTR(trcextout1, ARMV8_PMUV3_PERFCTR_TRCEXTOUT1),
250 ARMV8_EVENT_ATTR(trcextout2, ARMV8_PMUV3_PERFCTR_TRCEXTOUT2),
251 ARMV8_EVENT_ATTR(trcextout3, ARMV8_PMUV3_PERFCTR_TRCEXTOUT3),
252 ARMV8_EVENT_ATTR(cti_trigout4, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4),
253 ARMV8_EVENT_ATTR(cti_trigout5, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5),
254 ARMV8_EVENT_ATTR(cti_trigout6, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6),
255 ARMV8_EVENT_ATTR(cti_trigout7, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7),
256 ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),
257 ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),
258 ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),
259 ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED),
260 ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD),
261 ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR),
266 armv8pmu_event_attr_is_visible(struct kobject *kobj,
267 struct attribute *attr, int unused)
269 struct device *dev = kobj_to_dev(kobj);
270 struct pmu *pmu = dev_get_drvdata(dev);
271 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
272 struct perf_pmu_events_attr *pmu_attr;
274 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
276 if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
277 test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
280 if (pmu_attr->id >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) {
281 u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE;
283 if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
284 test_bit(id, cpu_pmu->pmceid_ext_bitmap))
291 static const struct attribute_group armv8_pmuv3_events_attr_group = {
293 .attrs = armv8_pmuv3_event_attrs,
294 .is_visible = armv8pmu_event_attr_is_visible,
297 PMU_FORMAT_ATTR(event, "config:0-15");
298 PMU_FORMAT_ATTR(long, "config1:0");
299 PMU_FORMAT_ATTR(rdpmc, "config1:1");
301 static int sysctl_perf_user_access __read_mostly;
303 static inline bool armv8pmu_event_is_64bit(struct perf_event *event)
305 return event->attr.config1 & 0x1;
308 static inline bool armv8pmu_event_want_user_access(struct perf_event *event)
310 return event->attr.config1 & 0x2;
313 static struct attribute *armv8_pmuv3_format_attrs[] = {
314 &format_attr_event.attr,
315 &format_attr_long.attr,
316 &format_attr_rdpmc.attr,
320 static const struct attribute_group armv8_pmuv3_format_attr_group = {
322 .attrs = armv8_pmuv3_format_attrs,
325 static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
328 struct pmu *pmu = dev_get_drvdata(dev);
329 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
330 u32 slots = cpu_pmu->reg_pmmir & ARMV8_PMU_SLOTS_MASK;
332 return sysfs_emit(page, "0x%08x\n", slots);
335 static DEVICE_ATTR_RO(slots);
337 static ssize_t bus_slots_show(struct device *dev, struct device_attribute *attr,
340 struct pmu *pmu = dev_get_drvdata(dev);
341 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
342 u32 bus_slots = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_SLOTS_SHIFT)
343 & ARMV8_PMU_BUS_SLOTS_MASK;
345 return sysfs_emit(page, "0x%08x\n", bus_slots);
348 static DEVICE_ATTR_RO(bus_slots);
350 static ssize_t bus_width_show(struct device *dev, struct device_attribute *attr,
353 struct pmu *pmu = dev_get_drvdata(dev);
354 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
355 u32 bus_width = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_WIDTH_SHIFT)
356 & ARMV8_PMU_BUS_WIDTH_MASK;
359 /* Encoded as Log2(number of bytes), plus one */
360 if (bus_width > 2 && bus_width < 13)
361 val = 1 << (bus_width - 1);
363 return sysfs_emit(page, "0x%08x\n", val);
366 static DEVICE_ATTR_RO(bus_width);
368 static struct attribute *armv8_pmuv3_caps_attrs[] = {
369 &dev_attr_slots.attr,
370 &dev_attr_bus_slots.attr,
371 &dev_attr_bus_width.attr,
375 static const struct attribute_group armv8_pmuv3_caps_attr_group = {
377 .attrs = armv8_pmuv3_caps_attrs,
381 * Perf Events' indices
383 #define ARMV8_IDX_CYCLE_COUNTER 0
384 #define ARMV8_IDX_COUNTER0 1
385 #define ARMV8_IDX_CYCLE_COUNTER_USER 32
388 * We unconditionally enable ARMv8.5-PMU long event counter support
389 * (64-bit events) where supported. Indicate if this arm_pmu has long
390 * event counter support.
392 * On AArch32, long counters make no sense (you can't access the top
393 * bits), so we only enable this on AArch64.
395 static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu)
397 return (IS_ENABLED(CONFIG_ARM64) && is_pmuv3p5(cpu_pmu->pmuver));
400 static inline bool armv8pmu_event_has_user_read(struct perf_event *event)
402 return event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT;
406 * We must chain two programmable counters for 64 bit events,
407 * except when we have allocated the 64bit cycle counter (for CPU
408 * cycles event) or when user space counter access is enabled.
410 static inline bool armv8pmu_event_is_chained(struct perf_event *event)
412 int idx = event->hw.idx;
413 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
415 return !armv8pmu_event_has_user_read(event) &&
416 armv8pmu_event_is_64bit(event) &&
417 !armv8pmu_has_long_event(cpu_pmu) &&
418 (idx != ARMV8_IDX_CYCLE_COUNTER);
422 * ARMv8 low level PMU access
426 * Perf Event to low level counters mapping
428 #define ARMV8_IDX_TO_COUNTER(x) \
429 (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
431 static inline u32 armv8pmu_pmcr_read(void)
436 static inline void armv8pmu_pmcr_write(u32 val)
438 val &= ARMV8_PMU_PMCR_MASK;
443 static inline int armv8pmu_has_overflowed(u32 pmovsr)
445 return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
448 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
450 return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
453 static inline u64 armv8pmu_read_evcntr(int idx)
455 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
457 return read_pmevcntrn(counter);
460 static inline u64 armv8pmu_read_hw_counter(struct perf_event *event)
462 int idx = event->hw.idx;
463 u64 val = armv8pmu_read_evcntr(idx);
465 if (armv8pmu_event_is_chained(event))
466 val = (val << 32) | armv8pmu_read_evcntr(idx - 1);
471 * The cycle counter is always a 64-bit counter. When ARMV8_PMU_PMCR_LP
472 * is set the event counters also become 64-bit counters. Unless the
473 * user has requested a long counter (attr.config1) then we want to
474 * interrupt upon 32-bit overflow - we achieve this by applying a bias.
476 static bool armv8pmu_event_needs_bias(struct perf_event *event)
478 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
479 struct hw_perf_event *hwc = &event->hw;
482 if (armv8pmu_event_is_64bit(event))
485 if (armv8pmu_has_long_event(cpu_pmu) ||
486 idx == ARMV8_IDX_CYCLE_COUNTER)
492 static u64 armv8pmu_bias_long_counter(struct perf_event *event, u64 value)
494 if (armv8pmu_event_needs_bias(event))
495 value |= GENMASK_ULL(63, 32);
500 static u64 armv8pmu_unbias_long_counter(struct perf_event *event, u64 value)
502 if (armv8pmu_event_needs_bias(event))
503 value &= ~GENMASK_ULL(63, 32);
508 static u64 armv8pmu_read_counter(struct perf_event *event)
510 struct hw_perf_event *hwc = &event->hw;
514 if (idx == ARMV8_IDX_CYCLE_COUNTER)
515 value = read_pmccntr();
517 value = armv8pmu_read_hw_counter(event);
519 return armv8pmu_unbias_long_counter(event, value);
522 static inline void armv8pmu_write_evcntr(int idx, u64 value)
524 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
526 write_pmevcntrn(counter, value);
529 static inline void armv8pmu_write_hw_counter(struct perf_event *event,
532 int idx = event->hw.idx;
534 if (armv8pmu_event_is_chained(event)) {
535 armv8pmu_write_evcntr(idx, upper_32_bits(value));
536 armv8pmu_write_evcntr(idx - 1, lower_32_bits(value));
538 armv8pmu_write_evcntr(idx, value);
542 static void armv8pmu_write_counter(struct perf_event *event, u64 value)
544 struct hw_perf_event *hwc = &event->hw;
547 value = armv8pmu_bias_long_counter(event, value);
549 if (idx == ARMV8_IDX_CYCLE_COUNTER)
550 write_pmccntr(value);
552 armv8pmu_write_hw_counter(event, value);
555 static inline void armv8pmu_write_evtype(int idx, u32 val)
557 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
559 val &= ARMV8_PMU_EVTYPE_MASK;
560 write_pmevtypern(counter, val);
563 static inline void armv8pmu_write_event_type(struct perf_event *event)
565 struct hw_perf_event *hwc = &event->hw;
569 * For chained events, the low counter is programmed to count
570 * the event of interest and the high counter is programmed
571 * with CHAIN event code with filters set to count at all ELs.
573 if (armv8pmu_event_is_chained(event)) {
574 u32 chain_evt = ARMV8_PMUV3_PERFCTR_CHAIN |
575 ARMV8_PMU_INCLUDE_EL2;
577 armv8pmu_write_evtype(idx - 1, hwc->config_base);
578 armv8pmu_write_evtype(idx, chain_evt);
580 if (idx == ARMV8_IDX_CYCLE_COUNTER)
581 write_pmccfiltr(hwc->config_base);
583 armv8pmu_write_evtype(idx, hwc->config_base);
587 static u32 armv8pmu_event_cnten_mask(struct perf_event *event)
589 int counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
590 u32 mask = BIT(counter);
592 if (armv8pmu_event_is_chained(event))
593 mask |= BIT(counter - 1);
597 static inline void armv8pmu_enable_counter(u32 mask)
600 * Make sure event configuration register writes are visible before we
601 * enable the counter.
604 write_pmcntenset(mask);
607 static inline void armv8pmu_enable_event_counter(struct perf_event *event)
609 struct perf_event_attr *attr = &event->attr;
610 u32 mask = armv8pmu_event_cnten_mask(event);
612 kvm_set_pmu_events(mask, attr);
614 /* We rely on the hypervisor switch code to enable guest counters */
615 if (!kvm_pmu_counter_deferred(attr))
616 armv8pmu_enable_counter(mask);
619 static inline void armv8pmu_disable_counter(u32 mask)
621 write_pmcntenclr(mask);
623 * Make sure the effects of disabling the counter are visible before we
624 * start configuring the event.
629 static inline void armv8pmu_disable_event_counter(struct perf_event *event)
631 struct perf_event_attr *attr = &event->attr;
632 u32 mask = armv8pmu_event_cnten_mask(event);
634 kvm_clr_pmu_events(mask);
636 /* We rely on the hypervisor switch code to disable guest counters */
637 if (!kvm_pmu_counter_deferred(attr))
638 armv8pmu_disable_counter(mask);
641 static inline void armv8pmu_enable_intens(u32 mask)
643 write_pmintenset(mask);
646 static inline void armv8pmu_enable_event_irq(struct perf_event *event)
648 u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
649 armv8pmu_enable_intens(BIT(counter));
652 static inline void armv8pmu_disable_intens(u32 mask)
654 write_pmintenclr(mask);
656 /* Clear the overflow flag in case an interrupt is pending. */
657 write_pmovsclr(mask);
661 static inline void armv8pmu_disable_event_irq(struct perf_event *event)
663 u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
664 armv8pmu_disable_intens(BIT(counter));
667 static inline u32 armv8pmu_getreset_flags(void)
672 value = read_pmovsclr();
674 /* Write to clear flags */
675 value &= ARMV8_PMU_OVSR_MASK;
676 write_pmovsclr(value);
681 static void update_pmuserenr(u64 val)
683 lockdep_assert_irqs_disabled();
686 * The current PMUSERENR_EL0 value might be the value for the guest.
687 * If that's the case, have KVM keep tracking of the register value
688 * for the host EL0 so that KVM can restore it before returning to
689 * the host EL0. Otherwise, update the register now.
691 if (kvm_set_pmuserenr(val))
694 write_pmuserenr(val);
697 static void armv8pmu_disable_user_access(void)
702 static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu)
705 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
707 /* Clear any unused counters to avoid leaking their contents */
708 for_each_clear_bit(i, cpuc->used_mask, cpu_pmu->num_events) {
709 if (i == ARMV8_IDX_CYCLE_COUNTER)
712 armv8pmu_write_evcntr(i, 0);
715 update_pmuserenr(ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_CR);
718 static void armv8pmu_enable_event(struct perf_event *event)
721 * Enable counter and interrupt, and set the counter to count
722 * the event that we're interested in.
724 armv8pmu_disable_event_counter(event);
725 armv8pmu_write_event_type(event);
726 armv8pmu_enable_event_irq(event);
727 armv8pmu_enable_event_counter(event);
730 static void armv8pmu_disable_event(struct perf_event *event)
732 armv8pmu_disable_event_counter(event);
733 armv8pmu_disable_event_irq(event);
736 static void armv8pmu_start(struct arm_pmu *cpu_pmu)
738 struct perf_event_context *ctx;
741 ctx = perf_cpu_task_ctx();
743 nr_user = ctx->nr_user;
745 if (sysctl_perf_user_access && nr_user)
746 armv8pmu_enable_user_access(cpu_pmu);
748 armv8pmu_disable_user_access();
750 /* Enable all counters */
751 armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
754 static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
756 /* Disable all counters */
757 armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
760 static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu)
763 struct perf_sample_data data;
764 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
765 struct pt_regs *regs;
769 * Get and reset the IRQ flags
771 pmovsr = armv8pmu_getreset_flags();
774 * Did an overflow occur?
776 if (!armv8pmu_has_overflowed(pmovsr))
780 * Handle the counter(s) overflow(s)
782 regs = get_irq_regs();
785 * Stop the PMU while processing the counter overflows
786 * to prevent skews in group events.
788 armv8pmu_stop(cpu_pmu);
789 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
790 struct perf_event *event = cpuc->events[idx];
791 struct hw_perf_event *hwc;
793 /* Ignore if we don't have an event. */
798 * We have a single interrupt for all counters. Check that
799 * each counter has overflowed before we process it.
801 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
805 armpmu_event_update(event);
806 perf_sample_data_init(&data, 0, hwc->last_period);
807 if (!armpmu_event_set_period(event))
811 * Perf event overflow will queue the processing of the event as
812 * an irq_work which will be taken care of in the handling of
815 if (perf_event_overflow(event, &data, regs))
816 cpu_pmu->disable(event);
818 armv8pmu_start(cpu_pmu);
823 static int armv8pmu_get_single_idx(struct pmu_hw_events *cpuc,
824 struct arm_pmu *cpu_pmu)
828 for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; idx++) {
829 if (!test_and_set_bit(idx, cpuc->used_mask))
835 static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc,
836 struct arm_pmu *cpu_pmu)
841 * Chaining requires two consecutive event counters, where
842 * the lower idx must be even.
844 for (idx = ARMV8_IDX_COUNTER0 + 1; idx < cpu_pmu->num_events; idx += 2) {
845 if (!test_and_set_bit(idx, cpuc->used_mask)) {
846 /* Check if the preceding even counter is available */
847 if (!test_and_set_bit(idx - 1, cpuc->used_mask))
849 /* Release the Odd counter */
850 clear_bit(idx, cpuc->used_mask);
856 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
857 struct perf_event *event)
859 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
860 struct hw_perf_event *hwc = &event->hw;
861 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
863 /* Always prefer to place a cycle counter into the cycle counter. */
864 if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
865 if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
866 return ARMV8_IDX_CYCLE_COUNTER;
867 else if (armv8pmu_event_is_64bit(event) &&
868 armv8pmu_event_want_user_access(event) &&
869 !armv8pmu_has_long_event(cpu_pmu))
874 * Otherwise use events counters
876 if (armv8pmu_event_is_chained(event))
877 return armv8pmu_get_chain_idx(cpuc, cpu_pmu);
879 return armv8pmu_get_single_idx(cpuc, cpu_pmu);
882 static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc,
883 struct perf_event *event)
885 int idx = event->hw.idx;
887 clear_bit(idx, cpuc->used_mask);
888 if (armv8pmu_event_is_chained(event))
889 clear_bit(idx - 1, cpuc->used_mask);
892 static int armv8pmu_user_event_idx(struct perf_event *event)
894 if (!sysctl_perf_user_access || !armv8pmu_event_has_user_read(event))
898 * We remap the cycle counter index to 32 to
899 * match the offset applied to the rest of
900 * the counter indices.
902 if (event->hw.idx == ARMV8_IDX_CYCLE_COUNTER)
903 return ARMV8_IDX_CYCLE_COUNTER_USER;
905 return event->hw.idx;
909 * Add an event filter to a given event.
911 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
912 struct perf_event_attr *attr)
914 unsigned long config_base = 0;
916 if (attr->exclude_idle)
920 * If we're running in hyp mode, then we *are* the hypervisor.
921 * Therefore we ignore exclude_hv in this configuration, since
922 * there's no hypervisor to sample anyway. This is consistent
923 * with other architectures (x86 and Power).
925 if (is_kernel_in_hyp_mode()) {
926 if (!attr->exclude_kernel && !attr->exclude_host)
927 config_base |= ARMV8_PMU_INCLUDE_EL2;
928 if (attr->exclude_guest)
929 config_base |= ARMV8_PMU_EXCLUDE_EL1;
930 if (attr->exclude_host)
931 config_base |= ARMV8_PMU_EXCLUDE_EL0;
933 if (!attr->exclude_hv && !attr->exclude_host)
934 config_base |= ARMV8_PMU_INCLUDE_EL2;
938 * Filter out !VHE kernels and guest kernels
940 if (attr->exclude_kernel)
941 config_base |= ARMV8_PMU_EXCLUDE_EL1;
943 if (attr->exclude_user)
944 config_base |= ARMV8_PMU_EXCLUDE_EL0;
947 * Install the filter into config_base as this is used to
948 * construct the event type.
950 event->config_base = config_base;
955 static void armv8pmu_reset(void *info)
957 struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
960 /* The counter and interrupt enable registers are unknown at reset. */
961 armv8pmu_disable_counter(U32_MAX);
962 armv8pmu_disable_intens(U32_MAX);
964 /* Clear the counters we flip at guest entry/exit */
965 kvm_clr_pmu_events(U32_MAX);
968 * Initialize & Reset PMNC. Request overflow interrupt for
969 * 64 bit cycle counter but cheat in armv8pmu_write_counter().
971 pmcr = ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC;
973 /* Enable long event counter support where available */
974 if (armv8pmu_has_long_event(cpu_pmu))
975 pmcr |= ARMV8_PMU_PMCR_LP;
977 armv8pmu_pmcr_write(pmcr);
980 static int __armv8_pmuv3_map_event_id(struct arm_pmu *armpmu,
981 struct perf_event *event)
983 if (event->attr.type == PERF_TYPE_HARDWARE &&
984 event->attr.config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) {
986 if (test_bit(ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
987 armpmu->pmceid_bitmap))
988 return ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED;
990 if (test_bit(ARMV8_PMUV3_PERFCTR_BR_RETIRED,
991 armpmu->pmceid_bitmap))
992 return ARMV8_PMUV3_PERFCTR_BR_RETIRED;
994 return HW_OP_UNSUPPORTED;
997 return armpmu_map_event(event, &armv8_pmuv3_perf_map,
998 &armv8_pmuv3_perf_cache_map,
999 ARMV8_PMU_EVTYPE_EVENT);
1002 static int __armv8_pmuv3_map_event(struct perf_event *event,
1003 const unsigned (*extra_event_map)
1004 [PERF_COUNT_HW_MAX],
1005 const unsigned (*extra_cache_map)
1006 [PERF_COUNT_HW_CACHE_MAX]
1007 [PERF_COUNT_HW_CACHE_OP_MAX]
1008 [PERF_COUNT_HW_CACHE_RESULT_MAX])
1011 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
1013 hw_event_id = __armv8_pmuv3_map_event_id(armpmu, event);
1016 * CHAIN events only work when paired with an adjacent counter, and it
1017 * never makes sense for a user to open one in isolation, as they'll be
1018 * rotated arbitrarily.
1020 if (hw_event_id == ARMV8_PMUV3_PERFCTR_CHAIN)
1023 if (armv8pmu_event_is_64bit(event))
1024 event->hw.flags |= ARMPMU_EVT_64BIT;
1027 * User events must be allocated into a single counter, and so
1028 * must not be chained.
1030 * Most 64-bit events require long counter support, but 64-bit
1031 * CPU_CYCLES events can be placed into the dedicated cycle
1032 * counter when this is free.
1034 if (armv8pmu_event_want_user_access(event)) {
1035 if (!(event->attach_state & PERF_ATTACH_TASK))
1037 if (armv8pmu_event_is_64bit(event) &&
1038 (hw_event_id != ARMV8_PMUV3_PERFCTR_CPU_CYCLES) &&
1039 !armv8pmu_has_long_event(armpmu))
1042 event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
1045 /* Only expose micro/arch events supported by this PMU */
1046 if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS)
1047 && test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
1051 return armpmu_map_event(event, extra_event_map, extra_cache_map,
1052 ARMV8_PMU_EVTYPE_EVENT);
1055 static int armv8_pmuv3_map_event(struct perf_event *event)
1057 return __armv8_pmuv3_map_event(event, NULL, NULL);
1060 static int armv8_a53_map_event(struct perf_event *event)
1062 return __armv8_pmuv3_map_event(event, NULL, &armv8_a53_perf_cache_map);
1065 static int armv8_a57_map_event(struct perf_event *event)
1067 return __armv8_pmuv3_map_event(event, NULL, &armv8_a57_perf_cache_map);
1070 static int armv8_a73_map_event(struct perf_event *event)
1072 return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map);
1075 static int armv8_thunder_map_event(struct perf_event *event)
1077 return __armv8_pmuv3_map_event(event, NULL,
1078 &armv8_thunder_perf_cache_map);
1081 static int armv8_vulcan_map_event(struct perf_event *event)
1083 return __armv8_pmuv3_map_event(event, NULL,
1084 &armv8_vulcan_perf_cache_map);
1087 struct armv8pmu_probe_info {
1088 struct arm_pmu *pmu;
1092 static void __armv8pmu_probe_pmu(void *info)
1094 struct armv8pmu_probe_info *probe = info;
1095 struct arm_pmu *cpu_pmu = probe->pmu;
1100 pmuver = read_pmuver();
1101 if (!pmuv3_implemented(pmuver))
1104 cpu_pmu->pmuver = pmuver;
1105 probe->present = true;
1107 /* Read the nb of CNTx counters supported from PMNC */
1108 cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
1109 & ARMV8_PMU_PMCR_N_MASK;
1111 /* Add the CPU cycles counter */
1112 cpu_pmu->num_events += 1;
1114 pmceid[0] = pmceid_raw[0] = read_pmceid0();
1115 pmceid[1] = pmceid_raw[1] = read_pmceid1();
1117 bitmap_from_arr32(cpu_pmu->pmceid_bitmap,
1118 pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1120 pmceid[0] = pmceid_raw[0] >> 32;
1121 pmceid[1] = pmceid_raw[1] >> 32;
1123 bitmap_from_arr32(cpu_pmu->pmceid_ext_bitmap,
1124 pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1126 /* store PMMIR register for sysfs */
1127 if (is_pmuv3p4(pmuver) && (pmceid_raw[1] & BIT(31)))
1128 cpu_pmu->reg_pmmir = read_pmmir();
1130 cpu_pmu->reg_pmmir = 0;
1133 static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
1135 struct armv8pmu_probe_info probe = {
1141 ret = smp_call_function_any(&cpu_pmu->supported_cpus,
1142 __armv8pmu_probe_pmu,
1147 return probe.present ? 0 : -ENODEV;
1150 static void armv8pmu_disable_user_access_ipi(void *unused)
1152 armv8pmu_disable_user_access();
1155 static int armv8pmu_proc_user_access_handler(struct ctl_table *table, int write,
1156 void *buffer, size_t *lenp, loff_t *ppos)
1158 int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
1159 if (ret || !write || sysctl_perf_user_access)
1162 on_each_cpu(armv8pmu_disable_user_access_ipi, NULL, 1);
1166 static struct ctl_table armv8_pmu_sysctl_table[] = {
1168 .procname = "perf_user_access",
1169 .data = &sysctl_perf_user_access,
1170 .maxlen = sizeof(unsigned int),
1172 .proc_handler = armv8pmu_proc_user_access_handler,
1173 .extra1 = SYSCTL_ZERO,
1174 .extra2 = SYSCTL_ONE,
1179 static void armv8_pmu_register_sysctl_table(void)
1181 static u32 tbl_registered = 0;
1183 if (!cmpxchg_relaxed(&tbl_registered, 0, 1))
1184 register_sysctl("kernel", armv8_pmu_sysctl_table);
1187 static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
1188 int (*map_event)(struct perf_event *event),
1189 const struct attribute_group *events,
1190 const struct attribute_group *format,
1191 const struct attribute_group *caps)
1193 int ret = armv8pmu_probe_pmu(cpu_pmu);
1197 cpu_pmu->handle_irq = armv8pmu_handle_irq;
1198 cpu_pmu->enable = armv8pmu_enable_event;
1199 cpu_pmu->disable = armv8pmu_disable_event;
1200 cpu_pmu->read_counter = armv8pmu_read_counter;
1201 cpu_pmu->write_counter = armv8pmu_write_counter;
1202 cpu_pmu->get_event_idx = armv8pmu_get_event_idx;
1203 cpu_pmu->clear_event_idx = armv8pmu_clear_event_idx;
1204 cpu_pmu->start = armv8pmu_start;
1205 cpu_pmu->stop = armv8pmu_stop;
1206 cpu_pmu->reset = armv8pmu_reset;
1207 cpu_pmu->set_event_filter = armv8pmu_set_event_filter;
1209 cpu_pmu->pmu.event_idx = armv8pmu_user_event_idx;
1211 cpu_pmu->name = name;
1212 cpu_pmu->map_event = map_event;
1213 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ?
1214 events : &armv8_pmuv3_events_attr_group;
1215 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?
1216 format : &armv8_pmuv3_format_attr_group;
1217 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ?
1218 caps : &armv8_pmuv3_caps_attr_group;
1220 armv8_pmu_register_sysctl_table();
1224 static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name,
1225 int (*map_event)(struct perf_event *event))
1227 return armv8_pmu_init(cpu_pmu, name, map_event, NULL, NULL, NULL);
1230 #define PMUV3_INIT_SIMPLE(name) \
1231 static int name##_pmu_init(struct arm_pmu *cpu_pmu) \
1233 return armv8_pmu_init_nogroups(cpu_pmu, #name, armv8_pmuv3_map_event);\
1236 PMUV3_INIT_SIMPLE(armv8_pmuv3)
1238 PMUV3_INIT_SIMPLE(armv8_cortex_a34)
1239 PMUV3_INIT_SIMPLE(armv8_cortex_a55)
1240 PMUV3_INIT_SIMPLE(armv8_cortex_a65)
1241 PMUV3_INIT_SIMPLE(armv8_cortex_a75)
1242 PMUV3_INIT_SIMPLE(armv8_cortex_a76)
1243 PMUV3_INIT_SIMPLE(armv8_cortex_a77)
1244 PMUV3_INIT_SIMPLE(armv8_cortex_a78)
1245 PMUV3_INIT_SIMPLE(armv9_cortex_a510)
1246 PMUV3_INIT_SIMPLE(armv9_cortex_a520)
1247 PMUV3_INIT_SIMPLE(armv9_cortex_a710)
1248 PMUV3_INIT_SIMPLE(armv9_cortex_a715)
1249 PMUV3_INIT_SIMPLE(armv9_cortex_a720)
1250 PMUV3_INIT_SIMPLE(armv8_cortex_x1)
1251 PMUV3_INIT_SIMPLE(armv9_cortex_x2)
1252 PMUV3_INIT_SIMPLE(armv9_cortex_x3)
1253 PMUV3_INIT_SIMPLE(armv9_cortex_x4)
1254 PMUV3_INIT_SIMPLE(armv8_neoverse_e1)
1255 PMUV3_INIT_SIMPLE(armv8_neoverse_n1)
1256 PMUV3_INIT_SIMPLE(armv9_neoverse_n2)
1257 PMUV3_INIT_SIMPLE(armv8_neoverse_v1)
1259 PMUV3_INIT_SIMPLE(armv8_nvidia_carmel)
1260 PMUV3_INIT_SIMPLE(armv8_nvidia_denver)
1262 static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
1264 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a35",
1265 armv8_a53_map_event);
1268 static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
1270 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a53",
1271 armv8_a53_map_event);
1274 static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
1276 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a57",
1277 armv8_a57_map_event);
1280 static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
1282 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a72",
1283 armv8_a57_map_event);
1286 static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
1288 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a73",
1289 armv8_a73_map_event);
1292 static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
1294 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",
1295 armv8_thunder_map_event);
1298 static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
1300 return armv8_pmu_init_nogroups(cpu_pmu, "armv8_brcm_vulcan",
1301 armv8_vulcan_map_event);
1304 static const struct of_device_id armv8_pmu_of_device_ids[] = {
1305 {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_pmu_init},
1306 {.compatible = "arm,cortex-a34-pmu", .data = armv8_cortex_a34_pmu_init},
1307 {.compatible = "arm,cortex-a35-pmu", .data = armv8_a35_pmu_init},
1308 {.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init},
1309 {.compatible = "arm,cortex-a55-pmu", .data = armv8_cortex_a55_pmu_init},
1310 {.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init},
1311 {.compatible = "arm,cortex-a65-pmu", .data = armv8_cortex_a65_pmu_init},
1312 {.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init},
1313 {.compatible = "arm,cortex-a73-pmu", .data = armv8_a73_pmu_init},
1314 {.compatible = "arm,cortex-a75-pmu", .data = armv8_cortex_a75_pmu_init},
1315 {.compatible = "arm,cortex-a76-pmu", .data = armv8_cortex_a76_pmu_init},
1316 {.compatible = "arm,cortex-a77-pmu", .data = armv8_cortex_a77_pmu_init},
1317 {.compatible = "arm,cortex-a78-pmu", .data = armv8_cortex_a78_pmu_init},
1318 {.compatible = "arm,cortex-a510-pmu", .data = armv9_cortex_a510_pmu_init},
1319 {.compatible = "arm,cortex-a520-pmu", .data = armv9_cortex_a520_pmu_init},
1320 {.compatible = "arm,cortex-a710-pmu", .data = armv9_cortex_a710_pmu_init},
1321 {.compatible = "arm,cortex-a715-pmu", .data = armv9_cortex_a715_pmu_init},
1322 {.compatible = "arm,cortex-a720-pmu", .data = armv9_cortex_a720_pmu_init},
1323 {.compatible = "arm,cortex-x1-pmu", .data = armv8_cortex_x1_pmu_init},
1324 {.compatible = "arm,cortex-x2-pmu", .data = armv9_cortex_x2_pmu_init},
1325 {.compatible = "arm,cortex-x3-pmu", .data = armv9_cortex_x3_pmu_init},
1326 {.compatible = "arm,cortex-x4-pmu", .data = armv9_cortex_x4_pmu_init},
1327 {.compatible = "arm,neoverse-e1-pmu", .data = armv8_neoverse_e1_pmu_init},
1328 {.compatible = "arm,neoverse-n1-pmu", .data = armv8_neoverse_n1_pmu_init},
1329 {.compatible = "arm,neoverse-n2-pmu", .data = armv9_neoverse_n2_pmu_init},
1330 {.compatible = "arm,neoverse-v1-pmu", .data = armv8_neoverse_v1_pmu_init},
1331 {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init},
1332 {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init},
1333 {.compatible = "nvidia,carmel-pmu", .data = armv8_nvidia_carmel_pmu_init},
1334 {.compatible = "nvidia,denver-pmu", .data = armv8_nvidia_denver_pmu_init},
1338 static int armv8_pmu_device_probe(struct platform_device *pdev)
1340 return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL);
1343 static struct platform_driver armv8_pmu_driver = {
1345 .name = ARMV8_PMU_PDEV_NAME,
1346 .of_match_table = armv8_pmu_of_device_ids,
1347 .suppress_bind_attrs = true,
1349 .probe = armv8_pmu_device_probe,
1352 static int __init armv8_pmu_driver_init(void)
1357 ret = platform_driver_register(&armv8_pmu_driver);
1359 ret = arm_pmu_acpi_probe(armv8_pmuv3_pmu_init);
1362 lockup_detector_retry_init();
1366 device_initcall(armv8_pmu_driver_init)
1368 void arch_perf_update_userpage(struct perf_event *event,
1369 struct perf_event_mmap_page *userpg, u64 now)
1371 struct clock_read_data *rd;
1375 userpg->cap_user_time = 0;
1376 userpg->cap_user_time_zero = 0;
1377 userpg->cap_user_time_short = 0;
1378 userpg->cap_user_rdpmc = armv8pmu_event_has_user_read(event);
1380 if (userpg->cap_user_rdpmc) {
1381 if (event->hw.flags & ARMPMU_EVT_64BIT)
1382 userpg->pmc_width = 64;
1384 userpg->pmc_width = 32;
1388 rd = sched_clock_read_begin(&seq);
1390 if (rd->read_sched_clock != arch_timer_read_counter)
1393 userpg->time_mult = rd->mult;
1394 userpg->time_shift = rd->shift;
1395 userpg->time_zero = rd->epoch_ns;
1396 userpg->time_cycles = rd->epoch_cyc;
1397 userpg->time_mask = rd->sched_clock_mask;
1400 * Subtract the cycle base, such that software that
1401 * doesn't know about cap_user_time_short still 'works'
1402 * assuming no wraps.
1404 ns = mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift);
1405 userpg->time_zero -= ns;
1407 } while (sched_clock_read_retry(seq));
1409 userpg->time_offset = userpg->time_zero - now;
1412 * time_shift is not expected to be greater than 31 due to
1413 * the original published conversion algorithm shifting a
1414 * 32-bit value (now specifies a 64-bit value) - refer
1415 * perf_event_mmap_page documentation in perf_event.h.
1417 if (userpg->time_shift == 32) {
1418 userpg->time_shift = 31;
1419 userpg->time_mult >>= 1;
1423 * Internal timekeeping for enabled/running/stopped times
1424 * is always computed with the sched_clock.
1426 userpg->cap_user_time = 1;
1427 userpg->cap_user_time_zero = 1;
1428 userpg->cap_user_time_short = 1;