1 // SPDX-License-Identifier: GPL-2.0-only
5 * ARM performance counter support.
7 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
8 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
10 * This code is based on the sparc64 perf event code, which is in turn based
13 #define pr_fmt(fmt) "hw perfevents: " fmt
15 #include <linux/bitmap.h>
16 #include <linux/cpumask.h>
17 #include <linux/cpu_pm.h>
18 #include <linux/export.h>
19 #include <linux/kernel.h>
20 #include <linux/perf/arm_pmu.h>
21 #include <linux/slab.h>
22 #include <linux/sched/clock.h>
23 #include <linux/spinlock.h>
24 #include <linux/irq.h>
25 #include <linux/irqdesc.h>
27 #include <asm/irq_regs.h>
29 static int armpmu_count_irq_users(const int irq);
32 void (*enable_pmuirq)(unsigned int irq);
33 void (*disable_pmuirq)(unsigned int irq);
34 void (*free_pmuirq)(unsigned int irq, int cpu, void __percpu *devid);
37 static void armpmu_free_pmuirq(unsigned int irq, int cpu, void __percpu *devid)
39 free_irq(irq, per_cpu_ptr(devid, cpu));
42 static const struct pmu_irq_ops pmuirq_ops = {
43 .enable_pmuirq = enable_irq,
44 .disable_pmuirq = disable_irq_nosync,
45 .free_pmuirq = armpmu_free_pmuirq
48 static void armpmu_free_pmunmi(unsigned int irq, int cpu, void __percpu *devid)
50 free_nmi(irq, per_cpu_ptr(devid, cpu));
53 static const struct pmu_irq_ops pmunmi_ops = {
54 .enable_pmuirq = enable_nmi,
55 .disable_pmuirq = disable_nmi_nosync,
56 .free_pmuirq = armpmu_free_pmunmi
59 static void armpmu_enable_percpu_pmuirq(unsigned int irq)
61 enable_percpu_irq(irq, IRQ_TYPE_NONE);
64 static void armpmu_free_percpu_pmuirq(unsigned int irq, int cpu,
67 if (armpmu_count_irq_users(irq) == 1)
68 free_percpu_irq(irq, devid);
71 static const struct pmu_irq_ops percpu_pmuirq_ops = {
72 .enable_pmuirq = armpmu_enable_percpu_pmuirq,
73 .disable_pmuirq = disable_percpu_irq,
74 .free_pmuirq = armpmu_free_percpu_pmuirq
77 static void armpmu_enable_percpu_pmunmi(unsigned int irq)
79 if (!prepare_percpu_nmi(irq))
80 enable_percpu_nmi(irq, IRQ_TYPE_NONE);
83 static void armpmu_disable_percpu_pmunmi(unsigned int irq)
85 disable_percpu_nmi(irq);
86 teardown_percpu_nmi(irq);
89 static void armpmu_free_percpu_pmunmi(unsigned int irq, int cpu,
92 if (armpmu_count_irq_users(irq) == 1)
93 free_percpu_nmi(irq, devid);
96 static const struct pmu_irq_ops percpu_pmunmi_ops = {
97 .enable_pmuirq = armpmu_enable_percpu_pmunmi,
98 .disable_pmuirq = armpmu_disable_percpu_pmunmi,
99 .free_pmuirq = armpmu_free_percpu_pmunmi
102 static DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu);
103 static DEFINE_PER_CPU(int, cpu_irq);
104 static DEFINE_PER_CPU(const struct pmu_irq_ops *, cpu_irq_ops);
108 static inline u64 arm_pmu_event_max_period(struct perf_event *event)
110 if (event->hw.flags & ARMPMU_EVT_64BIT)
111 return GENMASK_ULL(63, 0);
113 return GENMASK_ULL(31, 0);
117 armpmu_map_cache_event(const unsigned (*cache_map)
118 [PERF_COUNT_HW_CACHE_MAX]
119 [PERF_COUNT_HW_CACHE_OP_MAX]
120 [PERF_COUNT_HW_CACHE_RESULT_MAX],
123 unsigned int cache_type, cache_op, cache_result, ret;
125 cache_type = (config >> 0) & 0xff;
126 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
129 cache_op = (config >> 8) & 0xff;
130 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
133 cache_result = (config >> 16) & 0xff;
134 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
140 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
142 if (ret == CACHE_OP_UNSUPPORTED)
149 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
153 if (config >= PERF_COUNT_HW_MAX)
159 mapping = (*event_map)[config];
160 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
164 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
166 return (int)(config & raw_event_mask);
170 armpmu_map_event(struct perf_event *event,
171 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
172 const unsigned (*cache_map)
173 [PERF_COUNT_HW_CACHE_MAX]
174 [PERF_COUNT_HW_CACHE_OP_MAX]
175 [PERF_COUNT_HW_CACHE_RESULT_MAX],
178 u64 config = event->attr.config;
179 int type = event->attr.type;
181 if (type == event->pmu->type)
182 return armpmu_map_raw_event(raw_event_mask, config);
185 case PERF_TYPE_HARDWARE:
186 return armpmu_map_hw_event(event_map, config);
187 case PERF_TYPE_HW_CACHE:
188 return armpmu_map_cache_event(cache_map, config);
190 return armpmu_map_raw_event(raw_event_mask, config);
196 int armpmu_event_set_period(struct perf_event *event)
198 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
199 struct hw_perf_event *hwc = &event->hw;
200 s64 left = local64_read(&hwc->period_left);
201 s64 period = hwc->sample_period;
205 max_period = arm_pmu_event_max_period(event);
206 if (unlikely(left <= -period)) {
208 local64_set(&hwc->period_left, left);
209 hwc->last_period = period;
213 if (unlikely(left <= 0)) {
215 local64_set(&hwc->period_left, left);
216 hwc->last_period = period;
221 * Limit the maximum period to prevent the counter value
222 * from overtaking the one we are about to program. In
223 * effect we are reducing max_period to account for
224 * interrupt latency (and we are being very conservative).
226 if (left > (max_period >> 1))
227 left = (max_period >> 1);
229 local64_set(&hwc->prev_count, (u64)-left);
231 armpmu->write_counter(event, (u64)(-left) & max_period);
233 perf_event_update_userpage(event);
238 u64 armpmu_event_update(struct perf_event *event)
240 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
241 struct hw_perf_event *hwc = &event->hw;
242 u64 delta, prev_raw_count, new_raw_count;
243 u64 max_period = arm_pmu_event_max_period(event);
246 prev_raw_count = local64_read(&hwc->prev_count);
247 new_raw_count = armpmu->read_counter(event);
249 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
250 new_raw_count) != prev_raw_count)
253 delta = (new_raw_count - prev_raw_count) & max_period;
255 local64_add(delta, &event->count);
256 local64_sub(delta, &hwc->period_left);
258 return new_raw_count;
262 armpmu_read(struct perf_event *event)
264 armpmu_event_update(event);
268 armpmu_stop(struct perf_event *event, int flags)
270 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
271 struct hw_perf_event *hwc = &event->hw;
274 * ARM pmu always has to update the counter, so ignore
275 * PERF_EF_UPDATE, see comments in armpmu_start().
277 if (!(hwc->state & PERF_HES_STOPPED)) {
278 armpmu->disable(event);
279 armpmu_event_update(event);
280 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
284 static void armpmu_start(struct perf_event *event, int flags)
286 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
287 struct hw_perf_event *hwc = &event->hw;
290 * ARM pmu always has to reprogram the period, so ignore
291 * PERF_EF_RELOAD, see the comment below.
293 if (flags & PERF_EF_RELOAD)
294 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
298 * Set the period again. Some counters can't be stopped, so when we
299 * were stopped we simply disabled the IRQ source and the counter
300 * may have been left counting. If we don't do this step then we may
301 * get an interrupt too soon or *way* too late if the overflow has
302 * happened since disabling.
304 armpmu_event_set_period(event);
305 armpmu->enable(event);
309 armpmu_del(struct perf_event *event, int flags)
311 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
312 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
313 struct hw_perf_event *hwc = &event->hw;
316 armpmu_stop(event, PERF_EF_UPDATE);
317 hw_events->events[idx] = NULL;
318 armpmu->clear_event_idx(hw_events, event);
319 perf_event_update_userpage(event);
320 /* Clear the allocated counter */
325 armpmu_add(struct perf_event *event, int flags)
327 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
328 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
329 struct hw_perf_event *hwc = &event->hw;
332 /* An event following a process won't be stopped earlier */
333 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
336 /* If we don't have a space for the counter then finish early. */
337 idx = armpmu->get_event_idx(hw_events, event);
342 * If there is an event in the counter we are going to use then make
343 * sure it is disabled.
346 armpmu->disable(event);
347 hw_events->events[idx] = event;
349 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
350 if (flags & PERF_EF_START)
351 armpmu_start(event, PERF_EF_RELOAD);
353 /* Propagate our changes to the userspace mapping. */
354 perf_event_update_userpage(event);
360 validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
361 struct perf_event *event)
363 struct arm_pmu *armpmu;
365 if (is_software_event(event))
369 * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
370 * core perf code won't check that the pmu->ctx == leader->ctx
371 * until after pmu->event_init(event).
373 if (event->pmu != pmu)
376 if (event->state < PERF_EVENT_STATE_OFF)
379 if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
382 armpmu = to_arm_pmu(event->pmu);
383 return armpmu->get_event_idx(hw_events, event) >= 0;
387 validate_group(struct perf_event *event)
389 struct perf_event *sibling, *leader = event->group_leader;
390 struct pmu_hw_events fake_pmu;
393 * Initialise the fake PMU. We only need to populate the
394 * used_mask for the purposes of validation.
396 memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
398 if (!validate_event(event->pmu, &fake_pmu, leader))
401 for_each_sibling_event(sibling, leader) {
402 if (!validate_event(event->pmu, &fake_pmu, sibling))
406 if (!validate_event(event->pmu, &fake_pmu, event))
412 static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
414 struct arm_pmu *armpmu;
416 u64 start_clock, finish_clock;
419 * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
420 * the handlers expect a struct arm_pmu*. The percpu_irq framework will
421 * do any necessary shifting, we just need to perform the first
424 armpmu = *(void **)dev;
425 if (WARN_ON_ONCE(!armpmu))
428 start_clock = sched_clock();
429 ret = armpmu->handle_irq(armpmu);
430 finish_clock = sched_clock();
432 perf_sample_event_took(finish_clock - start_clock);
437 __hw_perf_event_init(struct perf_event *event)
439 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
440 struct hw_perf_event *hwc = &event->hw;
444 mapping = armpmu->map_event(event);
447 pr_debug("event %x:%llx not supported\n", event->attr.type,
453 * We don't assign an index until we actually place the event onto
454 * hardware. Use -1 to signify that we haven't decided where to put it
455 * yet. For SMP systems, each core has it's own PMU so we can't do any
456 * clever allocation or constraints checking at this point.
459 hwc->config_base = 0;
464 * Check whether we need to exclude the counter from certain modes.
466 if (armpmu->set_event_filter &&
467 armpmu->set_event_filter(hwc, &event->attr)) {
468 pr_debug("ARM performance counters do not support "
474 * Store the event encoding into the config_base field.
476 hwc->config_base |= (unsigned long)mapping;
478 if (!is_sampling_event(event)) {
480 * For non-sampling runs, limit the sample_period to half
481 * of the counter width. That way, the new counter value
482 * is far less likely to overtake the previous one unless
483 * you have some serious IRQ latency issues.
485 hwc->sample_period = arm_pmu_event_max_period(event) >> 1;
486 hwc->last_period = hwc->sample_period;
487 local64_set(&hwc->period_left, hwc->sample_period);
490 if (event->group_leader != event) {
491 if (validate_group(event) != 0)
498 static int armpmu_event_init(struct perf_event *event)
500 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
503 * Reject CPU-affine events for CPUs that are of a different class to
504 * that which this PMU handles. Process-following events (where
505 * event->cpu == -1) can be migrated between CPUs, and thus we have to
506 * reject them later (in armpmu_add) if they're scheduled on a
507 * different class of CPU.
509 if (event->cpu != -1 &&
510 !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
513 /* does not support taken branch sampling */
514 if (has_branch_stack(event))
517 if (armpmu->map_event(event) == -ENOENT)
520 return __hw_perf_event_init(event);
523 static void armpmu_enable(struct pmu *pmu)
525 struct arm_pmu *armpmu = to_arm_pmu(pmu);
526 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
527 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
529 /* For task-bound events we may be called on other CPUs */
530 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
534 armpmu->start(armpmu);
537 static void armpmu_disable(struct pmu *pmu)
539 struct arm_pmu *armpmu = to_arm_pmu(pmu);
541 /* For task-bound events we may be called on other CPUs */
542 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
545 armpmu->stop(armpmu);
549 * In heterogeneous systems, events are specific to a particular
550 * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
551 * the same microarchitecture.
553 static int armpmu_filter_match(struct perf_event *event)
555 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
556 unsigned int cpu = smp_processor_id();
559 ret = cpumask_test_cpu(cpu, &armpmu->supported_cpus);
560 if (ret && armpmu->filter_match)
561 return armpmu->filter_match(event);
566 static ssize_t armpmu_cpumask_show(struct device *dev,
567 struct device_attribute *attr, char *buf)
569 struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev));
570 return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus);
573 static DEVICE_ATTR(cpus, S_IRUGO, armpmu_cpumask_show, NULL);
575 static struct attribute *armpmu_common_attrs[] = {
580 static struct attribute_group armpmu_common_attr_group = {
581 .attrs = armpmu_common_attrs,
584 /* Set at runtime when we know what CPU type we are. */
585 static struct arm_pmu *__oprofile_cpu_pmu;
588 * Despite the names, these two functions are CPU-specific and are used
589 * by the OProfile/perf code.
591 const char *perf_pmu_name(void)
593 if (!__oprofile_cpu_pmu)
596 return __oprofile_cpu_pmu->name;
598 EXPORT_SYMBOL_GPL(perf_pmu_name);
600 int perf_num_counters(void)
604 if (__oprofile_cpu_pmu != NULL)
605 max_events = __oprofile_cpu_pmu->num_events;
609 EXPORT_SYMBOL_GPL(perf_num_counters);
611 static int armpmu_count_irq_users(const int irq)
615 for_each_possible_cpu(cpu) {
616 if (per_cpu(cpu_irq, cpu) == irq)
623 static const struct pmu_irq_ops *armpmu_find_irq_ops(int irq)
625 const struct pmu_irq_ops *ops = NULL;
628 for_each_possible_cpu(cpu) {
629 if (per_cpu(cpu_irq, cpu) != irq)
632 ops = per_cpu(cpu_irq_ops, cpu);
640 void armpmu_free_irq(int irq, int cpu)
642 if (per_cpu(cpu_irq, cpu) == 0)
644 if (WARN_ON(irq != per_cpu(cpu_irq, cpu)))
647 per_cpu(cpu_irq_ops, cpu)->free_pmuirq(irq, cpu, &cpu_armpmu);
649 per_cpu(cpu_irq, cpu) = 0;
650 per_cpu(cpu_irq_ops, cpu) = NULL;
653 int armpmu_request_irq(int irq, int cpu)
656 const irq_handler_t handler = armpmu_dispatch_irq;
657 const struct pmu_irq_ops *irq_ops;
662 if (!irq_is_percpu_devid(irq)) {
663 unsigned long irq_flags;
665 err = irq_force_affinity(irq, cpumask_of(cpu));
667 if (err && num_possible_cpus() > 1) {
668 pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
673 irq_flags = IRQF_PERCPU |
677 irq_set_status_flags(irq, IRQ_NOAUTOEN);
679 err = request_nmi(irq, handler, irq_flags, "arm-pmu",
680 per_cpu_ptr(&cpu_armpmu, cpu));
682 /* If cannot get an NMI, get a normal interrupt */
684 err = request_irq(irq, handler, irq_flags, "arm-pmu",
685 per_cpu_ptr(&cpu_armpmu, cpu));
686 irq_ops = &pmuirq_ops;
689 irq_ops = &pmunmi_ops;
691 } else if (armpmu_count_irq_users(irq) == 0) {
692 err = request_percpu_nmi(irq, handler, "arm-pmu", &cpu_armpmu);
694 /* If cannot get an NMI, get a normal interrupt */
696 err = request_percpu_irq(irq, handler, "arm-pmu",
698 irq_ops = &percpu_pmuirq_ops;
701 irq_ops = &percpu_pmunmi_ops;
704 /* Per cpudevid irq was already requested by another CPU */
705 irq_ops = armpmu_find_irq_ops(irq);
707 if (WARN_ON(!irq_ops))
714 per_cpu(cpu_irq, cpu) = irq;
715 per_cpu(cpu_irq_ops, cpu) = irq_ops;
719 pr_err("unable to request IRQ%d for ARM PMU counters\n", irq);
723 static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu)
725 struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
726 return per_cpu(hw_events->irq, cpu);
730 * PMU hardware loses all context when a CPU goes offline.
731 * When a CPU is hotplugged back in, since some hardware registers are
732 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
733 * junk values out of them.
735 static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node)
737 struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
740 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
745 per_cpu(cpu_armpmu, cpu) = pmu;
747 irq = armpmu_get_cpu_irq(pmu, cpu);
749 per_cpu(cpu_irq_ops, cpu)->enable_pmuirq(irq);
754 static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node)
756 struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
759 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
762 irq = armpmu_get_cpu_irq(pmu, cpu);
764 per_cpu(cpu_irq_ops, cpu)->disable_pmuirq(irq);
766 per_cpu(cpu_armpmu, cpu) = NULL;
772 static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
774 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
775 struct perf_event *event;
778 for (idx = 0; idx < armpmu->num_events; idx++) {
779 event = hw_events->events[idx];
786 * Stop and update the counter
788 armpmu_stop(event, PERF_EF_UPDATE);
791 case CPU_PM_ENTER_FAILED:
793 * Restore and enable the counter.
794 * armpmu_start() indirectly calls
796 * perf_event_update_userpage()
798 * that requires RCU read locking to be functional,
799 * wrap the call within RCU_NONIDLE to make the
800 * RCU subsystem aware this cpu is not idle from
801 * an RCU perspective for the armpmu_start() call
804 RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
812 static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
815 struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
816 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
817 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
819 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
823 * Always reset the PMU registers on power-up even if
824 * there are no events running.
826 if (cmd == CPU_PM_EXIT && armpmu->reset)
827 armpmu->reset(armpmu);
834 armpmu->stop(armpmu);
835 cpu_pm_pmu_setup(armpmu, cmd);
838 case CPU_PM_ENTER_FAILED:
839 cpu_pm_pmu_setup(armpmu, cmd);
840 armpmu->start(armpmu);
849 static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
851 cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
852 return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
855 static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
857 cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
860 static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
861 static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
864 static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
868 err = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_STARTING,
873 err = cpu_pm_pmu_register(cpu_pmu);
880 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
886 static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
888 cpu_pm_pmu_unregister(cpu_pmu);
889 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
893 static struct arm_pmu *__armpmu_alloc(gfp_t flags)
898 pmu = kzalloc(sizeof(*pmu), flags);
900 pr_info("failed to allocate PMU device!\n");
904 pmu->hw_events = alloc_percpu_gfp(struct pmu_hw_events, flags);
905 if (!pmu->hw_events) {
906 pr_info("failed to allocate per-cpu PMU data.\n");
910 pmu->pmu = (struct pmu) {
911 .pmu_enable = armpmu_enable,
912 .pmu_disable = armpmu_disable,
913 .event_init = armpmu_event_init,
916 .start = armpmu_start,
919 .filter_match = armpmu_filter_match,
920 .attr_groups = pmu->attr_groups,
922 * This is a CPU PMU potentially in a heterogeneous
923 * configuration (e.g. big.LITTLE). This is not an uncore PMU,
924 * and we have taken ctx sharing into account (e.g. with our
925 * pmu::filter_match callback and pmu::event_init group
928 .capabilities = PERF_PMU_CAP_HETEROGENEOUS_CPUS,
931 pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =
932 &armpmu_common_attr_group;
934 for_each_possible_cpu(cpu) {
935 struct pmu_hw_events *events;
937 events = per_cpu_ptr(pmu->hw_events, cpu);
938 raw_spin_lock_init(&events->pmu_lock);
939 events->percpu_pmu = pmu;
950 struct arm_pmu *armpmu_alloc(void)
952 return __armpmu_alloc(GFP_KERNEL);
955 struct arm_pmu *armpmu_alloc_atomic(void)
957 return __armpmu_alloc(GFP_ATOMIC);
961 void armpmu_free(struct arm_pmu *pmu)
963 free_percpu(pmu->hw_events);
967 int armpmu_register(struct arm_pmu *pmu)
971 ret = cpu_pmu_init(pmu);
975 if (!pmu->set_event_filter)
976 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;
978 ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
982 if (!__oprofile_cpu_pmu)
983 __oprofile_cpu_pmu = pmu;
985 pr_info("enabled with %s PMU driver, %d counters available%s\n",
986 pmu->name, pmu->num_events,
987 has_nmi ? ", using NMIs" : "");
992 cpu_pmu_destroy(pmu);
996 static int arm_pmu_hp_init(void)
1000 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING,
1001 "perf/arm/pmu:starting",
1002 arm_perf_starting_cpu,
1003 arm_perf_teardown_cpu);
1005 pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n",
1009 subsys_initcall(arm_pmu_hp_init);