drivers/perf/arm_pmu.c

   1 #undef DEBUG
   2
   3 /*
   4  * ARM performance counter support.
   5  *
   6  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
   7  * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
   8  *
   9  * This code is based on the sparc64 perf event code, which is in turn based
  10  * on the x86 code.
  11  */
  12 #define pr_fmt(fmt) "hw perfevents: " fmt
  13
  14 #include <linux/bitmap.h>
  15 #include <linux/cpumask.h>
  16 #include <linux/cpu_pm.h>
  17 #include <linux/export.h>
  18 #include <linux/kernel.h>
  19 #include <linux/perf/arm_pmu.h>
  20 #include <linux/slab.h>
  21 #include <linux/sched/clock.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/irq.h>
  24 #include <linux/irqdesc.h>
  25
  26 #include <asm/irq_regs.h>
  27
  28 static DEFINE_PER_CPU(struct arm_pmu *, cpu_armpmu);
  29 static DEFINE_PER_CPU(int, cpu_irq);
  30
  31 static int
  32 armpmu_map_cache_event(const unsigned (*cache_map)
  33                                       [PERF_COUNT_HW_CACHE_MAX]
  34                                       [PERF_COUNT_HW_CACHE_OP_MAX]
  35                                       [PERF_COUNT_HW_CACHE_RESULT_MAX],
  36                        u64 config)
  37 {
  38         unsigned int cache_type, cache_op, cache_result, ret;
  39
  40         cache_type = (config >>  0) & 0xff;
  41         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
  42                 return -EINVAL;
  43
  44         cache_op = (config >>  8) & 0xff;
  45         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
  46                 return -EINVAL;
  47
  48         cache_result = (config >> 16) & 0xff;
  49         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  50                 return -EINVAL;
  51
  52         if (!cache_map)
  53                 return -ENOENT;
  54
  55         ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
  56
  57         if (ret == CACHE_OP_UNSUPPORTED)
  58                 return -ENOENT;
  59
  60         return ret;
  61 }
  62
  63 static int
  64 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
  65 {
  66         int mapping;
  67
  68         if (config >= PERF_COUNT_HW_MAX)
  69                 return -EINVAL;
  70
  71         if (!event_map)
  72                 return -ENOENT;
  73
  74         mapping = (*event_map)[config];
  75         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
  76 }
  77
  78 static int
  79 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
  80 {
  81         return (int)(config & raw_event_mask);
  82 }
  83
  84 int
  85 armpmu_map_event(struct perf_event *event,
  86                  const unsigned (*event_map)[PERF_COUNT_HW_MAX],
  87                  const unsigned (*cache_map)
  88                                 [PERF_COUNT_HW_CACHE_MAX]
  89                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  90                                 [PERF_COUNT_HW_CACHE_RESULT_MAX],
  91                  u32 raw_event_mask)
  92 {
  93         u64 config = event->attr.config;
  94         int type = event->attr.type;
  95
  96         if (type == event->pmu->type)
  97                 return armpmu_map_raw_event(raw_event_mask, config);
  98
  99         switch (type) {
 100         case PERF_TYPE_HARDWARE:
 101                 return armpmu_map_hw_event(event_map, config);
 102         case PERF_TYPE_HW_CACHE:
 103                 return armpmu_map_cache_event(cache_map, config);
 104         case PERF_TYPE_RAW:
 105                 return armpmu_map_raw_event(raw_event_mask, config);
 106         }
 107
 108         return -ENOENT;
 109 }
 110
 111 int armpmu_event_set_period(struct perf_event *event)
 112 {
 113         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 114         struct hw_perf_event *hwc = &event->hw;
 115         s64 left = local64_read(&hwc->period_left);
 116         s64 period = hwc->sample_period;
 117         int ret = 0;
 118
 119         if (unlikely(left <= -period)) {
 120                 left = period;
 121                 local64_set(&hwc->period_left, left);
 122                 hwc->last_period = period;
 123                 ret = 1;
 124         }
 125
 126         if (unlikely(left <= 0)) {
 127                 left += period;
 128                 local64_set(&hwc->period_left, left);
 129                 hwc->last_period = period;
 130                 ret = 1;
 131         }
 132
 133         /*
 134          * Limit the maximum period to prevent the counter value
 135          * from overtaking the one we are about to program. In
 136          * effect we are reducing max_period to account for
 137          * interrupt latency (and we are being very conservative).
 138          */
 139         if (left > (armpmu->max_period >> 1))
 140                 left = armpmu->max_period >> 1;
 141
 142         local64_set(&hwc->prev_count, (u64)-left);
 143
 144         armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
 145
 146         perf_event_update_userpage(event);
 147
 148         return ret;
 149 }
 150
 151 u64 armpmu_event_update(struct perf_event *event)
 152 {
 153         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 154         struct hw_perf_event *hwc = &event->hw;
 155         u64 delta, prev_raw_count, new_raw_count;
 156
 157 again:
 158         prev_raw_count = local64_read(&hwc->prev_count);
 159         new_raw_count = armpmu->read_counter(event);
 160
 161         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 162                              new_raw_count) != prev_raw_count)
 163                 goto again;
 164
 165         delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
 166
 167         local64_add(delta, &event->count);
 168         local64_sub(delta, &hwc->period_left);
 169
 170         return new_raw_count;
 171 }
 172
 173 static void
 174 armpmu_read(struct perf_event *event)
 175 {
 176         armpmu_event_update(event);
 177 }
 178
 179 static void
 180 armpmu_stop(struct perf_event *event, int flags)
 181 {
 182         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 183         struct hw_perf_event *hwc = &event->hw;
 184
 185         /*
 186          * ARM pmu always has to update the counter, so ignore
 187          * PERF_EF_UPDATE, see comments in armpmu_start().
 188          */
 189         if (!(hwc->state & PERF_HES_STOPPED)) {
 190                 armpmu->disable(event);
 191                 armpmu_event_update(event);
 192                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 193         }
 194 }
 195
 196 static void armpmu_start(struct perf_event *event, int flags)
 197 {
 198         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 199         struct hw_perf_event *hwc = &event->hw;
 200
 201         /*
 202          * ARM pmu always has to reprogram the period, so ignore
 203          * PERF_EF_RELOAD, see the comment below.
 204          */
 205         if (flags & PERF_EF_RELOAD)
 206                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 207
 208         hwc->state = 0;
 209         /*
 210          * Set the period again. Some counters can't be stopped, so when we
 211          * were stopped we simply disabled the IRQ source and the counter
 212          * may have been left counting. If we don't do this step then we may
 213          * get an interrupt too soon or *way* too late if the overflow has
 214          * happened since disabling.
 215          */
 216         armpmu_event_set_period(event);
 217         armpmu->enable(event);
 218 }
 219
 220 static void
 221 armpmu_del(struct perf_event *event, int flags)
 222 {
 223         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 224         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 225         struct hw_perf_event *hwc = &event->hw;
 226         int idx = hwc->idx;
 227
 228         armpmu_stop(event, PERF_EF_UPDATE);
 229         hw_events->events[idx] = NULL;
 230         clear_bit(idx, hw_events->used_mask);
 231         if (armpmu->clear_event_idx)
 232                 armpmu->clear_event_idx(hw_events, event);
 233
 234         perf_event_update_userpage(event);
 235 }
 236
 237 static int
 238 armpmu_add(struct perf_event *event, int flags)
 239 {
 240         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 241         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 242         struct hw_perf_event *hwc = &event->hw;
 243         int idx;
 244
 245         /* An event following a process won't be stopped earlier */
 246         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 247                 return -ENOENT;
 248
 249         /* If we don't have a space for the counter then finish early. */
 250         idx = armpmu->get_event_idx(hw_events, event);
 251         if (idx < 0)
 252                 return idx;
 253
 254         /*
 255          * If there is an event in the counter we are going to use then make
 256          * sure it is disabled.
 257          */
 258         event->hw.idx = idx;
 259         armpmu->disable(event);
 260         hw_events->events[idx] = event;
 261
 262         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 263         if (flags & PERF_EF_START)
 264                 armpmu_start(event, PERF_EF_RELOAD);
 265
 266         /* Propagate our changes to the userspace mapping. */
 267         perf_event_update_userpage(event);
 268
 269         return 0;
 270 }
 271
 272 static int
 273 validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
 274                                struct perf_event *event)
 275 {
 276         struct arm_pmu *armpmu;
 277
 278         if (is_software_event(event))
 279                 return 1;
 280
 281         /*
 282          * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
 283          * core perf code won't check that the pmu->ctx == leader->ctx
 284          * until after pmu->event_init(event).
 285          */
 286         if (event->pmu != pmu)
 287                 return 0;
 288
 289         if (event->state < PERF_EVENT_STATE_OFF)
 290                 return 1;
 291
 292         if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
 293                 return 1;
 294
 295         armpmu = to_arm_pmu(event->pmu);
 296         return armpmu->get_event_idx(hw_events, event) >= 0;
 297 }
 298
 299 static int
 300 validate_group(struct perf_event *event)
 301 {
 302         struct perf_event *sibling, *leader = event->group_leader;
 303         struct pmu_hw_events fake_pmu;
 304
 305         /*
 306          * Initialise the fake PMU. We only need to populate the
 307          * used_mask for the purposes of validation.
 308          */
 309         memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
 310
 311         if (!validate_event(event->pmu, &fake_pmu, leader))
 312                 return -EINVAL;
 313
 314         for_each_sibling_event(sibling, leader) {
 315                 if (!validate_event(event->pmu, &fake_pmu, sibling))
 316                         return -EINVAL;
 317         }
 318
 319         if (!validate_event(event->pmu, &fake_pmu, event))
 320                 return -EINVAL;
 321
 322         return 0;
 323 }
 324
 325 static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
 326 {
 327         struct arm_pmu *armpmu;
 328         int ret;
 329         u64 start_clock, finish_clock;
 330
 331         /*
 332          * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
 333          * the handlers expect a struct arm_pmu*. The percpu_irq framework will
 334          * do any necessary shifting, we just need to perform the first
 335          * dereference.
 336          */
 337         armpmu = *(void **)dev;
 338         if (WARN_ON_ONCE(!armpmu))
 339                 return IRQ_NONE;
 340
 341         start_clock = sched_clock();
 342         ret = armpmu->handle_irq(armpmu);
 343         finish_clock = sched_clock();
 344
 345         perf_sample_event_took(finish_clock - start_clock);
 346         return ret;
 347 }
 348
 349 static int
 350 event_requires_mode_exclusion(struct perf_event_attr *attr)
 351 {
 352         return attr->exclude_idle || attr->exclude_user ||
 353                attr->exclude_kernel || attr->exclude_hv;
 354 }
 355
 356 static int
 357 __hw_perf_event_init(struct perf_event *event)
 358 {
 359         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 360         struct hw_perf_event *hwc = &event->hw;
 361         int mapping;
 362
 363         mapping = armpmu->map_event(event);
 364
 365         if (mapping < 0) {
 366                 pr_debug("event %x:%llx not supported\n", event->attr.type,
 367                          event->attr.config);
 368                 return mapping;
 369         }
 370
 371         /*
 372          * We don't assign an index until we actually place the event onto
 373          * hardware. Use -1 to signify that we haven't decided where to put it
 374          * yet. For SMP systems, each core has it's own PMU so we can't do any
 375          * clever allocation or constraints checking at this point.
 376          */
 377         hwc->idx                = -1;
 378         hwc->config_base        = 0;
 379         hwc->config             = 0;
 380         hwc->event_base         = 0;
 381
 382         /*
 383          * Check whether we need to exclude the counter from certain modes.
 384          */
 385         if ((!armpmu->set_event_filter ||
 386              armpmu->set_event_filter(hwc, &event->attr)) &&
 387              event_requires_mode_exclusion(&event->attr)) {
 388                 pr_debug("ARM performance counters do not support "
 389                          "mode exclusion\n");
 390                 return -EOPNOTSUPP;
 391         }
 392
 393         /*
 394          * Store the event encoding into the config_base field.
 395          */
 396         hwc->config_base            |= (unsigned long)mapping;
 397
 398         if (!is_sampling_event(event)) {
 399                 /*
 400                  * For non-sampling runs, limit the sample_period to half
 401                  * of the counter width. That way, the new counter value
 402                  * is far less likely to overtake the previous one unless
 403                  * you have some serious IRQ latency issues.
 404                  */
 405                 hwc->sample_period  = armpmu->max_period >> 1;
 406                 hwc->last_period    = hwc->sample_period;
 407                 local64_set(&hwc->period_left, hwc->sample_period);
 408         }
 409
 410         if (event->group_leader != event) {
 411                 if (validate_group(event) != 0)
 412                         return -EINVAL;
 413         }
 414
 415         return 0;
 416 }
 417
 418 static int armpmu_event_init(struct perf_event *event)
 419 {
 420         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 421
 422         /*
 423          * Reject CPU-affine events for CPUs that are of a different class to
 424          * that which this PMU handles. Process-following events (where
 425          * event->cpu == -1) can be migrated between CPUs, and thus we have to
 426          * reject them later (in armpmu_add) if they're scheduled on a
 427          * different class of CPU.
 428          */
 429         if (event->cpu != -1 &&
 430                 !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
 431                 return -ENOENT;
 432
 433         /* does not support taken branch sampling */
 434         if (has_branch_stack(event))
 435                 return -EOPNOTSUPP;
 436
 437         if (armpmu->map_event(event) == -ENOENT)
 438                 return -ENOENT;
 439
 440         return __hw_perf_event_init(event);
 441 }
 442
 443 static void armpmu_enable(struct pmu *pmu)
 444 {
 445         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 446         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 447         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
 448
 449         /* For task-bound events we may be called on other CPUs */
 450         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 451                 return;
 452
 453         if (enabled)
 454                 armpmu->start(armpmu);
 455 }
 456
 457 static void armpmu_disable(struct pmu *pmu)
 458 {
 459         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 460
 461         /* For task-bound events we may be called on other CPUs */
 462         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 463                 return;
 464
 465         armpmu->stop(armpmu);
 466 }
 467
 468 /*
 469  * In heterogeneous systems, events are specific to a particular
 470  * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
 471  * the same microarchitecture.
 472  */
 473 static int armpmu_filter_match(struct perf_event *event)
 474 {
 475         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 476         unsigned int cpu = smp_processor_id();
 477         return cpumask_test_cpu(cpu, &armpmu->supported_cpus);
 478 }
 479
 480 static ssize_t armpmu_cpumask_show(struct device *dev,
 481                                    struct device_attribute *attr, char *buf)
 482 {
 483         struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev));
 484         return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus);
 485 }
 486
 487 static DEVICE_ATTR(cpus, S_IRUGO, armpmu_cpumask_show, NULL);
 488
 489 static struct attribute *armpmu_common_attrs[] = {
 490         &dev_attr_cpus.attr,
 491         NULL,
 492 };
 493
 494 static struct attribute_group armpmu_common_attr_group = {
 495         .attrs = armpmu_common_attrs,
 496 };
 497
 498 /* Set at runtime when we know what CPU type we are. */
 499 static struct arm_pmu *__oprofile_cpu_pmu;
 500
 501 /*
 502  * Despite the names, these two functions are CPU-specific and are used
 503  * by the OProfile/perf code.
 504  */
 505 const char *perf_pmu_name(void)
 506 {
 507         if (!__oprofile_cpu_pmu)
 508                 return NULL;
 509
 510         return __oprofile_cpu_pmu->name;
 511 }
 512 EXPORT_SYMBOL_GPL(perf_pmu_name);
 513
 514 int perf_num_counters(void)
 515 {
 516         int max_events = 0;
 517
 518         if (__oprofile_cpu_pmu != NULL)
 519                 max_events = __oprofile_cpu_pmu->num_events;
 520
 521         return max_events;
 522 }
 523 EXPORT_SYMBOL_GPL(perf_num_counters);
 524
 525 static int armpmu_count_irq_users(const int irq)
 526 {
 527         int cpu, count = 0;
 528
 529         for_each_possible_cpu(cpu) {
 530                 if (per_cpu(cpu_irq, cpu) == irq)
 531                         count++;
 532         }
 533
 534         return count;
 535 }
 536
 537 void armpmu_free_irq(int irq, int cpu)
 538 {
 539         if (per_cpu(cpu_irq, cpu) == 0)
 540                 return;
 541         if (WARN_ON(irq != per_cpu(cpu_irq, cpu)))
 542                 return;
 543
 544         if (!irq_is_percpu_devid(irq))
 545                 free_irq(irq, per_cpu_ptr(&cpu_armpmu, cpu));
 546         else if (armpmu_count_irq_users(irq) == 1)
 547                 free_percpu_irq(irq, &cpu_armpmu);
 548
 549         per_cpu(cpu_irq, cpu) = 0;
 550 }
 551
 552 int armpmu_request_irq(int irq, int cpu)
 553 {
 554         int err = 0;
 555         const irq_handler_t handler = armpmu_dispatch_irq;
 556         if (!irq)
 557                 return 0;
 558
 559         if (!irq_is_percpu_devid(irq)) {
 560                 unsigned long irq_flags;
 561
 562                 err = irq_force_affinity(irq, cpumask_of(cpu));
 563
 564                 if (err && num_possible_cpus() > 1) {
 565                         pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
 566                                 irq, cpu);
 567                         goto err_out;
 568                 }
 569
 570                 irq_flags = IRQF_PERCPU |
 571                             IRQF_NOBALANCING |
 572                             IRQF_NO_THREAD;
 573
 574                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
 575                 err = request_irq(irq, handler, irq_flags, "arm-pmu",
 576                                   per_cpu_ptr(&cpu_armpmu, cpu));
 577         } else if (armpmu_count_irq_users(irq) == 0) {
 578                 err = request_percpu_irq(irq, handler, "arm-pmu",
 579                                          &cpu_armpmu);
 580         }
 581
 582         if (err)
 583                 goto err_out;
 584
 585         per_cpu(cpu_irq, cpu) = irq;
 586         return 0;
 587
 588 err_out:
 589         pr_err("unable to request IRQ%d for ARM PMU counters\n", irq);
 590         return err;
 591 }
 592
 593 static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu)
 594 {
 595         struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
 596         return per_cpu(hw_events->irq, cpu);
 597 }
 598
 599 /*
 600  * PMU hardware loses all context when a CPU goes offline.
 601  * When a CPU is hotplugged back in, since some hardware registers are
 602  * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
 603  * junk values out of them.
 604  */
 605 static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node)
 606 {
 607         struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
 608         int irq;
 609
 610         if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
 611                 return 0;
 612         if (pmu->reset)
 613                 pmu->reset(pmu);
 614
 615         per_cpu(cpu_armpmu, cpu) = pmu;
 616
 617         irq = armpmu_get_cpu_irq(pmu, cpu);
 618         if (irq) {
 619                 if (irq_is_percpu_devid(irq))
 620                         enable_percpu_irq(irq, IRQ_TYPE_NONE);
 621                 else
 622                         enable_irq(irq);
 623         }
 624
 625         return 0;
 626 }
 627
 628 static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node)
 629 {
 630         struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
 631         int irq;
 632
 633         if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
 634                 return 0;
 635
 636         irq = armpmu_get_cpu_irq(pmu, cpu);
 637         if (irq) {
 638                 if (irq_is_percpu_devid(irq))
 639                         disable_percpu_irq(irq);
 640                 else
 641                         disable_irq_nosync(irq);
 642         }
 643
 644         per_cpu(cpu_armpmu, cpu) = NULL;
 645
 646         return 0;
 647 }
 648
 649 #ifdef CONFIG_CPU_PM
 650 static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
 651 {
 652         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 653         struct perf_event *event;
 654         int idx;
 655
 656         for (idx = 0; idx < armpmu->num_events; idx++) {
 657                 /*
 658                  * If the counter is not used skip it, there is no
 659                  * need of stopping/restarting it.
 660                  */
 661                 if (!test_bit(idx, hw_events->used_mask))
 662                         continue;
 663
 664                 event = hw_events->events[idx];
 665
 666                 switch (cmd) {
 667                 case CPU_PM_ENTER:
 668                         /*
 669                          * Stop and update the counter
 670                          */
 671                         armpmu_stop(event, PERF_EF_UPDATE);
 672                         break;
 673                 case CPU_PM_EXIT:
 674                 case CPU_PM_ENTER_FAILED:
 675                          /*
 676                           * Restore and enable the counter.
 677                           * armpmu_start() indirectly calls
 678                           *
 679                           * perf_event_update_userpage()
 680                           *
 681                           * that requires RCU read locking to be functional,
 682                           * wrap the call within RCU_NONIDLE to make the
 683                           * RCU subsystem aware this cpu is not idle from
 684                           * an RCU perspective for the armpmu_start() call
 685                           * duration.
 686                           */
 687                         RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
 688                         break;
 689                 default:
 690                         break;
 691                 }
 692         }
 693 }
 694
 695 static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
 696                              void *v)
 697 {
 698         struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
 699         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 700         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
 701
 702         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 703                 return NOTIFY_DONE;
 704
 705         /*
 706          * Always reset the PMU registers on power-up even if
 707          * there are no events running.
 708          */
 709         if (cmd == CPU_PM_EXIT && armpmu->reset)
 710                 armpmu->reset(armpmu);
 711
 712         if (!enabled)
 713                 return NOTIFY_OK;
 714
 715         switch (cmd) {
 716         case CPU_PM_ENTER:
 717                 armpmu->stop(armpmu);
 718                 cpu_pm_pmu_setup(armpmu, cmd);
 719                 break;
 720         case CPU_PM_EXIT:
 721                 cpu_pm_pmu_setup(armpmu, cmd);
 722         case CPU_PM_ENTER_FAILED:
 723                 armpmu->start(armpmu);
 724                 break;
 725         default:
 726                 return NOTIFY_DONE;
 727         }
 728
 729         return NOTIFY_OK;
 730 }
 731
 732 static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
 733 {
 734         cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
 735         return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
 736 }
 737
 738 static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
 739 {
 740         cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
 741 }
 742 #else
 743 static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
 744 static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
 745 #endif
 746
 747 static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
 748 {
 749         int err;
 750
 751         err = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_STARTING,
 752                                        &cpu_pmu->node);
 753         if (err)
 754                 goto out;
 755
 756         err = cpu_pm_pmu_register(cpu_pmu);
 757         if (err)
 758                 goto out_unregister;
 759
 760         return 0;
 761
 762 out_unregister:
 763         cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
 764                                             &cpu_pmu->node);
 765 out:
 766         return err;
 767 }
 768
 769 static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
 770 {
 771         cpu_pm_pmu_unregister(cpu_pmu);
 772         cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
 773                                             &cpu_pmu->node);
 774 }
 775
 776 static struct arm_pmu *__armpmu_alloc(gfp_t flags)
 777 {
 778         struct arm_pmu *pmu;
 779         int cpu;
 780
 781         pmu = kzalloc(sizeof(*pmu), flags);
 782         if (!pmu) {
 783                 pr_info("failed to allocate PMU device!\n");
 784                 goto out;
 785         }
 786
 787         pmu->hw_events = alloc_percpu_gfp(struct pmu_hw_events, flags);
 788         if (!pmu->hw_events) {
 789                 pr_info("failed to allocate per-cpu PMU data.\n");
 790                 goto out_free_pmu;
 791         }
 792
 793         pmu->pmu = (struct pmu) {
 794                 .pmu_enable     = armpmu_enable,
 795                 .pmu_disable    = armpmu_disable,
 796                 .event_init     = armpmu_event_init,
 797                 .add            = armpmu_add,
 798                 .del            = armpmu_del,
 799                 .start          = armpmu_start,
 800                 .stop           = armpmu_stop,
 801                 .read           = armpmu_read,
 802                 .filter_match   = armpmu_filter_match,
 803                 .attr_groups    = pmu->attr_groups,
 804                 /*
 805                  * This is a CPU PMU potentially in a heterogeneous
 806                  * configuration (e.g. big.LITTLE). This is not an uncore PMU,
 807                  * and we have taken ctx sharing into account (e.g. with our
 808                  * pmu::filter_match callback and pmu::event_init group
 809                  * validation).
 810                  */
 811                 .capabilities   = PERF_PMU_CAP_HETEROGENEOUS_CPUS,
 812         };
 813
 814         pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =
 815                 &armpmu_common_attr_group;
 816
 817         for_each_possible_cpu(cpu) {
 818                 struct pmu_hw_events *events;
 819
 820                 events = per_cpu_ptr(pmu->hw_events, cpu);
 821                 raw_spin_lock_init(&events->pmu_lock);
 822                 events->percpu_pmu = pmu;
 823         }
 824
 825         return pmu;
 826
 827 out_free_pmu:
 828         kfree(pmu);
 829 out:
 830         return NULL;
 831 }
 832
 833 struct arm_pmu *armpmu_alloc(void)
 834 {
 835         return __armpmu_alloc(GFP_KERNEL);
 836 }
 837
 838 struct arm_pmu *armpmu_alloc_atomic(void)
 839 {
 840         return __armpmu_alloc(GFP_ATOMIC);
 841 }
 842
 843
 844 void armpmu_free(struct arm_pmu *pmu)
 845 {
 846         free_percpu(pmu->hw_events);
 847         kfree(pmu);
 848 }
 849
 850 int armpmu_register(struct arm_pmu *pmu)
 851 {
 852         int ret;
 853
 854         ret = cpu_pmu_init(pmu);
 855         if (ret)
 856                 return ret;
 857
 858         ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
 859         if (ret)
 860                 goto out_destroy;
 861
 862         if (!__oprofile_cpu_pmu)
 863                 __oprofile_cpu_pmu = pmu;
 864
 865         pr_info("enabled with %s PMU driver, %d counters available\n",
 866                 pmu->name, pmu->num_events);
 867
 868         return 0;
 869
 870 out_destroy:
 871         cpu_pmu_destroy(pmu);
 872         return ret;
 873 }
 874
 875 static int arm_pmu_hp_init(void)
 876 {
 877         int ret;
 878
 879         ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING,
 880                                       "perf/arm/pmu:starting",
 881                                       arm_perf_starting_cpu,
 882                                       arm_perf_teardown_cpu);
 883         if (ret)
 884                 pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n",
 885                        ret);
 886         return ret;
 887 }
 888 subsys_initcall(arm_pmu_hp_init);