drivers/perf/arm_pmu.c

   1 #undef DEBUG
   2
   3 /*
   4  * ARM performance counter support.
   5  *
   6  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
   7  * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
   8  *
   9  * This code is based on the sparc64 perf event code, which is in turn based
  10  * on the x86 code.
  11  */
  12 #define pr_fmt(fmt) "hw perfevents: " fmt
  13
  14 #include <linux/bitmap.h>
  15 #include <linux/cpumask.h>
  16 #include <linux/cpu_pm.h>
  17 #include <linux/export.h>
  18 #include <linux/kernel.h>
  19 #include <linux/of_device.h>
  20 #include <linux/perf/arm_pmu.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23 #include <linux/sched/clock.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/irq.h>
  26 #include <linux/irqdesc.h>
  27
  28 #include <asm/cputype.h>
  29 #include <asm/irq_regs.h>
  30
  31 static int
  32 armpmu_map_cache_event(const unsigned (*cache_map)
  33                                       [PERF_COUNT_HW_CACHE_MAX]
  34                                       [PERF_COUNT_HW_CACHE_OP_MAX]
  35                                       [PERF_COUNT_HW_CACHE_RESULT_MAX],
  36                        u64 config)
  37 {
  38         unsigned int cache_type, cache_op, cache_result, ret;
  39
  40         cache_type = (config >>  0) & 0xff;
  41         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
  42                 return -EINVAL;
  43
  44         cache_op = (config >>  8) & 0xff;
  45         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
  46                 return -EINVAL;
  47
  48         cache_result = (config >> 16) & 0xff;
  49         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  50                 return -EINVAL;
  51
  52         ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
  53
  54         if (ret == CACHE_OP_UNSUPPORTED)
  55                 return -ENOENT;
  56
  57         return ret;
  58 }
  59
  60 static int
  61 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
  62 {
  63         int mapping;
  64
  65         if (config >= PERF_COUNT_HW_MAX)
  66                 return -EINVAL;
  67
  68         mapping = (*event_map)[config];
  69         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
  70 }
  71
  72 static int
  73 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
  74 {
  75         return (int)(config & raw_event_mask);
  76 }
  77
  78 int
  79 armpmu_map_event(struct perf_event *event,
  80                  const unsigned (*event_map)[PERF_COUNT_HW_MAX],
  81                  const unsigned (*cache_map)
  82                                 [PERF_COUNT_HW_CACHE_MAX]
  83                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  84                                 [PERF_COUNT_HW_CACHE_RESULT_MAX],
  85                  u32 raw_event_mask)
  86 {
  87         u64 config = event->attr.config;
  88         int type = event->attr.type;
  89
  90         if (type == event->pmu->type)
  91                 return armpmu_map_raw_event(raw_event_mask, config);
  92
  93         switch (type) {
  94         case PERF_TYPE_HARDWARE:
  95                 return armpmu_map_hw_event(event_map, config);
  96         case PERF_TYPE_HW_CACHE:
  97                 return armpmu_map_cache_event(cache_map, config);
  98         case PERF_TYPE_RAW:
  99                 return armpmu_map_raw_event(raw_event_mask, config);
 100         }
 101
 102         return -ENOENT;
 103 }
 104
 105 int armpmu_event_set_period(struct perf_event *event)
 106 {
 107         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 108         struct hw_perf_event *hwc = &event->hw;
 109         s64 left = local64_read(&hwc->period_left);
 110         s64 period = hwc->sample_period;
 111         int ret = 0;
 112
 113         if (unlikely(left <= -period)) {
 114                 left = period;
 115                 local64_set(&hwc->period_left, left);
 116                 hwc->last_period = period;
 117                 ret = 1;
 118         }
 119
 120         if (unlikely(left <= 0)) {
 121                 left += period;
 122                 local64_set(&hwc->period_left, left);
 123                 hwc->last_period = period;
 124                 ret = 1;
 125         }
 126
 127         /*
 128          * Limit the maximum period to prevent the counter value
 129          * from overtaking the one we are about to program. In
 130          * effect we are reducing max_period to account for
 131          * interrupt latency (and we are being very conservative).
 132          */
 133         if (left > (armpmu->max_period >> 1))
 134                 left = armpmu->max_period >> 1;
 135
 136         local64_set(&hwc->prev_count, (u64)-left);
 137
 138         armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
 139
 140         perf_event_update_userpage(event);
 141
 142         return ret;
 143 }
 144
 145 u64 armpmu_event_update(struct perf_event *event)
 146 {
 147         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 148         struct hw_perf_event *hwc = &event->hw;
 149         u64 delta, prev_raw_count, new_raw_count;
 150
 151 again:
 152         prev_raw_count = local64_read(&hwc->prev_count);
 153         new_raw_count = armpmu->read_counter(event);
 154
 155         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 156                              new_raw_count) != prev_raw_count)
 157                 goto again;
 158
 159         delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
 160
 161         local64_add(delta, &event->count);
 162         local64_sub(delta, &hwc->period_left);
 163
 164         return new_raw_count;
 165 }
 166
 167 static void
 168 armpmu_read(struct perf_event *event)
 169 {
 170         armpmu_event_update(event);
 171 }
 172
 173 static void
 174 armpmu_stop(struct perf_event *event, int flags)
 175 {
 176         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 177         struct hw_perf_event *hwc = &event->hw;
 178
 179         /*
 180          * ARM pmu always has to update the counter, so ignore
 181          * PERF_EF_UPDATE, see comments in armpmu_start().
 182          */
 183         if (!(hwc->state & PERF_HES_STOPPED)) {
 184                 armpmu->disable(event);
 185                 armpmu_event_update(event);
 186                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 187         }
 188 }
 189
 190 static void armpmu_start(struct perf_event *event, int flags)
 191 {
 192         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 193         struct hw_perf_event *hwc = &event->hw;
 194
 195         /*
 196          * ARM pmu always has to reprogram the period, so ignore
 197          * PERF_EF_RELOAD, see the comment below.
 198          */
 199         if (flags & PERF_EF_RELOAD)
 200                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 201
 202         hwc->state = 0;
 203         /*
 204          * Set the period again. Some counters can't be stopped, so when we
 205          * were stopped we simply disabled the IRQ source and the counter
 206          * may have been left counting. If we don't do this step then we may
 207          * get an interrupt too soon or *way* too late if the overflow has
 208          * happened since disabling.
 209          */
 210         armpmu_event_set_period(event);
 211         armpmu->enable(event);
 212 }
 213
 214 static void
 215 armpmu_del(struct perf_event *event, int flags)
 216 {
 217         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 218         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 219         struct hw_perf_event *hwc = &event->hw;
 220         int idx = hwc->idx;
 221
 222         armpmu_stop(event, PERF_EF_UPDATE);
 223         hw_events->events[idx] = NULL;
 224         clear_bit(idx, hw_events->used_mask);
 225         if (armpmu->clear_event_idx)
 226                 armpmu->clear_event_idx(hw_events, event);
 227
 228         perf_event_update_userpage(event);
 229 }
 230
 231 static int
 232 armpmu_add(struct perf_event *event, int flags)
 233 {
 234         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 235         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 236         struct hw_perf_event *hwc = &event->hw;
 237         int idx;
 238
 239         /* An event following a process won't be stopped earlier */
 240         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 241                 return -ENOENT;
 242
 243         /* If we don't have a space for the counter then finish early. */
 244         idx = armpmu->get_event_idx(hw_events, event);
 245         if (idx < 0)
 246                 return idx;
 247
 248         /*
 249          * If there is an event in the counter we are going to use then make
 250          * sure it is disabled.
 251          */
 252         event->hw.idx = idx;
 253         armpmu->disable(event);
 254         hw_events->events[idx] = event;
 255
 256         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 257         if (flags & PERF_EF_START)
 258                 armpmu_start(event, PERF_EF_RELOAD);
 259
 260         /* Propagate our changes to the userspace mapping. */
 261         perf_event_update_userpage(event);
 262
 263         return 0;
 264 }
 265
 266 static int
 267 validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
 268                                struct perf_event *event)
 269 {
 270         struct arm_pmu *armpmu;
 271
 272         if (is_software_event(event))
 273                 return 1;
 274
 275         /*
 276          * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
 277          * core perf code won't check that the pmu->ctx == leader->ctx
 278          * until after pmu->event_init(event).
 279          */
 280         if (event->pmu != pmu)
 281                 return 0;
 282
 283         if (event->state < PERF_EVENT_STATE_OFF)
 284                 return 1;
 285
 286         if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
 287                 return 1;
 288
 289         armpmu = to_arm_pmu(event->pmu);
 290         return armpmu->get_event_idx(hw_events, event) >= 0;
 291 }
 292
 293 static int
 294 validate_group(struct perf_event *event)
 295 {
 296         struct perf_event *sibling, *leader = event->group_leader;
 297         struct pmu_hw_events fake_pmu;
 298
 299         /*
 300          * Initialise the fake PMU. We only need to populate the
 301          * used_mask for the purposes of validation.
 302          */
 303         memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
 304
 305         if (!validate_event(event->pmu, &fake_pmu, leader))
 306                 return -EINVAL;
 307
 308         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
 309                 if (!validate_event(event->pmu, &fake_pmu, sibling))
 310                         return -EINVAL;
 311         }
 312
 313         if (!validate_event(event->pmu, &fake_pmu, event))
 314                 return -EINVAL;
 315
 316         return 0;
 317 }
 318
 319 static struct arm_pmu_platdata *armpmu_get_platdata(struct arm_pmu *armpmu)
 320 {
 321         struct platform_device *pdev = armpmu->plat_device;
 322
 323         return pdev ? dev_get_platdata(&pdev->dev) : NULL;
 324 }
 325
 326 static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
 327 {
 328         struct arm_pmu *armpmu;
 329         struct arm_pmu_platdata *plat;
 330         int ret;
 331         u64 start_clock, finish_clock;
 332
 333         /*
 334          * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
 335          * the handlers expect a struct arm_pmu*. The percpu_irq framework will
 336          * do any necessary shifting, we just need to perform the first
 337          * dereference.
 338          */
 339         armpmu = *(void **)dev;
 340
 341         plat = armpmu_get_platdata(armpmu);
 342
 343         start_clock = sched_clock();
 344         if (plat && plat->handle_irq)
 345                 ret = plat->handle_irq(irq, armpmu, armpmu->handle_irq);
 346         else
 347                 ret = armpmu->handle_irq(irq, armpmu);
 348         finish_clock = sched_clock();
 349
 350         perf_sample_event_took(finish_clock - start_clock);
 351         return ret;
 352 }
 353
 354 static int
 355 event_requires_mode_exclusion(struct perf_event_attr *attr)
 356 {
 357         return attr->exclude_idle || attr->exclude_user ||
 358                attr->exclude_kernel || attr->exclude_hv;
 359 }
 360
 361 static int
 362 __hw_perf_event_init(struct perf_event *event)
 363 {
 364         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 365         struct hw_perf_event *hwc = &event->hw;
 366         int mapping;
 367
 368         mapping = armpmu->map_event(event);
 369
 370         if (mapping < 0) {
 371                 pr_debug("event %x:%llx not supported\n", event->attr.type,
 372                          event->attr.config);
 373                 return mapping;
 374         }
 375
 376         /*
 377          * We don't assign an index until we actually place the event onto
 378          * hardware. Use -1 to signify that we haven't decided where to put it
 379          * yet. For SMP systems, each core has it's own PMU so we can't do any
 380          * clever allocation or constraints checking at this point.
 381          */
 382         hwc->idx                = -1;
 383         hwc->config_base        = 0;
 384         hwc->config             = 0;
 385         hwc->event_base         = 0;
 386
 387         /*
 388          * Check whether we need to exclude the counter from certain modes.
 389          */
 390         if ((!armpmu->set_event_filter ||
 391              armpmu->set_event_filter(hwc, &event->attr)) &&
 392              event_requires_mode_exclusion(&event->attr)) {
 393                 pr_debug("ARM performance counters do not support "
 394                          "mode exclusion\n");
 395                 return -EOPNOTSUPP;
 396         }
 397
 398         /*
 399          * Store the event encoding into the config_base field.
 400          */
 401         hwc->config_base            |= (unsigned long)mapping;
 402
 403         if (!is_sampling_event(event)) {
 404                 /*
 405                  * For non-sampling runs, limit the sample_period to half
 406                  * of the counter width. That way, the new counter value
 407                  * is far less likely to overtake the previous one unless
 408                  * you have some serious IRQ latency issues.
 409                  */
 410                 hwc->sample_period  = armpmu->max_period >> 1;
 411                 hwc->last_period    = hwc->sample_period;
 412                 local64_set(&hwc->period_left, hwc->sample_period);
 413         }
 414
 415         if (event->group_leader != event) {
 416                 if (validate_group(event) != 0)
 417                         return -EINVAL;
 418         }
 419
 420         return 0;
 421 }
 422
 423 static int armpmu_event_init(struct perf_event *event)
 424 {
 425         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 426
 427         /*
 428          * Reject CPU-affine events for CPUs that are of a different class to
 429          * that which this PMU handles. Process-following events (where
 430          * event->cpu == -1) can be migrated between CPUs, and thus we have to
 431          * reject them later (in armpmu_add) if they're scheduled on a
 432          * different class of CPU.
 433          */
 434         if (event->cpu != -1 &&
 435                 !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
 436                 return -ENOENT;
 437
 438         /* does not support taken branch sampling */
 439         if (has_branch_stack(event))
 440                 return -EOPNOTSUPP;
 441
 442         if (armpmu->map_event(event) == -ENOENT)
 443                 return -ENOENT;
 444
 445         return __hw_perf_event_init(event);
 446 }
 447
 448 static void armpmu_enable(struct pmu *pmu)
 449 {
 450         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 451         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 452         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
 453
 454         /* For task-bound events we may be called on other CPUs */
 455         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 456                 return;
 457
 458         if (enabled)
 459                 armpmu->start(armpmu);
 460 }
 461
 462 static void armpmu_disable(struct pmu *pmu)
 463 {
 464         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 465
 466         /* For task-bound events we may be called on other CPUs */
 467         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 468                 return;
 469
 470         armpmu->stop(armpmu);
 471 }
 472
 473 /*
 474  * In heterogeneous systems, events are specific to a particular
 475  * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
 476  * the same microarchitecture.
 477  */
 478 static int armpmu_filter_match(struct perf_event *event)
 479 {
 480         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 481         unsigned int cpu = smp_processor_id();
 482         return cpumask_test_cpu(cpu, &armpmu->supported_cpus);
 483 }
 484
 485 static ssize_t armpmu_cpumask_show(struct device *dev,
 486                                    struct device_attribute *attr, char *buf)
 487 {
 488         struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev));
 489         return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus);
 490 }
 491
 492 static DEVICE_ATTR(cpus, S_IRUGO, armpmu_cpumask_show, NULL);
 493
 494 static struct attribute *armpmu_common_attrs[] = {
 495         &dev_attr_cpus.attr,
 496         NULL,
 497 };
 498
 499 static struct attribute_group armpmu_common_attr_group = {
 500         .attrs = armpmu_common_attrs,
 501 };
 502
 503 /* Set at runtime when we know what CPU type we are. */
 504 static struct arm_pmu *__oprofile_cpu_pmu;
 505
 506 /*
 507  * Despite the names, these two functions are CPU-specific and are used
 508  * by the OProfile/perf code.
 509  */
 510 const char *perf_pmu_name(void)
 511 {
 512         if (!__oprofile_cpu_pmu)
 513                 return NULL;
 514
 515         return __oprofile_cpu_pmu->name;
 516 }
 517 EXPORT_SYMBOL_GPL(perf_pmu_name);
 518
 519 int perf_num_counters(void)
 520 {
 521         int max_events = 0;
 522
 523         if (__oprofile_cpu_pmu != NULL)
 524                 max_events = __oprofile_cpu_pmu->num_events;
 525
 526         return max_events;
 527 }
 528 EXPORT_SYMBOL_GPL(perf_num_counters);
 529
 530 static void armpmu_free_irqs(struct arm_pmu *armpmu)
 531 {
 532         int cpu;
 533         struct pmu_hw_events __percpu *hw_events = armpmu->hw_events;
 534
 535         for_each_cpu(cpu, &armpmu->supported_cpus) {
 536                 int irq = per_cpu(hw_events->irq, cpu);
 537                 if (!irq)
 538                         continue;
 539
 540                 if (irq_is_percpu(irq)) {
 541                         free_percpu_irq(irq, &hw_events->percpu_pmu);
 542                         break;
 543                 }
 544
 545                 if (!cpumask_test_and_clear_cpu(cpu, &armpmu->active_irqs))
 546                         continue;
 547
 548                 free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, cpu));
 549         }
 550 }
 551
 552 static int armpmu_request_irqs(struct arm_pmu *armpmu)
 553 {
 554         int cpu, err;
 555         struct pmu_hw_events __percpu *hw_events = armpmu->hw_events;
 556         const irq_handler_t handler = armpmu_dispatch_irq;
 557
 558         for_each_cpu(cpu, &armpmu->supported_cpus) {
 559                 int irq = per_cpu(hw_events->irq, cpu);
 560                 if (!irq)
 561                         continue;
 562
 563                 if (irq_is_percpu(irq)) {
 564                         err = request_percpu_irq(irq, handler, "arm-pmu",
 565                                                  &hw_events->percpu_pmu);
 566                         if (err) {
 567                                 pr_err("unable to request IRQ%d for ARM PMU counters\n",
 568                                         irq);
 569                         }
 570
 571                         return err;
 572                 }
 573
 574                 err = request_irq(irq, handler,
 575                                   IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",
 576                                   per_cpu_ptr(&hw_events->percpu_pmu, cpu));
 577                 if (err) {
 578                         pr_err("unable to request IRQ%d for ARM PMU counters\n",
 579                                 irq);
 580                         return err;
 581                 }
 582
 583                 cpumask_set_cpu(cpu, &armpmu->active_irqs);
 584         }
 585
 586         return 0;
 587 }
 588
 589 static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu)
 590 {
 591         struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
 592         return per_cpu(hw_events->irq, cpu);
 593 }
 594
 595 /*
 596  * PMU hardware loses all context when a CPU goes offline.
 597  * When a CPU is hotplugged back in, since some hardware registers are
 598  * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
 599  * junk values out of them.
 600  */
 601 static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node)
 602 {
 603         struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
 604         int irq;
 605
 606         if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
 607                 return 0;
 608         if (pmu->reset)
 609                 pmu->reset(pmu);
 610
 611         irq = armpmu_get_cpu_irq(pmu, cpu);
 612         if (irq) {
 613                 if (irq_is_percpu(irq)) {
 614                         enable_percpu_irq(irq, IRQ_TYPE_NONE);
 615                         return 0;
 616                 }
 617
 618                 if (irq_force_affinity(irq, cpumask_of(cpu)) &&
 619                     num_possible_cpus() > 1) {
 620                         pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
 621                                 irq, cpu);
 622                 }
 623         }
 624
 625         return 0;
 626 }
 627
 628 static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node)
 629 {
 630         struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
 631         int irq;
 632
 633         if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
 634                 return 0;
 635
 636         irq = armpmu_get_cpu_irq(pmu, cpu);
 637         if (irq && irq_is_percpu(irq))
 638                 disable_percpu_irq(irq);
 639
 640         return 0;
 641 }
 642
 643 #ifdef CONFIG_CPU_PM
 644 static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
 645 {
 646         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 647         struct perf_event *event;
 648         int idx;
 649
 650         for (idx = 0; idx < armpmu->num_events; idx++) {
 651                 /*
 652                  * If the counter is not used skip it, there is no
 653                  * need of stopping/restarting it.
 654                  */
 655                 if (!test_bit(idx, hw_events->used_mask))
 656                         continue;
 657
 658                 event = hw_events->events[idx];
 659
 660                 switch (cmd) {
 661                 case CPU_PM_ENTER:
 662                         /*
 663                          * Stop and update the counter
 664                          */
 665                         armpmu_stop(event, PERF_EF_UPDATE);
 666                         break;
 667                 case CPU_PM_EXIT:
 668                 case CPU_PM_ENTER_FAILED:
 669                          /*
 670                           * Restore and enable the counter.
 671                           * armpmu_start() indirectly calls
 672                           *
 673                           * perf_event_update_userpage()
 674                           *
 675                           * that requires RCU read locking to be functional,
 676                           * wrap the call within RCU_NONIDLE to make the
 677                           * RCU subsystem aware this cpu is not idle from
 678                           * an RCU perspective for the armpmu_start() call
 679                           * duration.
 680                           */
 681                         RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
 682                         break;
 683                 default:
 684                         break;
 685                 }
 686         }
 687 }
 688
 689 static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
 690                              void *v)
 691 {
 692         struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
 693         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 694         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
 695
 696         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 697                 return NOTIFY_DONE;
 698
 699         /*
 700          * Always reset the PMU registers on power-up even if
 701          * there are no events running.
 702          */
 703         if (cmd == CPU_PM_EXIT && armpmu->reset)
 704                 armpmu->reset(armpmu);
 705
 706         if (!enabled)
 707                 return NOTIFY_OK;
 708
 709         switch (cmd) {
 710         case CPU_PM_ENTER:
 711                 armpmu->stop(armpmu);
 712                 cpu_pm_pmu_setup(armpmu, cmd);
 713                 break;
 714         case CPU_PM_EXIT:
 715                 cpu_pm_pmu_setup(armpmu, cmd);
 716         case CPU_PM_ENTER_FAILED:
 717                 armpmu->start(armpmu);
 718                 break;
 719         default:
 720                 return NOTIFY_DONE;
 721         }
 722
 723         return NOTIFY_OK;
 724 }
 725
 726 static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
 727 {
 728         cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
 729         return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
 730 }
 731
 732 static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
 733 {
 734         cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
 735 }
 736 #else
 737 static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
 738 static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
 739 #endif
 740
 741 static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
 742 {
 743         int err;
 744
 745         err = armpmu_request_irqs(cpu_pmu);
 746         if (err)
 747                 goto out;
 748
 749         err = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_STARTING,
 750                                        &cpu_pmu->node);
 751         if (err)
 752                 goto out;
 753
 754         err = cpu_pm_pmu_register(cpu_pmu);
 755         if (err)
 756                 goto out_unregister;
 757
 758         return 0;
 759
 760 out_unregister:
 761         cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
 762                                             &cpu_pmu->node);
 763 out:
 764         armpmu_free_irqs(cpu_pmu);
 765         return err;
 766 }
 767
 768 static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
 769 {
 770         cpu_pm_pmu_unregister(cpu_pmu);
 771         cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
 772                                             &cpu_pmu->node);
 773 }
 774
 775 /*
 776  * CPU PMU identification and probing.
 777  */
 778 static int probe_current_pmu(struct arm_pmu *pmu,
 779                              const struct pmu_probe_info *info)
 780 {
 781         int cpu = get_cpu();
 782         unsigned int cpuid = read_cpuid_id();
 783         int ret = -ENODEV;
 784
 785         pr_info("probing PMU on CPU %d\n", cpu);
 786
 787         for (; info->init != NULL; info++) {
 788                 if ((cpuid & info->mask) != info->cpuid)
 789                         continue;
 790                 ret = info->init(pmu);
 791                 break;
 792         }
 793
 794         put_cpu();
 795         return ret;
 796 }
 797
 798 static int pmu_parse_percpu_irq(struct arm_pmu *pmu, int irq)
 799 {
 800         int cpu, ret;
 801         struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
 802
 803         ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus);
 804         if (ret)
 805                 return ret;
 806
 807         for_each_cpu(cpu, &pmu->supported_cpus)
 808                 per_cpu(hw_events->irq, cpu) = irq;
 809
 810         return 0;
 811 }
 812
 813 static bool pmu_has_irq_affinity(struct device_node *node)
 814 {
 815         return !!of_find_property(node, "interrupt-affinity", NULL);
 816 }
 817
 818 static int pmu_parse_irq_affinity(struct device_node *node, int i)
 819 {
 820         struct device_node *dn;
 821         int cpu;
 822
 823         /*
 824          * If we don't have an interrupt-affinity property, we guess irq
 825          * affinity matches our logical CPU order, as we used to assume.
 826          * This is fragile, so we'll warn in pmu_parse_irqs().
 827          */
 828         if (!pmu_has_irq_affinity(node))
 829                 return i;
 830
 831         dn = of_parse_phandle(node, "interrupt-affinity", i);
 832         if (!dn) {
 833                 pr_warn("failed to parse interrupt-affinity[%d] for %s\n",
 834                         i, node->name);
 835                 return -EINVAL;
 836         }
 837
 838         /* Now look up the logical CPU number */
 839         for_each_possible_cpu(cpu) {
 840                 struct device_node *cpu_dn;
 841
 842                 cpu_dn = of_cpu_device_node_get(cpu);
 843                 of_node_put(cpu_dn);
 844
 845                 if (dn == cpu_dn)
 846                         break;
 847         }
 848
 849         if (cpu >= nr_cpu_ids) {
 850                 pr_warn("failed to find logical CPU for %s\n", dn->name);
 851         }
 852
 853         of_node_put(dn);
 854
 855         return cpu;
 856 }
 857
 858 static int pmu_parse_irqs(struct arm_pmu *pmu)
 859 {
 860         int i = 0, irqs;
 861         struct platform_device *pdev = pmu->plat_device;
 862         struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
 863
 864         irqs = platform_irq_count(pdev);
 865         if (irqs < 0) {
 866                 pr_err("unable to count PMU IRQs\n");
 867                 return irqs;
 868         }
 869
 870         /*
 871          * In this case we have no idea which CPUs are covered by the PMU.
 872          * To match our prior behaviour, we assume all CPUs in this case.
 873          */
 874         if (irqs == 0) {
 875                 pr_warn("no irqs for PMU, sampling events not supported\n");
 876                 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
 877                 cpumask_setall(&pmu->supported_cpus);
 878                 return 0;
 879         }
 880
 881         if (irqs == 1) {
 882                 int irq = platform_get_irq(pdev, 0);
 883                 if (irq && irq_is_percpu(irq))
 884                         return pmu_parse_percpu_irq(pmu, irq);
 885         }
 886
 887         if (!pmu_has_irq_affinity(pdev->dev.of_node)) {
 888                 pr_warn("no interrupt-affinity property for %s, guessing.\n",
 889                         of_node_full_name(pdev->dev.of_node));
 890         }
 891
 892         /*
 893          * Some platforms have all PMU IRQs OR'd into a single IRQ, with a
 894          * special platdata function that attempts to demux them.
 895          */
 896         if (dev_get_platdata(&pdev->dev))
 897                 cpumask_setall(&pmu->supported_cpus);
 898
 899         for (i = 0; i < irqs; i++) {
 900                 int cpu, irq;
 901
 902                 irq = platform_get_irq(pdev, i);
 903                 if (WARN_ON(irq <= 0))
 904                         continue;
 905
 906                 if (irq_is_percpu(irq)) {
 907                         pr_warn("multiple PPIs or mismatched SPI/PPI detected\n");
 908                         return -EINVAL;
 909                 }
 910
 911                 cpu = pmu_parse_irq_affinity(pdev->dev.of_node, i);
 912                 if (cpu < 0)
 913                         return cpu;
 914                 if (cpu >= nr_cpu_ids)
 915                         continue;
 916
 917                 if (per_cpu(hw_events->irq, cpu)) {
 918                         pr_warn("multiple PMU IRQs for the same CPU detected\n");
 919                         return -EINVAL;
 920                 }
 921
 922                 per_cpu(hw_events->irq, cpu) = irq;
 923                 cpumask_set_cpu(cpu, &pmu->supported_cpus);
 924         }
 925
 926         return 0;
 927 }
 928
 929 static struct arm_pmu *armpmu_alloc(void)
 930 {
 931         struct arm_pmu *pmu;
 932         int cpu;
 933
 934         pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
 935         if (!pmu) {
 936                 pr_info("failed to allocate PMU device!\n");
 937                 goto out;
 938         }
 939
 940         pmu->hw_events = alloc_percpu(struct pmu_hw_events);
 941         if (!pmu->hw_events) {
 942                 pr_info("failed to allocate per-cpu PMU data.\n");
 943                 goto out_free_pmu;
 944         }
 945
 946         pmu->pmu = (struct pmu) {
 947                 .pmu_enable     = armpmu_enable,
 948                 .pmu_disable    = armpmu_disable,
 949                 .event_init     = armpmu_event_init,
 950                 .add            = armpmu_add,
 951                 .del            = armpmu_del,
 952                 .start          = armpmu_start,
 953                 .stop           = armpmu_stop,
 954                 .read           = armpmu_read,
 955                 .filter_match   = armpmu_filter_match,
 956                 .attr_groups    = pmu->attr_groups,
 957                 /*
 958                  * This is a CPU PMU potentially in a heterogeneous
 959                  * configuration (e.g. big.LITTLE). This is not an uncore PMU,
 960                  * and we have taken ctx sharing into account (e.g. with our
 961                  * pmu::filter_match callback and pmu::event_init group
 962                  * validation).
 963                  */
 964                 .capabilities   = PERF_PMU_CAP_HETEROGENEOUS_CPUS,
 965         };
 966
 967         pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =
 968                 &armpmu_common_attr_group;
 969
 970         for_each_possible_cpu(cpu) {
 971                 struct pmu_hw_events *events;
 972
 973                 events = per_cpu_ptr(pmu->hw_events, cpu);
 974                 raw_spin_lock_init(&events->pmu_lock);
 975                 events->percpu_pmu = pmu;
 976         }
 977
 978         return pmu;
 979
 980 out_free_pmu:
 981         kfree(pmu);
 982 out:
 983         return NULL;
 984 }
 985
 986 static void armpmu_free(struct arm_pmu *pmu)
 987 {
 988         free_percpu(pmu->hw_events);
 989         kfree(pmu);
 990 }
 991
 992 int armpmu_register(struct arm_pmu *pmu)
 993 {
 994         int ret;
 995
 996         ret = cpu_pmu_init(pmu);
 997         if (ret)
 998                 return ret;
 999
1000         ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
1001         if (ret)
1002                 goto out_destroy;
1003
1004         if (!__oprofile_cpu_pmu)
1005                 __oprofile_cpu_pmu = pmu;
1006
1007         pr_info("enabled with %s PMU driver, %d counters available\n",
1008                 pmu->name, pmu->num_events);
1009
1010         return 0;
1011
1012 out_destroy:
1013         cpu_pmu_destroy(pmu);
1014         return ret;
1015 }
1016
1017 int arm_pmu_device_probe(struct platform_device *pdev,
1018                          const struct of_device_id *of_table,
1019                          const struct pmu_probe_info *probe_table)
1020 {
1021         const struct of_device_id *of_id;
1022         armpmu_init_fn init_fn;
1023         struct device_node *node = pdev->dev.of_node;
1024         struct arm_pmu *pmu;
1025         int ret = -ENODEV;
1026
1027         pmu = armpmu_alloc();
1028         if (!pmu)
1029                 return -ENOMEM;
1030
1031         pmu->plat_device = pdev;
1032
1033         ret = pmu_parse_irqs(pmu);
1034         if (ret)
1035                 goto out_free;
1036
1037         if (node && (of_id = of_match_node(of_table, pdev->dev.of_node))) {
1038                 init_fn = of_id->data;
1039
1040                 pmu->secure_access = of_property_read_bool(pdev->dev.of_node,
1041                                                            "secure-reg-access");
1042
1043                 /* arm64 systems boot only as non-secure */
1044                 if (IS_ENABLED(CONFIG_ARM64) && pmu->secure_access) {
1045                         pr_warn("ignoring \"secure-reg-access\" property for arm64\n");
1046                         pmu->secure_access = false;
1047                 }
1048
1049                 ret = init_fn(pmu);
1050         } else if (probe_table) {
1051                 cpumask_setall(&pmu->supported_cpus);
1052                 ret = probe_current_pmu(pmu, probe_table);
1053         }
1054
1055         if (ret) {
1056                 pr_info("%s: failed to probe PMU!\n", of_node_full_name(node));
1057                 goto out_free;
1058         }
1059
1060         ret = armpmu_register(pmu);
1061         if (ret)
1062                 goto out_free;
1063
1064         return 0;
1065
1066 out_free:
1067         pr_info("%s: failed to register PMU devices!\n",
1068                 of_node_full_name(node));
1069         armpmu_free(pmu);
1070         return ret;
1071 }
1072
1073 static int arm_pmu_hp_init(void)
1074 {
1075         int ret;
1076
1077         ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING,
1078                                       "perf/arm/pmu:starting",
1079                                       arm_perf_starting_cpu,
1080                                       arm_perf_teardown_cpu);
1081         if (ret)
1082                 pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n",
1083                        ret);
1084         return ret;
1085 }
1086 subsys_initcall(arm_pmu_hp_init);