1 // SPDX-License-Identifier: GPL-2.0
3 * Support routines for initializing a PCI subsystem
5 * Extruded from code written by
6 * Dave Rusling (david.rusling@reo.mts.dec.com)
7 * David Mosberger (davidm@cs.arizona.edu)
8 * David Miller (davem@redhat.com)
10 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
11 * PCI-PCI bridges cleanup, sorted resource allocation.
12 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
13 * Converted to allocation in 3 passes, which gives
14 * tighter packing. Prefetchable range support.
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/errno.h>
22 #include <linux/ioport.h>
23 #include <linux/cache.h>
24 #include <linux/slab.h>
25 #include <linux/acpi.h>
28 unsigned int pci_flags;
29 EXPORT_SYMBOL_GPL(pci_flags);
31 struct pci_dev_resource {
32 struct list_head list;
35 resource_size_t start;
37 resource_size_t add_size;
38 resource_size_t min_align;
42 static void free_list(struct list_head *head)
44 struct pci_dev_resource *dev_res, *tmp;
46 list_for_each_entry_safe(dev_res, tmp, head, list) {
47 list_del(&dev_res->list);
53 * add_to_list() - Add a new resource tracker to the list
54 * @head: Head of the list
55 * @dev: Device to which the resource belongs
56 * @res: Resource to be tracked
57 * @add_size: Additional size to be optionally added to the resource
59 static int add_to_list(struct list_head *head, struct pci_dev *dev,
60 struct resource *res, resource_size_t add_size,
61 resource_size_t min_align)
63 struct pci_dev_resource *tmp;
65 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
71 tmp->start = res->start;
73 tmp->flags = res->flags;
74 tmp->add_size = add_size;
75 tmp->min_align = min_align;
77 list_add(&tmp->list, head);
82 static void remove_from_list(struct list_head *head, struct resource *res)
84 struct pci_dev_resource *dev_res, *tmp;
86 list_for_each_entry_safe(dev_res, tmp, head, list) {
87 if (dev_res->res == res) {
88 list_del(&dev_res->list);
95 static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
98 struct pci_dev_resource *dev_res;
100 list_for_each_entry(dev_res, head, list) {
101 if (dev_res->res == res)
108 static resource_size_t get_res_add_size(struct list_head *head,
109 struct resource *res)
111 struct pci_dev_resource *dev_res;
113 dev_res = res_to_dev_res(head, res);
114 return dev_res ? dev_res->add_size : 0;
117 static resource_size_t get_res_add_align(struct list_head *head,
118 struct resource *res)
120 struct pci_dev_resource *dev_res;
122 dev_res = res_to_dev_res(head, res);
123 return dev_res ? dev_res->min_align : 0;
127 /* Sort resources by alignment */
128 static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
132 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
134 struct pci_dev_resource *dev_res, *tmp;
135 resource_size_t r_align;
138 r = &dev->resource[i];
140 if (r->flags & IORESOURCE_PCI_FIXED)
143 if (!(r->flags) || r->parent)
146 r_align = pci_resource_alignment(dev, r);
148 pci_warn(dev, "BAR %d: %pR has bogus alignment\n",
153 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
155 panic("pdev_sort_resources(): kmalloc() failed!\n");
159 /* Fallback is smallest one or list is empty */
161 list_for_each_entry(dev_res, head, list) {
162 resource_size_t align;
164 align = pci_resource_alignment(dev_res->dev,
167 if (r_align > align) {
172 /* Insert it just before n */
173 list_add_tail(&tmp->list, n);
177 static void __dev_sort_resources(struct pci_dev *dev, struct list_head *head)
179 u16 class = dev->class >> 8;
181 /* Don't touch classless devices or host bridges or IOAPICs */
182 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
185 /* Don't touch IOAPIC devices already enabled by firmware */
186 if (class == PCI_CLASS_SYSTEM_PIC) {
188 pci_read_config_word(dev, PCI_COMMAND, &command);
189 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
193 pdev_sort_resources(dev, head);
196 static inline void reset_resource(struct resource *res)
204 * reassign_resources_sorted() - Satisfy any additional resource requests
206 * @realloc_head: Head of the list tracking requests requiring
207 * additional resources
208 * @head: Head of the list tracking requests with allocated
211 * Walk through each element of the realloc_head and try to procure additional
212 * resources for the element, provided the element is in the head list.
214 static void reassign_resources_sorted(struct list_head *realloc_head,
215 struct list_head *head)
217 struct resource *res;
218 struct pci_dev_resource *add_res, *tmp;
219 struct pci_dev_resource *dev_res;
220 resource_size_t add_size, align;
223 list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
224 bool found_match = false;
227 /* Skip resource that has been reset */
231 /* Skip this resource if not found in head list */
232 list_for_each_entry(dev_res, head, list) {
233 if (dev_res->res == res) {
238 if (!found_match) /* Just skip */
241 idx = res - &add_res->dev->resource[0];
242 add_size = add_res->add_size;
243 align = add_res->min_align;
244 if (!resource_size(res)) {
246 res->end = res->start + add_size - 1;
247 if (pci_assign_resource(add_res->dev, idx))
250 res->flags |= add_res->flags &
251 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
252 if (pci_reassign_resource(add_res->dev, idx,
254 pci_info(add_res->dev, "failed to add %llx res[%d]=%pR\n",
255 (unsigned long long) add_size, idx,
259 list_del(&add_res->list);
265 * assign_requested_resources_sorted() - Satisfy resource requests
267 * @head: Head of the list tracking requests for resources
268 * @fail_head: Head of the list tracking requests that could not be
271 * Satisfy resource requests of each element in the list. Add requests that
272 * could not be satisfied to the failed_list.
274 static void assign_requested_resources_sorted(struct list_head *head,
275 struct list_head *fail_head)
277 struct resource *res;
278 struct pci_dev_resource *dev_res;
281 list_for_each_entry(dev_res, head, list) {
283 idx = res - &dev_res->dev->resource[0];
284 if (resource_size(res) &&
285 pci_assign_resource(dev_res->dev, idx)) {
288 * If the failed resource is a ROM BAR and
289 * it will be enabled later, don't add it
292 if (!((idx == PCI_ROM_RESOURCE) &&
293 (!(res->flags & IORESOURCE_ROM_ENABLE))))
294 add_to_list(fail_head,
304 static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
306 struct pci_dev_resource *fail_res;
307 unsigned long mask = 0;
309 /* Check failed type */
310 list_for_each_entry(fail_res, fail_head, list)
311 mask |= fail_res->flags;
314 * One pref failed resource will set IORESOURCE_MEM, as we can
315 * allocate pref in non-pref range. Will release all assigned
316 * non-pref sibling resources according to that bit.
318 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
321 static bool pci_need_to_release(unsigned long mask, struct resource *res)
323 if (res->flags & IORESOURCE_IO)
324 return !!(mask & IORESOURCE_IO);
326 /* Check pref at first */
327 if (res->flags & IORESOURCE_PREFETCH) {
328 if (mask & IORESOURCE_PREFETCH)
330 /* Count pref if its parent is non-pref */
331 else if ((mask & IORESOURCE_MEM) &&
332 !(res->parent->flags & IORESOURCE_PREFETCH))
338 if (res->flags & IORESOURCE_MEM)
339 return !!(mask & IORESOURCE_MEM);
341 return false; /* Should not get here */
344 static void __assign_resources_sorted(struct list_head *head,
345 struct list_head *realloc_head,
346 struct list_head *fail_head)
349 * Should not assign requested resources at first. They could be
350 * adjacent, so later reassign can not reallocate them one by one in
351 * parent resource window.
353 * Try to assign requested + add_size at beginning. If could do that,
354 * could get out early. If could not do that, we still try to assign
355 * requested at first, then try to reassign add_size for some resources.
357 * Separate three resource type checking if we need to release
358 * assigned resource after requested + add_size try.
360 * 1. If IO port assignment fails, will release assigned IO
362 * 2. If pref MMIO assignment fails, release assigned pref
363 * MMIO. If assigned pref MMIO's parent is non-pref MMIO
364 * and non-pref MMIO assignment fails, will release that
365 * assigned pref MMIO.
366 * 3. If non-pref MMIO assignment fails or pref MMIO
367 * assignment fails, will release assigned non-pref MMIO.
369 LIST_HEAD(save_head);
370 LIST_HEAD(local_fail_head);
371 struct pci_dev_resource *save_res;
372 struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
373 unsigned long fail_type;
374 resource_size_t add_align, align;
376 /* Check if optional add_size is there */
377 if (!realloc_head || list_empty(realloc_head))
378 goto requested_and_reassign;
380 /* Save original start, end, flags etc at first */
381 list_for_each_entry(dev_res, head, list) {
382 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
383 free_list(&save_head);
384 goto requested_and_reassign;
388 /* Update res in head list with add_size in realloc_head list */
389 list_for_each_entry_safe(dev_res, tmp_res, head, list) {
390 dev_res->res->end += get_res_add_size(realloc_head,
394 * There are two kinds of additional resources in the list:
395 * 1. bridge resource -- IORESOURCE_STARTALIGN
396 * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN
397 * Here just fix the additional alignment for bridge
399 if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
402 add_align = get_res_add_align(realloc_head, dev_res->res);
405 * The "head" list is sorted by alignment so resources with
406 * bigger alignment will be assigned first. After we
407 * change the alignment of a dev_res in "head" list, we
408 * need to reorder the list by alignment to make it
411 if (add_align > dev_res->res->start) {
412 resource_size_t r_size = resource_size(dev_res->res);
414 dev_res->res->start = add_align;
415 dev_res->res->end = add_align + r_size - 1;
417 list_for_each_entry(dev_res2, head, list) {
418 align = pci_resource_alignment(dev_res2->dev,
420 if (add_align > align) {
421 list_move_tail(&dev_res->list,
430 /* Try updated head list with add_size added */
431 assign_requested_resources_sorted(head, &local_fail_head);
433 /* All assigned with add_size? */
434 if (list_empty(&local_fail_head)) {
435 /* Remove head list from realloc_head list */
436 list_for_each_entry(dev_res, head, list)
437 remove_from_list(realloc_head, dev_res->res);
438 free_list(&save_head);
443 /* Check failed type */
444 fail_type = pci_fail_res_type_mask(&local_fail_head);
445 /* Remove not need to be released assigned res from head list etc */
446 list_for_each_entry_safe(dev_res, tmp_res, head, list)
447 if (dev_res->res->parent &&
448 !pci_need_to_release(fail_type, dev_res->res)) {
449 /* Remove it from realloc_head list */
450 remove_from_list(realloc_head, dev_res->res);
451 remove_from_list(&save_head, dev_res->res);
452 list_del(&dev_res->list);
456 free_list(&local_fail_head);
457 /* Release assigned resource */
458 list_for_each_entry(dev_res, head, list)
459 if (dev_res->res->parent)
460 release_resource(dev_res->res);
461 /* Restore start/end/flags from saved list */
462 list_for_each_entry(save_res, &save_head, list) {
463 struct resource *res = save_res->res;
465 res->start = save_res->start;
466 res->end = save_res->end;
467 res->flags = save_res->flags;
469 free_list(&save_head);
471 requested_and_reassign:
472 /* Satisfy the must-have resource requests */
473 assign_requested_resources_sorted(head, fail_head);
475 /* Try to satisfy any additional optional resource requests */
477 reassign_resources_sorted(realloc_head, head);
481 static void pdev_assign_resources_sorted(struct pci_dev *dev,
482 struct list_head *add_head,
483 struct list_head *fail_head)
487 __dev_sort_resources(dev, &head);
488 __assign_resources_sorted(&head, add_head, fail_head);
492 static void pbus_assign_resources_sorted(const struct pci_bus *bus,
493 struct list_head *realloc_head,
494 struct list_head *fail_head)
499 list_for_each_entry(dev, &bus->devices, bus_list)
500 __dev_sort_resources(dev, &head);
502 __assign_resources_sorted(&head, realloc_head, fail_head);
505 void pci_setup_cardbus(struct pci_bus *bus)
507 struct pci_dev *bridge = bus->self;
508 struct resource *res;
509 struct pci_bus_region region;
511 pci_info(bridge, "CardBus bridge to %pR\n",
514 res = bus->resource[0];
515 pcibios_resource_to_bus(bridge->bus, ®ion, res);
516 if (res->flags & IORESOURCE_IO) {
518 * The IO resource is allocated a range twice as large as it
519 * would normally need. This allows us to set both IO regs.
521 pci_info(bridge, " bridge window %pR\n", res);
522 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
524 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
528 res = bus->resource[1];
529 pcibios_resource_to_bus(bridge->bus, ®ion, res);
530 if (res->flags & IORESOURCE_IO) {
531 pci_info(bridge, " bridge window %pR\n", res);
532 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
534 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
538 res = bus->resource[2];
539 pcibios_resource_to_bus(bridge->bus, ®ion, res);
540 if (res->flags & IORESOURCE_MEM) {
541 pci_info(bridge, " bridge window %pR\n", res);
542 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
544 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
548 res = bus->resource[3];
549 pcibios_resource_to_bus(bridge->bus, ®ion, res);
550 if (res->flags & IORESOURCE_MEM) {
551 pci_info(bridge, " bridge window %pR\n", res);
552 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
554 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
558 EXPORT_SYMBOL(pci_setup_cardbus);
561 * Initialize bridges with base/limit values we have collected. PCI-to-PCI
562 * Bridge Architecture Specification rev. 1.1 (1998) requires that if there
563 * are no I/O ports or memory behind the bridge, the corresponding range
564 * must be turned off by writing base value greater than limit to the
565 * bridge's base/limit registers.
567 * Note: care must be taken when updating I/O base/limit registers of
568 * bridges which support 32-bit I/O. This update requires two config space
569 * writes, so it's quite possible that an I/O window of the bridge will
570 * have some undesirable address (e.g. 0) after the first write. Ditto
571 * 64-bit prefetchable MMIO.
573 static void pci_setup_bridge_io(struct pci_dev *bridge)
575 struct resource *res;
576 struct pci_bus_region region;
577 unsigned long io_mask;
578 u8 io_base_lo, io_limit_lo;
582 io_mask = PCI_IO_RANGE_MASK;
583 if (bridge->io_window_1k)
584 io_mask = PCI_IO_1K_RANGE_MASK;
586 /* Set up the top and bottom of the PCI I/O segment for this bus */
587 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
588 pcibios_resource_to_bus(bridge->bus, ®ion, res);
589 if (res->flags & IORESOURCE_IO) {
590 pci_read_config_word(bridge, PCI_IO_BASE, &l);
591 io_base_lo = (region.start >> 8) & io_mask;
592 io_limit_lo = (region.end >> 8) & io_mask;
593 l = ((u16) io_limit_lo << 8) | io_base_lo;
594 /* Set up upper 16 bits of I/O base/limit */
595 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
596 pci_info(bridge, " bridge window %pR\n", res);
598 /* Clear upper 16 bits of I/O base/limit */
602 /* Temporarily disable the I/O range before updating PCI_IO_BASE */
603 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
604 /* Update lower 16 bits of I/O base/limit */
605 pci_write_config_word(bridge, PCI_IO_BASE, l);
606 /* Update upper 16 bits of I/O base/limit */
607 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
610 static void pci_setup_bridge_mmio(struct pci_dev *bridge)
612 struct resource *res;
613 struct pci_bus_region region;
616 /* Set up the top and bottom of the PCI Memory segment for this bus */
617 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
618 pcibios_resource_to_bus(bridge->bus, ®ion, res);
619 if (res->flags & IORESOURCE_MEM) {
620 l = (region.start >> 16) & 0xfff0;
621 l |= region.end & 0xfff00000;
622 pci_info(bridge, " bridge window %pR\n", res);
626 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
629 static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
631 struct resource *res;
632 struct pci_bus_region region;
636 * Clear out the upper 32 bits of PREF limit. If
637 * PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables
638 * PREF range, which is ok.
640 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
642 /* Set up PREF base/limit */
644 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
645 pcibios_resource_to_bus(bridge->bus, ®ion, res);
646 if (res->flags & IORESOURCE_PREFETCH) {
647 l = (region.start >> 16) & 0xfff0;
648 l |= region.end & 0xfff00000;
649 if (res->flags & IORESOURCE_MEM_64) {
650 bu = upper_32_bits(region.start);
651 lu = upper_32_bits(region.end);
653 pci_info(bridge, " bridge window %pR\n", res);
657 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
659 /* Set the upper 32 bits of PREF base & limit */
660 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
661 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
664 static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
666 struct pci_dev *bridge = bus->self;
668 pci_info(bridge, "PCI bridge to %pR\n",
671 if (type & IORESOURCE_IO)
672 pci_setup_bridge_io(bridge);
674 if (type & IORESOURCE_MEM)
675 pci_setup_bridge_mmio(bridge);
677 if (type & IORESOURCE_PREFETCH)
678 pci_setup_bridge_mmio_pref(bridge);
680 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
683 void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
687 void pci_setup_bridge(struct pci_bus *bus)
689 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
692 pcibios_setup_bridge(bus, type);
693 __pci_setup_bridge(bus, type);
697 int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
699 if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
702 if (pci_claim_resource(bridge, i) == 0)
703 return 0; /* Claimed the window */
705 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
708 if (!pci_bus_clip_resource(bridge, i))
709 return -EINVAL; /* Clipping didn't change anything */
711 switch (i - PCI_BRIDGE_RESOURCES) {
713 pci_setup_bridge_io(bridge);
716 pci_setup_bridge_mmio(bridge);
719 pci_setup_bridge_mmio_pref(bridge);
725 if (pci_claim_resource(bridge, i) == 0)
726 return 0; /* Claimed a smaller window */
732 * Check whether the bridge supports optional I/O and prefetchable memory
733 * ranges. If not, the respective base/limit registers must be read-only
736 static void pci_bridge_check_ranges(struct pci_bus *bus)
738 struct pci_dev *bridge = bus->self;
739 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
741 b_res[1].flags |= IORESOURCE_MEM;
743 if (bridge->io_window)
744 b_res[0].flags |= IORESOURCE_IO;
746 if (bridge->pref_window) {
747 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
748 if (bridge->pref_64_window) {
749 b_res[2].flags |= IORESOURCE_MEM_64;
750 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
756 * Helper function for sizing routines. Assigned resources have non-NULL
759 * Return first unassigned resource of the correct type. If there is none,
760 * return first assigned resource of the correct type. If none of the
761 * above, return NULL.
763 * Returning an assigned resource of the correct type allows the caller to
764 * distinguish between already assigned and no resource of the correct type.
766 static struct resource *find_bus_resource_of_type(struct pci_bus *bus,
767 unsigned long type_mask,
770 struct resource *r, *r_assigned = NULL;
773 pci_bus_for_each_resource(bus, r, i) {
774 if (r == &ioport_resource || r == &iomem_resource)
776 if (r && (r->flags & type_mask) == type && !r->parent)
778 if (r && (r->flags & type_mask) == type && !r_assigned)
784 static resource_size_t calculate_iosize(resource_size_t size,
785 resource_size_t min_size,
786 resource_size_t size1,
787 resource_size_t add_size,
788 resource_size_t children_add_size,
789 resource_size_t old_size,
790 resource_size_t align)
797 * To be fixed in 2.5: we should have sort of HAVE_ISA flag in the
800 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
801 size = (size & 0xff) + ((size & ~0xffUL) << 2);
807 size = ALIGN(max(size, add_size) + children_add_size, align);
811 static resource_size_t calculate_memsize(resource_size_t size,
812 resource_size_t min_size,
813 resource_size_t add_size,
814 resource_size_t children_add_size,
815 resource_size_t old_size,
816 resource_size_t align)
825 size = ALIGN(max(size, add_size) + children_add_size, align);
829 resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
835 #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
836 #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
837 #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
839 static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type)
841 resource_size_t align = 1, arch_align;
843 if (type & IORESOURCE_MEM)
844 align = PCI_P2P_DEFAULT_MEM_ALIGN;
845 else if (type & IORESOURCE_IO) {
847 * Per spec, I/O windows are 4K-aligned, but some bridges have
848 * an extension to support 1K alignment.
850 if (bus->self && bus->self->io_window_1k)
851 align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
853 align = PCI_P2P_DEFAULT_IO_ALIGN;
856 arch_align = pcibios_window_alignment(bus, type);
857 return max(align, arch_align);
861 * pbus_size_io() - Size the I/O window of a given bus
864 * @min_size: The minimum I/O window that must be allocated
865 * @add_size: Additional optional I/O window
866 * @realloc_head: Track the additional I/O window on this list
868 * Sizing the I/O windows of the PCI-PCI bridge is trivial, since these
869 * windows have 1K or 4K granularity and the I/O ranges of non-bridge PCI
870 * devices are limited to 256 bytes. We must be careful with the ISA
873 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
874 resource_size_t add_size,
875 struct list_head *realloc_head)
878 struct resource *b_res = find_bus_resource_of_type(bus, IORESOURCE_IO,
880 resource_size_t size = 0, size0 = 0, size1 = 0;
881 resource_size_t children_add_size = 0;
882 resource_size_t min_align, align;
887 /* If resource is already assigned, nothing more to do */
891 min_align = window_alignment(bus, IORESOURCE_IO);
892 list_for_each_entry(dev, &bus->devices, bus_list) {
895 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
896 struct resource *r = &dev->resource[i];
897 unsigned long r_size;
899 if (r->parent || !(r->flags & IORESOURCE_IO))
901 r_size = resource_size(r);
904 /* Might be re-aligned for ISA */
909 align = pci_resource_alignment(dev, r);
910 if (align > min_align)
914 children_add_size += get_res_add_size(realloc_head, r);
918 size0 = calculate_iosize(size, min_size, size1, 0, 0,
919 resource_size(b_res), min_align);
920 size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
921 calculate_iosize(size, min_size, size1, add_size, children_add_size,
922 resource_size(b_res), min_align);
923 if (!size0 && !size1) {
924 if (bus->self && (b_res->start || b_res->end))
925 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
926 b_res, &bus->busn_res);
931 b_res->start = min_align;
932 b_res->end = b_res->start + size0 - 1;
933 b_res->flags |= IORESOURCE_STARTALIGN;
934 if (bus->self && size1 > size0 && realloc_head) {
935 add_to_list(realloc_head, bus->self, b_res, size1-size0,
937 pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n",
938 b_res, &bus->busn_res,
939 (unsigned long long) size1 - size0);
943 static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
946 resource_size_t align = 0;
947 resource_size_t min_align = 0;
950 for (order = 0; order <= max_order; order++) {
951 resource_size_t align1 = 1;
953 align1 <<= (order + 20);
957 else if (ALIGN(align + min_align, min_align) < align1)
958 min_align = align1 >> 1;
959 align += aligns[order];
966 * pbus_size_mem() - Size the memory window of a given bus
969 * @mask: Mask the resource flag, then compare it with type
970 * @type: The type of free resource from bridge
971 * @type2: Second match type
972 * @type3: Third match type
973 * @min_size: The minimum memory window that must be allocated
974 * @add_size: Additional optional memory window
975 * @realloc_head: Track the additional memory window on this list
977 * Calculate the size of the bus and minimal alignment which guarantees
978 * that all child resources fit in this size.
980 * Return -ENOSPC if there's no available bus resource of the desired
981 * type. Otherwise, set the bus resource start/end to indicate the
982 * required size, add things to realloc_head (if supplied), and return 0.
984 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
985 unsigned long type, unsigned long type2,
986 unsigned long type3, resource_size_t min_size,
987 resource_size_t add_size,
988 struct list_head *realloc_head)
991 resource_size_t min_align, align, size, size0, size1;
992 resource_size_t aligns[18]; /* Alignments from 1MB to 128GB */
993 int order, max_order;
994 struct resource *b_res = find_bus_resource_of_type(bus,
995 mask | IORESOURCE_PREFETCH, type);
996 resource_size_t children_add_size = 0;
997 resource_size_t children_add_align = 0;
998 resource_size_t add_align = 0;
1003 /* If resource is already assigned, nothing more to do */
1007 memset(aligns, 0, sizeof(aligns));
1011 list_for_each_entry(dev, &bus->devices, bus_list) {
1014 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1015 struct resource *r = &dev->resource[i];
1016 resource_size_t r_size;
1018 if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
1019 ((r->flags & mask) != type &&
1020 (r->flags & mask) != type2 &&
1021 (r->flags & mask) != type3))
1023 r_size = resource_size(r);
1024 #ifdef CONFIG_PCI_IOV
1025 /* Put SRIOV requested res to the optional list */
1026 if (realloc_head && i >= PCI_IOV_RESOURCES &&
1027 i <= PCI_IOV_RESOURCE_END) {
1028 add_align = max(pci_resource_alignment(dev, r), add_align);
1029 r->end = r->start - 1;
1030 add_to_list(realloc_head, dev, r, r_size, 0 /* Don't care */);
1031 children_add_size += r_size;
1036 * aligns[0] is for 1MB (since bridge memory
1037 * windows are always at least 1MB aligned), so
1038 * keep "order" from being negative for smaller
1041 align = pci_resource_alignment(dev, r);
1042 order = __ffs(align) - 20;
1045 if (order >= ARRAY_SIZE(aligns)) {
1046 pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
1047 i, r, (unsigned long long) align);
1051 size += max(r_size, align);
1053 * Exclude ranges with size > align from calculation of
1056 if (r_size <= align)
1057 aligns[order] += align;
1058 if (order > max_order)
1062 children_add_size += get_res_add_size(realloc_head, r);
1063 children_add_align = get_res_add_align(realloc_head, r);
1064 add_align = max(add_align, children_add_align);
1069 min_align = calculate_mem_align(aligns, max_order);
1070 min_align = max(min_align, window_alignment(bus, b_res->flags));
1071 size0 = calculate_memsize(size, min_size, 0, 0, resource_size(b_res), min_align);
1072 add_align = max(min_align, add_align);
1073 size1 = (!realloc_head || (realloc_head && !add_size && !children_add_size)) ? size0 :
1074 calculate_memsize(size, min_size, add_size, children_add_size,
1075 resource_size(b_res), add_align);
1076 if (!size0 && !size1) {
1077 if (bus->self && (b_res->start || b_res->end))
1078 pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
1079 b_res, &bus->busn_res);
1083 b_res->start = min_align;
1084 b_res->end = size0 + min_align - 1;
1085 b_res->flags |= IORESOURCE_STARTALIGN;
1086 if (bus->self && size1 > size0 && realloc_head) {
1087 add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
1088 pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
1089 b_res, &bus->busn_res,
1090 (unsigned long long) (size1 - size0),
1091 (unsigned long long) add_align);
1096 unsigned long pci_cardbus_resource_alignment(struct resource *res)
1098 if (res->flags & IORESOURCE_IO)
1099 return pci_cardbus_io_size;
1100 if (res->flags & IORESOURCE_MEM)
1101 return pci_cardbus_mem_size;
1105 static void pci_bus_size_cardbus(struct pci_bus *bus,
1106 struct list_head *realloc_head)
1108 struct pci_dev *bridge = bus->self;
1109 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
1110 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1113 if (b_res[0].parent)
1114 goto handle_b_res_1;
1116 * Reserve some resources for CardBus. We reserve a fixed amount
1117 * of bus space for CardBus bridges.
1119 b_res[0].start = pci_cardbus_io_size;
1120 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
1121 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1123 b_res[0].end -= pci_cardbus_io_size;
1124 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1125 pci_cardbus_io_size);
1129 if (b_res[1].parent)
1130 goto handle_b_res_2;
1131 b_res[1].start = pci_cardbus_io_size;
1132 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
1133 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1135 b_res[1].end -= pci_cardbus_io_size;
1136 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
1137 pci_cardbus_io_size);
1141 /* MEM1 must not be pref MMIO */
1142 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1143 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1144 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1145 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1146 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1149 /* Check whether prefetchable memory is supported by this bridge. */
1150 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1151 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1152 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1153 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1154 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1157 if (b_res[2].parent)
1158 goto handle_b_res_3;
1160 * If we have prefetchable memory support, allocate two regions.
1161 * Otherwise, allocate one region of twice the size.
1163 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1164 b_res[2].start = pci_cardbus_mem_size;
1165 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
1166 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1167 IORESOURCE_STARTALIGN;
1169 b_res[2].end -= pci_cardbus_mem_size;
1170 add_to_list(realloc_head, bridge, b_res+2,
1171 pci_cardbus_mem_size, pci_cardbus_mem_size);
1174 /* Reduce that to half */
1175 b_res_3_size = pci_cardbus_mem_size;
1179 if (b_res[3].parent)
1181 b_res[3].start = pci_cardbus_mem_size;
1182 b_res[3].end = b_res[3].start + b_res_3_size - 1;
1183 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1185 b_res[3].end -= b_res_3_size;
1186 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
1187 pci_cardbus_mem_size);
1194 void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1196 struct pci_dev *dev;
1197 unsigned long mask, prefmask, type2 = 0, type3 = 0;
1198 resource_size_t additional_io_size = 0, additional_mmio_size = 0,
1199 additional_mmio_pref_size = 0;
1200 struct resource *pref;
1201 struct pci_host_bridge *host;
1202 int hdr_type, i, ret;
1204 list_for_each_entry(dev, &bus->devices, bus_list) {
1205 struct pci_bus *b = dev->subordinate;
1209 switch (dev->hdr_type) {
1210 case PCI_HEADER_TYPE_CARDBUS:
1211 pci_bus_size_cardbus(b, realloc_head);
1214 case PCI_HEADER_TYPE_BRIDGE:
1216 __pci_bus_size_bridges(b, realloc_head);
1222 if (pci_is_root_bus(bus)) {
1223 host = to_pci_host_bridge(bus->bridge);
1224 if (!host->size_windows)
1226 pci_bus_for_each_resource(bus, pref, i)
1227 if (pref && (pref->flags & IORESOURCE_PREFETCH))
1229 hdr_type = -1; /* Intentionally invalid - not a PCI device. */
1231 pref = &bus->self->resource[PCI_BRIDGE_RESOURCES + 2];
1232 hdr_type = bus->self->hdr_type;
1236 case PCI_HEADER_TYPE_CARDBUS:
1237 /* Don't size CardBuses yet */
1240 case PCI_HEADER_TYPE_BRIDGE:
1241 pci_bridge_check_ranges(bus);
1242 if (bus->self->is_hotplug_bridge) {
1243 additional_io_size = pci_hotplug_io_size;
1244 additional_mmio_size = pci_hotplug_mmio_size;
1245 additional_mmio_pref_size = pci_hotplug_mmio_pref_size;
1249 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1250 additional_io_size, realloc_head);
1253 * If there's a 64-bit prefetchable MMIO window, compute
1254 * the size required to put all 64-bit prefetchable
1257 mask = IORESOURCE_MEM;
1258 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1259 if (pref && (pref->flags & IORESOURCE_MEM_64)) {
1260 prefmask |= IORESOURCE_MEM_64;
1261 ret = pbus_size_mem(bus, prefmask, prefmask,
1263 realloc_head ? 0 : additional_mmio_pref_size,
1264 additional_mmio_pref_size, realloc_head);
1267 * If successful, all non-prefetchable resources
1268 * and any 32-bit prefetchable resources will go in
1269 * the non-prefetchable window.
1273 type2 = prefmask & ~IORESOURCE_MEM_64;
1274 type3 = prefmask & ~IORESOURCE_PREFETCH;
1279 * If there is no 64-bit prefetchable window, compute the
1280 * size required to put all prefetchable resources in the
1281 * 32-bit prefetchable window (if there is one).
1284 prefmask &= ~IORESOURCE_MEM_64;
1285 ret = pbus_size_mem(bus, prefmask, prefmask,
1287 realloc_head ? 0 : additional_mmio_pref_size,
1288 additional_mmio_pref_size, realloc_head);
1291 * If successful, only non-prefetchable resources
1292 * will go in the non-prefetchable window.
1297 additional_mmio_size += additional_mmio_pref_size;
1299 type2 = type3 = IORESOURCE_MEM;
1303 * Compute the size required to put everything else in the
1304 * non-prefetchable window. This includes:
1306 * - all non-prefetchable resources
1307 * - 32-bit prefetchable resources if there's a 64-bit
1308 * prefetchable window or no prefetchable window at all
1309 * - 64-bit prefetchable resources if there's no prefetchable
1312 * Note that the strategy in __pci_assign_resource() must match
1313 * that used here. Specifically, we cannot put a 32-bit
1314 * prefetchable resource in a 64-bit prefetchable window.
1316 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1317 realloc_head ? 0 : additional_mmio_size,
1318 additional_mmio_size, realloc_head);
1323 void pci_bus_size_bridges(struct pci_bus *bus)
1325 __pci_bus_size_bridges(bus, NULL);
1327 EXPORT_SYMBOL(pci_bus_size_bridges);
1329 static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
1332 struct resource *parent_r;
1333 unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM |
1334 IORESOURCE_PREFETCH;
1336 pci_bus_for_each_resource(b, parent_r, i) {
1340 if ((r->flags & mask) == (parent_r->flags & mask) &&
1341 resource_contains(parent_r, r))
1342 request_resource(parent_r, r);
1347 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they are
1348 * skipped by pbus_assign_resources_sorted().
1350 static void pdev_assign_fixed_resources(struct pci_dev *dev)
1354 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1356 struct resource *r = &dev->resource[i];
1358 if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) ||
1359 !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
1363 while (b && !r->parent) {
1364 assign_fixed_resource_on_bus(b, r);
1370 void __pci_bus_assign_resources(const struct pci_bus *bus,
1371 struct list_head *realloc_head,
1372 struct list_head *fail_head)
1375 struct pci_dev *dev;
1377 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1379 list_for_each_entry(dev, &bus->devices, bus_list) {
1380 pdev_assign_fixed_resources(dev);
1382 b = dev->subordinate;
1386 __pci_bus_assign_resources(b, realloc_head, fail_head);
1388 switch (dev->hdr_type) {
1389 case PCI_HEADER_TYPE_BRIDGE:
1390 if (!pci_is_enabled(dev))
1391 pci_setup_bridge(b);
1394 case PCI_HEADER_TYPE_CARDBUS:
1395 pci_setup_cardbus(b);
1399 pci_info(dev, "not setting up bridge for bus %04x:%02x\n",
1400 pci_domain_nr(b), b->number);
1406 void pci_bus_assign_resources(const struct pci_bus *bus)
1408 __pci_bus_assign_resources(bus, NULL, NULL);
1410 EXPORT_SYMBOL(pci_bus_assign_resources);
1412 static void pci_claim_device_resources(struct pci_dev *dev)
1416 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
1417 struct resource *r = &dev->resource[i];
1419 if (!r->flags || r->parent)
1422 pci_claim_resource(dev, i);
1426 static void pci_claim_bridge_resources(struct pci_dev *dev)
1430 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
1431 struct resource *r = &dev->resource[i];
1433 if (!r->flags || r->parent)
1436 pci_claim_bridge_resource(dev, i);
1440 static void pci_bus_allocate_dev_resources(struct pci_bus *b)
1442 struct pci_dev *dev;
1443 struct pci_bus *child;
1445 list_for_each_entry(dev, &b->devices, bus_list) {
1446 pci_claim_device_resources(dev);
1448 child = dev->subordinate;
1450 pci_bus_allocate_dev_resources(child);
1454 static void pci_bus_allocate_resources(struct pci_bus *b)
1456 struct pci_bus *child;
1459 * Carry out a depth-first search on the PCI bus tree to allocate
1460 * bridge apertures. Read the programmed bridge bases and
1461 * recursively claim the respective bridge resources.
1464 pci_read_bridge_bases(b);
1465 pci_claim_bridge_resources(b->self);
1468 list_for_each_entry(child, &b->children, node)
1469 pci_bus_allocate_resources(child);
1472 void pci_bus_claim_resources(struct pci_bus *b)
1474 pci_bus_allocate_resources(b);
1475 pci_bus_allocate_dev_resources(b);
1477 EXPORT_SYMBOL(pci_bus_claim_resources);
1479 static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1480 struct list_head *add_head,
1481 struct list_head *fail_head)
1485 pdev_assign_resources_sorted((struct pci_dev *)bridge,
1486 add_head, fail_head);
1488 b = bridge->subordinate;
1492 __pci_bus_assign_resources(b, add_head, fail_head);
1494 switch (bridge->class >> 8) {
1495 case PCI_CLASS_BRIDGE_PCI:
1496 pci_setup_bridge(b);
1499 case PCI_CLASS_BRIDGE_CARDBUS:
1500 pci_setup_cardbus(b);
1504 pci_info(bridge, "not setting up bridge for bus %04x:%02x\n",
1505 pci_domain_nr(b), b->number);
1510 #define PCI_RES_TYPE_MASK \
1511 (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\
1514 static void pci_bridge_release_resources(struct pci_bus *bus,
1517 struct pci_dev *dev = bus->self;
1519 unsigned old_flags = 0;
1520 struct resource *b_res;
1523 b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1526 * 1. If IO port assignment fails, release bridge IO port.
1527 * 2. If non pref MMIO assignment fails, release bridge nonpref MMIO.
1528 * 3. If 64bit pref MMIO assignment fails, and bridge pref is 64bit,
1529 * release bridge pref MMIO.
1530 * 4. If pref MMIO assignment fails, and bridge pref is 32bit,
1531 * release bridge pref MMIO.
1532 * 5. If pref MMIO assignment fails, and bridge pref is not
1533 * assigned, release bridge nonpref MMIO.
1535 if (type & IORESOURCE_IO)
1537 else if (!(type & IORESOURCE_PREFETCH))
1539 else if ((type & IORESOURCE_MEM_64) &&
1540 (b_res[2].flags & IORESOURCE_MEM_64))
1542 else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
1543 (b_res[2].flags & IORESOURCE_PREFETCH))
1553 /* If there are children, release them all */
1554 release_child_resources(r);
1555 if (!release_resource(r)) {
1556 type = old_flags = r->flags & PCI_RES_TYPE_MASK;
1557 pci_info(dev, "resource %d %pR released\n",
1558 PCI_BRIDGE_RESOURCES + idx, r);
1559 /* Keep the old size */
1560 r->end = resource_size(r) - 1;
1564 /* Avoiding touch the one without PREF */
1565 if (type & IORESOURCE_PREFETCH)
1566 type = IORESOURCE_PREFETCH;
1567 __pci_setup_bridge(bus, type);
1568 /* For next child res under same bridge */
1569 r->flags = old_flags;
1579 * Try to release PCI bridge resources from leaf bridge, so we can allocate
1580 * a larger window later.
1582 static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1584 enum release_type rel_type)
1586 struct pci_dev *dev;
1587 bool is_leaf_bridge = true;
1589 list_for_each_entry(dev, &bus->devices, bus_list) {
1590 struct pci_bus *b = dev->subordinate;
1594 is_leaf_bridge = false;
1596 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1599 if (rel_type == whole_subtree)
1600 pci_bus_release_bridge_resources(b, type,
1604 if (pci_is_root_bus(bus))
1607 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1610 if ((rel_type == whole_subtree) || is_leaf_bridge)
1611 pci_bridge_release_resources(bus, type);
1614 static void pci_bus_dump_res(struct pci_bus *bus)
1616 struct resource *res;
1619 pci_bus_for_each_resource(bus, res, i) {
1620 if (!res || !res->end || !res->flags)
1623 dev_info(&bus->dev, "resource %d %pR\n", i, res);
1627 static void pci_bus_dump_resources(struct pci_bus *bus)
1630 struct pci_dev *dev;
1633 pci_bus_dump_res(bus);
1635 list_for_each_entry(dev, &bus->devices, bus_list) {
1636 b = dev->subordinate;
1640 pci_bus_dump_resources(b);
1644 static int pci_bus_get_depth(struct pci_bus *bus)
1647 struct pci_bus *child_bus;
1649 list_for_each_entry(child_bus, &bus->children, node) {
1652 ret = pci_bus_get_depth(child_bus);
1653 if (ret + 1 > depth)
1661 * -1: undefined, will auto detect later
1662 * 0: disabled by user
1663 * 1: disabled by auto detect
1664 * 2: enabled by user
1665 * 3: enabled by auto detect
1675 static enum enable_type pci_realloc_enable = undefined;
1676 void __init pci_realloc_get_opt(char *str)
1678 if (!strncmp(str, "off", 3))
1679 pci_realloc_enable = user_disabled;
1680 else if (!strncmp(str, "on", 2))
1681 pci_realloc_enable = user_enabled;
1683 static bool pci_realloc_enabled(enum enable_type enable)
1685 return enable >= user_enabled;
1688 #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1689 static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1692 bool *unassigned = data;
1694 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1695 struct resource *r = &dev->resource[i + PCI_IOV_RESOURCES];
1696 struct pci_bus_region region;
1698 /* Not assigned or rejected by kernel? */
1702 pcibios_resource_to_bus(dev->bus, ®ion, r);
1703 if (!region.start) {
1705 return 1; /* Return early from pci_walk_bus() */
1712 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1713 enum enable_type enable_local)
1715 bool unassigned = false;
1716 struct pci_host_bridge *host;
1718 if (enable_local != undefined)
1719 return enable_local;
1721 host = pci_find_host_bridge(bus);
1722 if (host->preserve_config)
1723 return auto_disabled;
1725 pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1727 return auto_enabled;
1729 return enable_local;
1732 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1733 enum enable_type enable_local)
1735 return enable_local;
1740 * First try will not touch PCI bridge res.
1741 * Second and later try will clear small leaf bridge res.
1742 * Will stop till to the max depth if can not find good one.
1744 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1746 LIST_HEAD(realloc_head);
1747 /* List of resources that want additional resources */
1748 struct list_head *add_list = NULL;
1749 int tried_times = 0;
1750 enum release_type rel_type = leaf_only;
1751 LIST_HEAD(fail_head);
1752 struct pci_dev_resource *fail_res;
1753 int pci_try_num = 1;
1754 enum enable_type enable_local;
1756 /* Don't realloc if asked to do so */
1757 enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1758 if (pci_realloc_enabled(enable_local)) {
1759 int max_depth = pci_bus_get_depth(bus);
1761 pci_try_num = max_depth + 1;
1762 dev_info(&bus->dev, "max bus depth: %d pci_try_num: %d\n",
1763 max_depth, pci_try_num);
1768 * Last try will use add_list, otherwise will try good to have as must
1769 * have, so can realloc parent bridge resource
1771 if (tried_times + 1 == pci_try_num)
1772 add_list = &realloc_head;
1774 * Depth first, calculate sizes and alignments of all subordinate buses.
1776 __pci_bus_size_bridges(bus, add_list);
1778 /* Depth last, allocate resources and update the hardware. */
1779 __pci_bus_assign_resources(bus, add_list, &fail_head);
1781 BUG_ON(!list_empty(add_list));
1784 /* Any device complain? */
1785 if (list_empty(&fail_head))
1788 if (tried_times >= pci_try_num) {
1789 if (enable_local == undefined)
1790 dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1791 else if (enable_local == auto_enabled)
1792 dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1794 free_list(&fail_head);
1798 dev_info(&bus->dev, "No. %d try to assign unassigned res\n",
1801 /* Third times and later will not check if it is leaf */
1802 if ((tried_times + 1) > 2)
1803 rel_type = whole_subtree;
1806 * Try to release leaf bridge's resources that doesn't fit resource of
1807 * child device under that bridge.
1809 list_for_each_entry(fail_res, &fail_head, list)
1810 pci_bus_release_bridge_resources(fail_res->dev->bus,
1811 fail_res->flags & PCI_RES_TYPE_MASK,
1814 /* Restore size and flags */
1815 list_for_each_entry(fail_res, &fail_head, list) {
1816 struct resource *res = fail_res->res;
1819 res->start = fail_res->start;
1820 res->end = fail_res->end;
1821 res->flags = fail_res->flags;
1823 if (pci_is_bridge(fail_res->dev)) {
1824 idx = res - &fail_res->dev->resource[0];
1825 if (idx >= PCI_BRIDGE_RESOURCES &&
1826 idx <= PCI_BRIDGE_RESOURCE_END)
1830 free_list(&fail_head);
1835 /* Dump the resource on buses */
1836 pci_bus_dump_resources(bus);
1839 void __init pci_assign_unassigned_resources(void)
1841 struct pci_bus *root_bus;
1843 list_for_each_entry(root_bus, &pci_root_buses, node) {
1844 pci_assign_unassigned_root_bus_resources(root_bus);
1846 /* Make sure the root bridge has a companion ACPI device */
1847 if (ACPI_HANDLE(root_bus->bridge))
1848 acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge));
1852 static void adjust_bridge_window(struct pci_dev *bridge, struct resource *res,
1853 struct list_head *add_list,
1854 resource_size_t new_size)
1856 resource_size_t add_size, size = resource_size(res);
1864 if (new_size > size) {
1865 add_size = new_size - size;
1866 pci_dbg(bridge, "bridge window %pR extended by %pa\n", res,
1868 } else if (new_size < size) {
1869 add_size = size - new_size;
1870 pci_dbg(bridge, "bridge window %pR shrunken by %pa\n", res,
1874 res->end = res->start + new_size - 1;
1875 remove_from_list(add_list, res);
1878 static void pci_bus_distribute_available_resources(struct pci_bus *bus,
1879 struct list_head *add_list,
1881 struct resource mmio,
1882 struct resource mmio_pref)
1884 unsigned int normal_bridges = 0, hotplug_bridges = 0;
1885 struct resource *io_res, *mmio_res, *mmio_pref_res;
1886 struct pci_dev *dev, *bridge = bus->self;
1887 resource_size_t io_per_hp, mmio_per_hp, mmio_pref_per_hp, align;
1889 io_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
1890 mmio_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
1891 mmio_pref_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
1894 * The alignment of this bridge is yet to be considered, hence it must
1895 * be done now before extending its bridge window.
1897 align = pci_resource_alignment(bridge, io_res);
1898 if (!io_res->parent && align)
1899 io.start = min(ALIGN(io.start, align), io.end + 1);
1901 align = pci_resource_alignment(bridge, mmio_res);
1902 if (!mmio_res->parent && align)
1903 mmio.start = min(ALIGN(mmio.start, align), mmio.end + 1);
1905 align = pci_resource_alignment(bridge, mmio_pref_res);
1906 if (!mmio_pref_res->parent && align)
1907 mmio_pref.start = min(ALIGN(mmio_pref.start, align),
1911 * Now that we have adjusted for alignment, update the bridge window
1912 * resources to fill as much remaining resource space as possible.
1914 adjust_bridge_window(bridge, io_res, add_list, resource_size(&io));
1915 adjust_bridge_window(bridge, mmio_res, add_list, resource_size(&mmio));
1916 adjust_bridge_window(bridge, mmio_pref_res, add_list,
1917 resource_size(&mmio_pref));
1920 * Calculate how many hotplug bridges and normal bridges there
1921 * are on this bus. We will distribute the additional available
1922 * resources between hotplug bridges.
1924 for_each_pci_bridge(dev, bus) {
1925 if (dev->is_hotplug_bridge)
1932 * There is only one bridge on the bus so it gets all available
1933 * resources which it can then distribute to the possible hotplug
1936 if (hotplug_bridges + normal_bridges == 1) {
1937 dev = list_first_entry(&bus->devices, struct pci_dev, bus_list);
1938 if (dev->subordinate)
1939 pci_bus_distribute_available_resources(dev->subordinate,
1940 add_list, io, mmio, mmio_pref);
1944 if (hotplug_bridges == 0)
1948 * Calculate the total amount of extra resource space we can
1949 * pass to bridges below this one. This is basically the
1950 * extra space reduced by the minimal required space for the
1951 * non-hotplug bridges.
1953 for_each_pci_bridge(dev, bus) {
1954 resource_size_t used_size;
1955 struct resource *res;
1957 if (dev->is_hotplug_bridge)
1961 * Reduce the available resource space by what the
1962 * bridge and devices below it occupy.
1964 res = &dev->resource[PCI_BRIDGE_RESOURCES + 0];
1965 align = pci_resource_alignment(dev, res);
1966 align = align ? ALIGN(io.start, align) - io.start : 0;
1967 used_size = align + resource_size(res);
1969 io.start = min(io.start + used_size, io.end + 1);
1971 res = &dev->resource[PCI_BRIDGE_RESOURCES + 1];
1972 align = pci_resource_alignment(dev, res);
1973 align = align ? ALIGN(mmio.start, align) - mmio.start : 0;
1974 used_size = align + resource_size(res);
1976 mmio.start = min(mmio.start + used_size, mmio.end + 1);
1978 res = &dev->resource[PCI_BRIDGE_RESOURCES + 2];
1979 align = pci_resource_alignment(dev, res);
1980 align = align ? ALIGN(mmio_pref.start, align) -
1981 mmio_pref.start : 0;
1982 used_size = align + resource_size(res);
1984 mmio_pref.start = min(mmio_pref.start + used_size,
1988 io_per_hp = div64_ul(resource_size(&io), hotplug_bridges);
1989 mmio_per_hp = div64_ul(resource_size(&mmio), hotplug_bridges);
1990 mmio_pref_per_hp = div64_ul(resource_size(&mmio_pref),
1994 * Go over devices on this bus and distribute the remaining
1995 * resource space between hotplug bridges.
1997 for_each_pci_bridge(dev, bus) {
2000 b = dev->subordinate;
2001 if (!b || !dev->is_hotplug_bridge)
2005 * Distribute available extra resources equally between
2006 * hotplug-capable downstream ports taking alignment into
2009 io.end = io.start + io_per_hp - 1;
2010 mmio.end = mmio.start + mmio_per_hp - 1;
2011 mmio_pref.end = mmio_pref.start + mmio_pref_per_hp - 1;
2013 pci_bus_distribute_available_resources(b, add_list, io, mmio,
2016 io.start += io_per_hp;
2017 mmio.start += mmio_per_hp;
2018 mmio_pref.start += mmio_pref_per_hp;
2022 static void pci_bridge_distribute_available_resources(struct pci_dev *bridge,
2023 struct list_head *add_list)
2025 struct resource available_io, available_mmio, available_mmio_pref;
2027 if (!bridge->is_hotplug_bridge)
2030 /* Take the initial extra resources from the hotplug port */
2031 available_io = bridge->resource[PCI_BRIDGE_RESOURCES + 0];
2032 available_mmio = bridge->resource[PCI_BRIDGE_RESOURCES + 1];
2033 available_mmio_pref = bridge->resource[PCI_BRIDGE_RESOURCES + 2];
2035 pci_bus_distribute_available_resources(bridge->subordinate,
2036 add_list, available_io,
2038 available_mmio_pref);
2041 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
2043 struct pci_bus *parent = bridge->subordinate;
2044 /* List of resources that want additional resources */
2045 LIST_HEAD(add_list);
2047 int tried_times = 0;
2048 LIST_HEAD(fail_head);
2049 struct pci_dev_resource *fail_res;
2053 __pci_bus_size_bridges(parent, &add_list);
2056 * Distribute remaining resources (if any) equally between hotplug
2057 * bridges below. This makes it possible to extend the hierarchy
2058 * later without running out of resources.
2060 pci_bridge_distribute_available_resources(bridge, &add_list);
2062 __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
2063 BUG_ON(!list_empty(&add_list));
2066 if (list_empty(&fail_head))
2069 if (tried_times >= 2) {
2070 /* Still fail, don't need to try more */
2071 free_list(&fail_head);
2075 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
2079 * Try to release leaf bridge's resources that aren't big enough
2080 * to contain child device resources.
2082 list_for_each_entry(fail_res, &fail_head, list)
2083 pci_bus_release_bridge_resources(fail_res->dev->bus,
2084 fail_res->flags & PCI_RES_TYPE_MASK,
2087 /* Restore size and flags */
2088 list_for_each_entry(fail_res, &fail_head, list) {
2089 struct resource *res = fail_res->res;
2092 res->start = fail_res->start;
2093 res->end = fail_res->end;
2094 res->flags = fail_res->flags;
2096 if (pci_is_bridge(fail_res->dev)) {
2097 idx = res - &fail_res->dev->resource[0];
2098 if (idx >= PCI_BRIDGE_RESOURCES &&
2099 idx <= PCI_BRIDGE_RESOURCE_END)
2103 free_list(&fail_head);
2108 retval = pci_reenable_device(bridge);
2110 pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
2111 pci_set_master(bridge);
2113 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
2115 int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
2117 struct pci_dev_resource *dev_res;
2118 struct pci_dev *next;
2125 down_read(&pci_bus_sem);
2127 /* Walk to the root hub, releasing bridge BARs when possible */
2131 for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
2133 struct resource *res = &bridge->resource[i];
2135 if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
2138 /* Ignore BARs which are still in use */
2142 ret = add_to_list(&saved, bridge, res, 0, 0);
2146 pci_info(bridge, "BAR %d: releasing %pR\n",
2150 release_resource(res);
2155 if (i == PCI_BRIDGE_RESOURCE_END)
2158 next = bridge->bus ? bridge->bus->self : NULL;
2161 if (list_empty(&saved)) {
2162 up_read(&pci_bus_sem);
2166 __pci_bus_size_bridges(bridge->subordinate, &added);
2167 __pci_bridge_assign_resources(bridge, &added, &failed);
2168 BUG_ON(!list_empty(&added));
2170 if (!list_empty(&failed)) {
2175 list_for_each_entry(dev_res, &saved, list) {
2176 /* Skip the bridge we just assigned resources for */
2177 if (bridge == dev_res->dev)
2180 bridge = dev_res->dev;
2181 pci_setup_bridge(bridge->subordinate);
2185 up_read(&pci_bus_sem);
2189 /* Restore size and flags */
2190 list_for_each_entry(dev_res, &failed, list) {
2191 struct resource *res = dev_res->res;
2193 res->start = dev_res->start;
2194 res->end = dev_res->end;
2195 res->flags = dev_res->flags;
2199 /* Revert to the old configuration */
2200 list_for_each_entry(dev_res, &saved, list) {
2201 struct resource *res = dev_res->res;
2203 bridge = dev_res->dev;
2204 i = res - bridge->resource;
2206 res->start = dev_res->start;
2207 res->end = dev_res->end;
2208 res->flags = dev_res->flags;
2210 pci_claim_resource(bridge, i);
2211 pci_setup_bridge(bridge->subordinate);
2214 up_read(&pci_bus_sem);
2219 void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
2221 struct pci_dev *dev;
2222 /* List of resources that want additional resources */
2223 LIST_HEAD(add_list);
2225 down_read(&pci_bus_sem);
2226 for_each_pci_bridge(dev, bus)
2227 if (pci_has_subordinate(dev))
2228 __pci_bus_size_bridges(dev->subordinate, &add_list);
2229 up_read(&pci_bus_sem);
2230 __pci_bus_assign_resources(bus, &add_list, NULL);
2231 BUG_ON(!list_empty(&add_list));
2233 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);