1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
11 * Init/reset quirks for USB host controllers should be in the USB quirks
12 * file, where their drivers can use them.
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/acpi.h>
22 #include <linux/dmi.h>
23 #include <linux/ioport.h>
24 #include <linux/sched.h>
25 #include <linux/ktime.h>
27 #include <linux/nvme.h>
28 #include <linux/platform_data/x86/apple.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/switchtec.h>
31 #include <asm/dma.h> /* isa_dma_bridge_buggy */
34 static ktime_t fixup_debug_start(struct pci_dev *dev,
35 void (*fn)(struct pci_dev *dev))
38 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current));
43 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
44 void (*fn)(struct pci_dev *dev))
46 ktime_t delta, rettime;
47 unsigned long long duration;
49 rettime = ktime_get();
50 delta = ktime_sub(rettime, calltime);
51 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
52 if (initcall_debug || duration > 10000)
53 pci_info(dev, "%pS took %lld usecs\n", fn, duration);
56 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
57 struct pci_fixup *end)
62 if ((f->class == (u32) (dev->class >> f->class_shift) ||
63 f->class == (u32) PCI_ANY_ID) &&
64 (f->vendor == dev->vendor ||
65 f->vendor == (u16) PCI_ANY_ID) &&
66 (f->device == dev->device ||
67 f->device == (u16) PCI_ANY_ID)) {
68 void (*hook)(struct pci_dev *dev);
69 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
70 hook = offset_to_ptr(&f->hook_offset);
74 calltime = fixup_debug_start(dev, hook);
76 fixup_debug_report(dev, calltime, hook);
80 extern struct pci_fixup __start_pci_fixups_early[];
81 extern struct pci_fixup __end_pci_fixups_early[];
82 extern struct pci_fixup __start_pci_fixups_header[];
83 extern struct pci_fixup __end_pci_fixups_header[];
84 extern struct pci_fixup __start_pci_fixups_final[];
85 extern struct pci_fixup __end_pci_fixups_final[];
86 extern struct pci_fixup __start_pci_fixups_enable[];
87 extern struct pci_fixup __end_pci_fixups_enable[];
88 extern struct pci_fixup __start_pci_fixups_resume[];
89 extern struct pci_fixup __end_pci_fixups_resume[];
90 extern struct pci_fixup __start_pci_fixups_resume_early[];
91 extern struct pci_fixup __end_pci_fixups_resume_early[];
92 extern struct pci_fixup __start_pci_fixups_suspend[];
93 extern struct pci_fixup __end_pci_fixups_suspend[];
94 extern struct pci_fixup __start_pci_fixups_suspend_late[];
95 extern struct pci_fixup __end_pci_fixups_suspend_late[];
97 static bool pci_apply_fixup_final_quirks;
99 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
101 struct pci_fixup *start, *end;
104 case pci_fixup_early:
105 start = __start_pci_fixups_early;
106 end = __end_pci_fixups_early;
109 case pci_fixup_header:
110 start = __start_pci_fixups_header;
111 end = __end_pci_fixups_header;
114 case pci_fixup_final:
115 if (!pci_apply_fixup_final_quirks)
117 start = __start_pci_fixups_final;
118 end = __end_pci_fixups_final;
121 case pci_fixup_enable:
122 start = __start_pci_fixups_enable;
123 end = __end_pci_fixups_enable;
126 case pci_fixup_resume:
127 start = __start_pci_fixups_resume;
128 end = __end_pci_fixups_resume;
131 case pci_fixup_resume_early:
132 start = __start_pci_fixups_resume_early;
133 end = __end_pci_fixups_resume_early;
136 case pci_fixup_suspend:
137 start = __start_pci_fixups_suspend;
138 end = __end_pci_fixups_suspend;
141 case pci_fixup_suspend_late:
142 start = __start_pci_fixups_suspend_late;
143 end = __end_pci_fixups_suspend_late;
147 /* stupid compiler warning, you would think with an enum... */
150 pci_do_fixups(dev, start, end);
152 EXPORT_SYMBOL(pci_fixup_device);
154 static int __init pci_apply_final_quirks(void)
156 struct pci_dev *dev = NULL;
160 if (pci_cache_line_size)
161 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
163 pci_apply_fixup_final_quirks = true;
164 for_each_pci_dev(dev) {
165 pci_fixup_device(pci_fixup_final, dev);
167 * If arch hasn't set it explicitly yet, use the CLS
168 * value shared by all PCI devices. If there's a
169 * mismatch, fall back to the default value.
171 if (!pci_cache_line_size) {
172 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
175 if (!tmp || cls == tmp)
178 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n",
180 pci_dfl_cache_line_size << 2);
181 pci_cache_line_size = pci_dfl_cache_line_size;
185 if (!pci_cache_line_size) {
186 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
187 pci_dfl_cache_line_size << 2);
188 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
193 fs_initcall_sync(pci_apply_final_quirks);
196 * Decoding should be disabled for a PCI device during BAR sizing to avoid
197 * conflict. But doing so may cause problems on host bridge and perhaps other
198 * key system devices. For devices that need to have mmio decoding always-on,
199 * we need to set the dev->mmio_always_on bit.
201 static void quirk_mmio_always_on(struct pci_dev *dev)
203 dev->mmio_always_on = 1;
205 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
206 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
209 * The Mellanox Tavor device gives false positive parity errors. Disable
210 * parity error reporting.
212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity);
213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity);
216 * Deal with broken BIOSes that neglect to enable passive release,
217 * which can cause problems in combination with the 82441FX/PPro MTRRs
219 static void quirk_passive_release(struct pci_dev *dev)
221 struct pci_dev *d = NULL;
225 * We have to make sure a particular bit is set in the PIIX3
226 * ISA bridge, so we have to go out and find it.
228 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
229 pci_read_config_byte(d, 0x82, &dlc);
231 pci_info(d, "PIIX3: Enabling Passive Release\n");
233 pci_write_config_byte(d, 0x82, dlc);
237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
238 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
241 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a
242 * workaround but VIA don't answer queries. If you happen to have good
243 * contacts at VIA ask them for me please -- Alan
245 * This appears to be BIOS not version dependent. So presumably there is a
248 static void quirk_isa_dma_hangs(struct pci_dev *dev)
250 if (!isa_dma_bridge_buggy) {
251 isa_dma_bridge_buggy = 1;
252 pci_info(dev, "Activating ISA DMA hang workarounds\n");
256 * It's not totally clear which chipsets are the problematic ones. We know
257 * 82C586 and 82C596 variants are affected.
259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
263 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
264 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
265 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
268 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
269 * for some HT machines to use C4 w/o hanging.
271 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
276 pci_read_config_dword(dev, 0x40, &pmbase);
277 pmbase = pmbase & 0xff80;
281 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
285 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
287 /* Chipsets where PCI->PCI transfers vanish or hang */
288 static void quirk_nopcipci(struct pci_dev *dev)
290 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
291 pci_info(dev, "Disabling direct PCI/PCI transfers\n");
292 pci_pci_problems |= PCIPCI_FAIL;
295 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
296 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
298 static void quirk_nopciamd(struct pci_dev *dev)
301 pci_read_config_byte(dev, 0x08, &rev);
304 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
305 pci_pci_problems |= PCIAGP_FAIL;
308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
310 /* Triton requires workarounds to be used by the drivers */
311 static void quirk_triton(struct pci_dev *dev)
313 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
314 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
315 pci_pci_problems |= PCIPCI_TRITON;
318 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
319 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
320 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
324 * VIA Apollo KT133 needs PCI latency patch
325 * Made according to a Windows driver-based patch by George E. Breese;
326 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
327 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
328 * which Mr Breese based his work.
330 * Updated based on further information from the site and also on
331 * information provided by VIA
333 static void quirk_vialatency(struct pci_dev *dev)
339 * Ok, we have a potential problem chipset here. Now see if we have
340 * a buggy southbridge.
342 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
346 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A;
348 * Check for buggy part revisions
350 if (p->revision < 0x40 || p->revision > 0x42)
353 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
354 if (p == NULL) /* No problem parts */
357 /* Check for buggy part revisions */
358 if (p->revision < 0x10 || p->revision > 0x12)
363 * Ok we have the problem. Now set the PCI master grant to occur
364 * every master grant. The apparent bug is that under high PCI load
365 * (quite common in Linux of course) you can get data loss when the
366 * CPU is held off the bus for 3 bus master requests. This happens
367 * to include the IDE controllers....
369 * VIA only apply this fix when an SB Live! is present but under
370 * both Linux and Windows this isn't enough, and we have seen
371 * corruption without SB Live! but with things like 3 UDMA IDE
372 * controllers. So we ignore that bit of the VIA recommendation..
374 pci_read_config_byte(dev, 0x76, &busarb);
377 * Set bit 4 and bit 5 of byte 76 to 0x01
378 * "Master priority rotation on every PCI master grant"
382 pci_write_config_byte(dev, 0x76, busarb);
383 pci_info(dev, "Applying VIA southbridge workaround\n");
387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
388 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
389 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
390 /* Must restore this on a resume from RAM */
391 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
392 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
393 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
395 /* VIA Apollo VP3 needs ETBF on BT848/878 */
396 static void quirk_viaetbf(struct pci_dev *dev)
398 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
399 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
400 pci_pci_problems |= PCIPCI_VIAETBF;
403 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
405 static void quirk_vsfx(struct pci_dev *dev)
407 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
408 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
409 pci_pci_problems |= PCIPCI_VSFX;
412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
415 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP
416 * space. Latency must be set to 0xA and Triton workaround applied too.
417 * [Info kindly provided by ALi]
419 static void quirk_alimagik(struct pci_dev *dev)
421 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
422 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
423 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
426 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
427 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
429 /* Natoma has some interesting boundary conditions with Zoran stuff at least */
430 static void quirk_natoma(struct pci_dev *dev)
432 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
433 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
434 pci_pci_problems |= PCIPCI_NATOMA;
437 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
438 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
439 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
440 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
441 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
442 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
445 * This chip can cause PCI parity errors if config register 0xA0 is read
446 * while DMAs are occurring.
448 static void quirk_citrine(struct pci_dev *dev)
450 dev->cfg_size = 0xA0;
452 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
455 * This chip can cause bus lockups if config addresses above 0x600
456 * are read or written.
458 static void quirk_nfp6000(struct pci_dev *dev)
460 dev->cfg_size = 0x600;
462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
463 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000);
465 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
467 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
468 static void quirk_extend_bar_to_page(struct pci_dev *dev)
472 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
473 struct resource *r = &dev->resource[i];
475 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
476 r->end = PAGE_SIZE - 1;
478 r->flags |= IORESOURCE_UNSET;
479 pci_info(dev, "expanded BAR %d to page size: %pR\n",
484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
487 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
488 * If it's needed, re-allocate the region.
490 static void quirk_s3_64M(struct pci_dev *dev)
492 struct resource *r = &dev->resource[0];
494 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
495 r->flags |= IORESOURCE_UNSET;
500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
503 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
507 struct pci_bus_region bus_region;
508 struct resource *res = dev->resource + pos;
510 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
515 res->name = pci_name(dev);
516 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
518 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
519 region &= ~(size - 1);
521 /* Convert from PCI bus to resource space */
522 bus_region.start = region;
523 bus_region.end = region + size - 1;
524 pcibios_bus_to_resource(dev->bus, res, &bus_region);
526 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
527 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
531 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
532 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
533 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
534 * (which conflicts w/ BAR1's memory range).
536 * CS553x's ISA PCI BARs may also be read-only (ref:
537 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
539 static void quirk_cs5536_vsa(struct pci_dev *dev)
541 static char *name = "CS5536 ISA bridge";
543 if (pci_resource_len(dev, 0) != 8) {
544 quirk_io(dev, 0, 8, name); /* SMB */
545 quirk_io(dev, 1, 256, name); /* GPIO */
546 quirk_io(dev, 2, 64, name); /* MFGPT */
547 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
551 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
553 static void quirk_io_region(struct pci_dev *dev, int port,
554 unsigned size, int nr, const char *name)
557 struct pci_bus_region bus_region;
558 struct resource *res = dev->resource + nr;
560 pci_read_config_word(dev, port, ®ion);
561 region &= ~(size - 1);
566 res->name = pci_name(dev);
567 res->flags = IORESOURCE_IO;
569 /* Convert from PCI bus to resource space */
570 bus_region.start = region;
571 bus_region.end = region + size - 1;
572 pcibios_bus_to_resource(dev->bus, res, &bus_region);
574 if (!pci_claim_resource(dev, nr))
575 pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
579 * ATI Northbridge setups MCE the processor if you even read somewhere
580 * between 0x3b0->0x3bb or read 0x3d3
582 static void quirk_ati_exploding_mce(struct pci_dev *dev)
584 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
585 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
586 request_region(0x3b0, 0x0C, "RadeonIGP");
587 request_region(0x3d3, 0x01, "RadeonIGP");
589 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
592 * In the AMD NL platform, this device ([1022:7912]) has a class code of
593 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
596 * But the dwc3 driver is a more specific driver for this device, and we'd
597 * prefer to use it instead of xhci. To prevent xhci from claiming the
598 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
599 * defines as "USB device (not host controller)". The dwc3 driver can then
600 * claim it based on its Vendor and Device ID.
602 static void quirk_amd_nl_class(struct pci_dev *pdev)
604 u32 class = pdev->class;
606 /* Use "USB Device (not host controller)" class */
607 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
608 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
615 * Synopsys USB 3.x host HAPS platform has a class code of
616 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
617 * devices should use dwc3-haps driver. Change these devices' class code to
618 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
621 static void quirk_synopsys_haps(struct pci_dev *pdev)
623 u32 class = pdev->class;
625 switch (pdev->device) {
626 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
627 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
628 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
629 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
630 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
635 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
636 PCI_CLASS_SERIAL_USB_XHCI, 0,
637 quirk_synopsys_haps);
640 * Let's make the southbridge information explicit instead of having to
641 * worry about people probing the ACPI areas, for example.. (Yes, it
642 * happens, and if you read the wrong ACPI register it will put the machine
643 * to sleep with no way of waking it up again. Bummer).
645 * ALI M7101: Two IO regions pointed to by words at
646 * 0xE0 (64 bytes of ACPI registers)
647 * 0xE2 (32 bytes of SMB registers)
649 static void quirk_ali7101_acpi(struct pci_dev *dev)
651 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
652 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
654 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
656 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
659 u32 mask, size, base;
661 pci_read_config_dword(dev, port, &devres);
662 if ((devres & enable) != enable)
664 mask = (devres >> 16) & 15;
665 base = devres & 0xffff;
668 unsigned bit = size >> 1;
669 if ((bit & mask) == bit)
674 * For now we only print it out. Eventually we'll want to
675 * reserve it (at least if it's in the 0x1000+ range), but
676 * let's get enough confirmation reports first.
679 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
682 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
685 u32 mask, size, base;
687 pci_read_config_dword(dev, port, &devres);
688 if ((devres & enable) != enable)
690 base = devres & 0xffff0000;
691 mask = (devres & 0x3f) << 16;
694 unsigned bit = size >> 1;
695 if ((bit & mask) == bit)
701 * For now we only print it out. Eventually we'll want to
702 * reserve it, but let's get enough confirmation reports first.
705 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
709 * PIIX4 ACPI: Two IO regions pointed to by longwords at
710 * 0x40 (64 bytes of ACPI registers)
711 * 0x90 (16 bytes of SMB registers)
712 * and a few strange programmable PIIX4 device resources.
714 static void quirk_piix4_acpi(struct pci_dev *dev)
718 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
719 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
721 /* Device resource A has enables for some of the other ones */
722 pci_read_config_dword(dev, 0x5c, &res_a);
724 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
725 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
727 /* Device resource D is just bitfields for static resources */
729 /* Device 12 enabled? */
730 if (res_a & (1 << 29)) {
731 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
732 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
734 /* Device 13 enabled? */
735 if (res_a & (1 << 30)) {
736 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
737 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
739 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
740 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
742 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
743 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
745 #define ICH_PMBASE 0x40
746 #define ICH_ACPI_CNTL 0x44
747 #define ICH4_ACPI_EN 0x10
748 #define ICH6_ACPI_EN 0x80
749 #define ICH4_GPIOBASE 0x58
750 #define ICH4_GPIO_CNTL 0x5c
751 #define ICH4_GPIO_EN 0x10
752 #define ICH6_GPIOBASE 0x48
753 #define ICH6_GPIO_CNTL 0x4c
754 #define ICH6_GPIO_EN 0x10
757 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
758 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
759 * 0x58 (64 bytes of GPIO I/O space)
761 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
766 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
767 * with low legacy (and fixed) ports. We don't know the decoding
768 * priority and can't tell whether the legacy device or the one created
769 * here is really at that address. This happens on boards with broken
772 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
773 if (enable & ICH4_ACPI_EN)
774 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
775 "ICH4 ACPI/GPIO/TCO");
777 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
778 if (enable & ICH4_GPIO_EN)
779 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
782 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
783 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
784 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
785 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
786 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
787 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
788 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
789 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
790 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
791 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
793 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
797 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
798 if (enable & ICH6_ACPI_EN)
799 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
800 "ICH6 ACPI/GPIO/TCO");
802 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
803 if (enable & ICH6_GPIO_EN)
804 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
808 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
809 const char *name, int dynsize)
814 pci_read_config_dword(dev, reg, &val);
822 * This is not correct. It is 16, 32 or 64 bytes depending on
823 * register D31:F0:ADh bits 5:4.
825 * But this gets us at least _part_ of it.
834 * Just print it out for now. We should reserve it after more
837 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
840 static void quirk_ich6_lpc(struct pci_dev *dev)
842 /* Shared ACPI/GPIO decode with all ICH6+ */
843 ich6_lpc_acpi_gpio(dev);
845 /* ICH6-specific generic IO decode */
846 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
847 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
849 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
850 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
852 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg,
858 pci_read_config_dword(dev, reg, &val);
864 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */
866 mask = (val >> 16) & 0xfc;
870 * Just print it out for now. We should reserve it after more
873 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
876 /* ICH7-10 has the same common LPC generic IO decode registers */
877 static void quirk_ich7_lpc(struct pci_dev *dev)
879 /* We share the common ACPI/GPIO decode with ICH6 */
880 ich6_lpc_acpi_gpio(dev);
882 /* And have 4 ICH7+ generic decodes */
883 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
884 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
885 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
886 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
888 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
889 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
890 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
891 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
892 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
893 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
894 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
896 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
897 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
899 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
903 * VIA ACPI: One IO region pointed to by longword at
904 * 0x48 or 0x20 (256 bytes of ACPI registers)
906 static void quirk_vt82c586_acpi(struct pci_dev *dev)
908 if (dev->revision & 0x10)
909 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
915 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
916 * 0x48 (256 bytes of ACPI registers)
917 * 0x70 (128 bytes of hardware monitoring register)
918 * 0x90 (16 bytes of SMB registers)
920 static void quirk_vt82c686_acpi(struct pci_dev *dev)
922 quirk_vt82c586_acpi(dev);
924 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
927 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
929 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
932 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
933 * 0x88 (128 bytes of power management registers)
934 * 0xd0 (16 bytes of SMB registers)
936 static void quirk_vt8235_acpi(struct pci_dev *dev)
938 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
939 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
941 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
944 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
945 * back-to-back: Disable fast back-to-back on the secondary bus segment
947 static void quirk_xio2000a(struct pci_dev *dev)
949 struct pci_dev *pdev;
952 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
953 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
954 pci_read_config_word(pdev, PCI_COMMAND, &command);
955 if (command & PCI_COMMAND_FAST_BACK)
956 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
959 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
962 #ifdef CONFIG_X86_IO_APIC
964 #include <asm/io_apic.h>
967 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
968 * devices to the external APIC.
970 * TODO: When we have device-specific interrupt routers, this code will go
973 static void quirk_via_ioapic(struct pci_dev *dev)
978 tmp = 0; /* nothing routed to external APIC */
980 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
982 pci_info(dev, "%sbling VIA external APIC routing\n",
983 tmp == 0 ? "Disa" : "Ena");
985 /* Offset 0x58: External APIC IRQ output control */
986 pci_write_config_byte(dev, 0x58, tmp);
988 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
989 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
992 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
993 * This leads to doubled level interrupt rates.
994 * Set this bit to get rid of cycle wastage.
995 * Otherwise uncritical.
997 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
1000 #define BYPASS_APIC_DEASSERT 8
1002 pci_read_config_byte(dev, 0x5B, &misc_control2);
1003 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
1004 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
1005 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
1008 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1009 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
1012 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1013 * We check all revs >= B0 (yet not in the pre production!) as the bug
1014 * is currently marked NoFix
1016 * We have multiple reports of hangs with this chipset that went away with
1017 * noapic specified. For the moment we assume it's the erratum. We may be wrong
1018 * of course. However the advice is demonstrably good even if so.
1020 static void quirk_amd_ioapic(struct pci_dev *dev)
1022 if (dev->revision >= 0x02) {
1023 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
1024 pci_warn(dev, " : booting with the \"noapic\" option\n");
1027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
1028 #endif /* CONFIG_X86_IO_APIC */
1030 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
1032 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
1034 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */
1035 if (dev->subsystem_device == 0xa118)
1036 dev->sriov->link = dev->devfn;
1038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
1042 * Some settings of MMRBC can lead to data corruption so block changes.
1043 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1045 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
1047 if (dev->subordinate && dev->revision <= 0x12) {
1048 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
1050 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
1053 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
1056 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up
1057 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register
1058 * at all. Therefore it seems like setting the pci_dev's IRQ to the value
1059 * of the ACPI SCI interrupt is only done for convenience.
1062 static void quirk_via_acpi(struct pci_dev *d)
1066 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */
1067 pci_read_config_byte(d, 0x42, &irq);
1069 if (irq && (irq != 2))
1072 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
1073 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
1075 /* VIA bridges which have VLink */
1076 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1078 static void quirk_via_bridge(struct pci_dev *dev)
1080 /* See what bridge we have and find the device ranges */
1081 switch (dev->device) {
1082 case PCI_DEVICE_ID_VIA_82C686:
1084 * The VT82C686 is special; it attaches to PCI and can have
1085 * any device number. All its subdevices are functions of
1086 * that single device.
1088 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
1089 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
1091 case PCI_DEVICE_ID_VIA_8237:
1092 case PCI_DEVICE_ID_VIA_8237A:
1093 via_vlink_dev_lo = 15;
1095 case PCI_DEVICE_ID_VIA_8235:
1096 via_vlink_dev_lo = 16;
1098 case PCI_DEVICE_ID_VIA_8231:
1099 case PCI_DEVICE_ID_VIA_8233_0:
1100 case PCI_DEVICE_ID_VIA_8233A:
1101 case PCI_DEVICE_ID_VIA_8233C_0:
1102 via_vlink_dev_lo = 17;
1106 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
1107 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
1108 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
1109 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
1110 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
1111 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
1112 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
1113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
1116 * quirk_via_vlink - VIA VLink IRQ number update
1119 * If the device we are dealing with is on a PIC IRQ we need to ensure that
1120 * the IRQ line register which usually is not relevant for PCI cards, is
1121 * actually written so that interrupts get sent to the right place.
1123 * We only do this on systems where a VIA south bridge was detected, and
1124 * only for VIA devices on the motherboard (see quirk_via_bridge above).
1126 static void quirk_via_vlink(struct pci_dev *dev)
1130 /* Check if we have VLink at all */
1131 if (via_vlink_dev_lo == -1)
1136 /* Don't quirk interrupts outside the legacy IRQ range */
1137 if (!new_irq || new_irq > 15)
1140 /* Internal device ? */
1141 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
1142 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
1146 * This is an internal VLink device on a PIC interrupt. The BIOS
1147 * ought to have set this but may not have, so we redo it.
1149 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1150 if (new_irq != irq) {
1151 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
1153 udelay(15); /* unknown if delay really needed */
1154 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
1157 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
1160 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID
1161 * of VT82C597 for backward compatibility. We need to switch it off to be
1162 * able to recognize the real type of the chip.
1164 static void quirk_vt82c598_id(struct pci_dev *dev)
1166 pci_write_config_byte(dev, 0xfc, 0);
1167 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
1169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
1172 * CardBus controllers have a legacy base address that enables them to
1173 * respond as i82365 pcmcia controllers. We don't want them to do this
1174 * even if the Linux CardBus driver is not loaded, because the Linux i82365
1175 * driver does not (and should not) handle CardBus.
1177 static void quirk_cardbus_legacy(struct pci_dev *dev)
1179 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1181 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1182 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1183 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
1184 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1187 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1188 * what the designers were smoking but let's not inhale...
1190 * To be fair to AMD, it follows the spec by default, it's BIOS people who
1193 static void quirk_amd_ordering(struct pci_dev *dev)
1196 pci_read_config_dword(dev, 0x4C, &pcic);
1197 if ((pcic & 6) != 6) {
1199 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1200 pci_write_config_dword(dev, 0x4C, pcic);
1201 pci_read_config_dword(dev, 0x84, &pcic);
1202 pcic |= (1 << 23); /* Required in this mode */
1203 pci_write_config_dword(dev, 0x84, pcic);
1206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1207 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1210 * DreamWorks-provided workaround for Dunord I-3000 problem
1212 * This card decodes and responds to addresses not apparently assigned to
1213 * it. We force a larger allocation to ensure that nothing gets put too
1216 static void quirk_dunord(struct pci_dev *dev)
1218 struct resource *r = &dev->resource[1];
1220 r->flags |= IORESOURCE_UNSET;
1224 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1227 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1228 * decoding (transparent), and does indicate this in the ProgIf.
1229 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1231 static void quirk_transparent_bridge(struct pci_dev *dev)
1233 dev->transparent = 1;
1235 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1239 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1240 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1241 * found at http://www.national.com/analog for info on what these bits do.
1242 * <christer@weinigel.se>
1244 static void quirk_mediagx_master(struct pci_dev *dev)
1248 pci_read_config_byte(dev, 0x41, ®);
1251 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1253 pci_write_config_byte(dev, 0x41, reg);
1256 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1257 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1260 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but
1261 * in the odd case it is not the results are corruption hence the presence
1264 static void quirk_disable_pxb(struct pci_dev *pdev)
1268 if (pdev->revision != 0x04) /* Only C0 requires this */
1270 pci_read_config_word(pdev, 0x40, &config);
1271 if (config & (1<<6)) {
1273 pci_write_config_word(pdev, 0x40, config);
1274 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1278 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1280 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1282 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1285 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1287 pci_read_config_byte(pdev, 0x40, &tmp);
1288 pci_write_config_byte(pdev, 0x40, tmp|1);
1289 pci_write_config_byte(pdev, 0x9, 1);
1290 pci_write_config_byte(pdev, 0xa, 6);
1291 pci_write_config_byte(pdev, 0x40, tmp);
1293 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1294 pci_info(pdev, "set SATA to AHCI mode\n");
1297 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1298 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1299 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1300 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1302 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1304 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1306 /* Serverworks CSB5 IDE does not fully support native mode */
1307 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1310 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1314 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1315 /* PCI layer will sort out resources */
1318 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1320 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1321 static void quirk_ide_samemode(struct pci_dev *pdev)
1325 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1327 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1328 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1331 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1334 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1336 /* Some ATA devices break if put into D3 */
1337 static void quirk_no_ata_d3(struct pci_dev *pdev)
1339 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1341 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1342 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1343 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1344 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1345 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1346 /* ALi loses some register settings that we cannot then restore */
1347 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1348 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1349 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1350 occur when mode detecting */
1351 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1352 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1355 * This was originally an Alpha-specific thing, but it really fits here.
1356 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1358 static void quirk_eisa_bridge(struct pci_dev *dev)
1360 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1362 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1365 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1366 * is not activated. The myth is that Asus said that they do not want the
1367 * users to be irritated by just another PCI Device in the Win98 device
1368 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1369 * package 2.7.0 for details)
1371 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1372 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1373 * becomes necessary to do this tweak in two steps -- the chosen trigger
1374 * is either the Host bridge (preferred) or on-board VGA controller.
1376 * Note that we used to unhide the SMBus that way on Toshiba laptops
1377 * (Satellite A40 and Tecra M2) but then found that the thermal management
1378 * was done by SMM code, which could cause unsynchronized concurrent
1379 * accesses to the SMBus registers, with potentially bad effects. Thus you
1380 * should be very careful when adding new entries: if SMM is accessing the
1381 * Intel SMBus, this is a very good reason to leave it hidden.
1383 * Likewise, many recent laptops use ACPI for thermal management. If the
1384 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1385 * natively, and keeping the SMBus hidden is the right thing to do. If you
1386 * are about to add an entry in the table below, please first disassemble
1387 * the DSDT and double-check that there is no code accessing the SMBus.
1389 static int asus_hides_smbus;
1391 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1393 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1394 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1395 switch (dev->subsystem_device) {
1396 case 0x8025: /* P4B-LX */
1397 case 0x8070: /* P4B */
1398 case 0x8088: /* P4B533 */
1399 case 0x1626: /* L3C notebook */
1400 asus_hides_smbus = 1;
1402 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1403 switch (dev->subsystem_device) {
1404 case 0x80b1: /* P4GE-V */
1405 case 0x80b2: /* P4PE */
1406 case 0x8093: /* P4B533-V */
1407 asus_hides_smbus = 1;
1409 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1410 switch (dev->subsystem_device) {
1411 case 0x8030: /* P4T533 */
1412 asus_hides_smbus = 1;
1414 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1415 switch (dev->subsystem_device) {
1416 case 0x8070: /* P4G8X Deluxe */
1417 asus_hides_smbus = 1;
1419 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1420 switch (dev->subsystem_device) {
1421 case 0x80c9: /* PU-DLS */
1422 asus_hides_smbus = 1;
1424 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1425 switch (dev->subsystem_device) {
1426 case 0x1751: /* M2N notebook */
1427 case 0x1821: /* M5N notebook */
1428 case 0x1897: /* A6L notebook */
1429 asus_hides_smbus = 1;
1431 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1432 switch (dev->subsystem_device) {
1433 case 0x184b: /* W1N notebook */
1434 case 0x186a: /* M6Ne notebook */
1435 asus_hides_smbus = 1;
1437 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1438 switch (dev->subsystem_device) {
1439 case 0x80f2: /* P4P800-X */
1440 asus_hides_smbus = 1;
1442 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1443 switch (dev->subsystem_device) {
1444 case 0x1882: /* M6V notebook */
1445 case 0x1977: /* A6VA notebook */
1446 asus_hides_smbus = 1;
1448 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1449 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1450 switch (dev->subsystem_device) {
1451 case 0x088C: /* HP Compaq nc8000 */
1452 case 0x0890: /* HP Compaq nc6000 */
1453 asus_hides_smbus = 1;
1455 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1456 switch (dev->subsystem_device) {
1457 case 0x12bc: /* HP D330L */
1458 case 0x12bd: /* HP D530 */
1459 case 0x006a: /* HP Compaq nx9500 */
1460 asus_hides_smbus = 1;
1462 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1463 switch (dev->subsystem_device) {
1464 case 0x12bf: /* HP xw4100 */
1465 asus_hides_smbus = 1;
1467 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1468 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1469 switch (dev->subsystem_device) {
1470 case 0xC00C: /* Samsung P35 notebook */
1471 asus_hides_smbus = 1;
1473 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1474 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1475 switch (dev->subsystem_device) {
1476 case 0x0058: /* Compaq Evo N620c */
1477 asus_hides_smbus = 1;
1479 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1480 switch (dev->subsystem_device) {
1481 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1482 /* Motherboard doesn't have Host bridge
1483 * subvendor/subdevice IDs, therefore checking
1484 * its on-board VGA controller */
1485 asus_hides_smbus = 1;
1487 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1488 switch (dev->subsystem_device) {
1489 case 0x00b8: /* Compaq Evo D510 CMT */
1490 case 0x00b9: /* Compaq Evo D510 SFF */
1491 case 0x00ba: /* Compaq Evo D510 USDT */
1492 /* Motherboard doesn't have Host bridge
1493 * subvendor/subdevice IDs and on-board VGA
1494 * controller is disabled if an AGP card is
1495 * inserted, therefore checking USB UHCI
1497 asus_hides_smbus = 1;
1499 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1500 switch (dev->subsystem_device) {
1501 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1502 /* Motherboard doesn't have host bridge
1503 * subvendor/subdevice IDs, therefore checking
1504 * its on-board VGA controller */
1505 asus_hides_smbus = 1;
1509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1513 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1516 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1517 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1522 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1524 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1528 if (likely(!asus_hides_smbus))
1531 pci_read_config_word(dev, 0xF2, &val);
1533 pci_write_config_word(dev, 0xF2, val & (~0x8));
1534 pci_read_config_word(dev, 0xF2, &val);
1536 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1539 pci_info(dev, "Enabled i801 SMBus device\n");
1542 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1543 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1544 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1545 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1546 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1547 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1548 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1549 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1550 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1551 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1552 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1553 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1554 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1555 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1557 /* It appears we just have one such device. If not, we have a warning */
1558 static void __iomem *asus_rcba_base;
1559 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1563 if (likely(!asus_hides_smbus))
1565 WARN_ON(asus_rcba_base);
1567 pci_read_config_dword(dev, 0xF0, &rcba);
1568 /* use bits 31:14, 16 kB aligned */
1569 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000);
1570 if (asus_rcba_base == NULL)
1574 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1578 if (likely(!asus_hides_smbus || !asus_rcba_base))
1581 /* read the Function Disable register, dword mode only */
1582 val = readl(asus_rcba_base + 0x3418);
1584 /* enable the SMBus device */
1585 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1588 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1590 if (likely(!asus_hides_smbus || !asus_rcba_base))
1593 iounmap(asus_rcba_base);
1594 asus_rcba_base = NULL;
1595 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1598 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1600 asus_hides_smbus_lpc_ich6_suspend(dev);
1601 asus_hides_smbus_lpc_ich6_resume_early(dev);
1602 asus_hides_smbus_lpc_ich6_resume(dev);
1604 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1605 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1606 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1607 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1609 /* SiS 96x south bridge: BIOS typically hides SMBus device... */
1610 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1613 pci_read_config_byte(dev, 0x77, &val);
1615 pci_info(dev, "Enabling SiS 96x SMBus\n");
1616 pci_write_config_byte(dev, 0x77, val & ~0x10);
1619 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1620 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1621 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1622 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1623 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1624 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1625 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1626 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1629 * ... This is further complicated by the fact that some SiS96x south
1630 * bridges pretend to be 85C503/5513 instead. In that case see if we
1631 * spotted a compatible north bridge to make sure.
1632 * (pci_find_device() doesn't work yet)
1634 * We can also enable the sis96x bit in the discovery register..
1636 #define SIS_DETECT_REGISTER 0x40
1638 static void quirk_sis_503(struct pci_dev *dev)
1643 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1644 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1645 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1646 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1647 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1652 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case
1653 * it has already been processed. (Depends on link order, which is
1654 * apparently not guaranteed)
1656 dev->device = devid;
1657 quirk_sis_96x_smbus(dev);
1659 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1660 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1663 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1664 * and MC97 modem controller are disabled when a second PCI soundcard is
1665 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1668 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1671 int asus_hides_ac97 = 0;
1673 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1674 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1675 asus_hides_ac97 = 1;
1678 if (!asus_hides_ac97)
1681 pci_read_config_byte(dev, 0x50, &val);
1683 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1684 pci_read_config_byte(dev, 0x50, &val);
1686 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1689 pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1692 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1693 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1695 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1698 * If we are using libata we can drive this chip properly but must do this
1699 * early on to make the additional device appear during the PCI scanning.
1701 static void quirk_jmicron_ata(struct pci_dev *pdev)
1703 u32 conf1, conf5, class;
1706 /* Only poke fn 0 */
1707 if (PCI_FUNC(pdev->devfn))
1710 pci_read_config_dword(pdev, 0x40, &conf1);
1711 pci_read_config_dword(pdev, 0x80, &conf5);
1713 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1714 conf5 &= ~(1 << 24); /* Clear bit 24 */
1716 switch (pdev->device) {
1717 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1718 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1719 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1720 /* The controller should be in single function ahci mode */
1721 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1724 case PCI_DEVICE_ID_JMICRON_JMB365:
1725 case PCI_DEVICE_ID_JMICRON_JMB366:
1726 /* Redirect IDE second PATA port to the right spot */
1729 case PCI_DEVICE_ID_JMICRON_JMB361:
1730 case PCI_DEVICE_ID_JMICRON_JMB363:
1731 case PCI_DEVICE_ID_JMICRON_JMB369:
1732 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1733 /* Set the class codes correctly and then direct IDE 0 */
1734 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1737 case PCI_DEVICE_ID_JMICRON_JMB368:
1738 /* The controller should be in single function IDE mode */
1739 conf1 |= 0x00C00000; /* Set 22, 23 */
1743 pci_write_config_dword(pdev, 0x40, conf1);
1744 pci_write_config_dword(pdev, 0x80, conf5);
1746 /* Update pdev accordingly */
1747 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1748 pdev->hdr_type = hdr & 0x7f;
1749 pdev->multifunction = !!(hdr & 0x80);
1751 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1752 pdev->class = class >> 8;
1754 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1755 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1756 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1757 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1758 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1759 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1760 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1761 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1762 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1763 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1764 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1765 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1766 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1767 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1768 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1769 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1770 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1771 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1775 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1777 if (dev->multifunction) {
1778 device_disable_async_suspend(&dev->dev);
1779 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1782 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1783 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1784 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1785 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1787 #ifdef CONFIG_X86_IO_APIC
1788 static void quirk_alder_ioapic(struct pci_dev *pdev)
1792 if ((pdev->class >> 8) != 0xff00)
1796 * The first BAR is the location of the IO-APIC... we must
1797 * not touch this (and it's already covered by the fixmap), so
1798 * forcibly insert it into the resource tree.
1800 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1801 insert_resource(&iomem_resource, &pdev->resource[0]);
1804 * The next five BARs all seem to be rubbish, so just clean
1807 for (i = 1; i < PCI_STD_NUM_BARS; i++)
1808 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1810 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1813 static void quirk_pcie_mch(struct pci_dev *pdev)
1817 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1818 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1819 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1821 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1824 * It's possible for the MSI to get corrupted if SHPC and ACPI are used
1825 * together on certain PXH-based systems.
1827 static void quirk_pcie_pxh(struct pci_dev *dev)
1830 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1832 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1833 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1834 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1835 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1836 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1839 * Some Intel PCI Express chipsets have trouble with downstream device
1842 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1844 pci_pm_d3hot_delay = 120;
1847 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1848 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1849 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1850 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1851 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1852 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1853 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1854 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1855 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1856 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1857 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1858 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1859 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1860 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1861 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1862 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1863 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1864 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1865 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1866 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1867 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1869 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)
1871 if (dev->d3hot_delay >= delay)
1874 dev->d3hot_delay = delay;
1875 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",
1879 static void quirk_radeon_pm(struct pci_dev *dev)
1881 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1882 dev->subsystem_device == 0x00e2)
1883 quirk_d3hot_delay(dev, 20);
1885 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1888 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.
1889 * https://bugzilla.kernel.org/show_bug.cgi?id=205587
1891 * The kernel attempts to transition these devices to D3cold, but that seems
1892 * to be ineffective on the platforms in question; the PCI device appears to
1893 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1894 * extended delay in order to succeed.
1896 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)
1898 quirk_d3hot_delay(dev, 20);
1900 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);
1901 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);
1903 #ifdef CONFIG_X86_IO_APIC
1904 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1906 noioapicreroute = 1;
1907 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1912 static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1914 * Systems to exclude from boot interrupt reroute quirks
1917 .callback = dmi_disable_ioapicreroute,
1918 .ident = "ASUSTek Computer INC. M2N-LR",
1920 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1921 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1928 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1929 * remap the original interrupt in the Linux kernel to the boot interrupt, so
1930 * that a PCI device's interrupt handler is installed on the boot interrupt
1933 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1935 dmi_check_system(boot_interrupt_dmi_table);
1936 if (noioapicquirk || noioapicreroute)
1939 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1940 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
1941 dev->vendor, dev->device);
1943 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1944 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1945 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1946 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1947 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1948 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1949 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1950 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1951 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1952 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1953 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1954 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1955 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1956 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1957 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1958 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1961 * On some chipsets we can disable the generation of legacy INTx boot
1966 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
1967 * 300641-004US, section 5.7.3.
1969 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
1970 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
1971 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
1972 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
1973 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
1974 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
1975 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
1976 * Core IO on Xeon D-1500, see Intel order no 332051-001.
1977 * Core IO on Xeon Scalable, see Intel order no 610950.
1979 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */
1980 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1982 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */
1983 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25)
1985 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1987 u16 pci_config_word;
1988 u32 pci_config_dword;
1993 switch (dev->device) {
1994 case PCI_DEVICE_ID_INTEL_ESB_10:
1995 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR,
1997 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1998 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR,
2001 case 0x3c28: /* Xeon E5 1600/2600/4600 */
2002 case 0x0e28: /* Xeon E5/E7 V2 */
2003 case 0x2f28: /* Xeon E5/E7 V3,V4 */
2004 case 0x6f28: /* Xeon D-1500 */
2005 case 0x2034: /* Xeon Scalable Family */
2006 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2008 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH;
2009 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET,
2015 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2016 dev->vendor, dev->device);
2019 * Device 29 Func 5 Device IDs of IO-APIC
2020 * containing ABAR—APIC1 Alternate Base Address Register
2022 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2023 quirk_disable_intel_boot_interrupt);
2024 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10,
2025 quirk_disable_intel_boot_interrupt);
2028 * Device 5 Func 0 Device IDs of Core IO modules/hubs
2029 * containing Coherent Interface Protocol Interrupt Control
2031 * Device IDs obtained from volume 2 datasheets of commented
2034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28,
2035 quirk_disable_intel_boot_interrupt);
2036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28,
2037 quirk_disable_intel_boot_interrupt);
2038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28,
2039 quirk_disable_intel_boot_interrupt);
2040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28,
2041 quirk_disable_intel_boot_interrupt);
2042 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034,
2043 quirk_disable_intel_boot_interrupt);
2044 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28,
2045 quirk_disable_intel_boot_interrupt);
2046 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28,
2047 quirk_disable_intel_boot_interrupt);
2048 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28,
2049 quirk_disable_intel_boot_interrupt);
2050 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28,
2051 quirk_disable_intel_boot_interrupt);
2052 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034,
2053 quirk_disable_intel_boot_interrupt);
2055 /* Disable boot interrupts on HT-1000 */
2056 #define BC_HT1000_FEATURE_REG 0x64
2057 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
2058 #define BC_HT1000_MAP_IDX 0xC00
2059 #define BC_HT1000_MAP_DATA 0xC01
2061 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
2063 u32 pci_config_dword;
2069 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
2070 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
2071 BC_HT1000_PIC_REGS_ENABLE);
2073 for (irq = 0x10; irq < 0x10 + 32; irq++) {
2074 outb(irq, BC_HT1000_MAP_IDX);
2075 outb(0x00, BC_HT1000_MAP_DATA);
2078 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
2080 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2081 dev->vendor, dev->device);
2083 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2084 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
2086 /* Disable boot interrupts on AMD and ATI chipsets */
2089 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
2090 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2091 * (due to an erratum).
2093 #define AMD_813X_MISC 0x40
2094 #define AMD_813X_NOIOAMODE (1<<0)
2095 #define AMD_813X_REV_B1 0x12
2096 #define AMD_813X_REV_B2 0x13
2098 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
2100 u32 pci_config_dword;
2104 if ((dev->revision == AMD_813X_REV_B1) ||
2105 (dev->revision == AMD_813X_REV_B2))
2108 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
2109 pci_config_dword &= ~AMD_813X_NOIOAMODE;
2110 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
2112 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2113 dev->vendor, dev->device);
2115 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2116 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2117 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2118 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
2120 #define AMD_8111_PCI_IRQ_ROUTING 0x56
2122 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
2124 u16 pci_config_word;
2129 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
2130 if (!pci_config_word) {
2131 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
2132 dev->vendor, dev->device);
2135 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
2136 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
2137 dev->vendor, dev->device);
2139 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2140 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
2141 #endif /* CONFIG_X86_IO_APIC */
2144 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2145 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
2146 * Re-allocate the region if needed...
2148 static void quirk_tc86c001_ide(struct pci_dev *dev)
2150 struct resource *r = &dev->resource[0];
2152 if (r->start & 0x8) {
2153 r->flags |= IORESOURCE_UNSET;
2158 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
2159 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
2160 quirk_tc86c001_ide);
2163 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2164 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
2165 * being read correctly if bit 7 of the base address is set.
2166 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
2167 * Re-allocate the regions to a 256-byte boundary if necessary.
2169 static void quirk_plx_pci9050(struct pci_dev *dev)
2173 /* Fixed in revision 2 (PCI 9052). */
2174 if (dev->revision >= 2)
2176 for (bar = 0; bar <= 1; bar++)
2177 if (pci_resource_len(dev, bar) == 0x80 &&
2178 (pci_resource_start(dev, bar) & 0x80)) {
2179 struct resource *r = &dev->resource[bar];
2180 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
2182 r->flags |= IORESOURCE_UNSET;
2187 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2190 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
2191 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2192 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
2193 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
2195 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
2198 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
2199 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
2201 static void quirk_netmos(struct pci_dev *dev)
2203 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
2204 unsigned int num_serial = dev->subsystem_device & 0xf;
2207 * These Netmos parts are multiport serial devices with optional
2208 * parallel ports. Even when parallel ports are present, they
2209 * are identified as class SERIAL, which means the serial driver
2210 * will claim them. To prevent this, mark them as class OTHER.
2211 * These combo devices should be claimed by parport_serial.
2213 * The subdevice ID is of the form 0x00PS, where <P> is the number
2214 * of parallel ports and <S> is the number of serial ports.
2216 switch (dev->device) {
2217 case PCI_DEVICE_ID_NETMOS_9835:
2218 /* Well, this rule doesn't hold for the following 9835 device */
2219 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
2220 dev->subsystem_device == 0x0299)
2223 case PCI_DEVICE_ID_NETMOS_9735:
2224 case PCI_DEVICE_ID_NETMOS_9745:
2225 case PCI_DEVICE_ID_NETMOS_9845:
2226 case PCI_DEVICE_ID_NETMOS_9855:
2228 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
2229 dev->device, num_parallel, num_serial);
2230 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
2231 (dev->class & 0xff);
2235 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
2236 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
2238 static void quirk_e100_interrupt(struct pci_dev *dev)
2244 switch (dev->device) {
2245 /* PCI IDs taken from drivers/net/e100.c */
2247 case 0x1030 ... 0x1034:
2248 case 0x1038 ... 0x103E:
2249 case 0x1050 ... 0x1057:
2251 case 0x1064 ... 0x106B:
2252 case 0x1091 ... 0x1095:
2265 * Some firmware hands off the e100 with interrupts enabled,
2266 * which can cause a flood of interrupts if packets are
2267 * received before the driver attaches to the device. So
2268 * disable all e100 interrupts here. The driver will
2269 * re-enable them when it's ready.
2271 pci_read_config_word(dev, PCI_COMMAND, &command);
2273 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2277 * Check that the device is in the D0 power state. If it's not,
2278 * there is no point to look any further.
2281 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2282 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2286 /* Convert from PCI bus to resource space. */
2287 csr = ioremap(pci_resource_start(dev, 0), 8);
2289 pci_warn(dev, "Can't map e100 registers\n");
2293 cmd_hi = readb(csr + 3);
2295 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2301 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2302 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2305 * The 82575 and 82598 may experience data corruption issues when transitioning
2306 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2308 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2310 pci_info(dev, "Disabling L0s\n");
2311 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2313 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2314 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2315 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2316 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2317 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2318 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2319 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2320 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2321 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2323 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2328 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev)
2330 pci_info(dev, "Disabling ASPM L0s/L1\n");
2331 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
2335 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2336 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2337 * disable both L0s and L1 for now to be safe.
2339 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1);
2342 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2343 * Link bit cleared after starting the link retrain process to allow this
2344 * process to finish.
2346 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the
2347 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf.
2349 static void quirk_enable_clear_retrain_link(struct pci_dev *dev)
2351 dev->clear_retrain_link = 1;
2352 pci_info(dev, "Enable PCIe Retrain Link quirk\n");
2354 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link);
2355 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link);
2356 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link);
2358 static void fixup_rev1_53c810(struct pci_dev *dev)
2360 u32 class = dev->class;
2363 * rev 1 ncr53c810 chips don't set the class at all which means
2364 * they don't get their resources remapped. Fix that here.
2369 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2370 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2373 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2375 /* Enable 1k I/O space granularity on the Intel P64H2 */
2376 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2380 pci_read_config_word(dev, 0x40, &en1k);
2383 pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2384 dev->io_window_1k = 1;
2387 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2390 * Under some circumstances, AER is not linked with extended capabilities.
2391 * Force it to be linked by setting the corresponding control bit in the
2394 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2398 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2400 pci_write_config_byte(dev, 0xf41, b | 0x20);
2401 pci_info(dev, "Linking AER extended capability\n");
2405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2406 quirk_nvidia_ck804_pcie_aer_ext_cap);
2407 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2408 quirk_nvidia_ck804_pcie_aer_ext_cap);
2410 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2413 * Disable PCI Bus Parking and PCI Master read caching on CX700
2414 * which causes unspecified timing errors with a VT6212L on the PCI
2415 * bus leading to USB2.0 packet loss.
2417 * This quirk is only enabled if a second (on the external PCI bus)
2418 * VT6212L is found -- the CX700 core itself also contains a USB
2419 * host controller with the same PCI ID as the VT6212L.
2422 /* Count VT6212L instances */
2423 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2424 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2428 * p should contain the first (internal) VT6212L -- see if we have
2429 * an external one by searching again.
2431 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2436 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2438 /* Turn off PCI Bus Parking */
2439 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2441 pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2445 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2447 /* Turn off PCI Master read caching */
2448 pci_write_config_byte(dev, 0x72, 0x0);
2450 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2451 pci_write_config_byte(dev, 0x75, 0x1);
2453 /* Disable "Read FIFO Timer" */
2454 pci_write_config_byte(dev, 0x77, 0x0);
2456 pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2460 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2462 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2466 pci_read_config_dword(dev, 0xf4, &rev);
2468 /* Only CAP the MRRS if the device is a 5719 A0 */
2469 if (rev == 0x05719000) {
2470 int readrq = pcie_get_readrq(dev);
2472 pcie_set_readrq(dev, 2048);
2475 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2476 PCI_DEVICE_ID_TIGON3_5719,
2477 quirk_brcm_5719_limit_mrrs);
2480 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to
2481 * hide device 6 which configures the overflow device access containing the
2482 * DRBs - this is where we expose device 6.
2483 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2485 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2489 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2490 pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2491 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2494 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2495 quirk_unhide_mch_dev6);
2496 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2497 quirk_unhide_mch_dev6);
2499 #ifdef CONFIG_PCI_MSI
2501 * Some chipsets do not support MSI. We cannot easily rely on setting
2502 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some
2503 * other buses controlled by the chipset even if Linux is not aware of it.
2504 * Instead of setting the flag on all buses in the machine, simply disable
2507 static void quirk_disable_all_msi(struct pci_dev *dev)
2510 pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2512 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2513 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2514 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2515 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2516 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2517 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2518 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2519 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2520 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi);
2522 /* Disable MSI on chipsets that are known to not support it */
2523 static void quirk_disable_msi(struct pci_dev *dev)
2525 if (dev->subordinate) {
2526 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2527 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2530 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2531 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2532 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2535 * The APC bridge device in AMD 780 family northbridges has some random
2536 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2537 * we use the possible vendor/device IDs of the host bridge for the
2538 * declared quirk, and search for the APC bridge by slot number.
2540 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2542 struct pci_dev *apc_bridge;
2544 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2546 if (apc_bridge->device == 0x9602)
2547 quirk_disable_msi(apc_bridge);
2548 pci_dev_put(apc_bridge);
2551 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2552 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2555 * Go through the list of HyperTransport capabilities and return 1 if a HT
2556 * MSI capability is found and enabled.
2558 static int msi_ht_cap_enabled(struct pci_dev *dev)
2560 int pos, ttl = PCI_FIND_CAP_TTL;
2562 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2563 while (pos && ttl--) {
2566 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2568 pci_info(dev, "Found %s HT MSI Mapping\n",
2569 flags & HT_MSI_FLAGS_ENABLE ?
2570 "enabled" : "disabled");
2571 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2574 pos = pci_find_next_ht_capability(dev, pos,
2575 HT_CAPTYPE_MSI_MAPPING);
2580 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */
2581 static void quirk_msi_ht_cap(struct pci_dev *dev)
2583 if (!msi_ht_cap_enabled(dev))
2584 quirk_disable_msi(dev);
2586 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2590 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported
2591 * if the MSI capability is set in any of these mappings.
2593 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2595 struct pci_dev *pdev;
2598 * Check HT MSI cap on this chipset and the root one. A single one
2599 * having MSI is enough to be sure that MSI is supported.
2601 pdev = pci_get_slot(dev->bus, 0);
2604 if (!msi_ht_cap_enabled(pdev))
2605 quirk_msi_ht_cap(dev);
2608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2609 quirk_nvidia_ck804_msi_ht_cap);
2611 /* Force enable MSI mapping capability on HT bridges */
2612 static void ht_enable_msi_mapping(struct pci_dev *dev)
2614 int pos, ttl = PCI_FIND_CAP_TTL;
2616 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2617 while (pos && ttl--) {
2620 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2622 pci_info(dev, "Enabling HT MSI Mapping\n");
2624 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2625 flags | HT_MSI_FLAGS_ENABLE);
2627 pos = pci_find_next_ht_capability(dev, pos,
2628 HT_CAPTYPE_MSI_MAPPING);
2631 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2632 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2633 ht_enable_msi_mapping);
2634 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2635 ht_enable_msi_mapping);
2638 * The P5N32-SLI motherboards from Asus have a problem with MSI
2639 * for the MCP55 NIC. It is not yet determined whether the MSI problem
2640 * also affects other devices. As for now, turn off MSI for this device.
2642 static void nvenet_msi_disable(struct pci_dev *dev)
2644 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2647 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2648 strstr(board_name, "P5N32-E SLI"))) {
2649 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2653 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2654 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2655 nvenet_msi_disable);
2658 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2659 * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
2660 * generate MSI interrupts for PME and AER events instead only INTx interrupts
2661 * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
2662 * for other events, since PCIe specificiation doesn't support using a mix of
2663 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2664 * service drivers registering their respective ISRs for MSIs.
2666 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
2670 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
2671 PCI_CLASS_BRIDGE_PCI, 8,
2672 pci_quirk_nvidia_tegra_disable_rp_msi);
2673 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
2674 PCI_CLASS_BRIDGE_PCI, 8,
2675 pci_quirk_nvidia_tegra_disable_rp_msi);
2676 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
2677 PCI_CLASS_BRIDGE_PCI, 8,
2678 pci_quirk_nvidia_tegra_disable_rp_msi);
2679 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
2680 PCI_CLASS_BRIDGE_PCI, 8,
2681 pci_quirk_nvidia_tegra_disable_rp_msi);
2682 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
2683 PCI_CLASS_BRIDGE_PCI, 8,
2684 pci_quirk_nvidia_tegra_disable_rp_msi);
2685 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
2686 PCI_CLASS_BRIDGE_PCI, 8,
2687 pci_quirk_nvidia_tegra_disable_rp_msi);
2688 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
2689 PCI_CLASS_BRIDGE_PCI, 8,
2690 pci_quirk_nvidia_tegra_disable_rp_msi);
2691 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
2692 PCI_CLASS_BRIDGE_PCI, 8,
2693 pci_quirk_nvidia_tegra_disable_rp_msi);
2694 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
2695 PCI_CLASS_BRIDGE_PCI, 8,
2696 pci_quirk_nvidia_tegra_disable_rp_msi);
2697 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
2698 PCI_CLASS_BRIDGE_PCI, 8,
2699 pci_quirk_nvidia_tegra_disable_rp_msi);
2700 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
2701 PCI_CLASS_BRIDGE_PCI, 8,
2702 pci_quirk_nvidia_tegra_disable_rp_msi);
2703 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
2704 PCI_CLASS_BRIDGE_PCI, 8,
2705 pci_quirk_nvidia_tegra_disable_rp_msi);
2706 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
2707 PCI_CLASS_BRIDGE_PCI, 8,
2708 pci_quirk_nvidia_tegra_disable_rp_msi);
2711 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2712 * config register. This register controls the routing of legacy
2713 * interrupts from devices that route through the MCP55. If this register
2714 * is misprogrammed, interrupts are only sent to the BSP, unlike
2715 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2716 * having this register set properly prevents kdump from booting up
2717 * properly, so let's make sure that we have it set correctly.
2718 * Note that this is an undocumented register.
2720 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2724 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2727 pci_read_config_dword(dev, 0x74, &cfg);
2729 if (cfg & ((1 << 2) | (1 << 15))) {
2730 pr_info("Rewriting IRQ routing register on MCP55\n");
2731 cfg &= ~((1 << 2) | (1 << 15));
2732 pci_write_config_dword(dev, 0x74, cfg);
2735 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2736 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2737 nvbridge_check_legacy_irq_routing);
2738 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2739 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2740 nvbridge_check_legacy_irq_routing);
2742 static int ht_check_msi_mapping(struct pci_dev *dev)
2744 int pos, ttl = PCI_FIND_CAP_TTL;
2747 /* Check if there is HT MSI cap or enabled on this device */
2748 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2749 while (pos && ttl--) {
2754 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2756 if (flags & HT_MSI_FLAGS_ENABLE) {
2763 pos = pci_find_next_ht_capability(dev, pos,
2764 HT_CAPTYPE_MSI_MAPPING);
2770 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2772 struct pci_dev *dev;
2777 dev_no = host_bridge->devfn >> 3;
2778 for (i = dev_no + 1; i < 0x20; i++) {
2779 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2783 /* found next host bridge? */
2784 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2790 if (ht_check_msi_mapping(dev)) {
2801 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2802 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2804 static int is_end_of_ht_chain(struct pci_dev *dev)
2810 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2815 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2817 ctrl_off = ((flags >> 10) & 1) ?
2818 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2819 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2821 if (ctrl & (1 << 6))
2828 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2830 struct pci_dev *host_bridge;
2835 dev_no = dev->devfn >> 3;
2836 for (i = dev_no; i >= 0; i--) {
2837 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2841 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2846 pci_dev_put(host_bridge);
2852 /* don't enable end_device/host_bridge with leaf directly here */
2853 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2854 host_bridge_with_leaf(host_bridge))
2857 /* root did that ! */
2858 if (msi_ht_cap_enabled(host_bridge))
2861 ht_enable_msi_mapping(dev);
2864 pci_dev_put(host_bridge);
2867 static void ht_disable_msi_mapping(struct pci_dev *dev)
2869 int pos, ttl = PCI_FIND_CAP_TTL;
2871 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2872 while (pos && ttl--) {
2875 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2877 pci_info(dev, "Disabling HT MSI Mapping\n");
2879 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2880 flags & ~HT_MSI_FLAGS_ENABLE);
2882 pos = pci_find_next_ht_capability(dev, pos,
2883 HT_CAPTYPE_MSI_MAPPING);
2887 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2889 struct pci_dev *host_bridge;
2893 if (!pci_msi_enabled())
2896 /* check if there is HT MSI cap or enabled on this device */
2897 found = ht_check_msi_mapping(dev);
2904 * HT MSI mapping should be disabled on devices that are below
2905 * a non-Hypertransport host bridge. Locate the host bridge...
2907 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2909 if (host_bridge == NULL) {
2910 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2914 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2916 /* Host bridge is to HT */
2918 /* it is not enabled, try to enable it */
2920 ht_enable_msi_mapping(dev);
2922 nv_ht_enable_msi_mapping(dev);
2927 /* HT MSI is not enabled */
2931 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2932 ht_disable_msi_mapping(dev);
2935 pci_dev_put(host_bridge);
2938 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2940 return __nv_msi_ht_cap_quirk(dev, 1);
2942 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2943 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2945 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2947 return __nv_msi_ht_cap_quirk(dev, 0);
2949 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2950 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2952 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2954 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2957 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2962 * SB700 MSI issue will be fixed at HW level from revision A21;
2963 * we need check PCI REVISION ID of SMBus controller to get SB700
2966 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2971 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2972 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2976 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2978 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2979 if (dev->revision < 0x18) {
2980 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
2981 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2984 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2985 PCI_DEVICE_ID_TIGON3_5780,
2986 quirk_msi_intx_disable_bug);
2987 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2988 PCI_DEVICE_ID_TIGON3_5780S,
2989 quirk_msi_intx_disable_bug);
2990 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2991 PCI_DEVICE_ID_TIGON3_5714,
2992 quirk_msi_intx_disable_bug);
2993 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2994 PCI_DEVICE_ID_TIGON3_5714S,
2995 quirk_msi_intx_disable_bug);
2996 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2997 PCI_DEVICE_ID_TIGON3_5715,
2998 quirk_msi_intx_disable_bug);
2999 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
3000 PCI_DEVICE_ID_TIGON3_5715S,
3001 quirk_msi_intx_disable_bug);
3003 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
3004 quirk_msi_intx_disable_ati_bug);
3005 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
3006 quirk_msi_intx_disable_ati_bug);
3007 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
3008 quirk_msi_intx_disable_ati_bug);
3009 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
3010 quirk_msi_intx_disable_ati_bug);
3011 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
3012 quirk_msi_intx_disable_ati_bug);
3014 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
3015 quirk_msi_intx_disable_bug);
3016 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
3017 quirk_msi_intx_disable_bug);
3018 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
3019 quirk_msi_intx_disable_bug);
3021 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
3022 quirk_msi_intx_disable_bug);
3023 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
3024 quirk_msi_intx_disable_bug);
3025 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
3026 quirk_msi_intx_disable_bug);
3027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
3028 quirk_msi_intx_disable_bug);
3029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
3030 quirk_msi_intx_disable_bug);
3031 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
3032 quirk_msi_intx_disable_bug);
3033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
3034 quirk_msi_intx_disable_qca_bug);
3035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
3036 quirk_msi_intx_disable_qca_bug);
3037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
3038 quirk_msi_intx_disable_qca_bug);
3039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
3040 quirk_msi_intx_disable_qca_bug);
3041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
3042 quirk_msi_intx_disable_qca_bug);
3045 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3046 * should be disabled on platforms where the device (mistakenly) advertises it.
3048 * Notice that this quirk also disables MSI (which may work, but hasn't been
3049 * tested), since currently there is no standard way to disable only MSI-X.
3051 * The 0031 device id is reused for other non Root Port device types,
3052 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
3054 static void quirk_al_msi_disable(struct pci_dev *dev)
3057 pci_warn(dev, "Disabling MSI/MSI-X\n");
3059 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
3060 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
3061 #endif /* CONFIG_PCI_MSI */
3064 * Allow manual resource allocation for PCI hotplug bridges via
3065 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3066 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to
3067 * allocate resources when hotplug device is inserted and PCI bus is
3070 static void quirk_hotplug_bridge(struct pci_dev *dev)
3072 dev->is_hotplug_bridge = 1;
3074 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
3077 * This is a quirk for the Ricoh MMC controller found as a part of some
3078 * multifunction chips.
3080 * This is very similar and based on the ricoh_mmc driver written by
3081 * Philip Langdale. Thank you for these magic sequences.
3083 * These chips implement the four main memory card controllers (SD, MMC,
3084 * MS, xD) and one or both of CardBus or FireWire.
3086 * It happens that they implement SD and MMC support as separate
3087 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3088 * cards but the chip detects MMC cards in hardware and directs them to the
3089 * MMC controller - so the SDHCI driver never sees them.
3091 * To get around this, we must disable the useless MMC controller. At that
3092 * point, the SDHCI controller will start seeing them. It seems to be the
3093 * case that the relevant PCI registers to deactivate the MMC controller
3094 * live on PCI function 0, which might be the CardBus controller or the
3095 * FireWire controller, depending on the particular chip in question
3097 * This has to be done early, because as soon as we disable the MMC controller
3098 * other PCI functions shift up one level, e.g. function #2 becomes function
3099 * #1, and this will confuse the PCI core.
3101 #ifdef CONFIG_MMC_RICOH_MMC
3102 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
3109 * Disable via CardBus interface
3111 * This must be done via function #0
3113 if (PCI_FUNC(dev->devfn))
3116 pci_read_config_byte(dev, 0xB7, &disable);
3120 pci_read_config_byte(dev, 0x8E, &write_enable);
3121 pci_write_config_byte(dev, 0x8E, 0xAA);
3122 pci_read_config_byte(dev, 0x8D, &write_target);
3123 pci_write_config_byte(dev, 0x8D, 0xB7);
3124 pci_write_config_byte(dev, 0xB7, disable | 0x02);
3125 pci_write_config_byte(dev, 0x8E, write_enable);
3126 pci_write_config_byte(dev, 0x8D, write_target);
3128 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n");
3129 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3131 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3132 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
3134 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
3140 * Disable via FireWire interface
3142 * This must be done via function #0
3144 if (PCI_FUNC(dev->devfn))
3147 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
3148 * certain types of SD/MMC cards. Lowering the SD base clock
3149 * frequency from 200Mhz to 50Mhz fixes this issue.
3151 * 0x150 - SD2.0 mode enable for changing base clock
3152 * frequency to 50Mhz
3153 * 0xe1 - Base clock frequency
3154 * 0x32 - 50Mhz new clock frequency
3155 * 0xf9 - Key register for 0x150
3156 * 0xfc - key register for 0xe1
3158 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
3159 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
3160 pci_write_config_byte(dev, 0xf9, 0xfc);
3161 pci_write_config_byte(dev, 0x150, 0x10);
3162 pci_write_config_byte(dev, 0xf9, 0x00);
3163 pci_write_config_byte(dev, 0xfc, 0x01);
3164 pci_write_config_byte(dev, 0xe1, 0x32);
3165 pci_write_config_byte(dev, 0xfc, 0x00);
3167 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
3170 pci_read_config_byte(dev, 0xCB, &disable);
3175 pci_read_config_byte(dev, 0xCA, &write_enable);
3176 pci_write_config_byte(dev, 0xCA, 0x57);
3177 pci_write_config_byte(dev, 0xCB, disable | 0x02);
3178 pci_write_config_byte(dev, 0xCA, write_enable);
3180 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n");
3181 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
3184 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3185 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
3186 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3187 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
3188 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3189 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
3190 #endif /*CONFIG_MMC_RICOH_MMC*/
3192 #ifdef CONFIG_DMAR_TABLE
3193 #define VTUNCERRMSK_REG 0x1ac
3194 #define VTD_MSK_SPEC_ERRORS (1 << 31)
3196 * This is a quirk for masking VT-d spec-defined errors to platform error
3197 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets
3198 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
3199 * on the RAS config settings of the platform) when a VT-d fault happens.
3200 * The resulting SMI caused the system to hang.
3202 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3203 * need to report the same error through other channels.
3205 static void vtd_mask_spec_errors(struct pci_dev *dev)
3209 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
3210 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
3212 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
3213 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
3216 static void fixup_ti816x_class(struct pci_dev *dev)
3218 u32 class = dev->class;
3220 /* TI 816x devices do not have class code set when in PCIe boot mode */
3221 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
3222 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
3225 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
3226 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
3229 * Some PCIe devices do not work reliably with the claimed maximum
3230 * payload size supported.
3232 static void fixup_mpss_256(struct pci_dev *dev)
3234 dev->pcie_mpss = 1; /* 256 bytes */
3236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3237 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3238 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3239 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3241 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3244 * Intel 5000 and 5100 Memory controllers have an erratum with read completion
3245 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3246 * Since there is no way of knowing what the PCIe MPS on each fabric will be
3247 * until all of the devices are discovered and buses walked, read completion
3248 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3249 * it is possible to hotplug a device with MPS of 256B.
3251 static void quirk_intel_mc_errata(struct pci_dev *dev)
3256 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3257 pcie_bus_config == PCIE_BUS_DEFAULT)
3261 * Intel erratum specifies bits to change but does not say what
3262 * they are. Keeping them magical until such time as the registers
3263 * and values can be explained.
3265 err = pci_read_config_word(dev, 0x48, &rcc);
3267 pci_err(dev, "Error attempting to read the read completion coalescing register\n");
3271 if (!(rcc & (1 << 10)))
3276 err = pci_write_config_word(dev, 0x48, rcc);
3278 pci_err(dev, "Error attempting to write the read completion coalescing register\n");
3282 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n");
3284 /* Intel 5000 series memory controllers and ports 2-7 */
3285 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3293 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3294 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3295 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3296 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3297 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3298 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3299 /* Intel 5100 series memory controllers and ports 2-7 */
3300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3303 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3305 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3309 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3313 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
3314 * To work around this, query the size it should be configured to by the
3315 * device and modify the resource end to correspond to this new size.
3317 static void quirk_intel_ntb(struct pci_dev *dev)
3322 rc = pci_read_config_byte(dev, 0x00D0, &val);
3326 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3328 rc = pci_read_config_byte(dev, 0x00D1, &val);
3332 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3338 * Some BIOS implementations leave the Intel GPU interrupts enabled, even
3339 * though no one is handling them (e.g., if the i915 driver is never
3340 * loaded). Additionally the interrupt destination is not set up properly
3341 * and the interrupt ends up -somewhere-.
3343 * These spurious interrupts are "sticky" and the kernel disables the
3344 * (shared) interrupt line after 100,000+ generated interrupts.
3346 * Fix it by disabling the still enabled interrupts. This resolves crashes
3347 * often seen on monitor unplug.
3349 #define I915_DEIER_REG 0x4400c
3350 static void disable_igfx_irq(struct pci_dev *dev)
3352 void __iomem *regs = pci_iomap(dev, 0, 0);
3354 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3358 /* Check if any interrupt line is still enabled */
3359 if (readl(regs + I915_DEIER_REG) != 0) {
3360 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3362 writel(0, regs + I915_DEIER_REG);
3365 pci_iounmap(dev, regs);
3367 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3368 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3369 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
3370 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3371 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
3372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3376 * PCI devices which are on Intel chips can skip the 10ms delay
3377 * before entering D3 mode.
3379 static void quirk_remove_d3hot_delay(struct pci_dev *dev)
3381 dev->d3hot_delay = 0;
3383 /* C600 Series devices do not need 10ms d3hot_delay */
3384 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay);
3385 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay);
3386 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay);
3387 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3388 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay);
3389 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay);
3390 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay);
3391 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay);
3392 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay);
3393 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay);
3394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay);
3395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay);
3396 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay);
3397 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay);
3398 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay);
3399 /* Intel Cherrytrail devices do not need 10ms d3hot_delay */
3400 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay);
3401 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay);
3402 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay);
3403 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay);
3404 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay);
3405 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay);
3406 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay);
3407 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay);
3408 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay);
3411 * Some devices may pass our check in pci_intx_mask_supported() if
3412 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3413 * support this feature.
3415 static void quirk_broken_intx_masking(struct pci_dev *dev)
3417 dev->broken_intx_masking = 1;
3419 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3420 quirk_broken_intx_masking);
3421 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3422 quirk_broken_intx_masking);
3423 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
3424 quirk_broken_intx_masking);
3427 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3428 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3430 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3432 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3433 quirk_broken_intx_masking);
3436 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3437 * DisINTx can be set but the interrupt status bit is non-functional.
3439 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking);
3440 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking);
3441 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking);
3442 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking);
3443 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking);
3444 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking);
3445 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking);
3446 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking);
3447 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking);
3448 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking);
3449 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking);
3450 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking);
3451 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking);
3452 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking);
3453 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking);
3454 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking);
3456 static u16 mellanox_broken_intx_devs[] = {
3457 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3458 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3459 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3460 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3461 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3462 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3463 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3464 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3465 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3466 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3467 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3468 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3469 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3470 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3473 #define CONNECTX_4_CURR_MAX_MINOR 99
3474 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3477 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3478 * If so, don't mark it as broken.
3479 * FW minor > 99 means older FW version format and no INTx masking support.
3480 * FW minor < 14 means new FW version format and no INTx masking support.
3482 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3484 __be32 __iomem *fw_ver;
3492 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3493 if (pdev->device == mellanox_broken_intx_devs[i]) {
3494 pdev->broken_intx_masking = 1;
3500 * Getting here means Connect-IB cards and up. Connect-IB has no INTx
3501 * support so shouldn't be checked further
3503 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3506 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3507 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3510 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3511 if (pci_enable_device_mem(pdev)) {
3512 pci_warn(pdev, "Can't enable device memory\n");
3516 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3518 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3522 /* Reading from resource space should be 32b aligned */
3523 fw_maj_min = ioread32be(fw_ver);
3524 fw_sub_min = ioread32be(fw_ver + 1);
3525 fw_major = fw_maj_min & 0xffff;
3526 fw_minor = fw_maj_min >> 16;
3527 fw_subminor = fw_sub_min & 0xffff;
3528 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3529 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3530 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3531 fw_major, fw_minor, fw_subminor, pdev->device ==
3532 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3533 pdev->broken_intx_masking = 1;
3539 pci_disable_device(pdev);
3541 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3542 mellanox_check_broken_intx_masking);
3544 static void quirk_no_bus_reset(struct pci_dev *dev)
3546 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3550 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
3551 * prevented for those affected devices.
3553 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
3555 if ((dev->device & 0xffc0) == 0x2340)
3556 quirk_no_bus_reset(dev);
3558 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
3559 quirk_nvidia_no_bus_reset);
3562 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3563 * The device will throw a Link Down error on AER-capable systems and
3564 * regardless of AER, config space of the device is never accessible again
3565 * and typically causes the system to hang or reset when access is attempted.
3566 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
3568 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3569 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3570 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3571 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3572 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
3575 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3576 * reset when used with certain child devices. After the reset, config
3577 * accesses to the child may fail.
3579 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3582 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS
3583 * automatically disables LTSSM when Secondary Bus Reset is received and
3584 * the device stops working. Prevent bus reset for these devices. With
3585 * this change, the device can be assigned to VMs with VFIO, but it will
3586 * leak state between VMs. Reference
3587 * https://e2e.ti.com/support/processors/f/791/t/954382
3589 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset);
3591 static void quirk_no_pm_reset(struct pci_dev *dev)
3594 * We can't do a bus reset on root bus devices, but an ineffective
3595 * PM reset may be better than nothing.
3597 if (!pci_is_root_bus(dev->bus))
3598 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3602 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3603 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3604 * to have no effect on the device: it retains the framebuffer contents and
3605 * monitor sync. Advertising this support makes other layers, like VFIO,
3606 * assume pci_reset_function() is viable for this device. Mark it as
3607 * unavailable to skip it when testing reset methods.
3609 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3610 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3613 * Thunderbolt controllers with broken MSI hotplug signaling:
3614 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3615 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3617 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3619 if (pdev->is_hotplug_bridge &&
3620 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3621 pdev->revision <= 1))
3624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3625 quirk_thunderbolt_hotplug_msi);
3626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3627 quirk_thunderbolt_hotplug_msi);
3628 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3629 quirk_thunderbolt_hotplug_msi);
3630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3631 quirk_thunderbolt_hotplug_msi);
3632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3633 quirk_thunderbolt_hotplug_msi);
3637 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3639 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3640 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3641 * be present after resume if a device was plugged in before suspend.
3643 * The Thunderbolt controller consists of a PCIe switch with downstream
3644 * bridges leading to the NHI and to the tunnel PCI bridges.
3646 * This quirk cuts power to the whole chip. Therefore we have to apply it
3647 * during suspend_noirq of the upstream bridge.
3649 * Power is automagically restored before resume. No action is needed.
3651 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3653 acpi_handle bridge, SXIO, SXFP, SXLV;
3655 if (!x86_apple_machine)
3657 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3659 bridge = ACPI_HANDLE(&dev->dev);
3664 * SXIO and SXLV are present only on machines requiring this quirk.
3665 * Thunderbolt bridges in external devices might have the same
3666 * device ID as those on the host, but they will not have the
3667 * associated ACPI methods. This implicitly checks that we are at
3670 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3671 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3672 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3674 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n");
3676 /* magic sequence */
3677 acpi_execute_simple_method(SXIO, NULL, 1);
3678 acpi_execute_simple_method(SXFP, NULL, 0);
3680 acpi_execute_simple_method(SXLV, NULL, 0);
3681 acpi_execute_simple_method(SXIO, NULL, 0);
3682 acpi_execute_simple_method(SXLV, NULL, 0);
3684 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3685 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3686 quirk_apple_poweroff_thunderbolt);
3690 * Following are device-specific reset methods which can be used to
3691 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3694 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3697 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3699 * The 82599 supports FLR on VFs, but FLR support is reported only
3700 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3701 * Thus we must call pcie_flr() directly without first checking if it is
3709 #define SOUTH_CHICKEN2 0xc2004
3710 #define PCH_PP_STATUS 0xc7200
3711 #define PCH_PP_CONTROL 0xc7204
3712 #define MSG_CTL 0x45010
3713 #define NSDE_PWR_STATE 0xd0100
3714 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3716 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3718 void __iomem *mmio_base;
3719 unsigned long timeout;
3725 mmio_base = pci_iomap(dev, 0, 0);
3729 iowrite32(0x00000002, mmio_base + MSG_CTL);
3732 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3733 * driver loaded sets the right bits. However, this's a reset and
3734 * the bits have been set by i915 previously, so we clobber
3735 * SOUTH_CHICKEN2 register directly here.
3737 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3739 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3740 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3742 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3744 val = ioread32(mmio_base + PCH_PP_STATUS);
3745 if ((val & 0xb0000000) == 0)
3746 goto reset_complete;
3748 } while (time_before(jiffies, timeout));
3749 pci_warn(dev, "timeout during reset\n");
3752 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3754 pci_iounmap(dev, mmio_base);
3758 /* Device-specific reset method for Chelsio T4-based adapters */
3759 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3765 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3766 * that we have no device-specific reset method.
3768 if ((dev->device & 0xf000) != 0x4000)
3772 * If this is the "probe" phase, return 0 indicating that we can
3773 * reset this device.
3779 * T4 can wedge if there are DMAs in flight within the chip and Bus
3780 * Master has been disabled. We need to have it on till the Function
3781 * Level Reset completes. (BUS_MASTER is disabled in
3782 * pci_reset_function()).
3784 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3785 pci_write_config_word(dev, PCI_COMMAND,
3786 old_command | PCI_COMMAND_MASTER);
3789 * Perform the actual device function reset, saving and restoring
3790 * configuration information around the reset.
3792 pci_save_state(dev);
3795 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3796 * are disabled when an MSI-X interrupt message needs to be delivered.
3797 * So we briefly re-enable MSI-X interrupts for the duration of the
3798 * FLR. The pci_restore_state() below will restore the original
3801 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3802 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3803 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3805 PCI_MSIX_FLAGS_ENABLE |
3806 PCI_MSIX_FLAGS_MASKALL);
3811 * Restore the configuration information (BAR values, etc.) including
3812 * the original PCI Configuration Space Command word, and return
3815 pci_restore_state(dev);
3816 pci_write_config_word(dev, PCI_COMMAND, old_command);
3820 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3821 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3822 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3825 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after
3826 * FLR where config space reads from the device return -1. We seem to be
3827 * able to avoid this condition if we disable the NVMe controller prior to
3828 * FLR. This quirk is generic for any NVMe class device requiring similar
3829 * assistance to quiesce the device prior to FLR.
3831 * NVMe specification: https://nvmexpress.org/resources/specifications/
3833 * Chapter 2: Required and optional PCI config registers
3834 * Chapter 3: NVMe control registers
3835 * Chapter 7.3: Reset behavior
3837 static int nvme_disable_and_flr(struct pci_dev *dev, int probe)
3843 if (dev->class != PCI_CLASS_STORAGE_EXPRESS ||
3844 !pcie_has_flr(dev) || !pci_resource_start(dev, 0))
3850 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg));
3854 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3855 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY);
3857 cfg = readl(bar + NVME_REG_CC);
3859 /* Disable controller if enabled */
3860 if (cfg & NVME_CC_ENABLE) {
3861 u32 cap = readl(bar + NVME_REG_CAP);
3862 unsigned long timeout;
3865 * Per nvme_disable_ctrl() skip shutdown notification as it
3866 * could complete commands to the admin queue. We only intend
3867 * to quiesce the device before reset.
3869 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE);
3871 writel(cfg, bar + NVME_REG_CC);
3874 * Some controllers require an additional delay here, see
3875 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet
3876 * supported by this quirk.
3879 /* Cap register provides max timeout in 500ms increments */
3880 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
3883 u32 status = readl(bar + NVME_REG_CSTS);
3885 /* Ready status becomes zero on disable complete */
3886 if (!(status & NVME_CSTS_RDY))
3891 if (time_after(jiffies, timeout)) {
3892 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n");
3898 pci_iounmap(dev, bar);
3906 * Intel DC P3700 NVMe controller will timeout waiting for ready status
3907 * to change after NVMe enable if the driver starts interacting with the
3908 * device too soon after FLR. A 250ms delay after FLR has heuristically
3909 * proven to produce reliably working results for device assignment cases.
3911 static int delay_250ms_after_flr(struct pci_dev *dev, int probe)
3913 if (!pcie_has_flr(dev))
3926 #define PCI_DEVICE_ID_HINIC_VF 0x375E
3927 #define HINIC_VF_FLR_TYPE 0x1000
3928 #define HINIC_VF_FLR_CAP_BIT (1UL << 30)
3929 #define HINIC_VF_OP 0xE80
3930 #define HINIC_VF_FLR_PROC_BIT (1UL << 18)
3931 #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */
3933 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
3934 static int reset_hinic_vf_dev(struct pci_dev *pdev, int probe)
3936 unsigned long timeout;
3943 bar = pci_iomap(pdev, 0, 0);
3947 /* Get and check firmware capabilities */
3948 val = ioread32be(bar + HINIC_VF_FLR_TYPE);
3949 if (!(val & HINIC_VF_FLR_CAP_BIT)) {
3950 pci_iounmap(pdev, bar);
3954 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */
3955 val = ioread32be(bar + HINIC_VF_OP);
3956 val = val | HINIC_VF_FLR_PROC_BIT;
3957 iowrite32be(val, bar + HINIC_VF_OP);
3962 * The device must recapture its Bus and Device Numbers after FLR
3963 * in order generate Completions. Issue a config write to let the
3964 * device capture this information.
3966 pci_write_config_word(pdev, PCI_VENDOR_ID, 0);
3968 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */
3969 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT);
3971 val = ioread32be(bar + HINIC_VF_OP);
3972 if (!(val & HINIC_VF_FLR_PROC_BIT))
3973 goto reset_complete;
3975 } while (time_before(jiffies, timeout));
3977 val = ioread32be(bar + HINIC_VF_OP);
3978 if (!(val & HINIC_VF_FLR_PROC_BIT))
3979 goto reset_complete;
3981 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val);
3984 pci_iounmap(pdev, bar);
3989 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3990 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3991 reset_intel_82599_sfp_virtfn },
3992 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3994 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3996 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr },
3997 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr },
3998 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr },
3999 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4000 reset_chelsio_generic_dev },
4001 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF,
4002 reset_hinic_vf_dev },
4007 * These device-specific reset methods are here rather than in a driver
4008 * because when a host assigns a device to a guest VM, the host may need
4009 * to reset the device but probably doesn't have a driver for it.
4011 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
4013 const struct pci_dev_reset_methods *i;
4015 for (i = pci_dev_reset_methods; i->reset; i++) {
4016 if ((i->vendor == dev->vendor ||
4017 i->vendor == (u16)PCI_ANY_ID) &&
4018 (i->device == dev->device ||
4019 i->device == (u16)PCI_ANY_ID))
4020 return i->reset(dev, probe);
4026 static void quirk_dma_func0_alias(struct pci_dev *dev)
4028 if (PCI_FUNC(dev->devfn) != 0)
4029 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1);
4033 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
4035 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
4037 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
4038 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
4040 static void quirk_dma_func1_alias(struct pci_dev *dev)
4042 if (PCI_FUNC(dev->devfn) != 1)
4043 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1);
4047 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
4048 * SKUs function 1 is present and is a legacy IDE controller, in other
4049 * SKUs this function is not present, making this a ghost requester.
4050 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
4052 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
4053 quirk_dma_func1_alias);
4054 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
4055 quirk_dma_func1_alias);
4056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
4057 quirk_dma_func1_alias);
4058 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
4059 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
4060 quirk_dma_func1_alias);
4061 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
4062 quirk_dma_func1_alias);
4063 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
4064 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
4065 quirk_dma_func1_alias);
4066 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
4067 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
4068 quirk_dma_func1_alias);
4069 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
4070 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
4071 quirk_dma_func1_alias);
4072 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */
4073 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183,
4074 quirk_dma_func1_alias);
4075 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
4076 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
4077 quirk_dma_func1_alias);
4078 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */
4079 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215,
4080 quirk_dma_func1_alias);
4081 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
4082 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
4083 quirk_dma_func1_alias);
4084 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
4085 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
4086 quirk_dma_func1_alias);
4087 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
4088 quirk_dma_func1_alias);
4089 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
4090 quirk_dma_func1_alias);
4091 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
4092 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
4093 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
4094 quirk_dma_func1_alias);
4095 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
4096 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4097 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
4098 quirk_dma_func1_alias);
4101 * Some devices DMA with the wrong devfn, not just the wrong function.
4102 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
4103 * the alias is "fixed" and independent of the device devfn.
4105 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
4106 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4107 * single device on the secondary bus. In reality, the single exposed
4108 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
4109 * that provides a bridge to the internal bus of the I/O processor. The
4110 * controller supports private devices, which can be hidden from PCI config
4111 * space. In the case of the Adaptec 3405, a private device at 01.0
4112 * appears to be the DMA engine, which therefore needs to become a DMA
4113 * alias for the device.
4115 static const struct pci_device_id fixed_dma_alias_tbl[] = {
4116 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4117 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
4118 .driver_data = PCI_DEVFN(1, 0) },
4119 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
4120 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
4121 .driver_data = PCI_DEVFN(1, 0) },
4125 static void quirk_fixed_dma_alias(struct pci_dev *dev)
4127 const struct pci_device_id *id;
4129 id = pci_match_id(fixed_dma_alias_tbl, dev);
4131 pci_add_dma_alias(dev, id->driver_data, 1);
4133 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
4136 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4137 * using the wrong DMA alias for the device. Some of these devices can be
4138 * used as either forward or reverse bridges, so we need to test whether the
4139 * device is operating in the correct mode. We could probably apply this
4140 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
4141 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4142 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4144 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
4146 if (!pci_is_root_bus(pdev->bus) &&
4147 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4148 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
4149 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
4150 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
4152 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
4153 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
4154 quirk_use_pcie_bridge_dma_alias);
4155 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
4156 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
4157 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
4158 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
4159 /* ITE 8893 has the same problem as the 8892 */
4160 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
4161 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
4162 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
4165 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
4166 * be added as aliases to the DMA device in order to allow buffer access
4167 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4168 * programmed in the EEPROM.
4170 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
4172 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1);
4173 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1);
4174 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1);
4176 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
4177 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
4180 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4181 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx).
4183 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access
4184 * when IOMMU is enabled. These aliases allow computational unit access to
4185 * host memory. These aliases mark the whole VCA device as one IOMMU
4188 * All possible slot numbers (0x20) are used, since we are unable to tell
4189 * what slot is used on other side. This quirk is intended for both host
4190 * and computational unit sides. The VCA devices have up to five functions
4191 * (four for DMA channels and one additional).
4193 static void quirk_pex_vca_alias(struct pci_dev *pdev)
4195 const unsigned int num_pci_slots = 0x20;
4198 for (slot = 0; slot < num_pci_slots; slot++)
4199 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5);
4201 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias);
4202 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias);
4203 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias);
4204 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias);
4205 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias);
4206 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias);
4209 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
4210 * associated not at the root bus, but at a bridge below. This quirk avoids
4211 * generating invalid DMA aliases.
4213 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
4215 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
4217 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4218 quirk_bridge_cavm_thrx2_pcie_root);
4219 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4220 quirk_bridge_cavm_thrx2_pcie_root);
4223 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4224 * class code. Fix it.
4226 static void quirk_tw686x_class(struct pci_dev *pdev)
4228 u32 class = pdev->class;
4230 /* Use "Multimedia controller" class */
4231 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4232 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4233 class, pdev->class);
4235 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4236 quirk_tw686x_class);
4237 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4238 quirk_tw686x_class);
4239 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4240 quirk_tw686x_class);
4241 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4242 quirk_tw686x_class);
4245 * Some devices have problems with Transaction Layer Packets with the Relaxed
4246 * Ordering Attribute set. Such devices should mark themselves and other
4247 * device drivers should check before sending TLPs with RO set.
4249 static void quirk_relaxedordering_disable(struct pci_dev *dev)
4251 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4252 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4256 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4257 * Complex have a Flow Control Credit issue which can cause performance
4258 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4260 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4261 quirk_relaxedordering_disable);
4262 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4263 quirk_relaxedordering_disable);
4264 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4265 quirk_relaxedordering_disable);
4266 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4267 quirk_relaxedordering_disable);
4268 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4269 quirk_relaxedordering_disable);
4270 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4271 quirk_relaxedordering_disable);
4272 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4273 quirk_relaxedordering_disable);
4274 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4275 quirk_relaxedordering_disable);
4276 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4277 quirk_relaxedordering_disable);
4278 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4279 quirk_relaxedordering_disable);
4280 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4281 quirk_relaxedordering_disable);
4282 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4283 quirk_relaxedordering_disable);
4284 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4285 quirk_relaxedordering_disable);
4286 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4287 quirk_relaxedordering_disable);
4288 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4289 quirk_relaxedordering_disable);
4290 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4291 quirk_relaxedordering_disable);
4292 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4293 quirk_relaxedordering_disable);
4294 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4295 quirk_relaxedordering_disable);
4296 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4297 quirk_relaxedordering_disable);
4298 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4299 quirk_relaxedordering_disable);
4300 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4301 quirk_relaxedordering_disable);
4302 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4303 quirk_relaxedordering_disable);
4304 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4305 quirk_relaxedordering_disable);
4306 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4307 quirk_relaxedordering_disable);
4308 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4309 quirk_relaxedordering_disable);
4310 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4311 quirk_relaxedordering_disable);
4312 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4313 quirk_relaxedordering_disable);
4314 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4315 quirk_relaxedordering_disable);
4318 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex
4319 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4320 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4321 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4322 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4323 * November 10, 2010). As a result, on this platform we can't use Relaxed
4324 * Ordering for Upstream TLPs.
4326 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4327 quirk_relaxedordering_disable);
4328 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4329 quirk_relaxedordering_disable);
4330 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4331 quirk_relaxedordering_disable);
4334 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4335 * values for the Attribute as were supplied in the header of the
4336 * corresponding Request, except as explicitly allowed when IDO is used."
4338 * If a non-compliant device generates a completion with a different
4339 * attribute than the request, the receiver may accept it (which itself
4340 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4341 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4342 * device access timeout.
4344 * If the non-compliant device generates completions with zero attributes
4345 * (instead of copying the attributes from the request), we can work around
4346 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4347 * upstream devices so they always generate requests with zero attributes.
4349 * This affects other devices under the same Root Port, but since these
4350 * attributes are performance hints, there should be no functional problem.
4352 * Note that Configuration Space accesses are never supposed to have TLP
4353 * Attributes, so we're safe waiting till after any Configuration Space
4354 * accesses to do the Root Port fixup.
4356 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4358 struct pci_dev *root_port = pcie_find_root_port(pdev);
4361 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4365 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4366 dev_name(&pdev->dev));
4367 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4368 PCI_EXP_DEVCTL_RELAX_EN |
4369 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4373 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4374 * Completion it generates.
4376 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4379 * This mask/compare operation selects for Physical Function 4 on a
4380 * T5. We only need to fix up the Root Port once for any of the
4381 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4382 * 0x54xx so we use that one.
4384 if ((pdev->device & 0xff00) == 0x5400)
4385 quirk_disable_root_port_attributes(pdev);
4387 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4388 quirk_chelsio_T5_disable_root_port_attributes);
4391 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4393 * @acs_ctrl_req: Bitmask of desired ACS controls
4394 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by
4395 * the hardware design
4397 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included
4398 * in @acs_ctrl_ena, i.e., the device provides all the access controls the
4399 * caller desires. Return 0 otherwise.
4401 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena)
4403 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req)
4409 * AMD has indicated that the devices below do not support peer-to-peer
4410 * in any system where they are found in the southbridge with an AMD
4411 * IOMMU in the system. Multifunction devices that do not support
4412 * peer-to-peer between functions can claim to support a subset of ACS.
4413 * Such devices effectively enable request redirect (RR) and completion
4414 * redirect (CR) since all transactions are redirected to the upstream
4417 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/
4418 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/
4419 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/
4421 * 1002:4385 SBx00 SMBus Controller
4422 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4423 * 1002:4383 SBx00 Azalia (Intel HDA)
4424 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4425 * 1002:4384 SBx00 PCI to PCI Bridge
4426 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4428 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4430 * 1022:780f [AMD] FCH PCI Bridge
4431 * 1022:7809 [AMD] FCH USB OHCI Controller
4433 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4436 struct acpi_table_header *header = NULL;
4439 /* Targeting multifunction devices on the SB (appears on root bus) */
4440 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4443 /* The IVRS table describes the AMD IOMMU */
4444 status = acpi_get_table("IVRS", 0, &header);
4445 if (ACPI_FAILURE(status))
4448 acpi_put_table(header);
4450 /* Filter out flags not applicable to multifunction */
4451 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4453 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR);
4459 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4461 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4464 switch (dev->device) {
4466 * Effectively selects all downstream ports for whole ThunderX1
4467 * (which represents 8 SoCs).
4469 case 0xa000 ... 0xa7ff: /* ThunderX1 */
4470 case 0xaf84: /* ThunderX2 */
4471 case 0xb884: /* ThunderX3 */
4478 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4480 if (!pci_quirk_cavium_acs_match(dev))
4484 * Cavium Root Ports don't advertise an ACS capability. However,
4485 * the RTL internally implements similar protection as if ACS had
4486 * Source Validation, Request Redirection, Completion Redirection,
4487 * and Upstream Forwarding features enabled. Assert that the
4488 * hardware implements and enables equivalent ACS functionality for
4491 return pci_acs_ctrl_enabled(acs_flags,
4492 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4495 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4498 * X-Gene Root Ports matching this quirk do not allow peer-to-peer
4499 * transactions with others, allowing masking out these bits as if they
4500 * were unimplemented in the ACS capability.
4502 return pci_acs_ctrl_enabled(acs_flags,
4503 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4507 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability.
4508 * But the implementation could block peer-to-peer transactions between them
4509 * and provide ACS-like functionality.
4511 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags)
4513 if (!pci_is_pcie(dev) ||
4514 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) &&
4515 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)))
4518 switch (dev->device) {
4519 case 0x0710 ... 0x071e:
4521 case 0x0723 ... 0x0732:
4522 return pci_acs_ctrl_enabled(acs_flags,
4523 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4530 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4531 * transactions and validate bus numbers in requests, but do not provide an
4532 * actual PCIe ACS capability. This is the list of device IDs known to fall
4533 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4535 static const u16 pci_quirk_intel_pch_acs_ids[] = {
4537 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4538 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4539 /* Cougarpoint PCH */
4540 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4541 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4542 /* Pantherpoint PCH */
4543 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4544 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4545 /* Lynxpoint-H PCH */
4546 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4547 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4548 /* Lynxpoint-LP PCH */
4549 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4550 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4552 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4553 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4554 /* Patsburg (X79) PCH */
4555 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4556 /* Wellsburg (X99) PCH */
4557 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4558 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4559 /* Lynx Point (9 series) PCH */
4560 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4563 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4567 /* Filter out a few obvious non-matches first */
4568 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4571 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4572 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4578 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4580 if (!pci_quirk_intel_pch_acs_match(dev))
4583 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK)
4584 return pci_acs_ctrl_enabled(acs_flags,
4585 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4587 return pci_acs_ctrl_enabled(acs_flags, 0);
4591 * These QCOM Root Ports do provide ACS-like features to disable peer
4592 * transactions and validate bus numbers in requests, but do not provide an
4593 * actual PCIe ACS capability. Hardware supports source validation but it
4594 * will report the issue as Completer Abort instead of ACS Violation.
4595 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4596 * Complex with unique segment numbers. It is not possible for one Root
4597 * Port to pass traffic to another Root Port. All PCIe transactions are
4598 * terminated inside the Root Port.
4600 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4602 return pci_acs_ctrl_enabled(acs_flags,
4603 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4606 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags)
4608 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4612 * Amazon's Annapurna Labs root ports don't include an ACS capability,
4613 * but do include ACS-like functionality. The hardware doesn't support
4614 * peer-to-peer transactions via the root port and each has a unique
4617 * Additionally, the root ports cannot send traffic to each other.
4619 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4621 return acs_flags ? 0 : 1;
4625 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4626 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4627 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4628 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4629 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4630 * control register is at offset 8 instead of 6 and we should probably use
4631 * dword accesses to them. This applies to the following PCI Device IDs, as
4632 * found in volume 1 of the datasheet[2]:
4634 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4635 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4637 * N.B. This doesn't fix what lspci shows.
4639 * The 100 series chipset specification update includes this as errata #23[3].
4641 * The 200 series chipset (Union Point) has the same bug according to the
4642 * specification update (Intel 200 Series Chipset Family Platform Controller
4643 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4644 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4647 * 0xa290-0xa29f PCI Express Root port #{0-16}
4648 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4650 * Mobile chipsets are also affected, 7th & 8th Generation
4651 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4652 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4653 * Processor Family I/O for U Quad Core Platforms Specification Update,
4654 * August 2017, Revision 002, Document#: 334660-002)[6]
4655 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4656 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4657 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4659 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4661 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4662 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4663 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4664 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4665 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4666 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4667 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
4669 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4671 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4674 switch (dev->device) {
4675 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4676 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4677 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
4684 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4686 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4691 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4698 /* see pci_acs_flags_enabled() */
4699 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4700 acs_flags &= (cap | PCI_ACS_EC);
4702 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4704 return pci_acs_ctrl_enabled(acs_flags, ctrl);
4707 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4710 * SV, TB, and UF are not relevant to multifunction endpoints.
4712 * Multifunction devices are only required to implement RR, CR, and DT
4713 * in their ACS capability if they support peer-to-peer transactions.
4714 * Devices matching this quirk have been verified by the vendor to not
4715 * perform peer-to-peer with other functions, allowing us to mask out
4716 * these bits as if they were unimplemented in the ACS capability.
4718 return pci_acs_ctrl_enabled(acs_flags,
4719 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4720 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4723 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags)
4726 * Intel RCiEP's are required to allow p2p only on translated
4727 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16,
4728 * "Root-Complex Peer to Peer Considerations".
4730 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END)
4733 return pci_acs_ctrl_enabled(acs_flags,
4734 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4737 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags)
4740 * iProc PAXB Root Ports don't advertise an ACS capability, but
4741 * they do not allow peer-to-peer transactions between Root Ports.
4742 * Allow each Root Port to be in a separate IOMMU group by masking
4745 return pci_acs_ctrl_enabled(acs_flags,
4746 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4749 static const struct pci_dev_acs_enabled {
4752 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4753 } pci_dev_acs_enabled[] = {
4754 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4755 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4756 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4757 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4758 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4759 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4760 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4761 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4762 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4763 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4764 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4765 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4766 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4767 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4768 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4769 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4770 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4771 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4772 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4773 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4774 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4775 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4776 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4777 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4778 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4779 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4780 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4781 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4782 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4783 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4784 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4786 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4787 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4788 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4789 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4790 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4791 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4792 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4794 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4795 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4796 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4797 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4798 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4799 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4800 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4801 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4803 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4804 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4805 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4807 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4808 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4809 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4810 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4811 /* 82571 (Quads omitted due to non-ACS switch) */
4812 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4813 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4814 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4815 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4817 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4818 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4819 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs },
4820 /* QCOM QDF2xxx root ports */
4821 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs },
4822 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs },
4823 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */
4824 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs },
4825 /* Intel PCH root ports */
4826 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4827 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4828 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4829 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4830 /* Cavium ThunderX */
4831 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4833 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4834 /* Ampere Computing */
4835 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4836 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4837 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4838 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4839 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4840 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4841 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4842 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
4843 /* Broadcom multi-function device */
4844 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs },
4845 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs },
4846 /* Amazon Annapurna Labs */
4847 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs },
4848 /* Zhaoxin multi-function devices */
4849 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs },
4850 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs },
4851 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs },
4852 /* Zhaoxin Root/Downstream Ports */
4853 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs },
4858 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
4860 * @acs_flags: Bitmask of desired ACS controls
4863 * -ENOTTY: No quirk applies to this device; we can't tell whether the
4864 * device provides the desired controls
4865 * 0: Device does not provide all the desired controls
4866 * >0: Device provides all the controls in @acs_flags
4868 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4870 const struct pci_dev_acs_enabled *i;
4874 * Allow devices that do not expose standard PCIe ACS capabilities
4875 * or control to indicate their support here. Multi-function express
4876 * devices which do not allow internal peer-to-peer between functions,
4877 * but do not implement PCIe ACS may wish to return true here.
4879 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4880 if ((i->vendor == dev->vendor ||
4881 i->vendor == (u16)PCI_ANY_ID) &&
4882 (i->device == dev->device ||
4883 i->device == (u16)PCI_ANY_ID)) {
4884 ret = i->acs_enabled(dev, acs_flags);
4893 /* Config space offset of Root Complex Base Address register */
4894 #define INTEL_LPC_RCBA_REG 0xf0
4895 /* 31:14 RCBA address */
4896 #define INTEL_LPC_RCBA_MASK 0xffffc000
4898 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4900 /* Backbone Scratch Pad Register */
4901 #define INTEL_BSPR_REG 0x1104
4902 /* Backbone Peer Non-Posted Disable */
4903 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4904 /* Backbone Peer Posted Disable */
4905 #define INTEL_BSPR_REG_BPPD (1 << 9)
4907 /* Upstream Peer Decode Configuration Register */
4908 #define INTEL_UPDCR_REG 0x1014
4909 /* 5:0 Peer Decode Enable bits */
4910 #define INTEL_UPDCR_REG_MASK 0x3f
4912 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4914 u32 rcba, bspr, updcr;
4915 void __iomem *rcba_mem;
4918 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4919 * are D28:F* and therefore get probed before LPC, thus we can't
4920 * use pci_get_slot()/pci_read_config_dword() here.
4922 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4923 INTEL_LPC_RCBA_REG, &rcba);
4924 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4927 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK,
4928 PAGE_ALIGN(INTEL_UPDCR_REG));
4933 * The BSPR can disallow peer cycles, but it's set by soft strap and
4934 * therefore read-only. If both posted and non-posted peer cycles are
4935 * disallowed, we're ok. If either are allowed, then we need to use
4936 * the UPDCR to disable peer decodes for each port. This provides the
4937 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4939 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4940 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4941 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4942 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4943 if (updcr & INTEL_UPDCR_REG_MASK) {
4944 pci_info(dev, "Disabling UPDCR peer decodes\n");
4945 updcr &= ~INTEL_UPDCR_REG_MASK;
4946 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4954 /* Miscellaneous Port Configuration register */
4955 #define INTEL_MPC_REG 0xd8
4956 /* MPC: Invalid Receive Bus Number Check Enable */
4957 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4959 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4964 * When enabled, the IRBNCE bit of the MPC register enables the
4965 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4966 * ensures that requester IDs fall within the bus number range
4967 * of the bridge. Enable if not already.
4969 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4970 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4971 pci_info(dev, "Enabling MPC IRBNCE\n");
4972 mpc |= INTEL_MPC_REG_IRBNCE;
4973 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4978 * Currently this quirk does the equivalent of
4979 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4981 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB,
4982 * if dev->external_facing || dev->untrusted
4984 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4986 if (!pci_quirk_intel_pch_acs_match(dev))
4989 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4990 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
4994 pci_quirk_enable_intel_rp_mpc_acs(dev);
4996 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4998 pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
5003 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
5008 if (!pci_quirk_intel_spt_pch_acs_match(dev))
5015 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5016 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5018 ctrl |= (cap & PCI_ACS_SV);
5019 ctrl |= (cap & PCI_ACS_RR);
5020 ctrl |= (cap & PCI_ACS_CR);
5021 ctrl |= (cap & PCI_ACS_UF);
5023 if (dev->external_facing || dev->untrusted)
5024 ctrl |= (cap & PCI_ACS_TB);
5026 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5028 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
5033 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
5038 if (!pci_quirk_intel_spt_pch_acs_match(dev))
5045 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
5046 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
5048 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
5050 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
5052 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
5057 static const struct pci_dev_acs_ops {
5060 int (*enable_acs)(struct pci_dev *dev);
5061 int (*disable_acs_redir)(struct pci_dev *dev);
5062 } pci_dev_acs_ops[] = {
5063 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5064 .enable_acs = pci_quirk_enable_intel_pch_acs,
5066 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
5067 .enable_acs = pci_quirk_enable_intel_spt_pch_acs,
5068 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
5072 int pci_dev_specific_enable_acs(struct pci_dev *dev)
5074 const struct pci_dev_acs_ops *p;
5077 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5078 p = &pci_dev_acs_ops[i];
5079 if ((p->vendor == dev->vendor ||
5080 p->vendor == (u16)PCI_ANY_ID) &&
5081 (p->device == dev->device ||
5082 p->device == (u16)PCI_ANY_ID) &&
5084 ret = p->enable_acs(dev);
5093 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
5095 const struct pci_dev_acs_ops *p;
5098 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) {
5099 p = &pci_dev_acs_ops[i];
5100 if ((p->vendor == dev->vendor ||
5101 p->vendor == (u16)PCI_ANY_ID) &&
5102 (p->device == dev->device ||
5103 p->device == (u16)PCI_ANY_ID) &&
5104 p->disable_acs_redir) {
5105 ret = p->disable_acs_redir(dev);
5115 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5116 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
5117 * Next Capability pointer in the MSI Capability Structure should point to
5118 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
5121 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
5126 struct pci_cap_saved_state *state;
5128 /* Bail if the hardware bug is fixed */
5129 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
5132 /* Bail if MSI Capability Structure is not found for some reason */
5133 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
5138 * Bail if Next Capability pointer in the MSI Capability Structure
5139 * is not the expected incorrect 0x00.
5141 pci_read_config_byte(pdev, pos + 1, &next_cap);
5146 * PCIe Capability Structure is expected to be at 0x50 and should
5147 * terminate the list (Next Capability pointer is 0x00). Verify
5148 * Capability Id and Next Capability pointer is as expected.
5149 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
5150 * to correctly set kernel data structures which have already been
5151 * set incorrectly due to the hardware bug.
5154 pci_read_config_word(pdev, pos, ®16);
5155 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
5157 #ifndef PCI_EXP_SAVE_REGS
5158 #define PCI_EXP_SAVE_REGS 7
5160 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
5162 pdev->pcie_cap = pos;
5163 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
5164 pdev->pcie_flags_reg = reg16;
5165 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
5166 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
5168 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
5169 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
5170 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
5171 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
5173 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
5177 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
5181 state->cap.cap_nr = PCI_CAP_ID_EXP;
5182 state->cap.cap_extended = 0;
5183 state->cap.size = size;
5184 cap = (u16 *)&state->cap.data[0];
5185 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
5186 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
5187 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
5188 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
5189 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
5190 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
5191 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
5192 hlist_add_head(&state->next, &pdev->saved_cap_space);
5195 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
5198 * FLR may cause the following to devices to hang:
5200 * AMD Starship/Matisse HD Audio Controller 0x1487
5201 * AMD Starship USB 3.0 Host Controller 0x148c
5202 * AMD Matisse USB 3.0 Host Controller 0x149c
5203 * Intel 82579LM Gigabit Ethernet Controller 0x1502
5204 * Intel 82579V Gigabit Ethernet Controller 0x1503
5207 static void quirk_no_flr(struct pci_dev *dev)
5209 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
5211 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr);
5212 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr);
5213 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr);
5214 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr);
5215 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr);
5217 static void quirk_no_ext_tags(struct pci_dev *pdev)
5219 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
5224 bridge->no_ext_tags = 1;
5225 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
5227 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
5229 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
5230 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
5231 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
5232 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
5233 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
5234 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
5235 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
5237 #ifdef CONFIG_PCI_ATS
5239 * Some devices require additional driver setup to enable ATS. Don't use
5240 * ATS for those devices as ATS will be enabled before the driver has had a
5241 * chance to load and configure the device.
5243 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev)
5245 if ((pdev->device == 0x7312 && pdev->revision != 0x00) ||
5246 (pdev->device == 0x7340 && pdev->revision != 0xc5) ||
5247 (pdev->device == 0x7341 && pdev->revision != 0x00))
5250 if (pdev->device == 0x15d8) {
5251 if (pdev->revision == 0xcf &&
5252 pdev->subsystem_vendor == 0xea50 &&
5253 (pdev->subsystem_device == 0xce19 ||
5254 pdev->subsystem_device == 0xcc10 ||
5255 pdev->subsystem_device == 0xcc08))
5262 pci_info(pdev, "disabling ATS\n");
5266 /* AMD Stoney platform GPU */
5267 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats);
5268 /* AMD Iceland dGPU */
5269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats);
5270 /* AMD Navi10 dGPU */
5271 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats);
5272 /* AMD Navi14 dGPU */
5273 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats);
5274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats);
5275 /* AMD Raven platform iGPU */
5276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats);
5277 #endif /* CONFIG_PCI_ATS */
5279 /* Freescale PCIe doesn't support MSI in RC mode */
5280 static void quirk_fsl_no_msi(struct pci_dev *pdev)
5282 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5285 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5288 * Although not allowed by the spec, some multi-function devices have
5289 * dependencies of one function (consumer) on another (supplier). For the
5290 * consumer to work in D0, the supplier must also be in D0. Create a
5291 * device link from the consumer to the supplier to enforce this
5292 * dependency. Runtime PM is allowed by default on the consumer to prevent
5293 * it from permanently keeping the supplier awake.
5295 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer,
5296 unsigned int supplier, unsigned int class,
5297 unsigned int class_shift)
5299 struct pci_dev *supplier_pdev;
5301 if (PCI_FUNC(pdev->devfn) != consumer)
5304 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
5306 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier));
5307 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) {
5308 pci_dev_put(supplier_pdev);
5312 if (device_link_add(&pdev->dev, &supplier_pdev->dev,
5313 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
5314 pci_info(pdev, "D0 power state depends on %s\n",
5315 pci_name(supplier_pdev));
5317 pci_err(pdev, "Cannot enforce power dependency on %s\n",
5318 pci_name(supplier_pdev));
5320 pm_runtime_allow(&pdev->dev);
5321 pci_dev_put(supplier_pdev);
5325 * Create device link for GPUs with integrated HDA controller for streaming
5326 * audio to attached displays.
5328 static void quirk_gpu_hda(struct pci_dev *hda)
5330 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16);
5332 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
5333 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5334 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
5335 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5336 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5337 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
5340 * Create device link for NVIDIA GPU with integrated USB xHCI Host
5341 * controller to VGA.
5343 static void quirk_gpu_usb(struct pci_dev *usb)
5345 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16);
5347 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5348 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb);
5351 * Create device link for NVIDIA GPU with integrated Type-C UCSI controller
5352 * to VGA. Currently there is no class code defined for UCSI device over PCI
5353 * so using UNKNOWN class for now and it will be updated when UCSI
5354 * over PCI gets a class code.
5356 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
5357 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi)
5359 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16);
5361 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5362 PCI_CLASS_SERIAL_UNKNOWN, 8,
5363 quirk_gpu_usb_typec_ucsi);
5366 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it
5367 * disabled. https://devtalk.nvidia.com/default/topic/1024022
5369 static void quirk_nvidia_hda(struct pci_dev *gpu)
5374 /* There was no integrated HDA controller before MCP89 */
5375 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M)
5378 /* Bit 25 at offset 0x488 enables the HDA controller */
5379 pci_read_config_dword(gpu, 0x488, &val);
5383 pci_info(gpu, "Enabling HDA controller\n");
5384 pci_write_config_dword(gpu, 0x488, val | BIT(25));
5386 /* The GPU becomes a multi-function device when the HDA is enabled */
5387 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type);
5388 gpu->multifunction = !!(hdr_type & 0x80);
5390 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5391 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5392 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
5393 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda);
5396 * Some IDT switches incorrectly flag an ACS Source Validation error on
5397 * completions for config read requests even though PCIe r4.0, sec
5398 * 6.12.1.1, says that completions are never affected by ACS Source
5399 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5401 * Item #36 - Downstream port applies ACS Source Validation to Completions
5402 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5403 * completions are never affected by ACS Source Validation. However,
5404 * completions received by a downstream port of the PCIe switch from a
5405 * device that has not yet captured a PCIe bus number are incorrectly
5406 * dropped by ACS Source Validation by the switch downstream port.
5408 * The workaround suggested by IDT is to issue a config write to the
5409 * downstream device before issuing the first config read. This allows the
5410 * downstream device to capture its bus and device numbers (see PCIe r4.0,
5411 * sec 2.2.9), thus avoiding the ACS error on the completion.
5413 * However, we don't know when the device is ready to accept the config
5414 * write, so we do config reads until we receive a non-Config Request Retry
5415 * Status, then do the config write.
5417 * To avoid hitting the erratum when doing the config reads, we disable ACS
5418 * SV around this process.
5420 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout)
5425 struct pci_dev *bridge = bus->self;
5427 pos = bridge->acs_cap;
5429 /* Disable ACS SV before initial config reads */
5431 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl);
5432 if (ctrl & PCI_ACS_SV)
5433 pci_write_config_word(bridge, pos + PCI_ACS_CTRL,
5434 ctrl & ~PCI_ACS_SV);
5437 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
5439 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */
5441 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0);
5443 /* Re-enable ACS_SV if it was previously enabled */
5444 if (ctrl & PCI_ACS_SV)
5445 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl);
5451 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
5452 * NT endpoints via the internal switch fabric. These IDs replace the
5453 * originating requestor ID TLPs which access host memory on peer NTB
5454 * ports. Therefore, all proxy IDs must be aliased to the NTB device
5455 * to permit access when the IOMMU is turned on.
5457 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
5460 struct ntb_info_regs __iomem *mmio_ntb;
5461 struct ntb_ctrl_regs __iomem *mmio_ctrl;
5466 if (pci_enable_device(pdev)) {
5467 pci_err(pdev, "Cannot enable Switchtec device\n");
5471 mmio = pci_iomap(pdev, 0, 0);
5473 pci_disable_device(pdev);
5474 pci_err(pdev, "Cannot iomap Switchtec device\n");
5478 pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
5480 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
5481 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
5483 partition = ioread8(&mmio_ntb->partition_id);
5485 partition_map = ioread32(&mmio_ntb->ep_map);
5486 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
5487 partition_map &= ~(1ULL << partition);
5489 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
5490 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
5494 if (!(partition_map & (1ULL << pp)))
5497 pci_dbg(pdev, "Processing partition %d\n", pp);
5499 mmio_peer_ctrl = &mmio_ctrl[pp];
5501 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
5503 pci_warn(pdev, "Partition %d table_sz 0\n", pp);
5507 if (table_sz > 512) {
5509 "Invalid Switchtec partition %d table_sz %d\n",
5514 for (te = 0; te < table_sz; te++) {
5518 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
5519 devfn = (rid_entry >> 1) & 0xFF;
5521 "Aliasing Partition %d Proxy ID %02x.%d\n",
5522 pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
5523 pci_add_dma_alias(pdev, devfn, 1);
5527 pci_iounmap(pdev, mmio);
5528 pci_disable_device(pdev);
5530 #define SWITCHTEC_QUIRK(vid) \
5531 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \
5532 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias)
5534 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */
5535 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */
5536 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */
5537 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */
5538 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */
5539 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */
5540 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */
5541 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */
5542 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */
5543 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */
5544 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */
5545 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */
5546 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */
5547 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */
5548 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */
5549 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */
5550 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */
5551 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */
5552 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */
5553 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */
5554 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */
5555 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */
5556 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */
5557 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */
5558 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */
5559 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */
5560 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */
5561 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */
5562 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */
5563 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */
5564 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */
5565 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */
5566 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */
5567 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */
5568 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */
5569 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */
5570 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */
5571 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */
5572 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */
5573 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */
5574 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */
5575 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */
5576 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */
5577 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */
5578 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */
5579 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */
5580 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */
5581 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */
5584 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints.
5585 * These IDs are used to forward responses to the originator on the other
5586 * side of the NTB. Alias all possible IDs to the NTB to permit access when
5587 * the IOMMU is turned on.
5589 static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev)
5591 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n");
5592 /* PLX NTB may use all 256 devfns */
5593 pci_add_dma_alias(pdev, 0, 256);
5595 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias);
5596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias);
5599 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does
5600 * not always reset the secondary Nvidia GPU between reboots if the system
5601 * is configured to use Hybrid Graphics mode. This results in the GPU
5602 * being left in whatever state it was in during the *previous* boot, which
5603 * causes spurious interrupts from the GPU, which in turn causes us to
5604 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly,
5605 * this also completely breaks nouveau.
5607 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a
5608 * clean state and fixes all these issues.
5610 * When the machine is configured in Dedicated display mode, the issue
5611 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this
5612 * mode, so we can detect that and avoid resetting it.
5614 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
5619 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO ||
5620 pdev->subsystem_device != 0x222e ||
5624 if (pci_enable_device_mem(pdev))
5628 * Based on nvkm_device_ctor() in
5629 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
5631 map = pci_iomap(pdev, 0, 0x23000);
5633 pci_err(pdev, "Can't map MMIO space\n");
5638 * Make sure the GPU looks like it's been POSTed before resetting
5641 if (ioread32(map + 0x2240c) & 0x2) {
5642 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n");
5643 ret = pci_reset_bus(pdev);
5645 pci_err(pdev, "Failed to reset GPU: %d\n", ret);
5650 pci_disable_device(pdev);
5652 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
5653 PCI_CLASS_DISPLAY_VGA, 8,
5654 quirk_reset_lenovo_thinkpad_p50_nvgpu);
5657 * Device [1b21:2142]
5658 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device.
5660 static void pci_fixup_no_d0_pme(struct pci_dev *dev)
5662 pci_info(dev, "PME# does not work under D0, disabling it\n");
5663 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
5665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme);
5668 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI]
5670 * These devices advertise PME# support in all power states but don't
5671 * reliably assert it.
5673 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf)
5674 * says "The MSI Function is not implemented on this device" in chapters
5675 * 7.3.27, 7.3.29-7.3.31.
5677 static void pci_fixup_no_msi_no_pme(struct pci_dev *dev)
5679 #ifdef CONFIG_PCI_MSI
5680 pci_info(dev, "MSI is not implemented on this device, disabling it\n");
5683 pci_info(dev, "PME# is unreliable, disabling it\n");
5684 dev->pme_support = 0;
5686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme);
5687 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme);
5689 static void apex_pci_fixup_class(struct pci_dev *pdev)
5691 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class;
5693 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a,
5694 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class);