1 // SPDX-License-Identifier: GPL-2.0
3 * Procfs interface for the PCI bus
5 * Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
8 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/module.h>
12 #include <linux/proc_fs.h>
13 #include <linux/seq_file.h>
14 #include <linux/capability.h>
15 #include <linux/uaccess.h>
16 #include <linux/security.h>
17 #include <asm/byteorder.h>
20 static int proc_initialized; /* = 0 */
22 static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
24 struct pci_dev *dev = PDE_DATA(file_inode(file));
25 return fixed_size_llseek(file, off, whence, dev->cfg_size);
28 static ssize_t proc_bus_pci_read(struct file *file, char __user *buf,
29 size_t nbytes, loff_t *ppos)
31 struct pci_dev *dev = PDE_DATA(file_inode(file));
32 unsigned int pos = *ppos;
33 unsigned int cnt, size;
36 * Normal users can read only the standardized portion of the
37 * configuration space as several chips lock up when trying to read
38 * undefined locations (think of Intel PIIX4 as a typical example).
41 if (capable(CAP_SYS_ADMIN))
43 else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
52 if (pos + nbytes > size)
56 if (!access_ok(buf, cnt))
59 pci_config_pm_runtime_get(dev);
61 if ((pos & 1) && cnt) {
63 pci_user_read_config_byte(dev, pos, &val);
70 if ((pos & 3) && cnt > 2) {
72 pci_user_read_config_word(dev, pos, &val);
73 __put_user(cpu_to_le16(val), (__le16 __user *) buf);
81 pci_user_read_config_dword(dev, pos, &val);
82 __put_user(cpu_to_le32(val), (__le32 __user *) buf);
91 pci_user_read_config_word(dev, pos, &val);
92 __put_user(cpu_to_le16(val), (__le16 __user *) buf);
100 pci_user_read_config_byte(dev, pos, &val);
101 __put_user(val, buf);
107 pci_config_pm_runtime_put(dev);
113 static ssize_t proc_bus_pci_write(struct file *file, const char __user *buf,
114 size_t nbytes, loff_t *ppos)
116 struct inode *ino = file_inode(file);
117 struct pci_dev *dev = PDE_DATA(ino);
119 int size = dev->cfg_size;
122 ret = security_locked_down(LOCKDOWN_PCI_ACCESS);
130 if (pos + nbytes > size)
134 if (!access_ok(buf, cnt))
137 pci_config_pm_runtime_get(dev);
139 if ((pos & 1) && cnt) {
141 __get_user(val, buf);
142 pci_user_write_config_byte(dev, pos, val);
148 if ((pos & 3) && cnt > 2) {
150 __get_user(val, (__le16 __user *) buf);
151 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
159 __get_user(val, (__le32 __user *) buf);
160 pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
168 __get_user(val, (__le16 __user *) buf);
169 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
177 __get_user(val, buf);
178 pci_user_write_config_byte(dev, pos, val);
184 pci_config_pm_runtime_put(dev);
187 i_size_write(ino, dev->cfg_size);
191 struct pci_filp_private {
192 enum pci_mmap_state mmap_state;
196 static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
199 struct pci_dev *dev = PDE_DATA(file_inode(file));
201 struct pci_filp_private *fpriv = file->private_data;
202 #endif /* HAVE_PCI_MMAP */
205 ret = security_locked_down(LOCKDOWN_PCI_ACCESS);
210 case PCIIOC_CONTROLLER:
211 ret = pci_domain_nr(dev->bus);
215 case PCIIOC_MMAP_IS_IO:
216 if (!arch_can_pci_mmap_io())
218 fpriv->mmap_state = pci_mmap_io;
221 case PCIIOC_MMAP_IS_MEM:
222 fpriv->mmap_state = pci_mmap_mem;
225 case PCIIOC_WRITE_COMBINE:
226 if (arch_can_pci_mmap_wc()) {
228 fpriv->write_combine = 1;
230 fpriv->write_combine = 0;
233 /* If arch decided it can't, fall through... */
234 #endif /* HAVE_PCI_MMAP */
245 static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
247 struct pci_dev *dev = PDE_DATA(file_inode(file));
248 struct pci_filp_private *fpriv = file->private_data;
249 int i, ret, write_combine = 0, res_bit = IORESOURCE_MEM;
251 if (!capable(CAP_SYS_RAWIO) ||
252 security_locked_down(LOCKDOWN_PCI_ACCESS))
255 if (fpriv->mmap_state == pci_mmap_io) {
256 if (!arch_can_pci_mmap_io())
258 res_bit = IORESOURCE_IO;
261 /* Make sure the caller is mapping a real resource for this device */
262 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
263 if (dev->resource[i].flags & res_bit &&
264 pci_mmap_fits(dev, i, vma, PCI_MMAP_PROCFS))
268 if (i >= PCI_STD_NUM_BARS)
271 if (fpriv->mmap_state == pci_mmap_mem &&
272 fpriv->write_combine) {
273 if (dev->resource[i].flags & IORESOURCE_PREFETCH)
279 if (dev->resource[i].flags & IORESOURCE_MEM &&
280 iomem_is_exclusive(dev->resource[i].start))
283 ret = pci_mmap_page_range(dev, i, vma,
284 fpriv->mmap_state, write_combine);
291 static int proc_bus_pci_open(struct inode *inode, struct file *file)
293 struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);
298 fpriv->mmap_state = pci_mmap_io;
299 fpriv->write_combine = 0;
301 file->private_data = fpriv;
302 file->f_mapping = iomem_get_mapping();
307 static int proc_bus_pci_release(struct inode *inode, struct file *file)
309 kfree(file->private_data);
310 file->private_data = NULL;
314 #endif /* HAVE_PCI_MMAP */
316 static const struct proc_ops proc_bus_pci_ops = {
317 .proc_lseek = proc_bus_pci_lseek,
318 .proc_read = proc_bus_pci_read,
319 .proc_write = proc_bus_pci_write,
320 .proc_ioctl = proc_bus_pci_ioctl,
322 .proc_compat_ioctl = proc_bus_pci_ioctl,
325 .proc_open = proc_bus_pci_open,
326 .proc_release = proc_bus_pci_release,
327 .proc_mmap = proc_bus_pci_mmap,
328 #ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
329 .proc_get_unmapped_area = get_pci_unmapped_area,
330 #endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
331 #endif /* HAVE_PCI_MMAP */
335 static void *pci_seq_start(struct seq_file *m, loff_t *pos)
337 struct pci_dev *dev = NULL;
340 for_each_pci_dev(dev) {
347 static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
349 struct pci_dev *dev = v;
352 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
356 static void pci_seq_stop(struct seq_file *m, void *v)
359 struct pci_dev *dev = v;
364 static int show_device(struct seq_file *m, void *v)
366 const struct pci_dev *dev = v;
367 const struct pci_driver *drv;
373 drv = pci_dev_driver(dev);
374 seq_printf(m, "%02x%02x\t%04x%04x\t%x",
381 /* only print standard and ROM resources to preserve compatibility */
382 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
383 resource_size_t start, end;
384 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
385 seq_printf(m, "\t%16llx",
386 (unsigned long long)(start |
387 (dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
389 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
390 resource_size_t start, end;
391 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
392 seq_printf(m, "\t%16llx",
393 dev->resource[i].start < dev->resource[i].end ?
394 (unsigned long long)(end - start) + 1 : 0);
398 seq_puts(m, drv->name);
403 static const struct seq_operations proc_bus_pci_devices_op = {
404 .start = pci_seq_start,
405 .next = pci_seq_next,
406 .stop = pci_seq_stop,
410 static struct proc_dir_entry *proc_bus_pci_dir;
412 int pci_proc_attach_device(struct pci_dev *dev)
414 struct pci_bus *bus = dev->bus;
415 struct proc_dir_entry *e;
418 if (!proc_initialized)
422 if (pci_proc_domain(bus)) {
423 sprintf(name, "%04x:%02x", pci_domain_nr(bus),
426 sprintf(name, "%02x", bus->number);
428 bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
433 sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
434 e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
435 &proc_bus_pci_ops, dev);
438 proc_set_size(e, dev->cfg_size);
444 int pci_proc_detach_device(struct pci_dev *dev)
446 proc_remove(dev->procent);
451 int pci_proc_detach_bus(struct pci_bus *bus)
453 proc_remove(bus->procdir);
457 static int __init pci_proc_init(void)
459 struct pci_dev *dev = NULL;
460 proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
461 proc_create_seq("devices", 0, proc_bus_pci_dir,
462 &proc_bus_pci_devices_op);
463 proc_initialized = 1;
464 for_each_pci_dev(dev)
465 pci_proc_attach_device(dev);
469 device_initcall(pci_proc_init);