1 // SPDX-License-Identifier: GPL-2.0
3 * Procfs interface for the PCI bus
5 * Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
8 #include <linux/init.h>
10 #include <linux/slab.h>
11 #include <linux/module.h>
12 #include <linux/proc_fs.h>
13 #include <linux/seq_file.h>
14 #include <linux/capability.h>
15 #include <linux/uaccess.h>
16 #include <linux/security.h>
17 #include <asm/byteorder.h>
20 static int proc_initialized; /* = 0 */
22 static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
24 struct pci_dev *dev = PDE_DATA(file_inode(file));
25 return fixed_size_llseek(file, off, whence, dev->cfg_size);
28 static ssize_t proc_bus_pci_read(struct file *file, char __user *buf,
29 size_t nbytes, loff_t *ppos)
31 struct pci_dev *dev = PDE_DATA(file_inode(file));
32 unsigned int pos = *ppos;
33 unsigned int cnt, size;
36 * Normal users can read only the standardized portion of the
37 * configuration space as several chips lock up when trying to read
38 * undefined locations (think of Intel PIIX4 as a typical example).
41 if (capable(CAP_SYS_ADMIN))
43 else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
52 if (pos + nbytes > size)
56 if (!access_ok(buf, cnt))
59 pci_config_pm_runtime_get(dev);
61 if ((pos & 1) && cnt) {
63 pci_user_read_config_byte(dev, pos, &val);
70 if ((pos & 3) && cnt > 2) {
72 pci_user_read_config_word(dev, pos, &val);
73 __put_user(cpu_to_le16(val), (__le16 __user *) buf);
81 pci_user_read_config_dword(dev, pos, &val);
82 __put_user(cpu_to_le32(val), (__le32 __user *) buf);
90 pci_user_read_config_word(dev, pos, &val);
91 __put_user(cpu_to_le16(val), (__le16 __user *) buf);
99 pci_user_read_config_byte(dev, pos, &val);
100 __put_user(val, buf);
106 pci_config_pm_runtime_put(dev);
112 static ssize_t proc_bus_pci_write(struct file *file, const char __user *buf,
113 size_t nbytes, loff_t *ppos)
115 struct inode *ino = file_inode(file);
116 struct pci_dev *dev = PDE_DATA(ino);
118 int size = dev->cfg_size;
121 ret = security_locked_down(LOCKDOWN_PCI_ACCESS);
129 if (pos + nbytes > size)
133 if (!access_ok(buf, cnt))
136 pci_config_pm_runtime_get(dev);
138 if ((pos & 1) && cnt) {
140 __get_user(val, buf);
141 pci_user_write_config_byte(dev, pos, val);
147 if ((pos & 3) && cnt > 2) {
149 __get_user(val, (__le16 __user *) buf);
150 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
158 __get_user(val, (__le32 __user *) buf);
159 pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
167 __get_user(val, (__le16 __user *) buf);
168 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
176 __get_user(val, buf);
177 pci_user_write_config_byte(dev, pos, val);
183 pci_config_pm_runtime_put(dev);
186 i_size_write(ino, dev->cfg_size);
190 struct pci_filp_private {
191 enum pci_mmap_state mmap_state;
195 static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
198 struct pci_dev *dev = PDE_DATA(file_inode(file));
200 struct pci_filp_private *fpriv = file->private_data;
201 #endif /* HAVE_PCI_MMAP */
204 ret = security_locked_down(LOCKDOWN_PCI_ACCESS);
209 case PCIIOC_CONTROLLER:
210 ret = pci_domain_nr(dev->bus);
214 case PCIIOC_MMAP_IS_IO:
215 if (!arch_can_pci_mmap_io())
217 fpriv->mmap_state = pci_mmap_io;
220 case PCIIOC_MMAP_IS_MEM:
221 fpriv->mmap_state = pci_mmap_mem;
224 case PCIIOC_WRITE_COMBINE:
225 if (arch_can_pci_mmap_wc()) {
227 fpriv->write_combine = 1;
229 fpriv->write_combine = 0;
232 /* If arch decided it can't, fall through... */
234 #endif /* HAVE_PCI_MMAP */
244 static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
246 struct pci_dev *dev = PDE_DATA(file_inode(file));
247 struct pci_filp_private *fpriv = file->private_data;
248 int i, ret, write_combine = 0, res_bit = IORESOURCE_MEM;
250 if (!capable(CAP_SYS_RAWIO) ||
251 security_locked_down(LOCKDOWN_PCI_ACCESS))
254 if (fpriv->mmap_state == pci_mmap_io) {
255 if (!arch_can_pci_mmap_io())
257 res_bit = IORESOURCE_IO;
260 /* Make sure the caller is mapping a real resource for this device */
261 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
262 if (dev->resource[i].flags & res_bit &&
263 pci_mmap_fits(dev, i, vma, PCI_MMAP_PROCFS))
267 if (i >= PCI_STD_NUM_BARS)
270 if (fpriv->mmap_state == pci_mmap_mem &&
271 fpriv->write_combine) {
272 if (dev->resource[i].flags & IORESOURCE_PREFETCH)
278 if (dev->resource[i].flags & IORESOURCE_MEM &&
279 iomem_is_exclusive(dev->resource[i].start))
282 ret = pci_mmap_page_range(dev, i, vma,
283 fpriv->mmap_state, write_combine);
290 static int proc_bus_pci_open(struct inode *inode, struct file *file)
292 struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);
297 fpriv->mmap_state = pci_mmap_io;
298 fpriv->write_combine = 0;
300 file->private_data = fpriv;
301 file->f_mapping = iomem_get_mapping();
306 static int proc_bus_pci_release(struct inode *inode, struct file *file)
308 kfree(file->private_data);
309 file->private_data = NULL;
313 #endif /* HAVE_PCI_MMAP */
315 static const struct proc_ops proc_bus_pci_ops = {
316 .proc_lseek = proc_bus_pci_lseek,
317 .proc_read = proc_bus_pci_read,
318 .proc_write = proc_bus_pci_write,
319 .proc_ioctl = proc_bus_pci_ioctl,
321 .proc_compat_ioctl = proc_bus_pci_ioctl,
324 .proc_open = proc_bus_pci_open,
325 .proc_release = proc_bus_pci_release,
326 .proc_mmap = proc_bus_pci_mmap,
327 #ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
328 .proc_get_unmapped_area = get_pci_unmapped_area,
329 #endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
330 #endif /* HAVE_PCI_MMAP */
334 static void *pci_seq_start(struct seq_file *m, loff_t *pos)
336 struct pci_dev *dev = NULL;
339 for_each_pci_dev(dev) {
346 static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
348 struct pci_dev *dev = v;
351 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
355 static void pci_seq_stop(struct seq_file *m, void *v)
358 struct pci_dev *dev = v;
363 static int show_device(struct seq_file *m, void *v)
365 const struct pci_dev *dev = v;
366 const struct pci_driver *drv;
372 drv = pci_dev_driver(dev);
373 seq_printf(m, "%02x%02x\t%04x%04x\t%x",
380 /* only print standard and ROM resources to preserve compatibility */
381 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
382 resource_size_t start, end;
383 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
384 seq_printf(m, "\t%16llx",
385 (unsigned long long)(start |
386 (dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
388 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
389 resource_size_t start, end;
390 pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
391 seq_printf(m, "\t%16llx",
392 dev->resource[i].start < dev->resource[i].end ?
393 (unsigned long long)(end - start) + 1 : 0);
397 seq_puts(m, drv->name);
402 static const struct seq_operations proc_bus_pci_devices_op = {
403 .start = pci_seq_start,
404 .next = pci_seq_next,
405 .stop = pci_seq_stop,
409 static struct proc_dir_entry *proc_bus_pci_dir;
411 int pci_proc_attach_device(struct pci_dev *dev)
413 struct pci_bus *bus = dev->bus;
414 struct proc_dir_entry *e;
417 if (!proc_initialized)
421 if (pci_proc_domain(bus)) {
422 sprintf(name, "%04x:%02x", pci_domain_nr(bus),
425 sprintf(name, "%02x", bus->number);
427 bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
432 sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
433 e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
434 &proc_bus_pci_ops, dev);
437 proc_set_size(e, dev->cfg_size);
443 int pci_proc_detach_device(struct pci_dev *dev)
445 proc_remove(dev->procent);
450 int pci_proc_detach_bus(struct pci_bus *bus)
452 proc_remove(bus->procdir);
456 static int __init pci_proc_init(void)
458 struct pci_dev *dev = NULL;
459 proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
460 proc_create_seq("devices", 0, proc_bus_pci_dir,
461 &proc_bus_pci_devices_op);
462 proc_initialized = 1;
463 for_each_pci_dev(dev)
464 pci_proc_attach_device(dev);
468 device_initcall(pci_proc_init);