1 // SPDX-License-Identifier: GPL-2.0
3 * probe.c - PCI detection and setup code
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/init.h>
10 #include <linux/of_device.h>
11 #include <linux/of_pci.h>
12 #include <linux/pci_hotplug.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/cpumask.h>
16 #include <linux/pci-aspm.h>
17 #include <linux/aer.h>
18 #include <linux/acpi.h>
19 #include <linux/hypervisor.h>
20 #include <linux/irqdomain.h>
21 #include <linux/pm_runtime.h>
24 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
25 #define CARDBUS_RESERVE_BUSNR 3
27 static struct resource busn_resource = {
31 .flags = IORESOURCE_BUS,
34 /* Ugh. Need to stop exporting this to modules. */
35 LIST_HEAD(pci_root_buses);
36 EXPORT_SYMBOL(pci_root_buses);
38 static LIST_HEAD(pci_domain_busn_res_list);
40 struct pci_domain_busn_res {
41 struct list_head list;
46 static struct resource *get_pci_domain_busn_res(int domain_nr)
48 struct pci_domain_busn_res *r;
50 list_for_each_entry(r, &pci_domain_busn_res_list, list)
51 if (r->domain_nr == domain_nr)
54 r = kzalloc(sizeof(*r), GFP_KERNEL);
58 r->domain_nr = domain_nr;
61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
63 list_add_tail(&r->list, &pci_domain_busn_res_list);
68 static int find_anything(struct device *dev, void *data)
74 * Some device drivers need know if PCI is initiated.
75 * Basically, we think PCI is not initiated when there
76 * is no device to be found on the pci_bus_type.
78 int no_pci_devices(void)
83 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
84 no_devices = (dev == NULL);
88 EXPORT_SYMBOL(no_pci_devices);
93 static void release_pcibus_dev(struct device *dev)
95 struct pci_bus *pci_bus = to_pci_bus(dev);
97 put_device(pci_bus->bridge);
98 pci_bus_remove_resources(pci_bus);
99 pci_release_bus_of_node(pci_bus);
103 static struct class pcibus_class = {
105 .dev_release = &release_pcibus_dev,
106 .dev_groups = pcibus_groups,
109 static int __init pcibus_class_init(void)
111 return class_register(&pcibus_class);
113 postcore_initcall(pcibus_class_init);
115 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
117 u64 size = mask & maxbase; /* Find the significant bits */
122 * Get the lowest of them to find the decode size, and from that
125 size = (size & ~(size-1)) - 1;
128 * base == maxbase can be valid only if the BAR has already been
129 * programmed with all 1s.
131 if (base == maxbase && ((base | size) & mask) != mask)
137 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
142 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
143 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
144 flags |= IORESOURCE_IO;
148 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
149 flags |= IORESOURCE_MEM;
150 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
151 flags |= IORESOURCE_PREFETCH;
153 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
155 case PCI_BASE_ADDRESS_MEM_TYPE_32:
157 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
158 /* 1M mem BAR treated as 32-bit BAR */
160 case PCI_BASE_ADDRESS_MEM_TYPE_64:
161 flags |= IORESOURCE_MEM_64;
164 /* mem unknown type treated as 32-bit BAR */
170 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
173 * pci_read_base - Read a PCI BAR
174 * @dev: the PCI device
175 * @type: type of the BAR
176 * @res: resource buffer to be filled in
177 * @pos: BAR position in the config space
179 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
181 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
182 struct resource *res, unsigned int pos)
184 u32 l = 0, sz = 0, mask;
185 u64 l64, sz64, mask64;
187 struct pci_bus_region region, inverted_region;
189 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
191 /* No printks while decoding is disabled! */
192 if (!dev->mmio_always_on) {
193 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
194 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
195 pci_write_config_word(dev, PCI_COMMAND,
196 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
200 res->name = pci_name(dev);
202 pci_read_config_dword(dev, pos, &l);
203 pci_write_config_dword(dev, pos, l | mask);
204 pci_read_config_dword(dev, pos, &sz);
205 pci_write_config_dword(dev, pos, l);
208 * All bits set in sz means the device isn't working properly.
209 * If the BAR isn't implemented, all bits must be 0. If it's a
210 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
213 if (sz == 0xffffffff)
217 * I don't know how l can have all bits set. Copied from old code.
218 * Maybe it fixes a bug on some ancient platform.
223 if (type == pci_bar_unknown) {
224 res->flags = decode_bar(dev, l);
225 res->flags |= IORESOURCE_SIZEALIGN;
226 if (res->flags & IORESOURCE_IO) {
227 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
228 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
229 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
231 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
232 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
233 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
236 if (l & PCI_ROM_ADDRESS_ENABLE)
237 res->flags |= IORESOURCE_ROM_ENABLE;
238 l64 = l & PCI_ROM_ADDRESS_MASK;
239 sz64 = sz & PCI_ROM_ADDRESS_MASK;
240 mask64 = PCI_ROM_ADDRESS_MASK;
243 if (res->flags & IORESOURCE_MEM_64) {
244 pci_read_config_dword(dev, pos + 4, &l);
245 pci_write_config_dword(dev, pos + 4, ~0);
246 pci_read_config_dword(dev, pos + 4, &sz);
247 pci_write_config_dword(dev, pos + 4, l);
249 l64 |= ((u64)l << 32);
250 sz64 |= ((u64)sz << 32);
251 mask64 |= ((u64)~0 << 32);
254 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
255 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
260 sz64 = pci_size(l64, sz64, mask64);
262 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
267 if (res->flags & IORESOURCE_MEM_64) {
268 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
269 && sz64 > 0x100000000ULL) {
270 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
273 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
274 pos, (unsigned long long)sz64);
278 if ((sizeof(pci_bus_addr_t) < 8) && l) {
279 /* Above 32-bit boundary; try to reallocate */
280 res->flags |= IORESOURCE_UNSET;
283 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
284 pos, (unsigned long long)l64);
290 region.end = l64 + sz64;
292 pcibios_bus_to_resource(dev->bus, res, ®ion);
293 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
296 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
297 * the corresponding resource address (the physical address used by
298 * the CPU. Converting that resource address back to a bus address
299 * should yield the original BAR value:
301 * resource_to_bus(bus_to_resource(A)) == A
303 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
304 * be claimed by the device.
306 if (inverted_region.start != region.start) {
307 res->flags |= IORESOURCE_UNSET;
309 res->end = region.end - region.start;
310 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
311 pos, (unsigned long long)region.start);
321 pci_printk(KERN_DEBUG, dev, "reg 0x%x: %pR\n", pos, res);
323 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
326 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
328 unsigned int pos, reg;
330 if (dev->non_compliant_bars)
333 for (pos = 0; pos < howmany; pos++) {
334 struct resource *res = &dev->resource[pos];
335 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
336 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
340 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
341 dev->rom_base_reg = rom;
342 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
343 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
344 __pci_read_base(dev, pci_bar_mem32, res, rom);
348 static void pci_read_bridge_io(struct pci_bus *child)
350 struct pci_dev *dev = child->self;
351 u8 io_base_lo, io_limit_lo;
352 unsigned long io_mask, io_granularity, base, limit;
353 struct pci_bus_region region;
354 struct resource *res;
356 io_mask = PCI_IO_RANGE_MASK;
357 io_granularity = 0x1000;
358 if (dev->io_window_1k) {
359 /* Support 1K I/O space granularity */
360 io_mask = PCI_IO_1K_RANGE_MASK;
361 io_granularity = 0x400;
364 res = child->resource[0];
365 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
366 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
367 base = (io_base_lo & io_mask) << 8;
368 limit = (io_limit_lo & io_mask) << 8;
370 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
371 u16 io_base_hi, io_limit_hi;
373 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
374 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
375 base |= ((unsigned long) io_base_hi << 16);
376 limit |= ((unsigned long) io_limit_hi << 16);
380 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
382 region.end = limit + io_granularity - 1;
383 pcibios_bus_to_resource(dev->bus, res, ®ion);
384 pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res);
388 static void pci_read_bridge_mmio(struct pci_bus *child)
390 struct pci_dev *dev = child->self;
391 u16 mem_base_lo, mem_limit_lo;
392 unsigned long base, limit;
393 struct pci_bus_region region;
394 struct resource *res;
396 res = child->resource[1];
397 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
398 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
399 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
400 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
402 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
404 region.end = limit + 0xfffff;
405 pcibios_bus_to_resource(dev->bus, res, ®ion);
406 pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res);
410 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
412 struct pci_dev *dev = child->self;
413 u16 mem_base_lo, mem_limit_lo;
415 pci_bus_addr_t base, limit;
416 struct pci_bus_region region;
417 struct resource *res;
419 res = child->resource[2];
420 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
421 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
422 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
423 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
425 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
426 u32 mem_base_hi, mem_limit_hi;
428 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
429 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
432 * Some bridges set the base > limit by default, and some
433 * (broken) BIOSes do not initialize them. If we find
434 * this, just assume they are not being used.
436 if (mem_base_hi <= mem_limit_hi) {
437 base64 |= (u64) mem_base_hi << 32;
438 limit64 |= (u64) mem_limit_hi << 32;
442 base = (pci_bus_addr_t) base64;
443 limit = (pci_bus_addr_t) limit64;
445 if (base != base64) {
446 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
447 (unsigned long long) base64);
452 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
453 IORESOURCE_MEM | IORESOURCE_PREFETCH;
454 if (res->flags & PCI_PREF_RANGE_TYPE_64)
455 res->flags |= IORESOURCE_MEM_64;
457 region.end = limit + 0xfffff;
458 pcibios_bus_to_resource(dev->bus, res, ®ion);
459 pci_printk(KERN_DEBUG, dev, " bridge window %pR\n", res);
463 void pci_read_bridge_bases(struct pci_bus *child)
465 struct pci_dev *dev = child->self;
466 struct resource *res;
469 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
472 pci_info(dev, "PCI bridge to %pR%s\n",
474 dev->transparent ? " (subtractive decode)" : "");
476 pci_bus_remove_resources(child);
477 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
478 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
480 pci_read_bridge_io(child);
481 pci_read_bridge_mmio(child);
482 pci_read_bridge_mmio_pref(child);
484 if (dev->transparent) {
485 pci_bus_for_each_resource(child->parent, res, i) {
486 if (res && res->flags) {
487 pci_bus_add_resource(child, res,
488 PCI_SUBTRACTIVE_DECODE);
489 pci_printk(KERN_DEBUG, dev,
490 " bridge window %pR (subtractive decode)\n",
497 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
501 b = kzalloc(sizeof(*b), GFP_KERNEL);
505 INIT_LIST_HEAD(&b->node);
506 INIT_LIST_HEAD(&b->children);
507 INIT_LIST_HEAD(&b->devices);
508 INIT_LIST_HEAD(&b->slots);
509 INIT_LIST_HEAD(&b->resources);
510 b->max_bus_speed = PCI_SPEED_UNKNOWN;
511 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
512 #ifdef CONFIG_PCI_DOMAINS_GENERIC
514 b->domain_nr = parent->domain_nr;
519 static void devm_pci_release_host_bridge_dev(struct device *dev)
521 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
523 if (bridge->release_fn)
524 bridge->release_fn(bridge);
527 static void pci_release_host_bridge_dev(struct device *dev)
529 devm_pci_release_host_bridge_dev(dev);
530 pci_free_host_bridge(to_pci_host_bridge(dev));
533 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
535 struct pci_host_bridge *bridge;
537 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
541 INIT_LIST_HEAD(&bridge->windows);
542 bridge->dev.release = pci_release_host_bridge_dev;
546 EXPORT_SYMBOL(pci_alloc_host_bridge);
548 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
551 struct pci_host_bridge *bridge;
553 bridge = devm_kzalloc(dev, sizeof(*bridge) + priv, GFP_KERNEL);
557 INIT_LIST_HEAD(&bridge->windows);
558 bridge->dev.release = devm_pci_release_host_bridge_dev;
562 EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
564 void pci_free_host_bridge(struct pci_host_bridge *bridge)
566 pci_free_resource_list(&bridge->windows);
570 EXPORT_SYMBOL(pci_free_host_bridge);
572 static const unsigned char pcix_bus_speed[] = {
573 PCI_SPEED_UNKNOWN, /* 0 */
574 PCI_SPEED_66MHz_PCIX, /* 1 */
575 PCI_SPEED_100MHz_PCIX, /* 2 */
576 PCI_SPEED_133MHz_PCIX, /* 3 */
577 PCI_SPEED_UNKNOWN, /* 4 */
578 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
579 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
580 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
581 PCI_SPEED_UNKNOWN, /* 8 */
582 PCI_SPEED_66MHz_PCIX_266, /* 9 */
583 PCI_SPEED_100MHz_PCIX_266, /* A */
584 PCI_SPEED_133MHz_PCIX_266, /* B */
585 PCI_SPEED_UNKNOWN, /* C */
586 PCI_SPEED_66MHz_PCIX_533, /* D */
587 PCI_SPEED_100MHz_PCIX_533, /* E */
588 PCI_SPEED_133MHz_PCIX_533 /* F */
591 const unsigned char pcie_link_speed[] = {
592 PCI_SPEED_UNKNOWN, /* 0 */
593 PCIE_SPEED_2_5GT, /* 1 */
594 PCIE_SPEED_5_0GT, /* 2 */
595 PCIE_SPEED_8_0GT, /* 3 */
596 PCI_SPEED_UNKNOWN, /* 4 */
597 PCI_SPEED_UNKNOWN, /* 5 */
598 PCI_SPEED_UNKNOWN, /* 6 */
599 PCI_SPEED_UNKNOWN, /* 7 */
600 PCI_SPEED_UNKNOWN, /* 8 */
601 PCI_SPEED_UNKNOWN, /* 9 */
602 PCI_SPEED_UNKNOWN, /* A */
603 PCI_SPEED_UNKNOWN, /* B */
604 PCI_SPEED_UNKNOWN, /* C */
605 PCI_SPEED_UNKNOWN, /* D */
606 PCI_SPEED_UNKNOWN, /* E */
607 PCI_SPEED_UNKNOWN /* F */
610 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
612 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
614 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
616 static unsigned char agp_speeds[] = {
624 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
630 else if (agpstat & 2)
632 else if (agpstat & 1)
644 return agp_speeds[index];
647 static void pci_set_bus_speed(struct pci_bus *bus)
649 struct pci_dev *bridge = bus->self;
652 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
654 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
658 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
659 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
661 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
662 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
665 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
668 enum pci_bus_speed max;
670 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
673 if (status & PCI_X_SSTATUS_533MHZ) {
674 max = PCI_SPEED_133MHz_PCIX_533;
675 } else if (status & PCI_X_SSTATUS_266MHZ) {
676 max = PCI_SPEED_133MHz_PCIX_266;
677 } else if (status & PCI_X_SSTATUS_133MHZ) {
678 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
679 max = PCI_SPEED_133MHz_PCIX_ECC;
681 max = PCI_SPEED_133MHz_PCIX;
683 max = PCI_SPEED_66MHz_PCIX;
686 bus->max_bus_speed = max;
687 bus->cur_bus_speed = pcix_bus_speed[
688 (status & PCI_X_SSTATUS_FREQ) >> 6];
693 if (pci_is_pcie(bridge)) {
697 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
698 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
700 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
701 pcie_update_link_speed(bus, linksta);
705 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
707 struct irq_domain *d;
710 * Any firmware interface that can resolve the msi_domain
711 * should be called from here.
713 d = pci_host_bridge_of_msi_domain(bus);
715 d = pci_host_bridge_acpi_msi_domain(bus);
717 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
719 * If no IRQ domain was found via the OF tree, try looking it up
720 * directly through the fwnode_handle.
723 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
726 d = irq_find_matching_fwnode(fwnode,
734 static void pci_set_bus_msi_domain(struct pci_bus *bus)
736 struct irq_domain *d;
740 * The bus can be a root bus, a subordinate bus, or a virtual bus
741 * created by an SR-IOV device. Walk up to the first bridge device
742 * found or derive the domain from the host bridge.
744 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
746 d = dev_get_msi_domain(&b->self->dev);
750 d = pci_host_bridge_msi_domain(b);
752 dev_set_msi_domain(&bus->dev, d);
755 static int pci_register_host_bridge(struct pci_host_bridge *bridge)
757 struct device *parent = bridge->dev.parent;
758 struct resource_entry *window, *n;
759 struct pci_bus *bus, *b;
760 resource_size_t offset;
761 LIST_HEAD(resources);
762 struct resource *res;
767 bus = pci_alloc_bus(NULL);
773 /* Temporarily move resources off the list */
774 list_splice_init(&bridge->windows, &resources);
775 bus->sysdata = bridge->sysdata;
776 bus->msi = bridge->msi;
777 bus->ops = bridge->ops;
778 bus->number = bus->busn_res.start = bridge->busnr;
779 #ifdef CONFIG_PCI_DOMAINS_GENERIC
780 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
783 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
785 /* Ignore it if we already got here via a different bridge */
786 dev_dbg(&b->dev, "bus already known\n");
791 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
794 err = pcibios_root_bridge_prepare(bridge);
798 err = device_register(&bridge->dev);
800 put_device(&bridge->dev);
802 bus->bridge = get_device(&bridge->dev);
803 device_enable_async_suspend(bus->bridge);
804 pci_set_bus_of_node(bus);
805 pci_set_bus_msi_domain(bus);
808 set_dev_node(bus->bridge, pcibus_to_node(bus));
810 bus->dev.class = &pcibus_class;
811 bus->dev.parent = bus->bridge;
813 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
814 name = dev_name(&bus->dev);
816 err = device_register(&bus->dev);
820 pcibios_add_bus(bus);
822 /* Create legacy_io and legacy_mem files for this bus */
823 pci_create_legacy_files(bus);
826 dev_info(parent, "PCI host bridge to bus %s\n", name);
828 pr_info("PCI host bridge to bus %s\n", name);
830 /* Add initial resources to the bus */
831 resource_list_for_each_entry_safe(window, n, &resources) {
832 list_move_tail(&window->node, &bridge->windows);
833 offset = window->offset;
836 if (res->flags & IORESOURCE_BUS)
837 pci_bus_insert_busn_res(bus, bus->number, res->end);
839 pci_bus_add_resource(bus, res, 0);
842 if (resource_type(res) == IORESOURCE_IO)
843 fmt = " (bus address [%#06llx-%#06llx])";
845 fmt = " (bus address [%#010llx-%#010llx])";
847 snprintf(addr, sizeof(addr), fmt,
848 (unsigned long long)(res->start - offset),
849 (unsigned long long)(res->end - offset));
853 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
856 down_write(&pci_bus_sem);
857 list_add_tail(&bus->node, &pci_root_buses);
858 up_write(&pci_bus_sem);
863 put_device(&bridge->dev);
864 device_unregister(&bridge->dev);
871 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
872 struct pci_dev *bridge, int busnr)
874 struct pci_bus *child;
878 /* Allocate a new bus and inherit stuff from the parent */
879 child = pci_alloc_bus(parent);
883 child->parent = parent;
884 child->ops = parent->ops;
885 child->msi = parent->msi;
886 child->sysdata = parent->sysdata;
887 child->bus_flags = parent->bus_flags;
890 * Initialize some portions of the bus device, but don't register
891 * it now as the parent is not properly set up yet.
893 child->dev.class = &pcibus_class;
894 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
896 /* Set up the primary, secondary and subordinate bus numbers */
897 child->number = child->busn_res.start = busnr;
898 child->primary = parent->busn_res.start;
899 child->busn_res.end = 0xff;
902 child->dev.parent = parent->bridge;
906 child->self = bridge;
907 child->bridge = get_device(&bridge->dev);
908 child->dev.parent = child->bridge;
909 pci_set_bus_of_node(child);
910 pci_set_bus_speed(child);
912 /* Set up default resource pointers and names */
913 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
914 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
915 child->resource[i]->name = child->name;
917 bridge->subordinate = child;
920 pci_set_bus_msi_domain(child);
921 ret = device_register(&child->dev);
924 pcibios_add_bus(child);
926 if (child->ops->add_bus) {
927 ret = child->ops->add_bus(child);
928 if (WARN_ON(ret < 0))
929 dev_err(&child->dev, "failed to add bus: %d\n", ret);
932 /* Create legacy_io and legacy_mem files for this bus */
933 pci_create_legacy_files(child);
938 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
941 struct pci_bus *child;
943 child = pci_alloc_child_bus(parent, dev, busnr);
945 down_write(&pci_bus_sem);
946 list_add_tail(&child->node, &parent->children);
947 up_write(&pci_bus_sem);
951 EXPORT_SYMBOL(pci_add_new_bus);
953 static void pci_enable_crs(struct pci_dev *pdev)
957 /* Enable CRS Software Visibility if supported */
958 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
959 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
960 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
961 PCI_EXP_RTCTL_CRSSVE);
964 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
965 unsigned int available_buses);
968 * pci_scan_bridge_extend() - Scan buses behind a bridge
969 * @bus: Parent bus the bridge is on
970 * @dev: Bridge itself
971 * @max: Starting subordinate number of buses behind this bridge
972 * @available_buses: Total number of buses available for this bridge and
973 * the devices below. After the minimal bus space has
974 * been allocated the remaining buses will be
975 * distributed equally between hotplug-capable bridges.
976 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
977 * that need to be reconfigured.
979 * If it's a bridge, configure it and scan the bus behind it.
980 * For CardBus bridges, we don't scan behind as the devices will
981 * be handled by the bridge driver itself.
983 * We need to process bridges in two passes -- first we scan those
984 * already configured by the BIOS and after we are done with all of
985 * them, we proceed to assigning numbers to the remaining buses in
986 * order to avoid overlaps between old and new bus numbers.
988 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
989 int max, unsigned int available_buses,
992 struct pci_bus *child;
993 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
996 u8 primary, secondary, subordinate;
1000 * Make sure the bridge is powered on to be able to access config
1001 * space of devices below it.
1003 pm_runtime_get_sync(&dev->dev);
1005 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1006 primary = buses & 0xFF;
1007 secondary = (buses >> 8) & 0xFF;
1008 subordinate = (buses >> 16) & 0xFF;
1010 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1011 secondary, subordinate, pass);
1013 if (!primary && (primary != bus->number) && secondary && subordinate) {
1014 pci_warn(dev, "Primary bus is hard wired to 0\n");
1015 primary = bus->number;
1018 /* Check if setup is sensible at all */
1020 (primary != bus->number || secondary <= bus->number ||
1021 secondary > subordinate)) {
1022 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1023 secondary, subordinate);
1028 * Disable Master-Abort Mode during probing to avoid reporting of
1029 * bus errors in some architectures.
1031 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1032 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1033 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1035 pci_enable_crs(dev);
1037 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1038 !is_cardbus && !broken) {
1042 * Bus already configured by firmware, process it in the
1043 * first pass and just note the configuration.
1049 * The bus might already exist for two reasons: Either we
1050 * are rescanning the bus or the bus is reachable through
1051 * more than one bridge. The second case can happen with
1052 * the i450NX chipset.
1054 child = pci_find_bus(pci_domain_nr(bus), secondary);
1056 child = pci_add_new_bus(bus, dev, secondary);
1059 child->primary = primary;
1060 pci_bus_insert_busn_res(child, secondary, subordinate);
1061 child->bridge_ctl = bctl;
1064 cmax = pci_scan_child_bus(child);
1065 if (cmax > subordinate)
1066 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1069 /* Subordinate should equal child->busn_res.end */
1070 if (subordinate > max)
1075 * We need to assign a number to this bus which we always
1076 * do in the second pass.
1079 if (pcibios_assign_all_busses() || broken || is_cardbus)
1082 * Temporarily disable forwarding of the
1083 * configuration cycles on all bridges in
1084 * this bus segment to avoid possible
1085 * conflicts in the second pass between two
1086 * bridges programmed with overlapping bus
1089 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1095 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1098 * Prevent assigning a bus number that already exists.
1099 * This can happen when a bridge is hot-plugged, so in this
1100 * case we only re-scan this bus.
1102 child = pci_find_bus(pci_domain_nr(bus), max+1);
1104 child = pci_add_new_bus(bus, dev, max+1);
1107 pci_bus_insert_busn_res(child, max+1,
1111 if (available_buses)
1114 buses = (buses & 0xff000000)
1115 | ((unsigned int)(child->primary) << 0)
1116 | ((unsigned int)(child->busn_res.start) << 8)
1117 | ((unsigned int)(child->busn_res.end) << 16);
1120 * yenta.c forces a secondary latency timer of 176.
1121 * Copy that behaviour here.
1124 buses &= ~0xff000000;
1125 buses |= CARDBUS_LATENCY_TIMER << 24;
1128 /* We need to blast all three values with a single write */
1129 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1132 child->bridge_ctl = bctl;
1133 max = pci_scan_child_bus_extend(child, available_buses);
1137 * For CardBus bridges, we leave 4 bus numbers as
1138 * cards with a PCI-to-PCI bridge can be inserted
1141 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1142 struct pci_bus *parent = bus;
1143 if (pci_find_bus(pci_domain_nr(bus),
1146 while (parent->parent) {
1147 if ((!pcibios_assign_all_busses()) &&
1148 (parent->busn_res.end > max) &&
1149 (parent->busn_res.end <= max+i)) {
1152 parent = parent->parent;
1157 * Often, there are two CardBus
1158 * bridges -- try to leave one
1159 * valid bus number for each one.
1168 /* Set subordinate bus number to its real value */
1169 pci_bus_update_busn_res_end(child, max);
1170 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1173 sprintf(child->name,
1174 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1175 pci_domain_nr(bus), child->number);
1177 /* Has only triggered on CardBus, fixup is in yenta_socket */
1178 while (bus->parent) {
1179 if ((child->busn_res.end > bus->busn_res.end) ||
1180 (child->number > bus->busn_res.end) ||
1181 (child->number < bus->number) ||
1182 (child->busn_res.end < bus->number)) {
1183 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
1185 (bus->number > child->busn_res.end &&
1186 bus->busn_res.end < child->number) ?
1187 "wholly" : "partially",
1188 bus->self->transparent ? " transparent" : "",
1189 dev_name(&bus->dev),
1196 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1198 pm_runtime_put(&dev->dev);
1204 * pci_scan_bridge() - Scan buses behind a bridge
1205 * @bus: Parent bus the bridge is on
1206 * @dev: Bridge itself
1207 * @max: Starting subordinate number of buses behind this bridge
1208 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1209 * that need to be reconfigured.
1211 * If it's a bridge, configure it and scan the bus behind it.
1212 * For CardBus bridges, we don't scan behind as the devices will
1213 * be handled by the bridge driver itself.
1215 * We need to process bridges in two passes -- first we scan those
1216 * already configured by the BIOS and after we are done with all of
1217 * them, we proceed to assigning numbers to the remaining buses in
1218 * order to avoid overlaps between old and new bus numbers.
1220 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1222 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1224 EXPORT_SYMBOL(pci_scan_bridge);
1227 * Read interrupt line and base address registers.
1228 * The architecture-dependent code can tweak these, of course.
1230 static void pci_read_irq(struct pci_dev *dev)
1234 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1237 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1241 void set_pcie_port_type(struct pci_dev *pdev)
1246 struct pci_dev *parent;
1248 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1252 pdev->pcie_cap = pos;
1253 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1254 pdev->pcie_flags_reg = reg16;
1255 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1256 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1259 * A Root Port or a PCI-to-PCIe bridge is always the upstream end
1260 * of a Link. No PCIe component has two Links. Two Links are
1261 * connected by a Switch that has a Port on each Link and internal
1262 * logic to connect the two Ports.
1264 type = pci_pcie_type(pdev);
1265 if (type == PCI_EXP_TYPE_ROOT_PORT ||
1266 type == PCI_EXP_TYPE_PCIE_BRIDGE)
1267 pdev->has_secondary_link = 1;
1268 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1269 type == PCI_EXP_TYPE_DOWNSTREAM) {
1270 parent = pci_upstream_bridge(pdev);
1273 * Usually there's an upstream device (Root Port or Switch
1274 * Downstream Port), but we can't assume one exists.
1276 if (parent && !parent->has_secondary_link)
1277 pdev->has_secondary_link = 1;
1281 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1285 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1286 if (reg32 & PCI_EXP_SLTCAP_HPC)
1287 pdev->is_hotplug_bridge = 1;
1290 static void set_pcie_thunderbolt(struct pci_dev *dev)
1295 while ((vsec = pci_find_next_ext_capability(dev, vsec,
1296 PCI_EXT_CAP_ID_VNDR))) {
1297 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
1299 /* Is the device part of a Thunderbolt controller? */
1300 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
1301 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
1302 dev->is_thunderbolt = 1;
1309 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1312 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1313 * when forwarding a type1 configuration request the bridge must check that
1314 * the extended register address field is zero. The bridge is not permitted
1315 * to forward the transactions and must handle it as an Unsupported Request.
1316 * Some bridges do not follow this rule and simply drop the extended register
1317 * bits, resulting in the standard config space being aliased, every 256
1318 * bytes across the entire configuration space. Test for this condition by
1319 * comparing the first dword of each potential alias to the vendor/device ID.
1321 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1322 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1324 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1326 #ifdef CONFIG_PCI_QUIRKS
1330 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1332 for (pos = PCI_CFG_SPACE_SIZE;
1333 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1334 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1346 * pci_cfg_space_size - Get the configuration space size of the PCI device
1349 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1350 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1351 * access it. Maybe we don't have a way to generate extended config space
1352 * accesses, or the device is behind a reverse Express bridge. So we try
1353 * reading the dword at 0x100 which must either be 0 or a valid extended
1354 * capability header.
1356 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1359 int pos = PCI_CFG_SPACE_SIZE;
1361 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1362 return PCI_CFG_SPACE_SIZE;
1363 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1364 return PCI_CFG_SPACE_SIZE;
1366 return PCI_CFG_SPACE_EXP_SIZE;
1369 int pci_cfg_space_size(struct pci_dev *dev)
1375 class = dev->class >> 8;
1376 if (class == PCI_CLASS_BRIDGE_HOST)
1377 return pci_cfg_space_size_ext(dev);
1379 if (pci_is_pcie(dev))
1380 return pci_cfg_space_size_ext(dev);
1382 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1384 return PCI_CFG_SPACE_SIZE;
1386 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1387 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1388 return pci_cfg_space_size_ext(dev);
1390 return PCI_CFG_SPACE_SIZE;
1393 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1395 static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1398 * Disable the MSI hardware to avoid screaming interrupts
1399 * during boot. This is the power on reset default so
1400 * usually this should be a noop.
1402 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1404 pci_msi_set_enable(dev, 0);
1406 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1408 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1412 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1415 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1416 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1418 static int pci_intx_mask_broken(struct pci_dev *dev)
1420 u16 orig, toggle, new;
1422 pci_read_config_word(dev, PCI_COMMAND, &orig);
1423 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1424 pci_write_config_word(dev, PCI_COMMAND, toggle);
1425 pci_read_config_word(dev, PCI_COMMAND, &new);
1427 pci_write_config_word(dev, PCI_COMMAND, orig);
1430 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1431 * r2.3, so strictly speaking, a device is not *broken* if it's not
1432 * writable. But we'll live with the misnomer for now.
1440 * pci_setup_device - Fill in class and map information of a device
1441 * @dev: the device structure to fill
1443 * Initialize the device structure with information about the device's
1444 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1445 * Called at initialisation of the PCI subsystem and by CardBus services.
1446 * Returns 0 on success and negative if unknown type of device (not normal,
1447 * bridge or CardBus).
1449 int pci_setup_device(struct pci_dev *dev)
1455 struct pci_bus_region region;
1456 struct resource *res;
1458 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1461 dev->sysdata = dev->bus->sysdata;
1462 dev->dev.parent = dev->bus->bridge;
1463 dev->dev.bus = &pci_bus_type;
1464 dev->hdr_type = hdr_type & 0x7f;
1465 dev->multifunction = !!(hdr_type & 0x80);
1466 dev->error_state = pci_channel_io_normal;
1467 set_pcie_port_type(dev);
1469 pci_dev_assign_slot(dev);
1472 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1473 * set this higher, assuming the system even supports it.
1475 dev->dma_mask = 0xffffffff;
1477 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1478 dev->bus->number, PCI_SLOT(dev->devfn),
1479 PCI_FUNC(dev->devfn));
1481 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1482 dev->revision = class & 0xff;
1483 dev->class = class >> 8; /* upper 3 bytes */
1485 pci_printk(KERN_DEBUG, dev, "[%04x:%04x] type %02x class %#08x\n",
1486 dev->vendor, dev->device, dev->hdr_type, dev->class);
1488 /* Need to have dev->class ready */
1489 dev->cfg_size = pci_cfg_space_size(dev);
1491 /* Need to have dev->cfg_size ready */
1492 set_pcie_thunderbolt(dev);
1494 /* "Unknown power state" */
1495 dev->current_state = PCI_UNKNOWN;
1497 /* Early fixups, before probing the BARs */
1498 pci_fixup_device(pci_fixup_early, dev);
1500 /* Device class may be changed after fixup */
1501 class = dev->class >> 8;
1503 if (dev->non_compliant_bars) {
1504 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1505 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1506 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1507 cmd &= ~PCI_COMMAND_IO;
1508 cmd &= ~PCI_COMMAND_MEMORY;
1509 pci_write_config_word(dev, PCI_COMMAND, cmd);
1513 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1515 switch (dev->hdr_type) { /* header type */
1516 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1517 if (class == PCI_CLASS_BRIDGE_PCI)
1520 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1521 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1522 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1525 * Do the ugly legacy mode stuff here rather than broken chip
1526 * quirk code. Legacy mode ATA controllers have fixed
1527 * addresses. These are not always echoed in BAR0-3, and
1528 * BAR0-3 in a few cases contain junk!
1530 if (class == PCI_CLASS_STORAGE_IDE) {
1532 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1533 if ((progif & 1) == 0) {
1534 region.start = 0x1F0;
1536 res = &dev->resource[0];
1537 res->flags = LEGACY_IO_RESOURCE;
1538 pcibios_bus_to_resource(dev->bus, res, ®ion);
1539 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1541 region.start = 0x3F6;
1543 res = &dev->resource[1];
1544 res->flags = LEGACY_IO_RESOURCE;
1545 pcibios_bus_to_resource(dev->bus, res, ®ion);
1546 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1549 if ((progif & 4) == 0) {
1550 region.start = 0x170;
1552 res = &dev->resource[2];
1553 res->flags = LEGACY_IO_RESOURCE;
1554 pcibios_bus_to_resource(dev->bus, res, ®ion);
1555 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1557 region.start = 0x376;
1559 res = &dev->resource[3];
1560 res->flags = LEGACY_IO_RESOURCE;
1561 pcibios_bus_to_resource(dev->bus, res, ®ion);
1562 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1568 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1569 if (class != PCI_CLASS_BRIDGE_PCI)
1573 * The PCI-to-PCI bridge spec requires that subtractive
1574 * decoding (i.e. transparent) bridge must have programming
1575 * interface code of 0x01.
1578 dev->transparent = ((dev->class & 0xff) == 1);
1579 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1580 set_pcie_hotplug_bridge(dev);
1581 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1583 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1584 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1588 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1589 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1592 pci_read_bases(dev, 1, 0);
1593 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1594 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1597 default: /* unknown header */
1598 pci_err(dev, "unknown header type %02x, ignoring device\n",
1603 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1604 dev->class, dev->hdr_type);
1605 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1608 /* We found a fine healthy device, go go go... */
1612 static void pci_configure_mps(struct pci_dev *dev)
1614 struct pci_dev *bridge = pci_upstream_bridge(dev);
1617 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1620 mps = pcie_get_mps(dev);
1621 p_mps = pcie_get_mps(bridge);
1626 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1627 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1628 mps, pci_name(bridge), p_mps);
1633 * Fancier MPS configuration is done later by
1634 * pcie_bus_configure_settings()
1636 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1639 rc = pcie_set_mps(dev, p_mps);
1641 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1646 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
1647 p_mps, mps, 128 << dev->pcie_mpss);
1650 static struct hpp_type0 pci_default_type0 = {
1652 .cache_line_size = 8,
1653 .latency_timer = 0x40,
1658 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1660 u16 pci_cmd, pci_bctl;
1663 hpp = &pci_default_type0;
1665 if (hpp->revision > 1) {
1666 pci_warn(dev, "PCI settings rev %d not supported; using defaults\n",
1668 hpp = &pci_default_type0;
1671 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1672 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1673 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1674 if (hpp->enable_serr)
1675 pci_cmd |= PCI_COMMAND_SERR;
1676 if (hpp->enable_perr)
1677 pci_cmd |= PCI_COMMAND_PARITY;
1678 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1680 /* Program bridge control value */
1681 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1682 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1683 hpp->latency_timer);
1684 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1685 if (hpp->enable_serr)
1686 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1687 if (hpp->enable_perr)
1688 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1689 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1693 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1700 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1704 pci_warn(dev, "PCI-X settings not supported\n");
1707 static bool pcie_root_rcb_set(struct pci_dev *dev)
1709 struct pci_dev *rp = pcie_find_root_port(dev);
1715 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1716 if (lnkctl & PCI_EXP_LNKCTL_RCB)
1722 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1730 if (!pci_is_pcie(dev))
1733 if (hpp->revision > 1) {
1734 pci_warn(dev, "PCIe settings rev %d not supported\n",
1740 * Don't allow _HPX to change MPS or MRRS settings. We manage
1741 * those to make sure they're consistent with the rest of the
1744 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1745 PCI_EXP_DEVCTL_READRQ;
1746 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1747 PCI_EXP_DEVCTL_READRQ);
1749 /* Initialize Device Control Register */
1750 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1751 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1753 /* Initialize Link Control Register */
1754 if (pcie_cap_has_lnkctl(dev)) {
1757 * If the Root Port supports Read Completion Boundary of
1758 * 128, set RCB to 128. Otherwise, clear it.
1760 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
1761 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
1762 if (pcie_root_rcb_set(dev))
1763 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
1765 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1766 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1769 /* Find Advanced Error Reporting Enhanced Capability */
1770 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1774 /* Initialize Uncorrectable Error Mask Register */
1775 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1776 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1777 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1779 /* Initialize Uncorrectable Error Severity Register */
1780 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1781 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1782 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1784 /* Initialize Correctable Error Mask Register */
1785 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1786 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1787 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1789 /* Initialize Advanced Error Capabilities and Control Register */
1790 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1791 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1793 /* Don't enable ECRC generation or checking if unsupported */
1794 if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
1795 reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
1796 if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC))
1797 reg32 &= ~PCI_ERR_CAP_ECRC_CHKE;
1798 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1801 * FIXME: The following two registers are not supported yet.
1803 * o Secondary Uncorrectable Error Severity Register
1804 * o Secondary Uncorrectable Error Mask Register
1808 int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
1810 struct pci_host_bridge *host;
1815 if (!pci_is_pcie(dev))
1818 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
1822 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
1825 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
1829 host = pci_find_host_bridge(dev->bus);
1834 * If some device in the hierarchy doesn't handle Extended Tags
1835 * correctly, make sure they're disabled.
1837 if (host->no_ext_tags) {
1838 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
1839 pci_info(dev, "disabling Extended Tags\n");
1840 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
1841 PCI_EXP_DEVCTL_EXT_TAG);
1846 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
1847 pci_info(dev, "enabling Extended Tags\n");
1848 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
1849 PCI_EXP_DEVCTL_EXT_TAG);
1855 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
1856 * @dev: PCI device to query
1858 * Returns true if the device has enabled relaxed ordering attribute.
1860 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
1864 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
1866 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
1868 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
1870 static void pci_configure_relaxed_ordering(struct pci_dev *dev)
1872 struct pci_dev *root;
1874 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
1878 if (!pcie_relaxed_ordering_enabled(dev))
1882 * For now, we only deal with Relaxed Ordering issues with Root
1883 * Ports. Peer-to-Peer DMA is another can of worms.
1885 root = pci_find_pcie_root_port(dev);
1889 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
1890 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
1891 PCI_EXP_DEVCTL_RELAX_EN);
1892 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
1896 static void pci_configure_ltr(struct pci_dev *dev)
1898 #ifdef CONFIG_PCIEASPM
1900 struct pci_dev *bridge;
1902 if (!pci_is_pcie(dev))
1905 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
1906 if (!(cap & PCI_EXP_DEVCAP2_LTR))
1910 * Software must not enable LTR in an Endpoint unless the Root
1911 * Complex and all intermediate Switches indicate support for LTR.
1912 * PCIe r3.1, sec 6.18.
1914 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
1917 bridge = pci_upstream_bridge(dev);
1918 if (bridge && bridge->ltr_path)
1923 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
1924 PCI_EXP_DEVCTL2_LTR_EN);
1928 static void pci_configure_device(struct pci_dev *dev)
1930 struct hotplug_params hpp;
1933 pci_configure_mps(dev);
1934 pci_configure_extended_tags(dev, NULL);
1935 pci_configure_relaxed_ordering(dev);
1936 pci_configure_ltr(dev);
1938 memset(&hpp, 0, sizeof(hpp));
1939 ret = pci_get_hp_params(dev, &hpp);
1943 program_hpp_type2(dev, hpp.t2);
1944 program_hpp_type1(dev, hpp.t1);
1945 program_hpp_type0(dev, hpp.t0);
1948 static void pci_release_capabilities(struct pci_dev *dev)
1950 pci_vpd_release(dev);
1951 pci_iov_release(dev);
1952 pci_free_cap_save_buffers(dev);
1956 * pci_release_dev - Free a PCI device structure when all users of it are
1958 * @dev: device that's been disconnected
1960 * Will be called only by the device core when all users of this PCI device are
1963 static void pci_release_dev(struct device *dev)
1965 struct pci_dev *pci_dev;
1967 pci_dev = to_pci_dev(dev);
1968 pci_release_capabilities(pci_dev);
1969 pci_release_of_node(pci_dev);
1970 pcibios_release_device(pci_dev);
1971 pci_bus_put(pci_dev->bus);
1972 kfree(pci_dev->driver_override);
1973 kfree(pci_dev->dma_alias_mask);
1977 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1979 struct pci_dev *dev;
1981 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1985 INIT_LIST_HEAD(&dev->bus_list);
1986 dev->dev.type = &pci_dev_type;
1987 dev->bus = pci_bus_get(bus);
1991 EXPORT_SYMBOL(pci_alloc_dev);
1993 static bool pci_bus_crs_vendor_id(u32 l)
1995 return (l & 0xffff) == 0x0001;
1998 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2003 if (!pci_bus_crs_vendor_id(*l))
2004 return true; /* not a CRS completion */
2007 return false; /* CRS, but caller doesn't want to wait */
2010 * We got the reserved Vendor ID that indicates a completion with
2011 * Configuration Request Retry Status (CRS). Retry until we get a
2012 * valid Vendor ID or we time out.
2014 while (pci_bus_crs_vendor_id(*l)) {
2015 if (delay > timeout) {
2016 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2017 pci_domain_nr(bus), bus->number,
2018 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2023 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2024 pci_domain_nr(bus), bus->number,
2025 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2030 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2035 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2036 pci_domain_nr(bus), bus->number,
2037 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2042 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2045 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2048 /* Some broken boards return 0 or ~0 if a slot is empty: */
2049 if (*l == 0xffffffff || *l == 0x00000000 ||
2050 *l == 0x0000ffff || *l == 0xffff0000)
2053 if (pci_bus_crs_vendor_id(*l))
2054 return pci_bus_wait_crs(bus, devfn, l, timeout);
2058 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2061 * Read the config data for a PCI device, sanity-check it,
2062 * and fill in the dev structure.
2064 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2066 struct pci_dev *dev;
2069 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2072 dev = pci_alloc_dev(bus);
2077 dev->vendor = l & 0xffff;
2078 dev->device = (l >> 16) & 0xffff;
2080 pci_set_of_node(dev);
2082 if (pci_setup_device(dev)) {
2083 pci_bus_put(dev->bus);
2091 static void pci_init_capabilities(struct pci_dev *dev)
2093 /* Enhanced Allocation */
2096 /* Setup MSI caps & disable MSI/MSI-X interrupts */
2097 pci_msi_setup_pci_dev(dev);
2099 /* Buffers for saving PCIe and PCI-X capabilities */
2100 pci_allocate_cap_save_buffers(dev);
2102 /* Power Management */
2105 /* Vital Product Data */
2108 /* Alternative Routing-ID Forwarding */
2109 pci_configure_ari(dev);
2111 /* Single Root I/O Virtualization */
2114 /* Address Translation Services */
2117 /* Enable ACS P2P upstream forwarding */
2118 pci_enable_acs(dev);
2120 /* Precision Time Measurement */
2123 /* Advanced Error Reporting */
2128 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2129 * devices. Firmware interfaces that can select the MSI domain on a
2130 * per-device basis should be called from here.
2132 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2134 struct irq_domain *d;
2137 * If a domain has been set through the pcibios_add_device()
2138 * callback, then this is the one (platform code knows best).
2140 d = dev_get_msi_domain(&dev->dev);
2145 * Let's see if we have a firmware interface able to provide
2148 d = pci_msi_get_device_domain(dev);
2155 static void pci_set_msi_domain(struct pci_dev *dev)
2157 struct irq_domain *d;
2160 * If the platform or firmware interfaces cannot supply a
2161 * device-specific MSI domain, then inherit the default domain
2162 * from the host bridge itself.
2164 d = pci_dev_msi_domain(dev);
2166 d = dev_get_msi_domain(&dev->bus->dev);
2168 dev_set_msi_domain(&dev->dev, d);
2171 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2175 pci_configure_device(dev);
2177 device_initialize(&dev->dev);
2178 dev->dev.release = pci_release_dev;
2180 set_dev_node(&dev->dev, pcibus_to_node(bus));
2181 dev->dev.dma_mask = &dev->dma_mask;
2182 dev->dev.dma_parms = &dev->dma_parms;
2183 dev->dev.coherent_dma_mask = 0xffffffffull;
2185 pci_set_dma_max_seg_size(dev, 65536);
2186 pci_set_dma_seg_boundary(dev, 0xffffffff);
2188 /* Fix up broken headers */
2189 pci_fixup_device(pci_fixup_header, dev);
2191 /* Moved out from quirk header fixup code */
2192 pci_reassigndev_resource_alignment(dev);
2194 /* Clear the state_saved flag */
2195 dev->state_saved = false;
2197 /* Initialize various capabilities */
2198 pci_init_capabilities(dev);
2201 * Add the device to our list of discovered devices
2202 * and the bus list for fixup functions, etc.
2204 down_write(&pci_bus_sem);
2205 list_add_tail(&dev->bus_list, &bus->devices);
2206 up_write(&pci_bus_sem);
2208 ret = pcibios_add_device(dev);
2211 /* Set up MSI IRQ domain */
2212 pci_set_msi_domain(dev);
2214 /* Notifier could use PCI capabilities */
2215 dev->match_driver = false;
2216 ret = device_add(&dev->dev);
2220 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2222 struct pci_dev *dev;
2224 dev = pci_get_slot(bus, devfn);
2230 dev = pci_scan_device(bus, devfn);
2234 pci_device_add(dev, bus);
2238 EXPORT_SYMBOL(pci_scan_single_device);
2240 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
2246 if (pci_ari_enabled(bus)) {
2249 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2253 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2254 next_fn = PCI_ARI_CAP_NFN(cap);
2256 return 0; /* protect against malformed list */
2261 /* dev may be NULL for non-contiguous multifunction devices */
2262 if (!dev || dev->multifunction)
2263 return (fn + 1) % 8;
2268 static int only_one_child(struct pci_bus *bus)
2270 struct pci_dev *bridge = bus->self;
2273 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2274 * we scan for all possible devices, not just Device 0.
2276 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2280 * A PCIe Downstream Port normally leads to a Link with only Device
2281 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2282 * only for Device 0 in that situation.
2284 * Checking has_secondary_link is a hack to identify Downstream
2285 * Ports because sometimes Switches are configured such that the
2286 * PCIe Port Type labels are backwards.
2288 if (bridge && pci_is_pcie(bridge) && bridge->has_secondary_link)
2295 * pci_scan_slot - Scan a PCI slot on a bus for devices
2296 * @bus: PCI bus to scan
2297 * @devfn: slot number to scan (must have zero function)
2299 * Scan a PCI slot on the specified PCI bus for devices, adding
2300 * discovered devices to the @bus->devices list. New devices
2301 * will not have is_added set.
2303 * Returns the number of new devices found.
2305 int pci_scan_slot(struct pci_bus *bus, int devfn)
2307 unsigned fn, nr = 0;
2308 struct pci_dev *dev;
2310 if (only_one_child(bus) && (devfn > 0))
2311 return 0; /* Already scanned the entire slot */
2313 dev = pci_scan_single_device(bus, devfn);
2319 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2320 dev = pci_scan_single_device(bus, devfn + fn);
2324 dev->multifunction = 1;
2328 /* Only one slot has PCIe device */
2329 if (bus->self && nr)
2330 pcie_aspm_init_link_state(bus->self);
2334 EXPORT_SYMBOL(pci_scan_slot);
2336 static int pcie_find_smpss(struct pci_dev *dev, void *data)
2340 if (!pci_is_pcie(dev))
2344 * We don't have a way to change MPS settings on devices that have
2345 * drivers attached. A hot-added device might support only the minimum
2346 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2347 * where devices may be hot-added, we limit the fabric MPS to 128 so
2348 * hot-added devices will work correctly.
2350 * However, if we hot-add a device to a slot directly below a Root
2351 * Port, it's impossible for there to be other existing devices below
2352 * the port. We don't limit the MPS in this case because we can
2353 * reconfigure MPS on both the Root Port and the hot-added device,
2354 * and there are no other devices involved.
2356 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2358 if (dev->is_hotplug_bridge &&
2359 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2362 if (*smpss > dev->pcie_mpss)
2363 *smpss = dev->pcie_mpss;
2368 static void pcie_write_mps(struct pci_dev *dev, int mps)
2372 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2373 mps = 128 << dev->pcie_mpss;
2375 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2379 * For "Performance", the assumption is made that
2380 * downstream communication will never be larger than
2381 * the MRRS. So, the MPS only needs to be configured
2382 * for the upstream communication. This being the case,
2383 * walk from the top down and set the MPS of the child
2384 * to that of the parent bus.
2386 * Configure the device MPS with the smaller of the
2387 * device MPSS or the bridge MPS (which is assumed to be
2388 * properly configured at this point to the largest
2389 * allowable MPS based on its parent bus).
2391 mps = min(mps, pcie_get_mps(dev->bus->self));
2394 rc = pcie_set_mps(dev, mps);
2396 pci_err(dev, "Failed attempting to set the MPS\n");
2399 static void pcie_write_mrrs(struct pci_dev *dev)
2404 * In the "safe" case, do not configure the MRRS. There appear to be
2405 * issues with setting MRRS to 0 on a number of devices.
2407 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2411 * For max performance, the MRRS must be set to the largest supported
2412 * value. However, it cannot be configured larger than the MPS the
2413 * device or the bus can support. This should already be properly
2414 * configured by a prior call to pcie_write_mps().
2416 mrrs = pcie_get_mps(dev);
2419 * MRRS is a R/W register. Invalid values can be written, but a
2420 * subsequent read will verify if the value is acceptable or not.
2421 * If the MRRS value provided is not acceptable (e.g., too large),
2422 * shrink the value until it is acceptable to the HW.
2424 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2425 rc = pcie_set_readrq(dev, mrrs);
2429 pci_warn(dev, "Failed attempting to set the MRRS\n");
2434 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2437 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2441 if (!pci_is_pcie(dev))
2444 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2445 pcie_bus_config == PCIE_BUS_DEFAULT)
2448 mps = 128 << *(u8 *)data;
2449 orig_mps = pcie_get_mps(dev);
2451 pcie_write_mps(dev, mps);
2452 pcie_write_mrrs(dev);
2454 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2455 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2456 orig_mps, pcie_get_readrq(dev));
2462 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2463 * parents then children fashion. If this changes, then this code will not
2466 void pcie_bus_configure_settings(struct pci_bus *bus)
2473 if (!pci_is_pcie(bus->self))
2477 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2478 * to be aware of the MPS of the destination. To work around this,
2479 * simply force the MPS of the entire system to the smallest possible.
2481 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2484 if (pcie_bus_config == PCIE_BUS_SAFE) {
2485 smpss = bus->self->pcie_mpss;
2487 pcie_find_smpss(bus->self, &smpss);
2488 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2491 pcie_bus_configure_set(bus->self, &smpss);
2492 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2494 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2497 * Called after each bus is probed, but before its children are examined. This
2498 * is marked as __weak because multiple architectures define it.
2500 void __weak pcibios_fixup_bus(struct pci_bus *bus)
2502 /* nothing to do, expected to be removed in the future */
2506 * pci_scan_child_bus_extend() - Scan devices below a bus
2507 * @bus: Bus to scan for devices
2508 * @available_buses: Total number of buses available (%0 does not try to
2509 * extend beyond the minimal)
2511 * Scans devices below @bus including subordinate buses. Returns new
2512 * subordinate number including all the found devices. Passing
2513 * @available_buses causes the remaining bus space to be distributed
2514 * equally between hotplug-capable bridges to allow future extension of the
2517 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2518 unsigned int available_buses)
2520 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2521 unsigned int start = bus->busn_res.start;
2522 unsigned int devfn, fn, cmax, max = start;
2523 struct pci_dev *dev;
2526 dev_dbg(&bus->dev, "scanning bus\n");
2528 /* Go find them, Rover! */
2529 for (devfn = 0; devfn < 256; devfn += 8) {
2530 nr_devs = pci_scan_slot(bus, devfn);
2533 * The Jailhouse hypervisor may pass individual functions of a
2534 * multi-function device to a guest without passing function 0.
2535 * Look for them as well.
2537 if (jailhouse_paravirt() && nr_devs == 0) {
2538 for (fn = 1; fn < 8; fn++) {
2539 dev = pci_scan_single_device(bus, devfn + fn);
2541 dev->multifunction = 1;
2546 /* Reserve buses for SR-IOV capability */
2547 used_buses = pci_iov_bus_range(bus);
2551 * After performing arch-dependent fixup of the bus, look behind
2552 * all PCI-to-PCI bridges on this bus.
2554 if (!bus->is_added) {
2555 dev_dbg(&bus->dev, "fixups for bus\n");
2556 pcibios_fixup_bus(bus);
2561 * Calculate how many hotplug bridges and normal bridges there
2562 * are on this bus. We will distribute the additional available
2563 * buses between hotplug bridges.
2565 for_each_pci_bridge(dev, bus) {
2566 if (dev->is_hotplug_bridge)
2573 * Scan bridges that are already configured. We don't touch them
2574 * unless they are misconfigured (which will be done in the second
2577 for_each_pci_bridge(dev, bus) {
2579 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2580 used_buses += cmax - max;
2583 /* Scan bridges that need to be reconfigured */
2584 for_each_pci_bridge(dev, bus) {
2585 unsigned int buses = 0;
2587 if (!hotplug_bridges && normal_bridges == 1) {
2590 * There is only one bridge on the bus (upstream
2591 * port) so it gets all available buses which it
2592 * can then distribute to the possible hotplug
2595 buses = available_buses;
2596 } else if (dev->is_hotplug_bridge) {
2599 * Distribute the extra buses between hotplug
2602 buses = available_buses / hotplug_bridges;
2603 buses = min(buses, available_buses - used_buses);
2607 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
2608 used_buses += max - cmax;
2612 * Make sure a hotplug bridge has at least the minimum requested
2613 * number of buses but allow it to grow up to the maximum available
2614 * bus number of there is room.
2616 if (bus->self && bus->self->is_hotplug_bridge) {
2617 used_buses = max_t(unsigned int, available_buses,
2618 pci_hotplug_bus_size - 1);
2619 if (max - start < used_buses) {
2620 max = start + used_buses;
2622 /* Do not allocate more buses than we have room left */
2623 if (max > bus->busn_res.end)
2624 max = bus->busn_res.end;
2626 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
2627 &bus->busn_res, max - start);
2632 * We've scanned the bus and so we know all about what's on
2633 * the other side of any bridges that may be on this bus plus
2636 * Return how far we've got finding sub-buses.
2638 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2643 * pci_scan_child_bus() - Scan devices below a bus
2644 * @bus: Bus to scan for devices
2646 * Scans devices below @bus including subordinate buses. Returns new
2647 * subordinate number including all the found devices.
2649 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2651 return pci_scan_child_bus_extend(bus, 0);
2653 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2656 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
2657 * @bridge: Host bridge to set up
2659 * Default empty implementation. Replace with an architecture-specific setup
2660 * routine, if necessary.
2662 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2667 void __weak pcibios_add_bus(struct pci_bus *bus)
2671 void __weak pcibios_remove_bus(struct pci_bus *bus)
2675 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2676 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2679 struct pci_host_bridge *bridge;
2681 bridge = pci_alloc_host_bridge(0);
2685 bridge->dev.parent = parent;
2687 list_splice_init(resources, &bridge->windows);
2688 bridge->sysdata = sysdata;
2689 bridge->busnr = bus;
2692 error = pci_register_host_bridge(bridge);
2702 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2704 int pci_host_probe(struct pci_host_bridge *bridge)
2706 struct pci_bus *bus, *child;
2709 ret = pci_scan_root_bus_bridge(bridge);
2711 dev_err(bridge->dev.parent, "Scanning root bridge failed");
2718 * We insert PCI resources into the iomem_resource and
2719 * ioport_resource trees in either pci_bus_claim_resources()
2720 * or pci_bus_assign_resources().
2722 if (pci_has_flag(PCI_PROBE_ONLY)) {
2723 pci_bus_claim_resources(bus);
2725 pci_bus_size_bridges(bus);
2726 pci_bus_assign_resources(bus);
2728 list_for_each_entry(child, &bus->children, node)
2729 pcie_bus_configure_settings(child);
2732 pci_bus_add_devices(bus);
2735 EXPORT_SYMBOL_GPL(pci_host_probe);
2737 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2739 struct resource *res = &b->busn_res;
2740 struct resource *parent_res, *conflict;
2744 res->flags = IORESOURCE_BUS;
2746 if (!pci_is_root_bus(b))
2747 parent_res = &b->parent->busn_res;
2749 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2750 res->flags |= IORESOURCE_PCI_FIXED;
2753 conflict = request_resource_conflict(parent_res, res);
2756 dev_printk(KERN_DEBUG, &b->dev,
2757 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2758 res, pci_is_root_bus(b) ? "domain " : "",
2759 parent_res, conflict->name, conflict);
2761 return conflict == NULL;
2764 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2766 struct resource *res = &b->busn_res;
2767 struct resource old_res = *res;
2768 resource_size_t size;
2771 if (res->start > bus_max)
2774 size = bus_max - res->start + 1;
2775 ret = adjust_resource(res, res->start, size);
2776 dev_printk(KERN_DEBUG, &b->dev,
2777 "busn_res: %pR end %s updated to %02x\n",
2778 &old_res, ret ? "can not be" : "is", bus_max);
2780 if (!ret && !res->parent)
2781 pci_bus_insert_busn_res(b, res->start, res->end);
2786 void pci_bus_release_busn_res(struct pci_bus *b)
2788 struct resource *res = &b->busn_res;
2791 if (!res->flags || !res->parent)
2794 ret = release_resource(res);
2795 dev_printk(KERN_DEBUG, &b->dev,
2796 "busn_res: %pR %s released\n",
2797 res, ret ? "can not be" : "is");
2800 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
2802 struct resource_entry *window;
2810 resource_list_for_each_entry(window, &bridge->windows)
2811 if (window->res->flags & IORESOURCE_BUS) {
2816 ret = pci_register_host_bridge(bridge);
2821 bus = bridge->busnr;
2825 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2827 pci_bus_insert_busn_res(b, bus, 255);
2830 max = pci_scan_child_bus(b);
2833 pci_bus_update_busn_res_end(b, max);
2837 EXPORT_SYMBOL(pci_scan_root_bus_bridge);
2839 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2840 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2842 struct resource_entry *window;
2847 resource_list_for_each_entry(window, resources)
2848 if (window->res->flags & IORESOURCE_BUS) {
2853 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2859 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2861 pci_bus_insert_busn_res(b, bus, 255);
2864 max = pci_scan_child_bus(b);
2867 pci_bus_update_busn_res_end(b, max);
2871 EXPORT_SYMBOL(pci_scan_root_bus);
2873 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2876 LIST_HEAD(resources);
2879 pci_add_resource(&resources, &ioport_resource);
2880 pci_add_resource(&resources, &iomem_resource);
2881 pci_add_resource(&resources, &busn_resource);
2882 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2884 pci_scan_child_bus(b);
2886 pci_free_resource_list(&resources);
2890 EXPORT_SYMBOL(pci_scan_bus);
2893 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
2894 * @bridge: PCI bridge for the bus to scan
2896 * Scan a PCI bus and child buses for new devices, add them,
2897 * and enable them, resizing bridge mmio/io resource if necessary
2898 * and possible. The caller must ensure the child devices are already
2899 * removed for resizing to occur.
2901 * Returns the max number of subordinate bus discovered.
2903 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2906 struct pci_bus *bus = bridge->subordinate;
2908 max = pci_scan_child_bus(bus);
2910 pci_assign_unassigned_bridge_resources(bridge);
2912 pci_bus_add_devices(bus);
2918 * pci_rescan_bus - Scan a PCI bus for devices
2919 * @bus: PCI bus to scan
2921 * Scan a PCI bus and child buses for new devices, add them,
2924 * Returns the max number of subordinate bus discovered.
2926 unsigned int pci_rescan_bus(struct pci_bus *bus)
2930 max = pci_scan_child_bus(bus);
2931 pci_assign_unassigned_bus_resources(bus);
2932 pci_bus_add_devices(bus);
2936 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2939 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2940 * routines should always be executed under this mutex.
2942 static DEFINE_MUTEX(pci_rescan_remove_lock);
2944 void pci_lock_rescan_remove(void)
2946 mutex_lock(&pci_rescan_remove_lock);
2948 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2950 void pci_unlock_rescan_remove(void)
2952 mutex_unlock(&pci_rescan_remove_lock);
2954 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2956 static int __init pci_sort_bf_cmp(const struct device *d_a,
2957 const struct device *d_b)
2959 const struct pci_dev *a = to_pci_dev(d_a);
2960 const struct pci_dev *b = to_pci_dev(d_b);
2962 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2963 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2965 if (a->bus->number < b->bus->number) return -1;
2966 else if (a->bus->number > b->bus->number) return 1;
2968 if (a->devfn < b->devfn) return -1;
2969 else if (a->devfn > b->devfn) return 1;
2974 void __init pci_sort_breadthfirst(void)
2976 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
2979 int pci_hp_add_bridge(struct pci_dev *dev)
2981 struct pci_bus *parent = dev->bus;
2982 int busnr, start = parent->busn_res.start;
2983 unsigned int available_buses = 0;
2984 int end = parent->busn_res.end;
2986 for (busnr = start; busnr <= end; busnr++) {
2987 if (!pci_find_bus(pci_domain_nr(parent), busnr))
2990 if (busnr-- > end) {
2991 pci_err(dev, "No bus number available for hot-added bridge\n");
2995 /* Scan bridges that are already configured */
2996 busnr = pci_scan_bridge(parent, dev, busnr, 0);
2999 * Distribute the available bus numbers between hotplug-capable
3000 * bridges to make extending the chain later possible.
3002 available_buses = end - busnr;
3004 /* Scan bridges that need to be reconfigured */
3005 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3007 if (!dev->subordinate)
3012 EXPORT_SYMBOL_GPL(pci_hp_add_bridge);