1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Express Precision Time Measurement
4 * Copyright (c) 2016, Intel Corporation.
7 #include <linux/module.h>
8 #include <linux/init.h>
12 static void pci_ptm_info(struct pci_dev *dev)
16 switch (dev->ptm_granularity) {
18 snprintf(clock_desc, sizeof(clock_desc), "unknown");
21 snprintf(clock_desc, sizeof(clock_desc), ">254ns");
24 snprintf(clock_desc, sizeof(clock_desc), "%uns",
25 dev->ptm_granularity);
28 pci_info(dev, "PTM enabled%s, %s granularity\n",
29 dev->ptm_root ? " (root)" : "", clock_desc);
32 void pci_disable_ptm(struct pci_dev *dev)
37 if (!pci_is_pcie(dev))
40 ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
44 pci_read_config_word(dev, ptm + PCI_PTM_CTRL, &ctrl);
45 ctrl &= ~(PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT);
46 pci_write_config_word(dev, ptm + PCI_PTM_CTRL, ctrl);
49 void pci_save_ptm_state(struct pci_dev *dev)
52 struct pci_cap_saved_state *save_state;
55 if (!pci_is_pcie(dev))
58 ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
62 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_PTM);
64 pci_err(dev, "no suspend buffer for PTM\n");
68 cap = (u16 *)&save_state->cap.data[0];
69 pci_read_config_word(dev, ptm + PCI_PTM_CTRL, cap);
72 void pci_restore_ptm_state(struct pci_dev *dev)
74 struct pci_cap_saved_state *save_state;
78 if (!pci_is_pcie(dev))
81 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_PTM);
82 ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
83 if (!save_state || !ptm)
86 cap = (u16 *)&save_state->cap.data[0];
87 pci_write_config_word(dev, ptm + PCI_PTM_CTRL, *cap);
90 void pci_ptm_init(struct pci_dev *dev)
97 if (!pci_is_pcie(dev))
101 * Enable PTM only on interior devices (root ports, switch ports,
102 * etc.) on the assumption that it causes no link traffic until an
103 * endpoint enables it.
105 if ((pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT ||
106 pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END))
110 * Switch Downstream Ports are not permitted to have a PTM
111 * capability; their PTM behavior is controlled by the Upstream
112 * Port (PCIe r5.0, sec 7.9.16).
114 ups = pci_upstream_bridge(dev);
115 if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM &&
116 ups && ups->ptm_enabled) {
117 dev->ptm_granularity = ups->ptm_granularity;
118 dev->ptm_enabled = 1;
122 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
126 pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_PTM, sizeof(u16));
128 pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
129 local_clock = (cap & PCI_PTM_GRANULARITY_MASK) >> 8;
132 * There's no point in enabling PTM unless it's enabled in the
133 * upstream device or this device can be a PTM Root itself. Per
134 * the spec recommendation (PCIe r3.1, sec 7.32.3), select the
135 * furthest upstream Time Source as the PTM Root.
137 if (ups && ups->ptm_enabled) {
138 ctrl = PCI_PTM_CTRL_ENABLE;
139 if (ups->ptm_granularity == 0)
140 dev->ptm_granularity = 0;
141 else if (ups->ptm_granularity > local_clock)
142 dev->ptm_granularity = ups->ptm_granularity;
144 if (cap & PCI_PTM_CAP_ROOT) {
145 ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT;
147 dev->ptm_granularity = local_clock;
152 ctrl |= dev->ptm_granularity << 8;
153 pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
154 dev->ptm_enabled = 1;
159 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
165 if (!pci_is_pcie(dev))
168 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
172 pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
173 if (!(cap & PCI_PTM_CAP_REQ))
177 * For a PCIe Endpoint, PTM is only useful if the endpoint can
178 * issue PTM requests to upstream devices that have PTM enabled.
180 * For Root Complex Integrated Endpoints, there is no upstream
181 * device, so there must be some implementation-specific way to
182 * associate the endpoint with a time source.
184 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT) {
185 ups = pci_upstream_bridge(dev);
186 if (!ups || !ups->ptm_enabled)
189 dev->ptm_granularity = ups->ptm_granularity;
190 } else if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
191 dev->ptm_granularity = 0;
195 ctrl = PCI_PTM_CTRL_ENABLE;
196 ctrl |= dev->ptm_granularity << 8;
197 pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
198 dev->ptm_enabled = 1;
203 *granularity = dev->ptm_granularity;
206 EXPORT_SYMBOL(pci_enable_ptm);