1 /* SPDX-License-Identifier: GPL-2.0 */
7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
8 #define MAX_NR_DEVFNS 256
10 #define PCI_FIND_CAP_TTL 48
12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
14 extern const unsigned char pcie_link_speed[];
15 extern bool pci_early_dump;
17 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
18 bool pcie_cap_has_rtctl(const struct pci_dev *dev);
20 /* Functions internal to the PCI core code */
22 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
23 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
24 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
25 static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
27 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
30 void pci_create_firmware_label_files(struct pci_dev *pdev);
31 void pci_remove_firmware_label_files(struct pci_dev *pdev);
33 void pci_cleanup_rom(struct pci_dev *dev);
36 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
37 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
39 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
40 enum pci_mmap_api mmap_api);
42 int pci_probe_reset_function(struct pci_dev *dev);
43 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
44 int pci_bus_error_reset(struct pci_dev *dev);
46 #define PCI_PM_D2_DELAY 200
47 #define PCI_PM_D3_WAIT 10
48 #define PCI_PM_D3COLD_WAIT 100
49 #define PCI_PM_BUS_WAIT 50
52 * struct pci_platform_pm_ops - Firmware PM callbacks
54 * @bridge_d3: Does the bridge allow entering into D3
56 * @is_manageable: returns 'true' if given device is power manageable by the
59 * @set_state: invokes the platform firmware to set the device's power state
61 * @get_state: queries the platform firmware for a device's current power state
63 * @refresh_state: asks the platform to refresh the device's power state data
65 * @choose_state: returns PCI power state of given device preferred by the
66 * platform; to be used during system-wide transitions from a
67 * sleeping state to the working state and vice versa
69 * @set_wakeup: enables/disables wakeup capability for the device
71 * @need_resume: returns 'true' if the given device (which is currently
72 * suspended) needs to be resumed to be configured for system
75 * If given platform is generally capable of power managing PCI devices, all of
76 * these callbacks are mandatory.
78 struct pci_platform_pm_ops {
79 bool (*bridge_d3)(struct pci_dev *dev);
80 bool (*is_manageable)(struct pci_dev *dev);
81 int (*set_state)(struct pci_dev *dev, pci_power_t state);
82 pci_power_t (*get_state)(struct pci_dev *dev);
83 void (*refresh_state)(struct pci_dev *dev);
84 pci_power_t (*choose_state)(struct pci_dev *dev);
85 int (*set_wakeup)(struct pci_dev *dev, bool enable);
86 bool (*need_resume)(struct pci_dev *dev);
89 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
90 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
91 void pci_refresh_power_state(struct pci_dev *dev);
92 int pci_power_up(struct pci_dev *dev);
93 void pci_disable_enabled_device(struct pci_dev *dev);
94 int pci_finish_runtime_suspend(struct pci_dev *dev);
95 void pcie_clear_device_status(struct pci_dev *dev);
96 void pcie_clear_root_pme_status(struct pci_dev *dev);
97 bool pci_check_pme_status(struct pci_dev *dev);
98 void pci_pme_wakeup_bus(struct pci_bus *bus);
99 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
100 void pci_pme_restore(struct pci_dev *dev);
101 bool pci_dev_need_resume(struct pci_dev *dev);
102 void pci_dev_adjust_pme(struct pci_dev *dev);
103 void pci_dev_complete_resume(struct pci_dev *pci_dev);
104 void pci_config_pm_runtime_get(struct pci_dev *dev);
105 void pci_config_pm_runtime_put(struct pci_dev *dev);
106 void pci_pm_init(struct pci_dev *dev);
107 void pci_ea_init(struct pci_dev *dev);
108 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
109 void pci_free_cap_save_buffers(struct pci_dev *dev);
110 bool pci_bridge_d3_possible(struct pci_dev *dev);
111 void pci_bridge_d3_update(struct pci_dev *dev);
112 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev);
114 static inline void pci_wakeup_event(struct pci_dev *dev)
116 /* Wait 100 ms before the system can be put into a sleep state. */
117 pm_wakeup_event(&dev->dev, 100);
120 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
122 return !!(pci_dev->subordinate);
125 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
128 * Currently we allow normal PCI devices and PCI bridges transition
129 * into D3 if their bridge_d3 is set.
131 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
134 static inline bool pcie_downstream_port(const struct pci_dev *dev)
136 int type = pci_pcie_type(dev);
138 return type == PCI_EXP_TYPE_ROOT_PORT ||
139 type == PCI_EXP_TYPE_DOWNSTREAM ||
140 type == PCI_EXP_TYPE_PCIE_BRIDGE;
143 int pci_vpd_init(struct pci_dev *dev);
144 void pci_vpd_release(struct pci_dev *dev);
145 void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
146 void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
148 /* PCI Virtual Channel */
149 int pci_save_vc_state(struct pci_dev *dev);
150 void pci_restore_vc_state(struct pci_dev *dev);
151 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
153 /* PCI /proc functions */
154 #ifdef CONFIG_PROC_FS
155 int pci_proc_attach_device(struct pci_dev *dev);
156 int pci_proc_detach_device(struct pci_dev *dev);
157 int pci_proc_detach_bus(struct pci_bus *bus);
159 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
160 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
161 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
164 /* Functions for PCI Hotplug drivers to use */
165 int pci_hp_add_bridge(struct pci_dev *dev);
167 #ifdef HAVE_PCI_LEGACY
168 void pci_create_legacy_files(struct pci_bus *bus);
169 void pci_remove_legacy_files(struct pci_bus *bus);
171 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
172 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
175 /* Lock for read/write access to pci device and bus lists */
176 extern struct rw_semaphore pci_bus_sem;
177 extern struct mutex pci_slot_mutex;
179 extern raw_spinlock_t pci_lock;
181 extern unsigned int pci_pm_d3_delay;
183 #ifdef CONFIG_PCI_MSI
184 void pci_no_msi(void);
186 static inline void pci_no_msi(void) { }
189 static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
193 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
194 control &= ~PCI_MSI_FLAGS_ENABLE;
196 control |= PCI_MSI_FLAGS_ENABLE;
197 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
200 static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
204 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
207 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
210 void pci_realloc_get_opt(char *);
212 static inline int pci_no_d1d2(struct pci_dev *dev)
214 unsigned int parent_dstates = 0;
217 parent_dstates = dev->bus->self->no_d1d2;
218 return (dev->no_d1d2 || parent_dstates);
221 extern const struct attribute_group *pci_dev_groups[];
222 extern const struct attribute_group *pcibus_groups[];
223 extern const struct device_type pci_dev_type;
224 extern const struct attribute_group *pci_bus_groups[];
226 extern unsigned long pci_hotplug_io_size;
227 extern unsigned long pci_hotplug_mmio_size;
228 extern unsigned long pci_hotplug_mmio_pref_size;
229 extern unsigned long pci_hotplug_bus_size;
232 * pci_match_one_device - Tell if a PCI device structure has a matching
233 * PCI device id structure
234 * @id: single PCI device id structure to match
235 * @dev: the PCI device structure to match against
237 * Returns the matching pci_device_id structure or %NULL if there is no match.
239 static inline const struct pci_device_id *
240 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
242 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
243 (id->device == PCI_ANY_ID || id->device == dev->device) &&
244 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
245 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
246 !((id->class ^ dev->class) & id->class_mask))
251 /* PCI slot sysfs helper code */
252 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
254 extern struct kset *pci_slots_kset;
256 struct pci_slot_attribute {
257 struct attribute attr;
258 ssize_t (*show)(struct pci_slot *, char *);
259 ssize_t (*store)(struct pci_slot *, const char *, size_t);
261 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
264 pci_bar_unknown, /* Standard PCI BAR probe */
265 pci_bar_io, /* An I/O port BAR */
266 pci_bar_mem32, /* A 32-bit memory BAR */
267 pci_bar_mem64, /* A 64-bit memory BAR */
270 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
271 void pci_put_host_bridge_device(struct device *dev);
273 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
274 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
276 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
278 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
280 int pci_setup_device(struct pci_dev *dev);
281 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
282 struct resource *res, unsigned int reg);
283 void pci_configure_ari(struct pci_dev *dev);
284 void __pci_bus_size_bridges(struct pci_bus *bus,
285 struct list_head *realloc_head);
286 void __pci_bus_assign_resources(const struct pci_bus *bus,
287 struct list_head *realloc_head,
288 struct list_head *fail_head);
289 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
291 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
292 void pci_disable_bridge_window(struct pci_dev *dev);
293 struct pci_bus *pci_bus_get(struct pci_bus *bus);
294 void pci_bus_put(struct pci_bus *bus);
296 /* PCIe link information from Link Capabilities 2 */
297 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
298 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
299 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
300 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
301 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
302 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
305 /* PCIe speed to Mb/s reduced by encoding overhead */
306 #define PCIE_SPEED2MBS_ENC(speed) \
307 ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
308 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
309 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
310 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
311 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
314 const char *pci_speed_string(enum pci_bus_speed speed);
315 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
316 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
317 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
318 enum pcie_link_width *width);
319 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
320 void pcie_report_downtraining(struct pci_dev *dev);
321 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
323 /* Single Root I/O Virtualization */
325 int pos; /* Capability position */
326 int nres; /* Number of resources */
327 u32 cap; /* SR-IOV Capabilities */
328 u16 ctrl; /* SR-IOV Control */
329 u16 total_VFs; /* Total VFs associated with the PF */
330 u16 initial_VFs; /* Initial VFs associated with the PF */
331 u16 num_VFs; /* Number of VFs available */
332 u16 offset; /* First VF Routing ID offset */
333 u16 stride; /* Following VF stride */
334 u16 vf_device; /* VF device ID */
335 u32 pgsz; /* Page size for BAR alignment */
336 u8 link; /* Function Dependency Link */
337 u8 max_VF_buses; /* Max buses consumed by VFs */
338 u16 driver_max_VFs; /* Max num VFs driver supports */
339 struct pci_dev *dev; /* Lowest numbered PF */
340 struct pci_dev *self; /* This PF */
341 u32 class; /* VF device */
342 u8 hdr_type; /* VF header type */
343 u16 subsystem_vendor; /* VF subsystem vendor */
344 u16 subsystem_device; /* VF subsystem device */
345 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
346 bool drivers_autoprobe; /* Auto probing of VFs by driver */
350 * pci_dev_set_io_state - Set the new error state if possible.
352 * @dev - pci device to set new error_state
353 * @new - the state we want dev to be in
355 * Must be called with device_lock held.
357 * Returns true if state has been changed to the requested state.
359 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
360 pci_channel_state_t new)
362 bool changed = false;
364 device_lock_assert(&dev->dev);
366 case pci_channel_io_perm_failure:
367 switch (dev->error_state) {
368 case pci_channel_io_frozen:
369 case pci_channel_io_normal:
370 case pci_channel_io_perm_failure:
375 case pci_channel_io_frozen:
376 switch (dev->error_state) {
377 case pci_channel_io_frozen:
378 case pci_channel_io_normal:
383 case pci_channel_io_normal:
384 switch (dev->error_state) {
385 case pci_channel_io_frozen:
386 case pci_channel_io_normal:
393 dev->error_state = new;
397 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
399 device_lock(&dev->dev);
400 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
401 device_unlock(&dev->dev);
406 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
408 return dev->error_state == pci_channel_io_perm_failure;
411 /* pci_dev priv_flags */
412 #define PCI_DEV_ADDED 0
414 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
416 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
419 static inline bool pci_dev_is_added(const struct pci_dev *dev)
421 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
424 #ifdef CONFIG_PCIEAER
425 #include <linux/aer.h>
427 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
429 struct aer_err_info {
430 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
435 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
436 unsigned int __pad1:5;
437 unsigned int multi_error_valid:1;
439 unsigned int first_error:5;
440 unsigned int __pad2:2;
441 unsigned int tlp_header_valid:1;
443 unsigned int status; /* COR/UNCOR Error Status */
444 unsigned int mask; /* COR/UNCOR Error Mask */
445 struct aer_header_log_regs tlp; /* TLP Header */
448 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
449 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
450 #endif /* CONFIG_PCIEAER */
452 #ifdef CONFIG_PCIE_DPC
453 void pci_save_dpc_state(struct pci_dev *dev);
454 void pci_restore_dpc_state(struct pci_dev *dev);
455 void pci_dpc_init(struct pci_dev *pdev);
456 void dpc_process_error(struct pci_dev *pdev);
457 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
459 static inline void pci_save_dpc_state(struct pci_dev *dev) {}
460 static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
461 static inline void pci_dpc_init(struct pci_dev *pdev) {}
464 #ifdef CONFIG_PCI_ATS
465 /* Address Translation Service */
466 void pci_ats_init(struct pci_dev *dev);
467 void pci_restore_ats_state(struct pci_dev *dev);
469 static inline void pci_ats_init(struct pci_dev *d) { }
470 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
471 #endif /* CONFIG_PCI_ATS */
473 #ifdef CONFIG_PCI_PRI
474 void pci_pri_init(struct pci_dev *dev);
475 void pci_restore_pri_state(struct pci_dev *pdev);
477 static inline void pci_pri_init(struct pci_dev *dev) { }
478 static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
481 #ifdef CONFIG_PCI_PASID
482 void pci_pasid_init(struct pci_dev *dev);
483 void pci_restore_pasid_state(struct pci_dev *pdev);
485 static inline void pci_pasid_init(struct pci_dev *dev) { }
486 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
489 #ifdef CONFIG_PCI_IOV
490 int pci_iov_init(struct pci_dev *dev);
491 void pci_iov_release(struct pci_dev *dev);
492 void pci_iov_remove(struct pci_dev *dev);
493 void pci_iov_update_resource(struct pci_dev *dev, int resno);
494 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
495 void pci_restore_iov_state(struct pci_dev *dev);
496 int pci_iov_bus_range(struct pci_bus *bus);
497 extern const struct attribute_group sriov_dev_attr_group;
499 static inline int pci_iov_init(struct pci_dev *dev)
503 static inline void pci_iov_release(struct pci_dev *dev)
507 static inline void pci_iov_remove(struct pci_dev *dev)
510 static inline void pci_restore_iov_state(struct pci_dev *dev)
513 static inline int pci_iov_bus_range(struct pci_bus *bus)
518 #endif /* CONFIG_PCI_IOV */
520 unsigned long pci_cardbus_resource_alignment(struct resource *);
522 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
523 struct resource *res)
525 #ifdef CONFIG_PCI_IOV
526 int resno = res - dev->resource;
528 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
529 return pci_sriov_resource_alignment(dev, resno);
531 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
532 return pci_cardbus_resource_alignment(res);
533 return resource_alignment(res);
536 void pci_acs_init(struct pci_dev *dev);
537 #ifdef CONFIG_PCI_QUIRKS
538 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
539 int pci_dev_specific_enable_acs(struct pci_dev *dev);
540 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
542 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
547 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
551 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
557 /* PCI error reporting and recovery */
558 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
559 pci_channel_state_t state,
560 pci_ers_result_t (*reset_link)(struct pci_dev *pdev));
562 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
563 #ifdef CONFIG_PCIEASPM
564 void pcie_aspm_init_link_state(struct pci_dev *pdev);
565 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
566 void pcie_aspm_pm_state_change(struct pci_dev *pdev);
567 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
569 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
570 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
571 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
572 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
575 #ifdef CONFIG_PCIE_ECRC
576 void pcie_set_ecrc_checking(struct pci_dev *dev);
577 void pcie_ecrc_get_policy(char *str);
579 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
580 static inline void pcie_ecrc_get_policy(char *str) { }
583 #ifdef CONFIG_PCIE_PTM
584 void pci_ptm_init(struct pci_dev *dev);
585 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
587 static inline void pci_ptm_init(struct pci_dev *dev) { }
588 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
592 struct pci_dev_reset_methods {
595 int (*reset)(struct pci_dev *dev, int probe);
598 #ifdef CONFIG_PCI_QUIRKS
599 int pci_dev_specific_reset(struct pci_dev *dev, int probe);
601 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
607 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
608 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
609 struct resource *res);
612 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
613 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
614 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
615 static inline u64 pci_rebar_size_to_bytes(int size)
617 return 1ULL << (size + 20);
623 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
624 int of_get_pci_domain_nr(struct device_node *node);
625 int of_pci_get_max_link_speed(struct device_node *node);
626 void pci_set_of_node(struct pci_dev *dev);
627 void pci_release_of_node(struct pci_dev *dev);
628 void pci_set_bus_of_node(struct pci_bus *bus);
629 void pci_release_bus_of_node(struct pci_bus *bus);
631 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
635 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
641 of_get_pci_domain_nr(struct device_node *node)
647 of_pci_get_max_link_speed(struct device_node *node)
652 static inline void pci_set_of_node(struct pci_dev *dev) { }
653 static inline void pci_release_of_node(struct pci_dev *dev) { }
654 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
655 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
657 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
662 #endif /* CONFIG_OF */
664 #ifdef CONFIG_PCIEAER
665 void pci_no_aer(void);
666 void pci_aer_init(struct pci_dev *dev);
667 void pci_aer_exit(struct pci_dev *dev);
668 extern const struct attribute_group aer_stats_attr_group;
669 void pci_aer_clear_fatal_status(struct pci_dev *dev);
670 int pci_aer_clear_status(struct pci_dev *dev);
671 int pci_aer_raw_clear_status(struct pci_dev *dev);
673 static inline void pci_no_aer(void) { }
674 static inline void pci_aer_init(struct pci_dev *d) { }
675 static inline void pci_aer_exit(struct pci_dev *d) { }
676 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
677 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
678 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
682 int pci_acpi_program_hp_params(struct pci_dev *dev);
684 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
690 #ifdef CONFIG_PCIEASPM
691 extern const struct attribute_group aspm_ctrl_attr_group;
694 #endif /* DRIVERS_PCI_H */