1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
17 #include <linux/of_pci.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/pci-aspm.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pci-ats.h>
33 #include <asm/setup.h>
35 #include <linux/aer.h>
38 const char *pci_power_names[] = {
39 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
41 EXPORT_SYMBOL_GPL(pci_power_names);
43 int isa_dma_bridge_buggy;
44 EXPORT_SYMBOL(isa_dma_bridge_buggy);
47 EXPORT_SYMBOL(pci_pci_problems);
49 unsigned int pci_pm_d3_delay;
51 static void pci_pme_list_scan(struct work_struct *work);
53 static LIST_HEAD(pci_pme_list);
54 static DEFINE_MUTEX(pci_pme_list_mutex);
55 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
57 struct pci_pme_device {
58 struct list_head list;
62 #define PME_TIMEOUT 1000 /* How long between PME checks */
64 static void pci_dev_d3_sleep(struct pci_dev *dev)
66 unsigned int delay = dev->d3_delay;
68 if (delay < pci_pm_d3_delay)
69 delay = pci_pm_d3_delay;
75 #ifdef CONFIG_PCI_DOMAINS
76 int pci_domains_supported = 1;
79 #define DEFAULT_CARDBUS_IO_SIZE (256)
80 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
81 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
82 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
83 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
85 #define DEFAULT_HOTPLUG_IO_SIZE (256)
86 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
87 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
88 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
89 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
91 #define DEFAULT_HOTPLUG_BUS_SIZE 1
92 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
94 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
97 * The default CLS is used if arch didn't set CLS explicitly and not
98 * all pci devices agree on the same value. Arch can override either
99 * the dfl or actual value as it sees fit. Don't forget this is
100 * measured in 32-bit words, not bytes.
102 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
103 u8 pci_cache_line_size;
106 * If we set up a device for bus mastering, we need to check the latency
107 * timer as certain BIOSes forget to set it properly.
109 unsigned int pcibios_max_latency = 255;
111 /* If set, the PCIe ARI capability will not be used. */
112 static bool pcie_ari_disabled;
114 /* Disable bridge_d3 for all PCIe ports */
115 static bool pci_bridge_d3_disable;
116 /* Force bridge_d3 for all PCIe ports */
117 static bool pci_bridge_d3_force;
119 static int __init pcie_port_pm_setup(char *str)
121 if (!strcmp(str, "off"))
122 pci_bridge_d3_disable = true;
123 else if (!strcmp(str, "force"))
124 pci_bridge_d3_force = true;
127 __setup("pcie_port_pm=", pcie_port_pm_setup);
130 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
131 * @bus: pointer to PCI bus structure to search
133 * Given a PCI bus, returns the highest PCI bus number present in the set
134 * including the given PCI bus and its list of child PCI buses.
136 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
139 unsigned char max, n;
141 max = bus->busn_res.end;
142 list_for_each_entry(tmp, &bus->children, node) {
143 n = pci_bus_max_busnr(tmp);
149 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
151 #ifdef CONFIG_HAS_IOMEM
152 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
154 struct resource *res = &pdev->resource[bar];
157 * Make sure the BAR is actually a memory resource, not an IO resource
159 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
160 pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
163 return ioremap_nocache(res->start, resource_size(res));
165 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
167 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
170 * Make sure the BAR is actually a memory resource, not an IO resource
172 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
176 return ioremap_wc(pci_resource_start(pdev, bar),
177 pci_resource_len(pdev, bar));
179 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
183 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
184 u8 pos, int cap, int *ttl)
189 pci_bus_read_config_byte(bus, devfn, pos, &pos);
195 pci_bus_read_config_word(bus, devfn, pos, &ent);
207 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
210 int ttl = PCI_FIND_CAP_TTL;
212 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
215 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
217 return __pci_find_next_cap(dev->bus, dev->devfn,
218 pos + PCI_CAP_LIST_NEXT, cap);
220 EXPORT_SYMBOL_GPL(pci_find_next_capability);
222 static int __pci_bus_find_cap_start(struct pci_bus *bus,
223 unsigned int devfn, u8 hdr_type)
227 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
228 if (!(status & PCI_STATUS_CAP_LIST))
232 case PCI_HEADER_TYPE_NORMAL:
233 case PCI_HEADER_TYPE_BRIDGE:
234 return PCI_CAPABILITY_LIST;
235 case PCI_HEADER_TYPE_CARDBUS:
236 return PCI_CB_CAPABILITY_LIST;
243 * pci_find_capability - query for devices' capabilities
244 * @dev: PCI device to query
245 * @cap: capability code
247 * Tell if a device supports a given PCI capability.
248 * Returns the address of the requested capability structure within the
249 * device's PCI configuration space or 0 in case the device does not
250 * support it. Possible values for @cap:
252 * %PCI_CAP_ID_PM Power Management
253 * %PCI_CAP_ID_AGP Accelerated Graphics Port
254 * %PCI_CAP_ID_VPD Vital Product Data
255 * %PCI_CAP_ID_SLOTID Slot Identification
256 * %PCI_CAP_ID_MSI Message Signalled Interrupts
257 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
258 * %PCI_CAP_ID_PCIX PCI-X
259 * %PCI_CAP_ID_EXP PCI Express
261 int pci_find_capability(struct pci_dev *dev, int cap)
265 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
267 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
271 EXPORT_SYMBOL(pci_find_capability);
274 * pci_bus_find_capability - query for devices' capabilities
275 * @bus: the PCI bus to query
276 * @devfn: PCI device to query
277 * @cap: capability code
279 * Like pci_find_capability() but works for pci devices that do not have a
280 * pci_dev structure set up yet.
282 * Returns the address of the requested capability structure within the
283 * device's PCI configuration space or 0 in case the device does not
286 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
291 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
293 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
295 pos = __pci_find_next_cap(bus, devfn, pos, cap);
299 EXPORT_SYMBOL(pci_bus_find_capability);
302 * pci_find_next_ext_capability - Find an extended capability
303 * @dev: PCI device to query
304 * @start: address at which to start looking (0 to start at beginning of list)
305 * @cap: capability code
307 * Returns the address of the next matching extended capability structure
308 * within the device's PCI configuration space or 0 if the device does
309 * not support it. Some capabilities can occur several times, e.g., the
310 * vendor-specific capability, and this provides a way to find them all.
312 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
316 int pos = PCI_CFG_SPACE_SIZE;
318 /* minimum 8 bytes per capability */
319 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
321 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
327 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
331 * If we have no capabilities, this is indicated by cap ID,
332 * cap version and next pointer all being 0.
338 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
341 pos = PCI_EXT_CAP_NEXT(header);
342 if (pos < PCI_CFG_SPACE_SIZE)
345 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
351 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
354 * pci_find_ext_capability - Find an extended capability
355 * @dev: PCI device to query
356 * @cap: capability code
358 * Returns the address of the requested extended capability structure
359 * within the device's PCI configuration space or 0 if the device does
360 * not support it. Possible values for @cap:
362 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
363 * %PCI_EXT_CAP_ID_VC Virtual Channel
364 * %PCI_EXT_CAP_ID_DSN Device Serial Number
365 * %PCI_EXT_CAP_ID_PWR Power Budgeting
367 int pci_find_ext_capability(struct pci_dev *dev, int cap)
369 return pci_find_next_ext_capability(dev, 0, cap);
371 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
373 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
375 int rc, ttl = PCI_FIND_CAP_TTL;
378 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
379 mask = HT_3BIT_CAP_MASK;
381 mask = HT_5BIT_CAP_MASK;
383 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
384 PCI_CAP_ID_HT, &ttl);
386 rc = pci_read_config_byte(dev, pos + 3, &cap);
387 if (rc != PCIBIOS_SUCCESSFUL)
390 if ((cap & mask) == ht_cap)
393 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
394 pos + PCI_CAP_LIST_NEXT,
395 PCI_CAP_ID_HT, &ttl);
401 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
402 * @dev: PCI device to query
403 * @pos: Position from which to continue searching
404 * @ht_cap: Hypertransport capability code
406 * To be used in conjunction with pci_find_ht_capability() to search for
407 * all capabilities matching @ht_cap. @pos should always be a value returned
408 * from pci_find_ht_capability().
410 * NB. To be 100% safe against broken PCI devices, the caller should take
411 * steps to avoid an infinite loop.
413 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
415 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
417 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
420 * pci_find_ht_capability - query a device's Hypertransport capabilities
421 * @dev: PCI device to query
422 * @ht_cap: Hypertransport capability code
424 * Tell if a device supports a given Hypertransport capability.
425 * Returns an address within the device's PCI configuration space
426 * or 0 in case the device does not support the request capability.
427 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
428 * which has a Hypertransport capability matching @ht_cap.
430 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
434 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
436 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
440 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
443 * pci_find_parent_resource - return resource region of parent bus of given region
444 * @dev: PCI device structure contains resources to be searched
445 * @res: child resource record for which parent is sought
447 * For given resource region of given device, return the resource
448 * region of parent bus the given region is contained in.
450 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
451 struct resource *res)
453 const struct pci_bus *bus = dev->bus;
457 pci_bus_for_each_resource(bus, r, i) {
460 if (resource_contains(r, res)) {
463 * If the window is prefetchable but the BAR is
464 * not, the allocator made a mistake.
466 if (r->flags & IORESOURCE_PREFETCH &&
467 !(res->flags & IORESOURCE_PREFETCH))
471 * If we're below a transparent bridge, there may
472 * be both a positively-decoded aperture and a
473 * subtractively-decoded region that contain the BAR.
474 * We want the positively-decoded one, so this depends
475 * on pci_bus_for_each_resource() giving us those
483 EXPORT_SYMBOL(pci_find_parent_resource);
486 * pci_find_resource - Return matching PCI device resource
487 * @dev: PCI device to query
488 * @res: Resource to look for
490 * Goes over standard PCI resources (BARs) and checks if the given resource
491 * is partially or fully contained in any of them. In that case the
492 * matching resource is returned, %NULL otherwise.
494 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
498 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
499 struct resource *r = &dev->resource[i];
501 if (r->start && resource_contains(r, res))
507 EXPORT_SYMBOL(pci_find_resource);
510 * pci_find_pcie_root_port - return PCIe Root Port
511 * @dev: PCI device to query
513 * Traverse up the parent chain and return the PCIe Root Port PCI Device
514 * for a given PCI Device.
516 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
518 struct pci_dev *bridge, *highest_pcie_bridge = dev;
520 bridge = pci_upstream_bridge(dev);
521 while (bridge && pci_is_pcie(bridge)) {
522 highest_pcie_bridge = bridge;
523 bridge = pci_upstream_bridge(bridge);
526 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
529 return highest_pcie_bridge;
531 EXPORT_SYMBOL(pci_find_pcie_root_port);
534 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
535 * @dev: the PCI device to operate on
536 * @pos: config space offset of status word
537 * @mask: mask of bit(s) to care about in status word
539 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
541 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
545 /* Wait for Transaction Pending bit clean */
546 for (i = 0; i < 4; i++) {
549 msleep((1 << (i - 1)) * 100);
551 pci_read_config_word(dev, pos, &status);
552 if (!(status & mask))
560 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
561 * @dev: PCI device to have its BARs restored
563 * Restore the BAR values for a given device, so as to make it
564 * accessible by its driver.
566 static void pci_restore_bars(struct pci_dev *dev)
570 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
571 pci_update_resource(dev, i);
574 static const struct pci_platform_pm_ops *pci_platform_pm;
576 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
578 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
579 !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
581 pci_platform_pm = ops;
585 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
587 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
590 static inline int platform_pci_set_power_state(struct pci_dev *dev,
593 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
596 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
598 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
601 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
603 return pci_platform_pm ?
604 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
607 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
609 return pci_platform_pm ?
610 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
613 static inline bool platform_pci_need_resume(struct pci_dev *dev)
615 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
619 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
621 * @dev: PCI device to handle.
622 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
625 * -EINVAL if the requested state is invalid.
626 * -EIO if device does not support PCI PM or its PM capabilities register has a
627 * wrong version, or device doesn't support the requested state.
628 * 0 if device already is in the requested state.
629 * 0 if device's power state has been successfully changed.
631 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
634 bool need_restore = false;
636 /* Check if we're already there */
637 if (dev->current_state == state)
643 if (state < PCI_D0 || state > PCI_D3hot)
646 /* Validate current state:
647 * Can enter D0 from any state, but if we can only go deeper
648 * to sleep if we're already in a low power state
650 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
651 && dev->current_state > state) {
652 pci_err(dev, "invalid power transition (from state %d to %d)\n",
653 dev->current_state, state);
657 /* check if this device supports the desired state */
658 if ((state == PCI_D1 && !dev->d1_support)
659 || (state == PCI_D2 && !dev->d2_support))
662 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
664 /* If we're (effectively) in D3, force entire word to 0.
665 * This doesn't affect PME_Status, disables PME_En, and
666 * sets PowerState to 0.
668 switch (dev->current_state) {
672 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
677 case PCI_UNKNOWN: /* Boot-up */
678 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
679 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
681 /* Fall-through: force to D0 */
687 /* enter specified state */
688 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
690 /* Mandatory power management transition delays */
691 /* see PCI PM 1.1 5.6.1 table 18 */
692 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
693 pci_dev_d3_sleep(dev);
694 else if (state == PCI_D2 || dev->current_state == PCI_D2)
695 udelay(PCI_PM_D2_DELAY);
697 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
698 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
699 if (dev->current_state != state && printk_ratelimit())
700 pci_info(dev, "Refused to change power state, currently in D%d\n",
704 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
705 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
706 * from D3hot to D0 _may_ perform an internal reset, thereby
707 * going to "D0 Uninitialized" rather than "D0 Initialized".
708 * For example, at least some versions of the 3c905B and the
709 * 3c556B exhibit this behaviour.
711 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
712 * devices in a D3hot state at boot. Consequently, we need to
713 * restore at least the BARs so that the device will be
714 * accessible to its driver.
717 pci_restore_bars(dev);
720 pcie_aspm_pm_state_change(dev->bus->self);
726 * pci_update_current_state - Read power state of given device and cache it
727 * @dev: PCI device to handle.
728 * @state: State to cache in case the device doesn't have the PM capability
730 * The power state is read from the PMCSR register, which however is
731 * inaccessible in D3cold. The platform firmware is therefore queried first
732 * to detect accessibility of the register. In case the platform firmware
733 * reports an incorrect state or the device isn't power manageable by the
734 * platform at all, we try to detect D3cold by testing accessibility of the
735 * vendor ID in config space.
737 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
739 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
740 !pci_device_is_present(dev)) {
741 dev->current_state = PCI_D3cold;
742 } else if (dev->pm_cap) {
745 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
746 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
748 dev->current_state = state;
753 * pci_power_up - Put the given device into D0 forcibly
754 * @dev: PCI device to power up
756 void pci_power_up(struct pci_dev *dev)
758 if (platform_pci_power_manageable(dev))
759 platform_pci_set_power_state(dev, PCI_D0);
761 pci_raw_set_power_state(dev, PCI_D0);
762 pci_update_current_state(dev, PCI_D0);
766 * pci_platform_power_transition - Use platform to change device power state
767 * @dev: PCI device to handle.
768 * @state: State to put the device into.
770 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
774 if (platform_pci_power_manageable(dev)) {
775 error = platform_pci_set_power_state(dev, state);
777 pci_update_current_state(dev, state);
781 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
782 dev->current_state = PCI_D0;
788 * pci_wakeup - Wake up a PCI device
789 * @pci_dev: Device to handle.
790 * @ign: ignored parameter
792 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
794 pci_wakeup_event(pci_dev);
795 pm_request_resume(&pci_dev->dev);
800 * pci_wakeup_bus - Walk given bus and wake up devices on it
801 * @bus: Top bus of the subtree to walk.
803 void pci_wakeup_bus(struct pci_bus *bus)
806 pci_walk_bus(bus, pci_wakeup, NULL);
810 * __pci_start_power_transition - Start power transition of a PCI device
811 * @dev: PCI device to handle.
812 * @state: State to put the device into.
814 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
816 if (state == PCI_D0) {
817 pci_platform_power_transition(dev, PCI_D0);
819 * Mandatory power management transition delays, see
820 * PCI Express Base Specification Revision 2.0 Section
821 * 6.6.1: Conventional Reset. Do not delay for
822 * devices powered on/off by corresponding bridge,
823 * because have already delayed for the bridge.
825 if (dev->runtime_d3cold) {
826 if (dev->d3cold_delay)
827 msleep(dev->d3cold_delay);
829 * When powering on a bridge from D3cold, the
830 * whole hierarchy may be powered on into
831 * D0uninitialized state, resume them to give
832 * them a chance to suspend again
834 pci_wakeup_bus(dev->subordinate);
840 * __pci_dev_set_current_state - Set current state of a PCI device
841 * @dev: Device to handle
842 * @data: pointer to state to be set
844 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
846 pci_power_t state = *(pci_power_t *)data;
848 dev->current_state = state;
853 * pci_bus_set_current_state - Walk given bus and set current state of devices
854 * @bus: Top bus of the subtree to walk.
855 * @state: state to be set
857 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
860 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
864 * __pci_complete_power_transition - Complete power transition of a PCI device
865 * @dev: PCI device to handle.
866 * @state: State to put the device into.
868 * This function should not be called directly by device drivers.
870 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
876 ret = pci_platform_power_transition(dev, state);
877 /* Power off the bridge may power off the whole hierarchy */
878 if (!ret && state == PCI_D3cold)
879 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
882 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
885 * pci_set_power_state - Set the power state of a PCI device
886 * @dev: PCI device to handle.
887 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
889 * Transition a device to a new power state, using the platform firmware and/or
890 * the device's PCI PM registers.
893 * -EINVAL if the requested state is invalid.
894 * -EIO if device does not support PCI PM or its PM capabilities register has a
895 * wrong version, or device doesn't support the requested state.
896 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
897 * 0 if device already is in the requested state.
898 * 0 if the transition is to D3 but D3 is not supported.
899 * 0 if device's power state has been successfully changed.
901 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
905 /* bound the state we're entering */
906 if (state > PCI_D3cold)
908 else if (state < PCI_D0)
910 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
912 * If the device or the parent bridge do not support PCI PM,
913 * ignore the request if we're doing anything other than putting
914 * it into D0 (which would only happen on boot).
918 /* Check if we're already there */
919 if (dev->current_state == state)
922 __pci_start_power_transition(dev, state);
924 /* This device is quirked not to be put into D3, so
925 don't put it in D3 */
926 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
930 * To put device in D3cold, we put device into D3hot in native
931 * way, then put device into D3cold with platform ops
933 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
936 if (!__pci_complete_power_transition(dev, state))
941 EXPORT_SYMBOL(pci_set_power_state);
944 * pci_choose_state - Choose the power state of a PCI device
945 * @dev: PCI device to be suspended
946 * @state: target sleep state for the whole system. This is the value
947 * that is passed to suspend() function.
949 * Returns PCI power state suitable for given device and given system
953 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
960 ret = platform_pci_choose_state(dev);
961 if (ret != PCI_POWER_ERROR)
964 switch (state.event) {
967 case PM_EVENT_FREEZE:
968 case PM_EVENT_PRETHAW:
969 /* REVISIT both freeze and pre-thaw "should" use D0 */
970 case PM_EVENT_SUSPEND:
971 case PM_EVENT_HIBERNATE:
974 pci_info(dev, "unrecognized suspend event %d\n",
980 EXPORT_SYMBOL(pci_choose_state);
982 #define PCI_EXP_SAVE_REGS 7
984 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
985 u16 cap, bool extended)
987 struct pci_cap_saved_state *tmp;
989 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
990 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
996 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
998 return _pci_find_saved_cap(dev, cap, false);
1001 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1003 return _pci_find_saved_cap(dev, cap, true);
1006 static int pci_save_pcie_state(struct pci_dev *dev)
1009 struct pci_cap_saved_state *save_state;
1012 if (!pci_is_pcie(dev))
1015 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1017 pci_err(dev, "buffer not found in %s\n", __func__);
1021 cap = (u16 *)&save_state->cap.data[0];
1022 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1023 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1024 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1025 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1026 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1027 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1028 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1033 static void pci_restore_pcie_state(struct pci_dev *dev)
1036 struct pci_cap_saved_state *save_state;
1039 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1043 cap = (u16 *)&save_state->cap.data[0];
1044 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1045 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1046 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1047 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1048 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1049 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1050 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1054 static int pci_save_pcix_state(struct pci_dev *dev)
1057 struct pci_cap_saved_state *save_state;
1059 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1063 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1065 pci_err(dev, "buffer not found in %s\n", __func__);
1069 pci_read_config_word(dev, pos + PCI_X_CMD,
1070 (u16 *)save_state->cap.data);
1075 static void pci_restore_pcix_state(struct pci_dev *dev)
1078 struct pci_cap_saved_state *save_state;
1081 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1082 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1083 if (!save_state || !pos)
1085 cap = (u16 *)&save_state->cap.data[0];
1087 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1092 * pci_save_state - save the PCI configuration space of a device before suspending
1093 * @dev: - PCI device that we're dealing with
1095 int pci_save_state(struct pci_dev *dev)
1098 /* XXX: 100% dword access ok here? */
1099 for (i = 0; i < 16; i++)
1100 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1101 dev->state_saved = true;
1103 i = pci_save_pcie_state(dev);
1107 i = pci_save_pcix_state(dev);
1111 return pci_save_vc_state(dev);
1113 EXPORT_SYMBOL(pci_save_state);
1115 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1116 u32 saved_val, int retry)
1120 pci_read_config_dword(pdev, offset, &val);
1121 if (val == saved_val)
1125 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1126 offset, val, saved_val);
1127 pci_write_config_dword(pdev, offset, saved_val);
1131 pci_read_config_dword(pdev, offset, &val);
1132 if (val == saved_val)
1139 static void pci_restore_config_space_range(struct pci_dev *pdev,
1140 int start, int end, int retry)
1144 for (index = end; index >= start; index--)
1145 pci_restore_config_dword(pdev, 4 * index,
1146 pdev->saved_config_space[index],
1150 static void pci_restore_config_space(struct pci_dev *pdev)
1152 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1153 pci_restore_config_space_range(pdev, 10, 15, 0);
1154 /* Restore BARs before the command register. */
1155 pci_restore_config_space_range(pdev, 4, 9, 10);
1156 pci_restore_config_space_range(pdev, 0, 3, 0);
1158 pci_restore_config_space_range(pdev, 0, 15, 0);
1163 * pci_restore_state - Restore the saved state of a PCI device
1164 * @dev: - PCI device that we're dealing with
1166 void pci_restore_state(struct pci_dev *dev)
1168 if (!dev->state_saved)
1171 /* PCI Express register must be restored first */
1172 pci_restore_pcie_state(dev);
1173 pci_restore_pasid_state(dev);
1174 pci_restore_pri_state(dev);
1175 pci_restore_ats_state(dev);
1176 pci_restore_vc_state(dev);
1178 pci_cleanup_aer_error_status_regs(dev);
1180 pci_restore_config_space(dev);
1182 pci_restore_pcix_state(dev);
1183 pci_restore_msi_state(dev);
1185 /* Restore ACS and IOV configuration state */
1186 pci_enable_acs(dev);
1187 pci_restore_iov_state(dev);
1189 dev->state_saved = false;
1191 EXPORT_SYMBOL(pci_restore_state);
1193 struct pci_saved_state {
1194 u32 config_space[16];
1195 struct pci_cap_saved_data cap[0];
1199 * pci_store_saved_state - Allocate and return an opaque struct containing
1200 * the device saved state.
1201 * @dev: PCI device that we're dealing with
1203 * Return NULL if no state or error.
1205 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1207 struct pci_saved_state *state;
1208 struct pci_cap_saved_state *tmp;
1209 struct pci_cap_saved_data *cap;
1212 if (!dev->state_saved)
1215 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1217 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1218 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1220 state = kzalloc(size, GFP_KERNEL);
1224 memcpy(state->config_space, dev->saved_config_space,
1225 sizeof(state->config_space));
1228 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1229 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1230 memcpy(cap, &tmp->cap, len);
1231 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1233 /* Empty cap_save terminates list */
1237 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1240 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1241 * @dev: PCI device that we're dealing with
1242 * @state: Saved state returned from pci_store_saved_state()
1244 int pci_load_saved_state(struct pci_dev *dev,
1245 struct pci_saved_state *state)
1247 struct pci_cap_saved_data *cap;
1249 dev->state_saved = false;
1254 memcpy(dev->saved_config_space, state->config_space,
1255 sizeof(state->config_space));
1259 struct pci_cap_saved_state *tmp;
1261 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1262 if (!tmp || tmp->cap.size != cap->size)
1265 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1266 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1267 sizeof(struct pci_cap_saved_data) + cap->size);
1270 dev->state_saved = true;
1273 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1276 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1277 * and free the memory allocated for it.
1278 * @dev: PCI device that we're dealing with
1279 * @state: Pointer to saved state returned from pci_store_saved_state()
1281 int pci_load_and_free_saved_state(struct pci_dev *dev,
1282 struct pci_saved_state **state)
1284 int ret = pci_load_saved_state(dev, *state);
1289 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1291 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1293 return pci_enable_resources(dev, bars);
1296 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1299 struct pci_dev *bridge;
1303 err = pci_set_power_state(dev, PCI_D0);
1304 if (err < 0 && err != -EIO)
1307 bridge = pci_upstream_bridge(dev);
1309 pcie_aspm_powersave_config_link(bridge);
1311 err = pcibios_enable_device(dev, bars);
1314 pci_fixup_device(pci_fixup_enable, dev);
1316 if (dev->msi_enabled || dev->msix_enabled)
1319 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1321 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1322 if (cmd & PCI_COMMAND_INTX_DISABLE)
1323 pci_write_config_word(dev, PCI_COMMAND,
1324 cmd & ~PCI_COMMAND_INTX_DISABLE);
1331 * pci_reenable_device - Resume abandoned device
1332 * @dev: PCI device to be resumed
1334 * Note this function is a backend of pci_default_resume and is not supposed
1335 * to be called by normal code, write proper resume handler and use it instead.
1337 int pci_reenable_device(struct pci_dev *dev)
1339 if (pci_is_enabled(dev))
1340 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1343 EXPORT_SYMBOL(pci_reenable_device);
1345 static void pci_enable_bridge(struct pci_dev *dev)
1347 struct pci_dev *bridge;
1350 bridge = pci_upstream_bridge(dev);
1352 pci_enable_bridge(bridge);
1354 if (pci_is_enabled(dev)) {
1355 if (!dev->is_busmaster)
1356 pci_set_master(dev);
1360 retval = pci_enable_device(dev);
1362 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1364 pci_set_master(dev);
1367 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1369 struct pci_dev *bridge;
1374 * Power state could be unknown at this point, either due to a fresh
1375 * boot or a device removal call. So get the current power state
1376 * so that things like MSI message writing will behave as expected
1377 * (e.g. if the device really is in D0 at enable time).
1381 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1382 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1385 if (atomic_inc_return(&dev->enable_cnt) > 1)
1386 return 0; /* already enabled */
1388 bridge = pci_upstream_bridge(dev);
1390 pci_enable_bridge(bridge);
1392 /* only skip sriov related */
1393 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1394 if (dev->resource[i].flags & flags)
1396 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1397 if (dev->resource[i].flags & flags)
1400 err = do_pci_enable_device(dev, bars);
1402 atomic_dec(&dev->enable_cnt);
1407 * pci_enable_device_io - Initialize a device for use with IO space
1408 * @dev: PCI device to be initialized
1410 * Initialize device before it's used by a driver. Ask low-level code
1411 * to enable I/O resources. Wake up the device if it was suspended.
1412 * Beware, this function can fail.
1414 int pci_enable_device_io(struct pci_dev *dev)
1416 return pci_enable_device_flags(dev, IORESOURCE_IO);
1418 EXPORT_SYMBOL(pci_enable_device_io);
1421 * pci_enable_device_mem - Initialize a device for use with Memory space
1422 * @dev: PCI device to be initialized
1424 * Initialize device before it's used by a driver. Ask low-level code
1425 * to enable Memory resources. Wake up the device if it was suspended.
1426 * Beware, this function can fail.
1428 int pci_enable_device_mem(struct pci_dev *dev)
1430 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1432 EXPORT_SYMBOL(pci_enable_device_mem);
1435 * pci_enable_device - Initialize device before it's used by a driver.
1436 * @dev: PCI device to be initialized
1438 * Initialize device before it's used by a driver. Ask low-level code
1439 * to enable I/O and memory. Wake up the device if it was suspended.
1440 * Beware, this function can fail.
1442 * Note we don't actually enable the device many times if we call
1443 * this function repeatedly (we just increment the count).
1445 int pci_enable_device(struct pci_dev *dev)
1447 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1449 EXPORT_SYMBOL(pci_enable_device);
1452 * Managed PCI resources. This manages device on/off, intx/msi/msix
1453 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1454 * there's no need to track it separately. pci_devres is initialized
1455 * when a device is enabled using managed PCI device enable interface.
1458 unsigned int enabled:1;
1459 unsigned int pinned:1;
1460 unsigned int orig_intx:1;
1461 unsigned int restore_intx:1;
1466 static void pcim_release(struct device *gendev, void *res)
1468 struct pci_dev *dev = to_pci_dev(gendev);
1469 struct pci_devres *this = res;
1472 if (dev->msi_enabled)
1473 pci_disable_msi(dev);
1474 if (dev->msix_enabled)
1475 pci_disable_msix(dev);
1477 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1478 if (this->region_mask & (1 << i))
1479 pci_release_region(dev, i);
1484 if (this->restore_intx)
1485 pci_intx(dev, this->orig_intx);
1487 if (this->enabled && !this->pinned)
1488 pci_disable_device(dev);
1491 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1493 struct pci_devres *dr, *new_dr;
1495 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1499 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1502 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1505 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1507 if (pci_is_managed(pdev))
1508 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1513 * pcim_enable_device - Managed pci_enable_device()
1514 * @pdev: PCI device to be initialized
1516 * Managed pci_enable_device().
1518 int pcim_enable_device(struct pci_dev *pdev)
1520 struct pci_devres *dr;
1523 dr = get_pci_dr(pdev);
1529 rc = pci_enable_device(pdev);
1531 pdev->is_managed = 1;
1536 EXPORT_SYMBOL(pcim_enable_device);
1539 * pcim_pin_device - Pin managed PCI device
1540 * @pdev: PCI device to pin
1542 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1543 * driver detach. @pdev must have been enabled with
1544 * pcim_enable_device().
1546 void pcim_pin_device(struct pci_dev *pdev)
1548 struct pci_devres *dr;
1550 dr = find_pci_dr(pdev);
1551 WARN_ON(!dr || !dr->enabled);
1555 EXPORT_SYMBOL(pcim_pin_device);
1558 * pcibios_add_device - provide arch specific hooks when adding device dev
1559 * @dev: the PCI device being added
1561 * Permits the platform to provide architecture specific functionality when
1562 * devices are added. This is the default implementation. Architecture
1563 * implementations can override this.
1565 int __weak pcibios_add_device(struct pci_dev *dev)
1571 * pcibios_release_device - provide arch specific hooks when releasing device dev
1572 * @dev: the PCI device being released
1574 * Permits the platform to provide architecture specific functionality when
1575 * devices are released. This is the default implementation. Architecture
1576 * implementations can override this.
1578 void __weak pcibios_release_device(struct pci_dev *dev) {}
1581 * pcibios_disable_device - disable arch specific PCI resources for device dev
1582 * @dev: the PCI device to disable
1584 * Disables architecture specific PCI resources for the device. This
1585 * is the default implementation. Architecture implementations can
1588 void __weak pcibios_disable_device(struct pci_dev *dev) {}
1591 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1592 * @irq: ISA IRQ to penalize
1593 * @active: IRQ active or not
1595 * Permits the platform to provide architecture-specific functionality when
1596 * penalizing ISA IRQs. This is the default implementation. Architecture
1597 * implementations can override this.
1599 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1601 static void do_pci_disable_device(struct pci_dev *dev)
1605 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1606 if (pci_command & PCI_COMMAND_MASTER) {
1607 pci_command &= ~PCI_COMMAND_MASTER;
1608 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1611 pcibios_disable_device(dev);
1615 * pci_disable_enabled_device - Disable device without updating enable_cnt
1616 * @dev: PCI device to disable
1618 * NOTE: This function is a backend of PCI power management routines and is
1619 * not supposed to be called drivers.
1621 void pci_disable_enabled_device(struct pci_dev *dev)
1623 if (pci_is_enabled(dev))
1624 do_pci_disable_device(dev);
1628 * pci_disable_device - Disable PCI device after use
1629 * @dev: PCI device to be disabled
1631 * Signal to the system that the PCI device is not in use by the system
1632 * anymore. This only involves disabling PCI bus-mastering, if active.
1634 * Note we don't actually disable the device until all callers of
1635 * pci_enable_device() have called pci_disable_device().
1637 void pci_disable_device(struct pci_dev *dev)
1639 struct pci_devres *dr;
1641 dr = find_pci_dr(dev);
1645 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1646 "disabling already-disabled device");
1648 if (atomic_dec_return(&dev->enable_cnt) != 0)
1651 do_pci_disable_device(dev);
1653 dev->is_busmaster = 0;
1655 EXPORT_SYMBOL(pci_disable_device);
1658 * pcibios_set_pcie_reset_state - set reset state for device dev
1659 * @dev: the PCIe device reset
1660 * @state: Reset state to enter into
1663 * Sets the PCIe reset state for the device. This is the default
1664 * implementation. Architecture implementations can override this.
1666 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1667 enum pcie_reset_state state)
1673 * pci_set_pcie_reset_state - set reset state for device dev
1674 * @dev: the PCIe device reset
1675 * @state: Reset state to enter into
1678 * Sets the PCI reset state for the device.
1680 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1682 return pcibios_set_pcie_reset_state(dev, state);
1684 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1687 * pci_check_pme_status - Check if given device has generated PME.
1688 * @dev: Device to check.
1690 * Check the PME status of the device and if set, clear it and clear PME enable
1691 * (if set). Return 'true' if PME status and PME enable were both set or
1692 * 'false' otherwise.
1694 bool pci_check_pme_status(struct pci_dev *dev)
1703 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1704 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1705 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1708 /* Clear PME status. */
1709 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1710 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1711 /* Disable PME to avoid interrupt flood. */
1712 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1716 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1722 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1723 * @dev: Device to handle.
1724 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1726 * Check if @dev has generated PME and queue a resume request for it in that
1729 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1731 if (pme_poll_reset && dev->pme_poll)
1732 dev->pme_poll = false;
1734 if (pci_check_pme_status(dev)) {
1735 pci_wakeup_event(dev);
1736 pm_request_resume(&dev->dev);
1742 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1743 * @bus: Top bus of the subtree to walk.
1745 void pci_pme_wakeup_bus(struct pci_bus *bus)
1748 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1753 * pci_pme_capable - check the capability of PCI device to generate PME#
1754 * @dev: PCI device to handle.
1755 * @state: PCI state from which device will issue PME#.
1757 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1762 return !!(dev->pme_support & (1 << state));
1764 EXPORT_SYMBOL(pci_pme_capable);
1766 static void pci_pme_list_scan(struct work_struct *work)
1768 struct pci_pme_device *pme_dev, *n;
1770 mutex_lock(&pci_pme_list_mutex);
1771 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1772 if (pme_dev->dev->pme_poll) {
1773 struct pci_dev *bridge;
1775 bridge = pme_dev->dev->bus->self;
1777 * If bridge is in low power state, the
1778 * configuration space of subordinate devices
1779 * may be not accessible
1781 if (bridge && bridge->current_state != PCI_D0)
1783 pci_pme_wakeup(pme_dev->dev, NULL);
1785 list_del(&pme_dev->list);
1789 if (!list_empty(&pci_pme_list))
1790 queue_delayed_work(system_freezable_wq, &pci_pme_work,
1791 msecs_to_jiffies(PME_TIMEOUT));
1792 mutex_unlock(&pci_pme_list_mutex);
1795 static void __pci_pme_active(struct pci_dev *dev, bool enable)
1799 if (!dev->pme_support)
1802 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1803 /* Clear PME_Status by writing 1 to it and enable PME# */
1804 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1806 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1808 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1812 * pci_pme_restore - Restore PME configuration after config space restore.
1813 * @dev: PCI device to update.
1815 void pci_pme_restore(struct pci_dev *dev)
1819 if (!dev->pme_support)
1822 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1823 if (dev->wakeup_prepared) {
1824 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
1825 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
1827 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1828 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1830 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1834 * pci_pme_active - enable or disable PCI device's PME# function
1835 * @dev: PCI device to handle.
1836 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1838 * The caller must verify that the device is capable of generating PME# before
1839 * calling this function with @enable equal to 'true'.
1841 void pci_pme_active(struct pci_dev *dev, bool enable)
1843 __pci_pme_active(dev, enable);
1846 * PCI (as opposed to PCIe) PME requires that the device have
1847 * its PME# line hooked up correctly. Not all hardware vendors
1848 * do this, so the PME never gets delivered and the device
1849 * remains asleep. The easiest way around this is to
1850 * periodically walk the list of suspended devices and check
1851 * whether any have their PME flag set. The assumption is that
1852 * we'll wake up often enough anyway that this won't be a huge
1853 * hit, and the power savings from the devices will still be a
1856 * Although PCIe uses in-band PME message instead of PME# line
1857 * to report PME, PME does not work for some PCIe devices in
1858 * reality. For example, there are devices that set their PME
1859 * status bits, but don't really bother to send a PME message;
1860 * there are PCI Express Root Ports that don't bother to
1861 * trigger interrupts when they receive PME messages from the
1862 * devices below. So PME poll is used for PCIe devices too.
1865 if (dev->pme_poll) {
1866 struct pci_pme_device *pme_dev;
1868 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1871 pci_warn(dev, "can't enable PME#\n");
1875 mutex_lock(&pci_pme_list_mutex);
1876 list_add(&pme_dev->list, &pci_pme_list);
1877 if (list_is_singular(&pci_pme_list))
1878 queue_delayed_work(system_freezable_wq,
1880 msecs_to_jiffies(PME_TIMEOUT));
1881 mutex_unlock(&pci_pme_list_mutex);
1883 mutex_lock(&pci_pme_list_mutex);
1884 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1885 if (pme_dev->dev == dev) {
1886 list_del(&pme_dev->list);
1891 mutex_unlock(&pci_pme_list_mutex);
1895 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
1897 EXPORT_SYMBOL(pci_pme_active);
1900 * pci_enable_wake - enable PCI device as wakeup event source
1901 * @dev: PCI device affected
1902 * @state: PCI state from which device will issue wakeup events
1903 * @enable: True to enable event generation; false to disable
1905 * This enables the device as a wakeup event source, or disables it.
1906 * When such events involves platform-specific hooks, those hooks are
1907 * called automatically by this routine.
1909 * Devices with legacy power management (no standard PCI PM capabilities)
1910 * always require such platform hooks.
1913 * 0 is returned on success
1914 * -EINVAL is returned if device is not supposed to wake up the system
1915 * Error code depending on the platform is returned if both the platform and
1916 * the native mechanism fail to enable the generation of wake-up events
1918 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
1923 * Bridges can only signal wakeup on behalf of subordinate devices,
1924 * but that is set up elsewhere, so skip them.
1926 if (pci_has_subordinate(dev))
1929 /* Don't do the same thing twice in a row for one device. */
1930 if (!!enable == !!dev->wakeup_prepared)
1934 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1935 * Anderson we should be doing PME# wake enable followed by ACPI wake
1936 * enable. To disable wake-up we call the platform first, for symmetry.
1942 if (pci_pme_capable(dev, state))
1943 pci_pme_active(dev, true);
1946 error = platform_pci_set_wakeup(dev, true);
1950 dev->wakeup_prepared = true;
1952 platform_pci_set_wakeup(dev, false);
1953 pci_pme_active(dev, false);
1954 dev->wakeup_prepared = false;
1959 EXPORT_SYMBOL(pci_enable_wake);
1962 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1963 * @dev: PCI device to prepare
1964 * @enable: True to enable wake-up event generation; false to disable
1966 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1967 * and this function allows them to set that up cleanly - pci_enable_wake()
1968 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1969 * ordering constraints.
1971 * This function only returns error code if the device is not capable of
1972 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1973 * enable wake-up power for it.
1975 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1977 return pci_pme_capable(dev, PCI_D3cold) ?
1978 pci_enable_wake(dev, PCI_D3cold, enable) :
1979 pci_enable_wake(dev, PCI_D3hot, enable);
1981 EXPORT_SYMBOL(pci_wake_from_d3);
1984 * pci_target_state - find an appropriate low power state for a given PCI dev
1986 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
1988 * Use underlying platform code to find a supported low power state for @dev.
1989 * If the platform can't manage @dev, return the deepest state from which it
1990 * can generate wake events, based on any available PME info.
1992 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
1994 pci_power_t target_state = PCI_D3hot;
1996 if (platform_pci_power_manageable(dev)) {
1998 * Call the platform to choose the target state of the device
1999 * and enable wake-up from this state if supported.
2001 pci_power_t state = platform_pci_choose_state(dev);
2004 case PCI_POWER_ERROR:
2009 if (pci_no_d1d2(dev))
2012 target_state = state;
2015 return target_state;
2019 target_state = PCI_D0;
2022 * If the device is in D3cold even though it's not power-manageable by
2023 * the platform, it may have been powered down by non-standard means.
2024 * Best to let it slumber.
2026 if (dev->current_state == PCI_D3cold)
2027 target_state = PCI_D3cold;
2031 * Find the deepest state from which the device can generate
2032 * wake-up events, make it the target state and enable device
2035 if (dev->pme_support) {
2037 && !(dev->pme_support & (1 << target_state)))
2042 return target_state;
2046 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2047 * @dev: Device to handle.
2049 * Choose the power state appropriate for the device depending on whether
2050 * it can wake up the system and/or is power manageable by the platform
2051 * (PCI_D3hot is the default) and put the device into that state.
2053 int pci_prepare_to_sleep(struct pci_dev *dev)
2055 bool wakeup = device_may_wakeup(&dev->dev);
2056 pci_power_t target_state = pci_target_state(dev, wakeup);
2059 if (target_state == PCI_POWER_ERROR)
2062 pci_enable_wake(dev, target_state, wakeup);
2064 error = pci_set_power_state(dev, target_state);
2067 pci_enable_wake(dev, target_state, false);
2071 EXPORT_SYMBOL(pci_prepare_to_sleep);
2074 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2075 * @dev: Device to handle.
2077 * Disable device's system wake-up capability and put it into D0.
2079 int pci_back_from_sleep(struct pci_dev *dev)
2081 pci_enable_wake(dev, PCI_D0, false);
2082 return pci_set_power_state(dev, PCI_D0);
2084 EXPORT_SYMBOL(pci_back_from_sleep);
2087 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2088 * @dev: PCI device being suspended.
2090 * Prepare @dev to generate wake-up events at run time and put it into a low
2093 int pci_finish_runtime_suspend(struct pci_dev *dev)
2095 pci_power_t target_state;
2098 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2099 if (target_state == PCI_POWER_ERROR)
2102 dev->runtime_d3cold = target_state == PCI_D3cold;
2104 pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2106 error = pci_set_power_state(dev, target_state);
2109 pci_enable_wake(dev, target_state, false);
2110 dev->runtime_d3cold = false;
2117 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2118 * @dev: Device to check.
2120 * Return true if the device itself is capable of generating wake-up events
2121 * (through the platform or using the native PCIe PME) or if the device supports
2122 * PME and one of its upstream bridges can generate wake-up events.
2124 bool pci_dev_run_wake(struct pci_dev *dev)
2126 struct pci_bus *bus = dev->bus;
2128 if (device_can_wakeup(&dev->dev))
2131 if (!dev->pme_support)
2134 /* PME-capable in principle, but not from the target power state */
2135 if (!pci_pme_capable(dev, pci_target_state(dev, false)))
2138 while (bus->parent) {
2139 struct pci_dev *bridge = bus->self;
2141 if (device_can_wakeup(&bridge->dev))
2147 /* We have reached the root bus. */
2149 return device_can_wakeup(bus->bridge);
2153 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2156 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2157 * @pci_dev: Device to check.
2159 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2160 * reconfigured due to wakeup settings difference between system and runtime
2161 * suspend and the current power state of it is suitable for the upcoming
2162 * (system) transition.
2164 * If the device is not configured for system wakeup, disable PME for it before
2165 * returning 'true' to prevent it from waking up the system unnecessarily.
2167 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2169 struct device *dev = &pci_dev->dev;
2170 bool wakeup = device_may_wakeup(dev);
2172 if (!pm_runtime_suspended(dev)
2173 || pci_target_state(pci_dev, wakeup) != pci_dev->current_state
2174 || platform_pci_need_resume(pci_dev))
2178 * At this point the device is good to go unless it's been configured
2179 * to generate PME at the runtime suspend time, but it is not supposed
2180 * to wake up the system. In that case, simply disable PME for it
2181 * (it will have to be re-enabled on exit from system resume).
2183 * If the device's power state is D3cold and the platform check above
2184 * hasn't triggered, the device's configuration is suitable and we don't
2185 * need to manipulate it at all.
2187 spin_lock_irq(&dev->power.lock);
2189 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2191 __pci_pme_active(pci_dev, false);
2193 spin_unlock_irq(&dev->power.lock);
2198 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2199 * @pci_dev: Device to handle.
2201 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2202 * it might have been disabled during the prepare phase of system suspend if
2203 * the device was not configured for system wakeup.
2205 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2207 struct device *dev = &pci_dev->dev;
2209 if (!pci_dev_run_wake(pci_dev))
2212 spin_lock_irq(&dev->power.lock);
2214 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2215 __pci_pme_active(pci_dev, true);
2217 spin_unlock_irq(&dev->power.lock);
2220 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2222 struct device *dev = &pdev->dev;
2223 struct device *parent = dev->parent;
2226 pm_runtime_get_sync(parent);
2227 pm_runtime_get_noresume(dev);
2229 * pdev->current_state is set to PCI_D3cold during suspending,
2230 * so wait until suspending completes
2232 pm_runtime_barrier(dev);
2234 * Only need to resume devices in D3cold, because config
2235 * registers are still accessible for devices suspended but
2238 if (pdev->current_state == PCI_D3cold)
2239 pm_runtime_resume(dev);
2242 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2244 struct device *dev = &pdev->dev;
2245 struct device *parent = dev->parent;
2247 pm_runtime_put(dev);
2249 pm_runtime_put_sync(parent);
2253 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2254 * @bridge: Bridge to check
2256 * This function checks if it is possible to move the bridge to D3.
2257 * Currently we only allow D3 for recent enough PCIe ports.
2259 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2261 if (!pci_is_pcie(bridge))
2264 switch (pci_pcie_type(bridge)) {
2265 case PCI_EXP_TYPE_ROOT_PORT:
2266 case PCI_EXP_TYPE_UPSTREAM:
2267 case PCI_EXP_TYPE_DOWNSTREAM:
2268 if (pci_bridge_d3_disable)
2272 * Hotplug interrupts cannot be delivered if the link is down,
2273 * so parents of a hotplug port must stay awake. In addition,
2274 * hotplug ports handled by firmware in System Management Mode
2275 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2276 * For simplicity, disallow in general for now.
2278 if (bridge->is_hotplug_bridge)
2281 if (pci_bridge_d3_force)
2285 * It should be safe to put PCIe ports from 2015 or newer
2288 if (dmi_get_bios_year() >= 2015)
2296 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2298 bool *d3cold_ok = data;
2300 if (/* The device needs to be allowed to go D3cold ... */
2301 dev->no_d3cold || !dev->d3cold_allowed ||
2303 /* ... and if it is wakeup capable to do so from D3cold. */
2304 (device_may_wakeup(&dev->dev) &&
2305 !pci_pme_capable(dev, PCI_D3cold)) ||
2307 /* If it is a bridge it must be allowed to go to D3. */
2308 !pci_power_manageable(dev))
2316 * pci_bridge_d3_update - Update bridge D3 capabilities
2317 * @dev: PCI device which is changed
2319 * Update upstream bridge PM capabilities accordingly depending on if the
2320 * device PM configuration was changed or the device is being removed. The
2321 * change is also propagated upstream.
2323 void pci_bridge_d3_update(struct pci_dev *dev)
2325 bool remove = !device_is_registered(&dev->dev);
2326 struct pci_dev *bridge;
2327 bool d3cold_ok = true;
2329 bridge = pci_upstream_bridge(dev);
2330 if (!bridge || !pci_bridge_d3_possible(bridge))
2334 * If D3 is currently allowed for the bridge, removing one of its
2335 * children won't change that.
2337 if (remove && bridge->bridge_d3)
2341 * If D3 is currently allowed for the bridge and a child is added or
2342 * changed, disallowance of D3 can only be caused by that child, so
2343 * we only need to check that single device, not any of its siblings.
2345 * If D3 is currently not allowed for the bridge, checking the device
2346 * first may allow us to skip checking its siblings.
2349 pci_dev_check_d3cold(dev, &d3cold_ok);
2352 * If D3 is currently not allowed for the bridge, this may be caused
2353 * either by the device being changed/removed or any of its siblings,
2354 * so we need to go through all children to find out if one of them
2355 * continues to block D3.
2357 if (d3cold_ok && !bridge->bridge_d3)
2358 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2361 if (bridge->bridge_d3 != d3cold_ok) {
2362 bridge->bridge_d3 = d3cold_ok;
2363 /* Propagate change to upstream bridges */
2364 pci_bridge_d3_update(bridge);
2369 * pci_d3cold_enable - Enable D3cold for device
2370 * @dev: PCI device to handle
2372 * This function can be used in drivers to enable D3cold from the device
2373 * they handle. It also updates upstream PCI bridge PM capabilities
2376 void pci_d3cold_enable(struct pci_dev *dev)
2378 if (dev->no_d3cold) {
2379 dev->no_d3cold = false;
2380 pci_bridge_d3_update(dev);
2383 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2386 * pci_d3cold_disable - Disable D3cold for device
2387 * @dev: PCI device to handle
2389 * This function can be used in drivers to disable D3cold from the device
2390 * they handle. It also updates upstream PCI bridge PM capabilities
2393 void pci_d3cold_disable(struct pci_dev *dev)
2395 if (!dev->no_d3cold) {
2396 dev->no_d3cold = true;
2397 pci_bridge_d3_update(dev);
2400 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2403 * pci_pm_init - Initialize PM functions of given PCI device
2404 * @dev: PCI device to handle.
2406 void pci_pm_init(struct pci_dev *dev)
2411 pm_runtime_forbid(&dev->dev);
2412 pm_runtime_set_active(&dev->dev);
2413 pm_runtime_enable(&dev->dev);
2414 device_enable_async_suspend(&dev->dev);
2415 dev->wakeup_prepared = false;
2418 dev->pme_support = 0;
2420 /* find PCI PM capability in list */
2421 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2424 /* Check device's ability to generate PME# */
2425 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2427 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2428 pci_err(dev, "unsupported PM cap regs version (%u)\n",
2429 pmc & PCI_PM_CAP_VER_MASK);
2434 dev->d3_delay = PCI_PM_D3_WAIT;
2435 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2436 dev->bridge_d3 = pci_bridge_d3_possible(dev);
2437 dev->d3cold_allowed = true;
2439 dev->d1_support = false;
2440 dev->d2_support = false;
2441 if (!pci_no_d1d2(dev)) {
2442 if (pmc & PCI_PM_CAP_D1)
2443 dev->d1_support = true;
2444 if (pmc & PCI_PM_CAP_D2)
2445 dev->d2_support = true;
2447 if (dev->d1_support || dev->d2_support)
2448 pci_printk(KERN_DEBUG, dev, "supports%s%s\n",
2449 dev->d1_support ? " D1" : "",
2450 dev->d2_support ? " D2" : "");
2453 pmc &= PCI_PM_CAP_PME_MASK;
2455 pci_printk(KERN_DEBUG, dev, "PME# supported from%s%s%s%s%s\n",
2456 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2457 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2458 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2459 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2460 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2461 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2462 dev->pme_poll = true;
2464 * Make device's PM flags reflect the wake-up capability, but
2465 * let the user space enable it to wake up the system as needed.
2467 device_set_wakeup_capable(&dev->dev, true);
2468 /* Disable the PME# generation functionality */
2469 pci_pme_active(dev, false);
2473 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2475 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
2479 case PCI_EA_P_VF_MEM:
2480 flags |= IORESOURCE_MEM;
2482 case PCI_EA_P_MEM_PREFETCH:
2483 case PCI_EA_P_VF_MEM_PREFETCH:
2484 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2487 flags |= IORESOURCE_IO;
2496 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2499 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2500 return &dev->resource[bei];
2501 #ifdef CONFIG_PCI_IOV
2502 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2503 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2504 return &dev->resource[PCI_IOV_RESOURCES +
2505 bei - PCI_EA_BEI_VF_BAR0];
2507 else if (bei == PCI_EA_BEI_ROM)
2508 return &dev->resource[PCI_ROM_RESOURCE];
2513 /* Read an Enhanced Allocation (EA) entry */
2514 static int pci_ea_read(struct pci_dev *dev, int offset)
2516 struct resource *res;
2517 int ent_size, ent_offset = offset;
2518 resource_size_t start, end;
2519 unsigned long flags;
2520 u32 dw0, bei, base, max_offset;
2522 bool support_64 = (sizeof(resource_size_t) >= 8);
2524 pci_read_config_dword(dev, ent_offset, &dw0);
2527 /* Entry size field indicates DWORDs after 1st */
2528 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2530 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2533 bei = (dw0 & PCI_EA_BEI) >> 4;
2534 prop = (dw0 & PCI_EA_PP) >> 8;
2537 * If the Property is in the reserved range, try the Secondary
2540 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2541 prop = (dw0 & PCI_EA_SP) >> 16;
2542 if (prop > PCI_EA_P_BRIDGE_IO)
2545 res = pci_ea_get_resource(dev, bei, prop);
2547 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
2551 flags = pci_ea_flags(dev, prop);
2553 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
2558 pci_read_config_dword(dev, ent_offset, &base);
2559 start = (base & PCI_EA_FIELD_MASK);
2562 /* Read MaxOffset */
2563 pci_read_config_dword(dev, ent_offset, &max_offset);
2566 /* Read Base MSBs (if 64-bit entry) */
2567 if (base & PCI_EA_IS_64) {
2570 pci_read_config_dword(dev, ent_offset, &base_upper);
2573 flags |= IORESOURCE_MEM_64;
2575 /* entry starts above 32-bit boundary, can't use */
2576 if (!support_64 && base_upper)
2580 start |= ((u64)base_upper << 32);
2583 end = start + (max_offset | 0x03);
2585 /* Read MaxOffset MSBs (if 64-bit entry) */
2586 if (max_offset & PCI_EA_IS_64) {
2587 u32 max_offset_upper;
2589 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2592 flags |= IORESOURCE_MEM_64;
2594 /* entry too big, can't use */
2595 if (!support_64 && max_offset_upper)
2599 end += ((u64)max_offset_upper << 32);
2603 pci_err(dev, "EA Entry crosses address boundary\n");
2607 if (ent_size != ent_offset - offset) {
2608 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
2609 ent_size, ent_offset - offset);
2613 res->name = pci_name(dev);
2618 if (bei <= PCI_EA_BEI_BAR5)
2619 pci_printk(KERN_DEBUG, dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2621 else if (bei == PCI_EA_BEI_ROM)
2622 pci_printk(KERN_DEBUG, dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2624 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2625 pci_printk(KERN_DEBUG, dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2626 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2628 pci_printk(KERN_DEBUG, dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2632 return offset + ent_size;
2635 /* Enhanced Allocation Initialization */
2636 void pci_ea_init(struct pci_dev *dev)
2643 /* find PCI EA capability in list */
2644 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2648 /* determine the number of entries */
2649 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2651 num_ent &= PCI_EA_NUM_ENT_MASK;
2653 offset = ea + PCI_EA_FIRST_ENT;
2655 /* Skip DWORD 2 for type 1 functions */
2656 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2659 /* parse each EA entry */
2660 for (i = 0; i < num_ent; ++i)
2661 offset = pci_ea_read(dev, offset);
2664 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2665 struct pci_cap_saved_state *new_cap)
2667 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2671 * _pci_add_cap_save_buffer - allocate buffer for saving given
2672 * capability registers
2673 * @dev: the PCI device
2674 * @cap: the capability to allocate the buffer for
2675 * @extended: Standard or Extended capability ID
2676 * @size: requested size of the buffer
2678 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2679 bool extended, unsigned int size)
2682 struct pci_cap_saved_state *save_state;
2685 pos = pci_find_ext_capability(dev, cap);
2687 pos = pci_find_capability(dev, cap);
2692 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2696 save_state->cap.cap_nr = cap;
2697 save_state->cap.cap_extended = extended;
2698 save_state->cap.size = size;
2699 pci_add_saved_cap(dev, save_state);
2704 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2706 return _pci_add_cap_save_buffer(dev, cap, false, size);
2709 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2711 return _pci_add_cap_save_buffer(dev, cap, true, size);
2715 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2716 * @dev: the PCI device
2718 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2722 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2723 PCI_EXP_SAVE_REGS * sizeof(u16));
2725 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
2727 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2729 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
2731 pci_allocate_vc_save_buffers(dev);
2734 void pci_free_cap_save_buffers(struct pci_dev *dev)
2736 struct pci_cap_saved_state *tmp;
2737 struct hlist_node *n;
2739 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2744 * pci_configure_ari - enable or disable ARI forwarding
2745 * @dev: the PCI device
2747 * If @dev and its upstream bridge both support ARI, enable ARI in the
2748 * bridge. Otherwise, disable ARI in the bridge.
2750 void pci_configure_ari(struct pci_dev *dev)
2753 struct pci_dev *bridge;
2755 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2758 bridge = dev->bus->self;
2762 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2763 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2766 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2767 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2768 PCI_EXP_DEVCTL2_ARI);
2769 bridge->ari_enabled = 1;
2771 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2772 PCI_EXP_DEVCTL2_ARI);
2773 bridge->ari_enabled = 0;
2777 static int pci_acs_enable;
2780 * pci_request_acs - ask for ACS to be enabled if supported
2782 void pci_request_acs(void)
2788 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2789 * @dev: the PCI device
2791 static void pci_std_enable_acs(struct pci_dev *dev)
2797 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2801 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2802 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2804 /* Source Validation */
2805 ctrl |= (cap & PCI_ACS_SV);
2807 /* P2P Request Redirect */
2808 ctrl |= (cap & PCI_ACS_RR);
2810 /* P2P Completion Redirect */
2811 ctrl |= (cap & PCI_ACS_CR);
2813 /* Upstream Forwarding */
2814 ctrl |= (cap & PCI_ACS_UF);
2816 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2820 * pci_enable_acs - enable ACS if hardware support it
2821 * @dev: the PCI device
2823 void pci_enable_acs(struct pci_dev *dev)
2825 if (!pci_acs_enable)
2828 if (!pci_dev_specific_enable_acs(dev))
2831 pci_std_enable_acs(dev);
2834 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2839 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2844 * Except for egress control, capabilities are either required
2845 * or only required if controllable. Features missing from the
2846 * capability field can therefore be assumed as hard-wired enabled.
2848 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2849 acs_flags &= (cap | PCI_ACS_EC);
2851 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2852 return (ctrl & acs_flags) == acs_flags;
2856 * pci_acs_enabled - test ACS against required flags for a given device
2857 * @pdev: device to test
2858 * @acs_flags: required PCI ACS flags
2860 * Return true if the device supports the provided flags. Automatically
2861 * filters out flags that are not implemented on multifunction devices.
2863 * Note that this interface checks the effective ACS capabilities of the
2864 * device rather than the actual capabilities. For instance, most single
2865 * function endpoints are not required to support ACS because they have no
2866 * opportunity for peer-to-peer access. We therefore return 'true'
2867 * regardless of whether the device exposes an ACS capability. This makes
2868 * it much easier for callers of this function to ignore the actual type
2869 * or topology of the device when testing ACS support.
2871 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2875 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2880 * Conventional PCI and PCI-X devices never support ACS, either
2881 * effectively or actually. The shared bus topology implies that
2882 * any device on the bus can receive or snoop DMA.
2884 if (!pci_is_pcie(pdev))
2887 switch (pci_pcie_type(pdev)) {
2889 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2890 * but since their primary interface is PCI/X, we conservatively
2891 * handle them as we would a non-PCIe device.
2893 case PCI_EXP_TYPE_PCIE_BRIDGE:
2895 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2896 * applicable... must never implement an ACS Extended Capability...".
2897 * This seems arbitrary, but we take a conservative interpretation
2898 * of this statement.
2900 case PCI_EXP_TYPE_PCI_BRIDGE:
2901 case PCI_EXP_TYPE_RC_EC:
2904 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2905 * implement ACS in order to indicate their peer-to-peer capabilities,
2906 * regardless of whether they are single- or multi-function devices.
2908 case PCI_EXP_TYPE_DOWNSTREAM:
2909 case PCI_EXP_TYPE_ROOT_PORT:
2910 return pci_acs_flags_enabled(pdev, acs_flags);
2912 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2913 * implemented by the remaining PCIe types to indicate peer-to-peer
2914 * capabilities, but only when they are part of a multifunction
2915 * device. The footnote for section 6.12 indicates the specific
2916 * PCIe types included here.
2918 case PCI_EXP_TYPE_ENDPOINT:
2919 case PCI_EXP_TYPE_UPSTREAM:
2920 case PCI_EXP_TYPE_LEG_END:
2921 case PCI_EXP_TYPE_RC_END:
2922 if (!pdev->multifunction)
2925 return pci_acs_flags_enabled(pdev, acs_flags);
2929 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2930 * to single function devices with the exception of downstream ports.
2936 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2937 * @start: starting downstream device
2938 * @end: ending upstream device or NULL to search to the root bus
2939 * @acs_flags: required flags
2941 * Walk up a device tree from start to end testing PCI ACS support. If
2942 * any step along the way does not support the required flags, return false.
2944 bool pci_acs_path_enabled(struct pci_dev *start,
2945 struct pci_dev *end, u16 acs_flags)
2947 struct pci_dev *pdev, *parent = start;
2952 if (!pci_acs_enabled(pdev, acs_flags))
2955 if (pci_is_root_bus(pdev->bus))
2956 return (end == NULL);
2958 parent = pdev->bus->self;
2959 } while (pdev != end);
2965 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
2969 * Helper to find the position of the ctrl register for a BAR.
2970 * Returns -ENOTSUPP if resizable BARs are not supported at all.
2971 * Returns -ENOENT if no ctrl register for the BAR could be found.
2973 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
2975 unsigned int pos, nbars, i;
2978 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
2982 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
2983 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
2984 PCI_REBAR_CTRL_NBAR_SHIFT;
2986 for (i = 0; i < nbars; i++, pos += 8) {
2989 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
2990 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
2999 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3001 * @bar: BAR to query
3003 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3004 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3006 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3011 pos = pci_rebar_find_pos(pdev, bar);
3015 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3016 return (cap & PCI_REBAR_CAP_SIZES) >> 4;
3020 * pci_rebar_get_current_size - get the current size of a BAR
3022 * @bar: BAR to set size to
3024 * Read the size of a BAR from the resizable BAR config.
3025 * Returns size if found or negative error code.
3027 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3032 pos = pci_rebar_find_pos(pdev, bar);
3036 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3037 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> 8;
3041 * pci_rebar_set_size - set a new size for a BAR
3043 * @bar: BAR to set size to
3044 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3046 * Set the new size of a BAR as defined in the spec.
3047 * Returns zero if resizing was successful, error code otherwise.
3049 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3054 pos = pci_rebar_find_pos(pdev, bar);
3058 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3059 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3061 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3066 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3067 * @dev: the PCI device
3068 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3069 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3070 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3071 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3073 * Return 0 if all upstream bridges support AtomicOp routing, egress
3074 * blocking is disabled on all upstream ports, and the root port supports
3075 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3076 * AtomicOp completion), or negative otherwise.
3078 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3080 struct pci_bus *bus = dev->bus;
3081 struct pci_dev *bridge;
3084 if (!pci_is_pcie(dev))
3088 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3089 * AtomicOp requesters. For now, we only support endpoints as
3090 * requesters and root ports as completers. No endpoints as
3091 * completers, and no peer-to-peer.
3094 switch (pci_pcie_type(dev)) {
3095 case PCI_EXP_TYPE_ENDPOINT:
3096 case PCI_EXP_TYPE_LEG_END:
3097 case PCI_EXP_TYPE_RC_END:
3103 while (bus->parent) {
3106 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3108 switch (pci_pcie_type(bridge)) {
3109 /* Ensure switch ports support AtomicOp routing */
3110 case PCI_EXP_TYPE_UPSTREAM:
3111 case PCI_EXP_TYPE_DOWNSTREAM:
3112 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3116 /* Ensure root port supports all the sizes we care about */
3117 case PCI_EXP_TYPE_ROOT_PORT:
3118 if ((cap & cap_mask) != cap_mask)
3123 /* Ensure upstream ports don't block AtomicOps on egress */
3124 if (!bridge->has_secondary_link) {
3125 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3127 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3134 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3135 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3138 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3141 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3142 * @dev: the PCI device
3143 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3145 * Perform INTx swizzling for a device behind one level of bridge. This is
3146 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3147 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3148 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3149 * the PCI Express Base Specification, Revision 2.1)
3151 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3155 if (pci_ari_enabled(dev->bus))
3158 slot = PCI_SLOT(dev->devfn);
3160 return (((pin - 1) + slot) % 4) + 1;
3163 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3171 while (!pci_is_root_bus(dev->bus)) {
3172 pin = pci_swizzle_interrupt_pin(dev, pin);
3173 dev = dev->bus->self;
3180 * pci_common_swizzle - swizzle INTx all the way to root bridge
3181 * @dev: the PCI device
3182 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3184 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3185 * bridges all the way up to a PCI root bus.
3187 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3191 while (!pci_is_root_bus(dev->bus)) {
3192 pin = pci_swizzle_interrupt_pin(dev, pin);
3193 dev = dev->bus->self;
3196 return PCI_SLOT(dev->devfn);
3198 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3201 * pci_release_region - Release a PCI bar
3202 * @pdev: PCI device whose resources were previously reserved by pci_request_region
3203 * @bar: BAR to release
3205 * Releases the PCI I/O and memory resources previously reserved by a
3206 * successful call to pci_request_region. Call this function only
3207 * after all use of the PCI regions has ceased.
3209 void pci_release_region(struct pci_dev *pdev, int bar)
3211 struct pci_devres *dr;
3213 if (pci_resource_len(pdev, bar) == 0)
3215 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3216 release_region(pci_resource_start(pdev, bar),
3217 pci_resource_len(pdev, bar));
3218 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3219 release_mem_region(pci_resource_start(pdev, bar),
3220 pci_resource_len(pdev, bar));
3222 dr = find_pci_dr(pdev);
3224 dr->region_mask &= ~(1 << bar);
3226 EXPORT_SYMBOL(pci_release_region);
3229 * __pci_request_region - Reserved PCI I/O and memory resource
3230 * @pdev: PCI device whose resources are to be reserved
3231 * @bar: BAR to be reserved
3232 * @res_name: Name to be associated with resource.
3233 * @exclusive: whether the region access is exclusive or not
3235 * Mark the PCI region associated with PCI device @pdev BR @bar as
3236 * being reserved by owner @res_name. Do not access any
3237 * address inside the PCI regions unless this call returns
3240 * If @exclusive is set, then the region is marked so that userspace
3241 * is explicitly not allowed to map the resource via /dev/mem or
3242 * sysfs MMIO access.
3244 * Returns 0 on success, or %EBUSY on error. A warning
3245 * message is also printed on failure.
3247 static int __pci_request_region(struct pci_dev *pdev, int bar,
3248 const char *res_name, int exclusive)
3250 struct pci_devres *dr;
3252 if (pci_resource_len(pdev, bar) == 0)
3255 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3256 if (!request_region(pci_resource_start(pdev, bar),
3257 pci_resource_len(pdev, bar), res_name))
3259 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3260 if (!__request_mem_region(pci_resource_start(pdev, bar),
3261 pci_resource_len(pdev, bar), res_name,
3266 dr = find_pci_dr(pdev);
3268 dr->region_mask |= 1 << bar;
3273 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3274 &pdev->resource[bar]);
3279 * pci_request_region - Reserve PCI I/O and memory resource
3280 * @pdev: PCI device whose resources are to be reserved
3281 * @bar: BAR to be reserved
3282 * @res_name: Name to be associated with resource
3284 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3285 * being reserved by owner @res_name. Do not access any
3286 * address inside the PCI regions unless this call returns
3289 * Returns 0 on success, or %EBUSY on error. A warning
3290 * message is also printed on failure.
3292 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3294 return __pci_request_region(pdev, bar, res_name, 0);
3296 EXPORT_SYMBOL(pci_request_region);
3299 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3300 * @pdev: PCI device whose resources are to be reserved
3301 * @bar: BAR to be reserved
3302 * @res_name: Name to be associated with resource.
3304 * Mark the PCI region associated with PCI device @pdev BR @bar as
3305 * being reserved by owner @res_name. Do not access any
3306 * address inside the PCI regions unless this call returns
3309 * Returns 0 on success, or %EBUSY on error. A warning
3310 * message is also printed on failure.
3312 * The key difference that _exclusive makes it that userspace is
3313 * explicitly not allowed to map the resource via /dev/mem or
3316 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3317 const char *res_name)
3319 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3321 EXPORT_SYMBOL(pci_request_region_exclusive);
3324 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3325 * @pdev: PCI device whose resources were previously reserved
3326 * @bars: Bitmask of BARs to be released
3328 * Release selected PCI I/O and memory resources previously reserved.
3329 * Call this function only after all use of the PCI regions has ceased.
3331 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3335 for (i = 0; i < 6; i++)
3336 if (bars & (1 << i))
3337 pci_release_region(pdev, i);
3339 EXPORT_SYMBOL(pci_release_selected_regions);
3341 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3342 const char *res_name, int excl)
3346 for (i = 0; i < 6; i++)
3347 if (bars & (1 << i))
3348 if (__pci_request_region(pdev, i, res_name, excl))
3354 if (bars & (1 << i))
3355 pci_release_region(pdev, i);
3362 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3363 * @pdev: PCI device whose resources are to be reserved
3364 * @bars: Bitmask of BARs to be requested
3365 * @res_name: Name to be associated with resource
3367 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3368 const char *res_name)
3370 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3372 EXPORT_SYMBOL(pci_request_selected_regions);
3374 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3375 const char *res_name)
3377 return __pci_request_selected_regions(pdev, bars, res_name,
3378 IORESOURCE_EXCLUSIVE);
3380 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3383 * pci_release_regions - Release reserved PCI I/O and memory resources
3384 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3386 * Releases all PCI I/O and memory resources previously reserved by a
3387 * successful call to pci_request_regions. Call this function only
3388 * after all use of the PCI regions has ceased.
3391 void pci_release_regions(struct pci_dev *pdev)
3393 pci_release_selected_regions(pdev, (1 << 6) - 1);
3395 EXPORT_SYMBOL(pci_release_regions);
3398 * pci_request_regions - Reserved PCI I/O and memory resources
3399 * @pdev: PCI device whose resources are to be reserved
3400 * @res_name: Name to be associated with resource.
3402 * Mark all PCI regions associated with PCI device @pdev as
3403 * being reserved by owner @res_name. Do not access any
3404 * address inside the PCI regions unless this call returns
3407 * Returns 0 on success, or %EBUSY on error. A warning
3408 * message is also printed on failure.
3410 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3412 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3414 EXPORT_SYMBOL(pci_request_regions);
3417 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3418 * @pdev: PCI device whose resources are to be reserved
3419 * @res_name: Name to be associated with resource.
3421 * Mark all PCI regions associated with PCI device @pdev as
3422 * being reserved by owner @res_name. Do not access any
3423 * address inside the PCI regions unless this call returns
3426 * pci_request_regions_exclusive() will mark the region so that
3427 * /dev/mem and the sysfs MMIO access will not be allowed.
3429 * Returns 0 on success, or %EBUSY on error. A warning
3430 * message is also printed on failure.
3432 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3434 return pci_request_selected_regions_exclusive(pdev,
3435 ((1 << 6) - 1), res_name);
3437 EXPORT_SYMBOL(pci_request_regions_exclusive);
3441 struct list_head list;
3443 resource_size_t size;
3446 static LIST_HEAD(io_range_list);
3447 static DEFINE_SPINLOCK(io_range_lock);
3451 * Record the PCI IO range (expressed as CPU physical address + size).
3452 * Return a negative value if an error has occured, zero otherwise
3454 int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
3459 struct io_range *range;
3460 resource_size_t allocated_size = 0;
3462 /* check if the range hasn't been previously recorded */
3463 spin_lock(&io_range_lock);
3464 list_for_each_entry(range, &io_range_list, list) {
3465 if (addr >= range->start && addr + size <= range->start + size) {
3466 /* range already registered, bail out */
3469 allocated_size += range->size;
3472 /* range not registed yet, check for available space */
3473 if (allocated_size + size - 1 > IO_SPACE_LIMIT) {
3474 /* if it's too big check if 64K space can be reserved */
3475 if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) {
3481 pr_warn("Requested IO range too big, new size set to 64K\n");
3484 /* add the range to the list */
3485 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3491 range->start = addr;
3494 list_add_tail(&range->list, &io_range_list);
3497 spin_unlock(&io_range_lock);
3503 phys_addr_t pci_pio_to_address(unsigned long pio)
3505 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3508 struct io_range *range;
3509 resource_size_t allocated_size = 0;
3511 if (pio > IO_SPACE_LIMIT)
3514 spin_lock(&io_range_lock);
3515 list_for_each_entry(range, &io_range_list, list) {
3516 if (pio >= allocated_size && pio < allocated_size + range->size) {
3517 address = range->start + pio - allocated_size;
3520 allocated_size += range->size;
3522 spin_unlock(&io_range_lock);
3528 unsigned long __weak pci_address_to_pio(phys_addr_t address)
3531 struct io_range *res;
3532 resource_size_t offset = 0;
3533 unsigned long addr = -1;
3535 spin_lock(&io_range_lock);
3536 list_for_each_entry(res, &io_range_list, list) {
3537 if (address >= res->start && address < res->start + res->size) {
3538 addr = address - res->start + offset;
3541 offset += res->size;
3543 spin_unlock(&io_range_lock);
3547 if (address > IO_SPACE_LIMIT)
3548 return (unsigned long)-1;
3550 return (unsigned long) address;
3555 * pci_remap_iospace - Remap the memory mapped I/O space
3556 * @res: Resource describing the I/O space
3557 * @phys_addr: physical address of range to be mapped
3559 * Remap the memory mapped I/O space described by the @res
3560 * and the CPU physical address @phys_addr into virtual address space.
3561 * Only architectures that have memory mapped IO functions defined
3562 * (and the PCI_IOBASE value defined) should call this function.
3564 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3566 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3567 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3569 if (!(res->flags & IORESOURCE_IO))
3572 if (res->end > IO_SPACE_LIMIT)
3575 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3576 pgprot_device(PAGE_KERNEL));
3578 /* this architecture does not have memory mapped I/O space,
3579 so this function should never be called */
3580 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3584 EXPORT_SYMBOL(pci_remap_iospace);
3587 * pci_unmap_iospace - Unmap the memory mapped I/O space
3588 * @res: resource to be unmapped
3590 * Unmap the CPU virtual address @res from virtual address space.
3591 * Only architectures that have memory mapped IO functions defined
3592 * (and the PCI_IOBASE value defined) should call this function.
3594 void pci_unmap_iospace(struct resource *res)
3596 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3597 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3599 unmap_kernel_range(vaddr, resource_size(res));
3602 EXPORT_SYMBOL(pci_unmap_iospace);
3605 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
3606 * @dev: Generic device to remap IO address for
3607 * @offset: Resource address to map
3608 * @size: Size of map
3610 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
3613 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
3614 resource_size_t offset,
3615 resource_size_t size)
3617 void __iomem **ptr, *addr;
3619 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
3623 addr = pci_remap_cfgspace(offset, size);
3626 devres_add(dev, ptr);
3632 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
3635 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
3636 * @dev: generic device to handle the resource for
3637 * @res: configuration space resource to be handled
3639 * Checks that a resource is a valid memory region, requests the memory
3640 * region and ioremaps with pci_remap_cfgspace() API that ensures the
3641 * proper PCI configuration space memory attributes are guaranteed.
3643 * All operations are managed and will be undone on driver detach.
3645 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
3646 * on failure. Usage example::
3648 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3649 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
3651 * return PTR_ERR(base);
3653 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
3654 struct resource *res)
3656 resource_size_t size;
3658 void __iomem *dest_ptr;
3662 if (!res || resource_type(res) != IORESOURCE_MEM) {
3663 dev_err(dev, "invalid resource\n");
3664 return IOMEM_ERR_PTR(-EINVAL);
3667 size = resource_size(res);
3668 name = res->name ?: dev_name(dev);
3670 if (!devm_request_mem_region(dev, res->start, size, name)) {
3671 dev_err(dev, "can't request region for resource %pR\n", res);
3672 return IOMEM_ERR_PTR(-EBUSY);
3675 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
3677 dev_err(dev, "ioremap failed for resource %pR\n", res);
3678 devm_release_mem_region(dev, res->start, size);
3679 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
3684 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
3686 static void __pci_set_master(struct pci_dev *dev, bool enable)
3690 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3692 cmd = old_cmd | PCI_COMMAND_MASTER;
3694 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3695 if (cmd != old_cmd) {
3696 pci_dbg(dev, "%s bus mastering\n",
3697 enable ? "enabling" : "disabling");
3698 pci_write_config_word(dev, PCI_COMMAND, cmd);
3700 dev->is_busmaster = enable;
3704 * pcibios_setup - process "pci=" kernel boot arguments
3705 * @str: string used to pass in "pci=" kernel boot arguments
3707 * Process kernel boot arguments. This is the default implementation.
3708 * Architecture specific implementations can override this as necessary.
3710 char * __weak __init pcibios_setup(char *str)
3716 * pcibios_set_master - enable PCI bus-mastering for device dev
3717 * @dev: the PCI device to enable
3719 * Enables PCI bus-mastering for the device. This is the default
3720 * implementation. Architecture specific implementations can override
3721 * this if necessary.
3723 void __weak pcibios_set_master(struct pci_dev *dev)
3727 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3728 if (pci_is_pcie(dev))
3731 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
3733 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
3734 else if (lat > pcibios_max_latency)
3735 lat = pcibios_max_latency;
3739 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
3743 * pci_set_master - enables bus-mastering for device dev
3744 * @dev: the PCI device to enable
3746 * Enables bus-mastering on the device and calls pcibios_set_master()
3747 * to do the needed arch specific settings.
3749 void pci_set_master(struct pci_dev *dev)
3751 __pci_set_master(dev, true);
3752 pcibios_set_master(dev);
3754 EXPORT_SYMBOL(pci_set_master);
3757 * pci_clear_master - disables bus-mastering for device dev
3758 * @dev: the PCI device to disable
3760 void pci_clear_master(struct pci_dev *dev)
3762 __pci_set_master(dev, false);
3764 EXPORT_SYMBOL(pci_clear_master);
3767 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3768 * @dev: the PCI device for which MWI is to be enabled
3770 * Helper function for pci_set_mwi.
3771 * Originally copied from drivers/net/acenic.c.
3772 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3774 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3776 int pci_set_cacheline_size(struct pci_dev *dev)
3780 if (!pci_cache_line_size)
3783 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3784 equal to or multiple of the right value. */
3785 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3786 if (cacheline_size >= pci_cache_line_size &&
3787 (cacheline_size % pci_cache_line_size) == 0)
3790 /* Write the correct value. */
3791 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
3793 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3794 if (cacheline_size == pci_cache_line_size)
3797 pci_printk(KERN_DEBUG, dev, "cache line size of %d is not supported\n",
3798 pci_cache_line_size << 2);
3802 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
3805 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3806 * @dev: the PCI device for which MWI is enabled
3808 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3810 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3812 int pci_set_mwi(struct pci_dev *dev)
3814 #ifdef PCI_DISABLE_MWI
3820 rc = pci_set_cacheline_size(dev);
3824 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3825 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
3826 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
3827 cmd |= PCI_COMMAND_INVALIDATE;
3828 pci_write_config_word(dev, PCI_COMMAND, cmd);
3833 EXPORT_SYMBOL(pci_set_mwi);
3836 * pcim_set_mwi - a device-managed pci_set_mwi()
3837 * @dev: the PCI device for which MWI is enabled
3839 * Managed pci_set_mwi().
3841 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3843 int pcim_set_mwi(struct pci_dev *dev)
3845 struct pci_devres *dr;
3847 dr = find_pci_dr(dev);
3852 return pci_set_mwi(dev);
3854 EXPORT_SYMBOL(pcim_set_mwi);
3857 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3858 * @dev: the PCI device for which MWI is enabled
3860 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3861 * Callers are not required to check the return value.
3863 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3865 int pci_try_set_mwi(struct pci_dev *dev)
3867 #ifdef PCI_DISABLE_MWI
3870 return pci_set_mwi(dev);
3873 EXPORT_SYMBOL(pci_try_set_mwi);
3876 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3877 * @dev: the PCI device to disable
3879 * Disables PCI Memory-Write-Invalidate transaction on the device
3881 void pci_clear_mwi(struct pci_dev *dev)
3883 #ifndef PCI_DISABLE_MWI
3886 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3887 if (cmd & PCI_COMMAND_INVALIDATE) {
3888 cmd &= ~PCI_COMMAND_INVALIDATE;
3889 pci_write_config_word(dev, PCI_COMMAND, cmd);
3893 EXPORT_SYMBOL(pci_clear_mwi);
3896 * pci_intx - enables/disables PCI INTx for device dev
3897 * @pdev: the PCI device to operate on
3898 * @enable: boolean: whether to enable or disable PCI INTx
3900 * Enables/disables PCI INTx for device dev
3902 void pci_intx(struct pci_dev *pdev, int enable)
3904 u16 pci_command, new;
3906 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3909 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3911 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3913 if (new != pci_command) {
3914 struct pci_devres *dr;
3916 pci_write_config_word(pdev, PCI_COMMAND, new);
3918 dr = find_pci_dr(pdev);
3919 if (dr && !dr->restore_intx) {
3920 dr->restore_intx = 1;
3921 dr->orig_intx = !enable;
3925 EXPORT_SYMBOL_GPL(pci_intx);
3927 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3929 struct pci_bus *bus = dev->bus;
3930 bool mask_updated = true;
3931 u32 cmd_status_dword;
3932 u16 origcmd, newcmd;
3933 unsigned long flags;
3937 * We do a single dword read to retrieve both command and status.
3938 * Document assumptions that make this possible.
3940 BUILD_BUG_ON(PCI_COMMAND % 4);
3941 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3943 raw_spin_lock_irqsave(&pci_lock, flags);
3945 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3947 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3950 * Check interrupt status register to see whether our device
3951 * triggered the interrupt (when masking) or the next IRQ is
3952 * already pending (when unmasking).
3954 if (mask != irq_pending) {
3955 mask_updated = false;
3959 origcmd = cmd_status_dword;
3960 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3962 newcmd |= PCI_COMMAND_INTX_DISABLE;
3963 if (newcmd != origcmd)
3964 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3967 raw_spin_unlock_irqrestore(&pci_lock, flags);
3969 return mask_updated;
3973 * pci_check_and_mask_intx - mask INTx on pending interrupt
3974 * @dev: the PCI device to operate on
3976 * Check if the device dev has its INTx line asserted, mask it and
3977 * return true in that case. False is returned if no interrupt was
3980 bool pci_check_and_mask_intx(struct pci_dev *dev)
3982 return pci_check_and_set_intx_mask(dev, true);
3984 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3987 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3988 * @dev: the PCI device to operate on
3990 * Check if the device dev has its INTx line asserted, unmask it if not
3991 * and return true. False is returned and the mask remains active if
3992 * there was still an interrupt pending.
3994 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3996 return pci_check_and_set_intx_mask(dev, false);
3998 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4001 * pci_wait_for_pending_transaction - waits for pending transaction
4002 * @dev: the PCI device to operate on
4004 * Return 0 if transaction is pending 1 otherwise.
4006 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4008 if (!pci_is_pcie(dev))
4011 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4012 PCI_EXP_DEVSTA_TRPND);
4014 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4016 static void pci_flr_wait(struct pci_dev *dev)
4018 int delay = 1, timeout = 60000;
4022 * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within
4023 * 100ms, but may silently discard requests while the FLR is in
4024 * progress. Wait 100ms before trying to access the device.
4029 * After 100ms, the device should not silently discard config
4030 * requests, but it may still indicate that it needs more time by
4031 * responding to them with CRS completions. The Root Port will
4032 * generally synthesize ~0 data to complete the read (except when
4033 * CRS SV is enabled and the read was for the Vendor ID; in that
4034 * case it synthesizes 0x0001 data).
4036 * Wait for the device to return a non-CRS completion. Read the
4037 * Command register instead of Vendor ID so we don't have to
4038 * contend with the CRS SV value.
4040 pci_read_config_dword(dev, PCI_COMMAND, &id);
4042 if (delay > timeout) {
4043 pci_warn(dev, "not ready %dms after FLR; giving up\n",
4049 pci_info(dev, "not ready %dms after FLR; waiting\n",
4054 pci_read_config_dword(dev, PCI_COMMAND, &id);
4058 pci_info(dev, "ready %dms after FLR\n", 100 + delay - 1);
4062 * pcie_has_flr - check if a device supports function level resets
4063 * @dev: device to check
4065 * Returns true if the device advertises support for PCIe function level
4068 static bool pcie_has_flr(struct pci_dev *dev)
4072 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4075 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
4076 return cap & PCI_EXP_DEVCAP_FLR;
4080 * pcie_flr - initiate a PCIe function level reset
4081 * @dev: device to reset
4083 * Initiate a function level reset on @dev. The caller should ensure the
4084 * device supports FLR before calling this function, e.g. by using the
4085 * pcie_has_flr() helper.
4087 void pcie_flr(struct pci_dev *dev)
4089 if (!pci_wait_for_pending_transaction(dev))
4090 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4092 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4095 EXPORT_SYMBOL_GPL(pcie_flr);
4097 static int pci_af_flr(struct pci_dev *dev, int probe)
4102 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4106 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4109 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4110 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4117 * Wait for Transaction Pending bit to clear. A word-aligned test
4118 * is used, so we use the conrol offset rather than status and shift
4119 * the test bit to match.
4121 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4122 PCI_AF_STATUS_TP << 8))
4123 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4125 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4131 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4132 * @dev: Device to reset.
4133 * @probe: If set, only check if the device can be reset this way.
4135 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4136 * unset, it will be reinitialized internally when going from PCI_D3hot to
4137 * PCI_D0. If that's the case and the device is not in a low-power state
4138 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4140 * NOTE: This causes the caller to sleep for twice the device power transition
4141 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4142 * by default (i.e. unless the @dev's d3_delay field has a different value).
4143 * Moreover, only devices in D0 can be reset by this function.
4145 static int pci_pm_reset(struct pci_dev *dev, int probe)
4149 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4152 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4153 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4159 if (dev->current_state != PCI_D0)
4162 csr &= ~PCI_PM_CTRL_STATE_MASK;
4164 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4165 pci_dev_d3_sleep(dev);
4167 csr &= ~PCI_PM_CTRL_STATE_MASK;
4169 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4170 pci_dev_d3_sleep(dev);
4175 void pci_reset_secondary_bus(struct pci_dev *dev)
4179 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4180 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4181 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4183 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4184 * this to 2ms to ensure that we meet the minimum requirement.
4188 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
4189 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4192 * Trhfa for conventional PCI is 2^25 clock cycles.
4193 * Assuming a minimum 33MHz clock this results in a 1s
4194 * delay before we can consider subordinate devices to
4195 * be re-initialized. PCIe has some ways to shorten this,
4196 * but we don't make use of them yet.
4201 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4203 pci_reset_secondary_bus(dev);
4207 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
4208 * @dev: Bridge device
4210 * Use the bridge control register to assert reset on the secondary bus.
4211 * Devices on the secondary bus are left in power-on state.
4213 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
4215 pcibios_reset_secondary_bus(dev);
4217 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
4219 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4221 struct pci_dev *pdev;
4223 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4224 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4227 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4234 pci_reset_bridge_secondary_bus(dev->bus->self);
4239 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
4243 if (!hotplug || !try_module_get(hotplug->ops->owner))
4246 if (hotplug->ops->reset_slot)
4247 rc = hotplug->ops->reset_slot(hotplug, probe);
4249 module_put(hotplug->ops->owner);
4254 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
4256 struct pci_dev *pdev;
4258 if (dev->subordinate || !dev->slot ||
4259 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4262 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4263 if (pdev != dev && pdev->slot == dev->slot)
4266 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
4269 static void pci_dev_lock(struct pci_dev *dev)
4271 pci_cfg_access_lock(dev);
4272 /* block PM suspend, driver probe, etc. */
4273 device_lock(&dev->dev);
4276 /* Return 1 on successful lock, 0 on contention */
4277 static int pci_dev_trylock(struct pci_dev *dev)
4279 if (pci_cfg_access_trylock(dev)) {
4280 if (device_trylock(&dev->dev))
4282 pci_cfg_access_unlock(dev);
4288 static void pci_dev_unlock(struct pci_dev *dev)
4290 device_unlock(&dev->dev);
4291 pci_cfg_access_unlock(dev);
4294 static void pci_dev_save_and_disable(struct pci_dev *dev)
4296 const struct pci_error_handlers *err_handler =
4297 dev->driver ? dev->driver->err_handler : NULL;
4300 * dev->driver->err_handler->reset_prepare() is protected against
4301 * races with ->remove() by the device lock, which must be held by
4304 if (err_handler && err_handler->reset_prepare)
4305 err_handler->reset_prepare(dev);
4308 * Wake-up device prior to save. PM registers default to D0 after
4309 * reset and a simple register restore doesn't reliably return
4310 * to a non-D0 state anyway.
4312 pci_set_power_state(dev, PCI_D0);
4314 pci_save_state(dev);
4316 * Disable the device by clearing the Command register, except for
4317 * INTx-disable which is set. This not only disables MMIO and I/O port
4318 * BARs, but also prevents the device from being Bus Master, preventing
4319 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4320 * compliant devices, INTx-disable prevents legacy interrupts.
4322 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4325 static void pci_dev_restore(struct pci_dev *dev)
4327 const struct pci_error_handlers *err_handler =
4328 dev->driver ? dev->driver->err_handler : NULL;
4330 pci_restore_state(dev);
4333 * dev->driver->err_handler->reset_done() is protected against
4334 * races with ->remove() by the device lock, which must be held by
4337 if (err_handler && err_handler->reset_done)
4338 err_handler->reset_done(dev);
4342 * __pci_reset_function_locked - reset a PCI device function while holding
4343 * the @dev mutex lock.
4344 * @dev: PCI device to reset
4346 * Some devices allow an individual function to be reset without affecting
4347 * other functions in the same device. The PCI device must be responsive
4348 * to PCI config space in order to use this function.
4350 * The device function is presumed to be unused and the caller is holding
4351 * the device mutex lock when this function is called.
4352 * Resetting the device will make the contents of PCI configuration space
4353 * random, so any caller of this must be prepared to reinitialise the
4354 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4357 * Returns 0 if the device function was successfully reset or negative if the
4358 * device doesn't support resetting a single function.
4360 int __pci_reset_function_locked(struct pci_dev *dev)
4367 * A reset method returns -ENOTTY if it doesn't support this device
4368 * and we should try the next method.
4370 * If it returns 0 (success), we're finished. If it returns any
4371 * other error, we're also finished: this indicates that further
4372 * reset mechanisms might be broken on the device.
4374 rc = pci_dev_specific_reset(dev, 0);
4377 if (pcie_has_flr(dev)) {
4381 rc = pci_af_flr(dev, 0);
4384 rc = pci_pm_reset(dev, 0);
4387 rc = pci_dev_reset_slot_function(dev, 0);
4390 return pci_parent_bus_reset(dev, 0);
4392 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4395 * pci_probe_reset_function - check whether the device can be safely reset
4396 * @dev: PCI device to reset
4398 * Some devices allow an individual function to be reset without affecting
4399 * other functions in the same device. The PCI device must be responsive
4400 * to PCI config space in order to use this function.
4402 * Returns 0 if the device function can be reset or negative if the
4403 * device doesn't support resetting a single function.
4405 int pci_probe_reset_function(struct pci_dev *dev)
4411 rc = pci_dev_specific_reset(dev, 1);
4414 if (pcie_has_flr(dev))
4416 rc = pci_af_flr(dev, 1);
4419 rc = pci_pm_reset(dev, 1);
4422 rc = pci_dev_reset_slot_function(dev, 1);
4426 return pci_parent_bus_reset(dev, 1);
4430 * pci_reset_function - quiesce and reset a PCI device function
4431 * @dev: PCI device to reset
4433 * Some devices allow an individual function to be reset without affecting
4434 * other functions in the same device. The PCI device must be responsive
4435 * to PCI config space in order to use this function.
4437 * This function does not just reset the PCI portion of a device, but
4438 * clears all the state associated with the device. This function differs
4439 * from __pci_reset_function_locked() in that it saves and restores device state
4440 * over the reset and takes the PCI device lock.
4442 * Returns 0 if the device function was successfully reset or negative if the
4443 * device doesn't support resetting a single function.
4445 int pci_reset_function(struct pci_dev *dev)
4449 rc = pci_probe_reset_function(dev);
4454 pci_dev_save_and_disable(dev);
4456 rc = __pci_reset_function_locked(dev);
4458 pci_dev_restore(dev);
4459 pci_dev_unlock(dev);
4463 EXPORT_SYMBOL_GPL(pci_reset_function);
4466 * pci_reset_function_locked - quiesce and reset a PCI device function
4467 * @dev: PCI device to reset
4469 * Some devices allow an individual function to be reset without affecting
4470 * other functions in the same device. The PCI device must be responsive
4471 * to PCI config space in order to use this function.
4473 * This function does not just reset the PCI portion of a device, but
4474 * clears all the state associated with the device. This function differs
4475 * from __pci_reset_function_locked() in that it saves and restores device state
4476 * over the reset. It also differs from pci_reset_function() in that it
4477 * requires the PCI device lock to be held.
4479 * Returns 0 if the device function was successfully reset or negative if the
4480 * device doesn't support resetting a single function.
4482 int pci_reset_function_locked(struct pci_dev *dev)
4486 rc = pci_probe_reset_function(dev);
4490 pci_dev_save_and_disable(dev);
4492 rc = __pci_reset_function_locked(dev);
4494 pci_dev_restore(dev);
4498 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
4501 * pci_try_reset_function - quiesce and reset a PCI device function
4502 * @dev: PCI device to reset
4504 * Same as above, except return -EAGAIN if unable to lock device.
4506 int pci_try_reset_function(struct pci_dev *dev)
4510 rc = pci_probe_reset_function(dev);
4514 if (!pci_dev_trylock(dev))
4517 pci_dev_save_and_disable(dev);
4518 rc = __pci_reset_function_locked(dev);
4519 pci_dev_unlock(dev);
4521 pci_dev_restore(dev);
4524 EXPORT_SYMBOL_GPL(pci_try_reset_function);
4526 /* Do any devices on or below this bus prevent a bus reset? */
4527 static bool pci_bus_resetable(struct pci_bus *bus)
4529 struct pci_dev *dev;
4532 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4535 list_for_each_entry(dev, &bus->devices, bus_list) {
4536 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4537 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4544 /* Lock devices from the top of the tree down */
4545 static void pci_bus_lock(struct pci_bus *bus)
4547 struct pci_dev *dev;
4549 list_for_each_entry(dev, &bus->devices, bus_list) {
4551 if (dev->subordinate)
4552 pci_bus_lock(dev->subordinate);
4556 /* Unlock devices from the bottom of the tree up */
4557 static void pci_bus_unlock(struct pci_bus *bus)
4559 struct pci_dev *dev;
4561 list_for_each_entry(dev, &bus->devices, bus_list) {
4562 if (dev->subordinate)
4563 pci_bus_unlock(dev->subordinate);
4564 pci_dev_unlock(dev);
4568 /* Return 1 on successful lock, 0 on contention */
4569 static int pci_bus_trylock(struct pci_bus *bus)
4571 struct pci_dev *dev;
4573 list_for_each_entry(dev, &bus->devices, bus_list) {
4574 if (!pci_dev_trylock(dev))
4576 if (dev->subordinate) {
4577 if (!pci_bus_trylock(dev->subordinate)) {
4578 pci_dev_unlock(dev);
4586 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
4587 if (dev->subordinate)
4588 pci_bus_unlock(dev->subordinate);
4589 pci_dev_unlock(dev);
4594 /* Do any devices on or below this slot prevent a bus reset? */
4595 static bool pci_slot_resetable(struct pci_slot *slot)
4597 struct pci_dev *dev;
4599 if (slot->bus->self &&
4600 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4603 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4604 if (!dev->slot || dev->slot != slot)
4606 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4607 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4614 /* Lock devices from the top of the tree down */
4615 static void pci_slot_lock(struct pci_slot *slot)
4617 struct pci_dev *dev;
4619 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4620 if (!dev->slot || dev->slot != slot)
4623 if (dev->subordinate)
4624 pci_bus_lock(dev->subordinate);
4628 /* Unlock devices from the bottom of the tree up */
4629 static void pci_slot_unlock(struct pci_slot *slot)
4631 struct pci_dev *dev;
4633 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4634 if (!dev->slot || dev->slot != slot)
4636 if (dev->subordinate)
4637 pci_bus_unlock(dev->subordinate);
4638 pci_dev_unlock(dev);
4642 /* Return 1 on successful lock, 0 on contention */
4643 static int pci_slot_trylock(struct pci_slot *slot)
4645 struct pci_dev *dev;
4647 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4648 if (!dev->slot || dev->slot != slot)
4650 if (!pci_dev_trylock(dev))
4652 if (dev->subordinate) {
4653 if (!pci_bus_trylock(dev->subordinate)) {
4654 pci_dev_unlock(dev);
4662 list_for_each_entry_continue_reverse(dev,
4663 &slot->bus->devices, bus_list) {
4664 if (!dev->slot || dev->slot != slot)
4666 if (dev->subordinate)
4667 pci_bus_unlock(dev->subordinate);
4668 pci_dev_unlock(dev);
4673 /* Save and disable devices from the top of the tree down */
4674 static void pci_bus_save_and_disable(struct pci_bus *bus)
4676 struct pci_dev *dev;
4678 list_for_each_entry(dev, &bus->devices, bus_list) {
4680 pci_dev_save_and_disable(dev);
4681 pci_dev_unlock(dev);
4682 if (dev->subordinate)
4683 pci_bus_save_and_disable(dev->subordinate);
4688 * Restore devices from top of the tree down - parent bridges need to be
4689 * restored before we can get to subordinate devices.
4691 static void pci_bus_restore(struct pci_bus *bus)
4693 struct pci_dev *dev;
4695 list_for_each_entry(dev, &bus->devices, bus_list) {
4697 pci_dev_restore(dev);
4698 pci_dev_unlock(dev);
4699 if (dev->subordinate)
4700 pci_bus_restore(dev->subordinate);
4704 /* Save and disable devices from the top of the tree down */
4705 static void pci_slot_save_and_disable(struct pci_slot *slot)
4707 struct pci_dev *dev;
4709 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4710 if (!dev->slot || dev->slot != slot)
4712 pci_dev_save_and_disable(dev);
4713 if (dev->subordinate)
4714 pci_bus_save_and_disable(dev->subordinate);
4719 * Restore devices from top of the tree down - parent bridges need to be
4720 * restored before we can get to subordinate devices.
4722 static void pci_slot_restore(struct pci_slot *slot)
4724 struct pci_dev *dev;
4726 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4727 if (!dev->slot || dev->slot != slot)
4729 pci_dev_restore(dev);
4730 if (dev->subordinate)
4731 pci_bus_restore(dev->subordinate);
4735 static int pci_slot_reset(struct pci_slot *slot, int probe)
4739 if (!slot || !pci_slot_resetable(slot))
4743 pci_slot_lock(slot);
4747 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
4750 pci_slot_unlock(slot);
4756 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4757 * @slot: PCI slot to probe
4759 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4761 int pci_probe_reset_slot(struct pci_slot *slot)
4763 return pci_slot_reset(slot, 1);
4765 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
4768 * pci_reset_slot - reset a PCI slot
4769 * @slot: PCI slot to reset
4771 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4772 * independent of other slots. For instance, some slots may support slot power
4773 * control. In the case of a 1:1 bus to slot architecture, this function may
4774 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4775 * Generally a slot reset should be attempted before a bus reset. All of the
4776 * function of the slot and any subordinate buses behind the slot are reset
4777 * through this function. PCI config space of all devices in the slot and
4778 * behind the slot is saved before and restored after reset.
4780 * Return 0 on success, non-zero on error.
4782 int pci_reset_slot(struct pci_slot *slot)
4786 rc = pci_slot_reset(slot, 1);
4790 pci_slot_save_and_disable(slot);
4792 rc = pci_slot_reset(slot, 0);
4794 pci_slot_restore(slot);
4798 EXPORT_SYMBOL_GPL(pci_reset_slot);
4801 * pci_try_reset_slot - Try to reset a PCI slot
4802 * @slot: PCI slot to reset
4804 * Same as above except return -EAGAIN if the slot cannot be locked
4806 int pci_try_reset_slot(struct pci_slot *slot)
4810 rc = pci_slot_reset(slot, 1);
4814 pci_slot_save_and_disable(slot);
4816 if (pci_slot_trylock(slot)) {
4818 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
4819 pci_slot_unlock(slot);
4823 pci_slot_restore(slot);
4827 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
4829 static int pci_bus_reset(struct pci_bus *bus, int probe)
4831 if (!bus->self || !pci_bus_resetable(bus))
4841 pci_reset_bridge_secondary_bus(bus->self);
4843 pci_bus_unlock(bus);
4849 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4850 * @bus: PCI bus to probe
4852 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4854 int pci_probe_reset_bus(struct pci_bus *bus)
4856 return pci_bus_reset(bus, 1);
4858 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
4861 * pci_reset_bus - reset a PCI bus
4862 * @bus: top level PCI bus to reset
4864 * Do a bus reset on the given bus and any subordinate buses, saving
4865 * and restoring state of all devices.
4867 * Return 0 on success, non-zero on error.
4869 int pci_reset_bus(struct pci_bus *bus)
4873 rc = pci_bus_reset(bus, 1);
4877 pci_bus_save_and_disable(bus);
4879 rc = pci_bus_reset(bus, 0);
4881 pci_bus_restore(bus);
4885 EXPORT_SYMBOL_GPL(pci_reset_bus);
4888 * pci_try_reset_bus - Try to reset a PCI bus
4889 * @bus: top level PCI bus to reset
4891 * Same as above except return -EAGAIN if the bus cannot be locked
4893 int pci_try_reset_bus(struct pci_bus *bus)
4897 rc = pci_bus_reset(bus, 1);
4901 pci_bus_save_and_disable(bus);
4903 if (pci_bus_trylock(bus)) {
4905 pci_reset_bridge_secondary_bus(bus->self);
4906 pci_bus_unlock(bus);
4910 pci_bus_restore(bus);
4914 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
4917 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4918 * @dev: PCI device to query
4920 * Returns mmrbc: maximum designed memory read count in bytes
4921 * or appropriate error value.
4923 int pcix_get_max_mmrbc(struct pci_dev *dev)
4928 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4932 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4935 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
4937 EXPORT_SYMBOL(pcix_get_max_mmrbc);
4940 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4941 * @dev: PCI device to query
4943 * Returns mmrbc: maximum memory read count in bytes
4944 * or appropriate error value.
4946 int pcix_get_mmrbc(struct pci_dev *dev)
4951 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4955 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4958 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
4960 EXPORT_SYMBOL(pcix_get_mmrbc);
4963 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4964 * @dev: PCI device to query
4965 * @mmrbc: maximum memory read count in bytes
4966 * valid values are 512, 1024, 2048, 4096
4968 * If possible sets maximum memory read byte count, some bridges have erratas
4969 * that prevent this.
4971 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
4977 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
4980 v = ffs(mmrbc) - 10;
4982 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4986 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4989 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
4992 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4995 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
4997 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5000 cmd &= ~PCI_X_CMD_MAX_READ;
5002 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5007 EXPORT_SYMBOL(pcix_set_mmrbc);
5010 * pcie_get_readrq - get PCI Express read request size
5011 * @dev: PCI device to query
5013 * Returns maximum memory read request in bytes
5014 * or appropriate error value.
5016 int pcie_get_readrq(struct pci_dev *dev)
5020 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5022 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5024 EXPORT_SYMBOL(pcie_get_readrq);
5027 * pcie_set_readrq - set PCI Express maximum memory read request
5028 * @dev: PCI device to query
5029 * @rq: maximum memory read count in bytes
5030 * valid values are 128, 256, 512, 1024, 2048, 4096
5032 * If possible sets maximum memory read request in bytes
5034 int pcie_set_readrq(struct pci_dev *dev, int rq)
5038 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5042 * If using the "performance" PCIe config, we clamp the
5043 * read rq size to the max packet size to prevent the
5044 * host bridge generating requests larger than we can
5047 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5048 int mps = pcie_get_mps(dev);
5054 v = (ffs(rq) - 8) << 12;
5056 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5057 PCI_EXP_DEVCTL_READRQ, v);
5059 EXPORT_SYMBOL(pcie_set_readrq);
5062 * pcie_get_mps - get PCI Express maximum payload size
5063 * @dev: PCI device to query
5065 * Returns maximum payload size in bytes
5067 int pcie_get_mps(struct pci_dev *dev)
5071 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5073 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5075 EXPORT_SYMBOL(pcie_get_mps);
5078 * pcie_set_mps - set PCI Express maximum payload size
5079 * @dev: PCI device to query
5080 * @mps: maximum payload size in bytes
5081 * valid values are 128, 256, 512, 1024, 2048, 4096
5083 * If possible sets maximum payload size
5085 int pcie_set_mps(struct pci_dev *dev, int mps)
5089 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
5093 if (v > dev->pcie_mpss)
5097 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5098 PCI_EXP_DEVCTL_PAYLOAD, v);
5100 EXPORT_SYMBOL(pcie_set_mps);
5103 * pcie_get_minimum_link - determine minimum link settings of a PCI device
5104 * @dev: PCI device to query
5105 * @speed: storage for minimum speed
5106 * @width: storage for minimum width
5108 * This function will walk up the PCI device chain and determine the minimum
5109 * link width and speed of the device.
5111 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
5112 enum pcie_link_width *width)
5116 *speed = PCI_SPEED_UNKNOWN;
5117 *width = PCIE_LNK_WIDTH_UNKNOWN;
5121 enum pci_bus_speed next_speed;
5122 enum pcie_link_width next_width;
5124 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
5128 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
5129 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
5130 PCI_EXP_LNKSTA_NLW_SHIFT;
5132 if (next_speed < *speed)
5133 *speed = next_speed;
5135 if (next_width < *width)
5136 *width = next_width;
5138 dev = dev->bus->self;
5143 EXPORT_SYMBOL(pcie_get_minimum_link);
5146 * pci_select_bars - Make BAR mask from the type of resource
5147 * @dev: the PCI device for which BAR mask is made
5148 * @flags: resource type mask to be selected
5150 * This helper routine makes bar mask from the type of resource.
5152 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
5155 for (i = 0; i < PCI_NUM_RESOURCES; i++)
5156 if (pci_resource_flags(dev, i) & flags)
5160 EXPORT_SYMBOL(pci_select_bars);
5162 /* Some architectures require additional programming to enable VGA */
5163 static arch_set_vga_state_t arch_set_vga_state;
5165 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
5167 arch_set_vga_state = func; /* NULL disables */
5170 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
5171 unsigned int command_bits, u32 flags)
5173 if (arch_set_vga_state)
5174 return arch_set_vga_state(dev, decode, command_bits,
5180 * pci_set_vga_state - set VGA decode state on device and parents if requested
5181 * @dev: the PCI device
5182 * @decode: true = enable decoding, false = disable decoding
5183 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
5184 * @flags: traverse ancestors and change bridges
5185 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
5187 int pci_set_vga_state(struct pci_dev *dev, bool decode,
5188 unsigned int command_bits, u32 flags)
5190 struct pci_bus *bus;
5191 struct pci_dev *bridge;
5195 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
5197 /* ARCH specific VGA enables */
5198 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
5202 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
5203 pci_read_config_word(dev, PCI_COMMAND, &cmd);
5205 cmd |= command_bits;
5207 cmd &= ~command_bits;
5208 pci_write_config_word(dev, PCI_COMMAND, cmd);
5211 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
5218 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
5221 cmd |= PCI_BRIDGE_CTL_VGA;
5223 cmd &= ~PCI_BRIDGE_CTL_VGA;
5224 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
5233 * pci_add_dma_alias - Add a DMA devfn alias for a device
5234 * @dev: the PCI device for which alias is added
5235 * @devfn: alias slot and function
5237 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
5238 * It should be called early, preferably as PCI fixup header quirk.
5240 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
5242 if (!dev->dma_alias_mask)
5243 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
5244 sizeof(long), GFP_KERNEL);
5245 if (!dev->dma_alias_mask) {
5246 pci_warn(dev, "Unable to allocate DMA alias mask\n");
5250 set_bit(devfn, dev->dma_alias_mask);
5251 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
5252 PCI_SLOT(devfn), PCI_FUNC(devfn));
5255 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
5257 return (dev1->dma_alias_mask &&
5258 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
5259 (dev2->dma_alias_mask &&
5260 test_bit(dev1->devfn, dev2->dma_alias_mask));
5263 bool pci_device_is_present(struct pci_dev *pdev)
5267 if (pci_dev_is_disconnected(pdev))
5269 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
5271 EXPORT_SYMBOL_GPL(pci_device_is_present);
5273 void pci_ignore_hotplug(struct pci_dev *dev)
5275 struct pci_dev *bridge = dev->bus->self;
5277 dev->ignore_hotplug = 1;
5278 /* Propagate the "ignore hotplug" setting to the parent bridge. */
5280 bridge->ignore_hotplug = 1;
5282 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
5284 resource_size_t __weak pcibios_default_alignment(void)
5289 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
5290 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
5291 static DEFINE_SPINLOCK(resource_alignment_lock);
5294 * pci_specified_resource_alignment - get resource alignment specified by user.
5295 * @dev: the PCI device to get
5296 * @resize: whether or not to change resources' size when reassigning alignment
5298 * RETURNS: Resource alignment if it is specified.
5299 * Zero if it is not specified.
5301 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
5304 int seg, bus, slot, func, align_order, count;
5305 unsigned short vendor, device, subsystem_vendor, subsystem_device;
5306 resource_size_t align = pcibios_default_alignment();
5309 spin_lock(&resource_alignment_lock);
5310 p = resource_alignment_param;
5313 if (pci_has_flag(PCI_PROBE_ONLY)) {
5315 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
5321 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
5327 if (strncmp(p, "pci:", 4) == 0) {
5328 /* PCI vendor/device (subvendor/subdevice) ids are specified */
5330 if (sscanf(p, "%hx:%hx:%hx:%hx%n",
5331 &vendor, &device, &subsystem_vendor, &subsystem_device, &count) != 4) {
5332 if (sscanf(p, "%hx:%hx%n", &vendor, &device, &count) != 2) {
5333 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: pci:%s\n",
5337 subsystem_vendor = subsystem_device = 0;
5340 if ((!vendor || (vendor == dev->vendor)) &&
5341 (!device || (device == dev->device)) &&
5342 (!subsystem_vendor || (subsystem_vendor == dev->subsystem_vendor)) &&
5343 (!subsystem_device || (subsystem_device == dev->subsystem_device))) {
5345 if (align_order == -1)
5348 align = 1 << align_order;
5354 if (sscanf(p, "%x:%x:%x.%x%n",
5355 &seg, &bus, &slot, &func, &count) != 4) {
5357 if (sscanf(p, "%x:%x.%x%n",
5358 &bus, &slot, &func, &count) != 3) {
5359 /* Invalid format */
5360 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
5366 if (seg == pci_domain_nr(dev->bus) &&
5367 bus == dev->bus->number &&
5368 slot == PCI_SLOT(dev->devfn) &&
5369 func == PCI_FUNC(dev->devfn)) {
5371 if (align_order == -1)
5374 align = 1 << align_order;
5379 if (*p != ';' && *p != ',') {
5380 /* End of param or invalid format */
5386 spin_unlock(&resource_alignment_lock);
5390 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
5391 resource_size_t align, bool resize)
5393 struct resource *r = &dev->resource[bar];
5394 resource_size_t size;
5396 if (!(r->flags & IORESOURCE_MEM))
5399 if (r->flags & IORESOURCE_PCI_FIXED) {
5400 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
5401 bar, r, (unsigned long long)align);
5405 size = resource_size(r);
5410 * Increase the alignment of the resource. There are two ways we
5413 * 1) Increase the size of the resource. BARs are aligned on their
5414 * size, so when we reallocate space for this resource, we'll
5415 * allocate it with the larger alignment. This also prevents
5416 * assignment of any other BARs inside the alignment region, so
5417 * if we're requesting page alignment, this means no other BARs
5418 * will share the page.
5420 * The disadvantage is that this makes the resource larger than
5421 * the hardware BAR, which may break drivers that compute things
5422 * based on the resource size, e.g., to find registers at a
5423 * fixed offset before the end of the BAR.
5425 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
5426 * set r->start to the desired alignment. By itself this
5427 * doesn't prevent other BARs being put inside the alignment
5428 * region, but if we realign *every* resource of every device in
5429 * the system, none of them will share an alignment region.
5431 * When the user has requested alignment for only some devices via
5432 * the "pci=resource_alignment" argument, "resize" is true and we
5433 * use the first method. Otherwise we assume we're aligning all
5434 * devices and we use the second.
5437 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
5438 bar, r, (unsigned long long)align);
5444 r->flags &= ~IORESOURCE_SIZEALIGN;
5445 r->flags |= IORESOURCE_STARTALIGN;
5447 r->end = r->start + size - 1;
5449 r->flags |= IORESOURCE_UNSET;
5453 * This function disables memory decoding and releases memory resources
5454 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5455 * It also rounds up size to specified alignment.
5456 * Later on, the kernel will assign page-aligned memory resource back
5459 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
5463 resource_size_t align;
5465 bool resize = false;
5468 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
5469 * 3.4.1.11. Their resources are allocated from the space
5470 * described by the VF BARx register in the PF's SR-IOV capability.
5471 * We can't influence their alignment here.
5476 /* check if specified PCI is target device to reassign */
5477 align = pci_specified_resource_alignment(dev, &resize);
5481 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
5482 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
5483 pci_warn(dev, "Can't reassign resources to host bridge\n");
5487 pci_info(dev, "Disabling memory decoding and releasing memory resources\n");
5488 pci_read_config_word(dev, PCI_COMMAND, &command);
5489 command &= ~PCI_COMMAND_MEMORY;
5490 pci_write_config_word(dev, PCI_COMMAND, command);
5492 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
5493 pci_request_resource_alignment(dev, i, align, resize);
5496 * Need to disable bridge's resource window,
5497 * to enable the kernel to reassign new resource
5500 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
5501 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
5502 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
5503 r = &dev->resource[i];
5504 if (!(r->flags & IORESOURCE_MEM))
5506 r->flags |= IORESOURCE_UNSET;
5507 r->end = resource_size(r) - 1;
5510 pci_disable_bridge_window(dev);
5514 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
5516 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
5517 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
5518 spin_lock(&resource_alignment_lock);
5519 strncpy(resource_alignment_param, buf, count);
5520 resource_alignment_param[count] = '\0';
5521 spin_unlock(&resource_alignment_lock);
5525 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
5528 spin_lock(&resource_alignment_lock);
5529 count = snprintf(buf, size, "%s", resource_alignment_param);
5530 spin_unlock(&resource_alignment_lock);
5534 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
5536 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
5539 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
5540 const char *buf, size_t count)
5542 return pci_set_resource_alignment_param(buf, count);
5545 static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
5546 pci_resource_alignment_store);
5548 static int __init pci_resource_alignment_sysfs_init(void)
5550 return bus_create_file(&pci_bus_type,
5551 &bus_attr_resource_alignment);
5553 late_initcall(pci_resource_alignment_sysfs_init);
5555 static void pci_no_domains(void)
5557 #ifdef CONFIG_PCI_DOMAINS
5558 pci_domains_supported = 0;
5562 #ifdef CONFIG_PCI_DOMAINS
5563 static atomic_t __domain_nr = ATOMIC_INIT(-1);
5565 int pci_get_new_domain_nr(void)
5567 return atomic_inc_return(&__domain_nr);
5570 #ifdef CONFIG_PCI_DOMAINS_GENERIC
5571 static int of_pci_bus_find_domain_nr(struct device *parent)
5573 static int use_dt_domains = -1;
5577 domain = of_get_pci_domain_nr(parent->of_node);
5579 * Check DT domain and use_dt_domains values.
5581 * If DT domain property is valid (domain >= 0) and
5582 * use_dt_domains != 0, the DT assignment is valid since this means
5583 * we have not previously allocated a domain number by using
5584 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5585 * 1, to indicate that we have just assigned a domain number from
5588 * If DT domain property value is not valid (ie domain < 0), and we
5589 * have not previously assigned a domain number from DT
5590 * (use_dt_domains != 1) we should assign a domain number by
5593 * pci_get_new_domain_nr()
5595 * API and update the use_dt_domains value to keep track of method we
5596 * are using to assign domain numbers (use_dt_domains = 0).
5598 * All other combinations imply we have a platform that is trying
5599 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5600 * which is a recipe for domain mishandling and it is prevented by
5601 * invalidating the domain value (domain = -1) and printing a
5602 * corresponding error.
5604 if (domain >= 0 && use_dt_domains) {
5606 } else if (domain < 0 && use_dt_domains != 1) {
5608 domain = pci_get_new_domain_nr();
5610 dev_err(parent, "Node %pOF has inconsistent \"linux,pci-domain\" property in DT\n",
5618 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
5620 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
5621 acpi_pci_bus_find_domain_nr(bus);
5627 * pci_ext_cfg_avail - can we access extended PCI config space?
5629 * Returns 1 if we can access PCI extended config space (offsets
5630 * greater than 0xff). This is the default implementation. Architecture
5631 * implementations can override this.
5633 int __weak pci_ext_cfg_avail(void)
5638 void __weak pci_fixup_cardbus(struct pci_bus *bus)
5641 EXPORT_SYMBOL(pci_fixup_cardbus);
5643 static int __init pci_setup(char *str)
5646 char *k = strchr(str, ',');
5649 if (*str && (str = pcibios_setup(str)) && *str) {
5650 if (!strcmp(str, "nomsi")) {
5652 } else if (!strcmp(str, "noaer")) {
5654 } else if (!strncmp(str, "realloc=", 8)) {
5655 pci_realloc_get_opt(str + 8);
5656 } else if (!strncmp(str, "realloc", 7)) {
5657 pci_realloc_get_opt("on");
5658 } else if (!strcmp(str, "nodomains")) {
5660 } else if (!strncmp(str, "noari", 5)) {
5661 pcie_ari_disabled = true;
5662 } else if (!strncmp(str, "cbiosize=", 9)) {
5663 pci_cardbus_io_size = memparse(str + 9, &str);
5664 } else if (!strncmp(str, "cbmemsize=", 10)) {
5665 pci_cardbus_mem_size = memparse(str + 10, &str);
5666 } else if (!strncmp(str, "resource_alignment=", 19)) {
5667 pci_set_resource_alignment_param(str + 19,
5669 } else if (!strncmp(str, "ecrc=", 5)) {
5670 pcie_ecrc_get_policy(str + 5);
5671 } else if (!strncmp(str, "hpiosize=", 9)) {
5672 pci_hotplug_io_size = memparse(str + 9, &str);
5673 } else if (!strncmp(str, "hpmemsize=", 10)) {
5674 pci_hotplug_mem_size = memparse(str + 10, &str);
5675 } else if (!strncmp(str, "hpbussize=", 10)) {
5676 pci_hotplug_bus_size =
5677 simple_strtoul(str + 10, &str, 0);
5678 if (pci_hotplug_bus_size > 0xff)
5679 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
5680 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
5681 pcie_bus_config = PCIE_BUS_TUNE_OFF;
5682 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
5683 pcie_bus_config = PCIE_BUS_SAFE;
5684 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
5685 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5686 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
5687 pcie_bus_config = PCIE_BUS_PEER2PEER;
5688 } else if (!strncmp(str, "pcie_scan_all", 13)) {
5689 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
5691 printk(KERN_ERR "PCI: Unknown option `%s'\n",
5699 early_param("pci", pci_setup);