1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
33 #include <linux/aer.h>
36 DEFINE_MUTEX(pci_slot_mutex);
38 const char *pci_power_names[] = {
39 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
41 EXPORT_SYMBOL_GPL(pci_power_names);
43 int isa_dma_bridge_buggy;
44 EXPORT_SYMBOL(isa_dma_bridge_buggy);
47 EXPORT_SYMBOL(pci_pci_problems);
49 unsigned int pci_pm_d3hot_delay;
51 static void pci_pme_list_scan(struct work_struct *work);
53 static LIST_HEAD(pci_pme_list);
54 static DEFINE_MUTEX(pci_pme_list_mutex);
55 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
57 struct pci_pme_device {
58 struct list_head list;
62 #define PME_TIMEOUT 1000 /* How long between PME checks */
64 static void pci_dev_d3_sleep(struct pci_dev *dev)
66 unsigned int delay = dev->d3hot_delay;
68 if (delay < pci_pm_d3hot_delay)
69 delay = pci_pm_d3hot_delay;
75 #ifdef CONFIG_PCI_DOMAINS
76 int pci_domains_supported = 1;
79 #define DEFAULT_CARDBUS_IO_SIZE (256)
80 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
81 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
82 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
83 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
85 #define DEFAULT_HOTPLUG_IO_SIZE (256)
86 #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
87 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
88 /* hpiosize=nn can override this */
89 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
91 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
92 * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
93 * pci=hpmemsize=nnM overrides both
95 unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
96 unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
98 #define DEFAULT_HOTPLUG_BUS_SIZE 1
99 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
102 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
103 #ifdef CONFIG_PCIE_BUS_TUNE_OFF
104 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
105 #elif defined CONFIG_PCIE_BUS_SAFE
106 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
107 #elif defined CONFIG_PCIE_BUS_PERFORMANCE
108 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
109 #elif defined CONFIG_PCIE_BUS_PEER2PEER
110 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
112 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
116 * The default CLS is used if arch didn't set CLS explicitly and not
117 * all pci devices agree on the same value. Arch can override either
118 * the dfl or actual value as it sees fit. Don't forget this is
119 * measured in 32-bit words, not bytes.
121 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
122 u8 pci_cache_line_size;
125 * If we set up a device for bus mastering, we need to check the latency
126 * timer as certain BIOSes forget to set it properly.
128 unsigned int pcibios_max_latency = 255;
130 /* If set, the PCIe ARI capability will not be used. */
131 static bool pcie_ari_disabled;
133 /* If set, the PCIe ATS capability will not be used. */
134 static bool pcie_ats_disabled;
136 /* If set, the PCI config space of each device is printed during boot. */
139 bool pci_ats_disabled(void)
141 return pcie_ats_disabled;
143 EXPORT_SYMBOL_GPL(pci_ats_disabled);
145 /* Disable bridge_d3 for all PCIe ports */
146 static bool pci_bridge_d3_disable;
147 /* Force bridge_d3 for all PCIe ports */
148 static bool pci_bridge_d3_force;
150 static int __init pcie_port_pm_setup(char *str)
152 if (!strcmp(str, "off"))
153 pci_bridge_d3_disable = true;
154 else if (!strcmp(str, "force"))
155 pci_bridge_d3_force = true;
158 __setup("pcie_port_pm=", pcie_port_pm_setup);
160 /* Time to wait after a reset for device to become responsive */
161 #define PCIE_RESET_READY_POLL_MS 60000
164 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
165 * @bus: pointer to PCI bus structure to search
167 * Given a PCI bus, returns the highest PCI bus number present in the set
168 * including the given PCI bus and its list of child PCI buses.
170 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
173 unsigned char max, n;
175 max = bus->busn_res.end;
176 list_for_each_entry(tmp, &bus->children, node) {
177 n = pci_bus_max_busnr(tmp);
183 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
186 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
187 * @pdev: the PCI device
189 * Returns error bits set in PCI_STATUS and clears them.
191 int pci_status_get_and_clear_errors(struct pci_dev *pdev)
196 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
197 if (ret != PCIBIOS_SUCCESSFUL)
200 status &= PCI_STATUS_ERROR_BITS;
202 pci_write_config_word(pdev, PCI_STATUS, status);
206 EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
208 #ifdef CONFIG_HAS_IOMEM
209 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
211 struct resource *res = &pdev->resource[bar];
214 * Make sure the BAR is actually a memory resource, not an IO resource
216 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
217 pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
220 return ioremap(res->start, resource_size(res));
222 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
224 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
227 * Make sure the BAR is actually a memory resource, not an IO resource
229 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
233 return ioremap_wc(pci_resource_start(pdev, bar),
234 pci_resource_len(pdev, bar));
236 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
240 * pci_dev_str_match_path - test if a path string matches a device
241 * @dev: the PCI device to test
242 * @path: string to match the device against
243 * @endptr: pointer to the string after the match
245 * Test if a string (typically from a kernel parameter) formatted as a
246 * path of device/function addresses matches a PCI device. The string must
249 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
251 * A path for a device can be obtained using 'lspci -t'. Using a path
252 * is more robust against bus renumbering than using only a single bus,
253 * device and function address.
255 * Returns 1 if the string matches the device, 0 if it does not and
256 * a negative error code if it fails to parse the string.
258 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
262 int seg, bus, slot, func;
266 *endptr = strchrnul(path, ';');
268 wpath = kmemdup_nul(path, *endptr - path, GFP_KERNEL);
273 p = strrchr(wpath, '/');
276 ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
282 if (dev->devfn != PCI_DEVFN(slot, func)) {
288 * Note: we don't need to get a reference to the upstream
289 * bridge because we hold a reference to the top level
290 * device which should hold a reference to the bridge,
293 dev = pci_upstream_bridge(dev);
302 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
306 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
313 ret = (seg == pci_domain_nr(dev->bus) &&
314 bus == dev->bus->number &&
315 dev->devfn == PCI_DEVFN(slot, func));
323 * pci_dev_str_match - test if a string matches a device
324 * @dev: the PCI device to test
325 * @p: string to match the device against
326 * @endptr: pointer to the string after the match
328 * Test if a string (typically from a kernel parameter) matches a specified
329 * PCI device. The string may be of one of the following formats:
331 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
332 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
334 * The first format specifies a PCI bus/device/function address which
335 * may change if new hardware is inserted, if motherboard firmware changes,
336 * or due to changes caused in kernel parameters. If the domain is
337 * left unspecified, it is taken to be 0. In order to be robust against
338 * bus renumbering issues, a path of PCI device/function numbers may be used
339 * to address the specific device. The path for a device can be determined
340 * through the use of 'lspci -t'.
342 * The second format matches devices using IDs in the configuration
343 * space which may match multiple devices in the system. A value of 0
344 * for any field will match all devices. (Note: this differs from
345 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
346 * legacy reasons and convenience so users don't have to specify
347 * FFFFFFFFs on the command line.)
349 * Returns 1 if the string matches the device, 0 if it does not and
350 * a negative error code if the string cannot be parsed.
352 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
357 unsigned short vendor, device, subsystem_vendor, subsystem_device;
359 if (strncmp(p, "pci:", 4) == 0) {
360 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
362 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
363 &subsystem_vendor, &subsystem_device, &count);
365 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
369 subsystem_vendor = 0;
370 subsystem_device = 0;
375 if ((!vendor || vendor == dev->vendor) &&
376 (!device || device == dev->device) &&
377 (!subsystem_vendor ||
378 subsystem_vendor == dev->subsystem_vendor) &&
379 (!subsystem_device ||
380 subsystem_device == dev->subsystem_device))
384 * PCI Bus, Device, Function IDs are specified
385 * (optionally, may include a path of devfns following it)
387 ret = pci_dev_str_match_path(dev, p, &p);
402 static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
403 u8 pos, int cap, int *ttl)
408 pci_bus_read_config_byte(bus, devfn, pos, &pos);
414 pci_bus_read_config_word(bus, devfn, pos, &ent);
426 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
429 int ttl = PCI_FIND_CAP_TTL;
431 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
434 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
436 return __pci_find_next_cap(dev->bus, dev->devfn,
437 pos + PCI_CAP_LIST_NEXT, cap);
439 EXPORT_SYMBOL_GPL(pci_find_next_capability);
441 static u8 __pci_bus_find_cap_start(struct pci_bus *bus,
442 unsigned int devfn, u8 hdr_type)
446 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
447 if (!(status & PCI_STATUS_CAP_LIST))
451 case PCI_HEADER_TYPE_NORMAL:
452 case PCI_HEADER_TYPE_BRIDGE:
453 return PCI_CAPABILITY_LIST;
454 case PCI_HEADER_TYPE_CARDBUS:
455 return PCI_CB_CAPABILITY_LIST;
462 * pci_find_capability - query for devices' capabilities
463 * @dev: PCI device to query
464 * @cap: capability code
466 * Tell if a device supports a given PCI capability.
467 * Returns the address of the requested capability structure within the
468 * device's PCI configuration space or 0 in case the device does not
469 * support it. Possible values for @cap include:
471 * %PCI_CAP_ID_PM Power Management
472 * %PCI_CAP_ID_AGP Accelerated Graphics Port
473 * %PCI_CAP_ID_VPD Vital Product Data
474 * %PCI_CAP_ID_SLOTID Slot Identification
475 * %PCI_CAP_ID_MSI Message Signalled Interrupts
476 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
477 * %PCI_CAP_ID_PCIX PCI-X
478 * %PCI_CAP_ID_EXP PCI Express
480 u8 pci_find_capability(struct pci_dev *dev, int cap)
484 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
486 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
490 EXPORT_SYMBOL(pci_find_capability);
493 * pci_bus_find_capability - query for devices' capabilities
494 * @bus: the PCI bus to query
495 * @devfn: PCI device to query
496 * @cap: capability code
498 * Like pci_find_capability() but works for PCI devices that do not have a
499 * pci_dev structure set up yet.
501 * Returns the address of the requested capability structure within the
502 * device's PCI configuration space or 0 in case the device does not
505 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
509 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
511 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
513 pos = __pci_find_next_cap(bus, devfn, pos, cap);
517 EXPORT_SYMBOL(pci_bus_find_capability);
520 * pci_find_next_ext_capability - Find an extended capability
521 * @dev: PCI device to query
522 * @start: address at which to start looking (0 to start at beginning of list)
523 * @cap: capability code
525 * Returns the address of the next matching extended capability structure
526 * within the device's PCI configuration space or 0 if the device does
527 * not support it. Some capabilities can occur several times, e.g., the
528 * vendor-specific capability, and this provides a way to find them all.
530 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
534 u16 pos = PCI_CFG_SPACE_SIZE;
536 /* minimum 8 bytes per capability */
537 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
539 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
545 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
549 * If we have no capabilities, this is indicated by cap ID,
550 * cap version and next pointer all being 0.
556 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
559 pos = PCI_EXT_CAP_NEXT(header);
560 if (pos < PCI_CFG_SPACE_SIZE)
563 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
569 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
572 * pci_find_ext_capability - Find an extended capability
573 * @dev: PCI device to query
574 * @cap: capability code
576 * Returns the address of the requested extended capability structure
577 * within the device's PCI configuration space or 0 if the device does
578 * not support it. Possible values for @cap include:
580 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
581 * %PCI_EXT_CAP_ID_VC Virtual Channel
582 * %PCI_EXT_CAP_ID_DSN Device Serial Number
583 * %PCI_EXT_CAP_ID_PWR Power Budgeting
585 u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
587 return pci_find_next_ext_capability(dev, 0, cap);
589 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
592 * pci_get_dsn - Read and return the 8-byte Device Serial Number
593 * @dev: PCI device to query
595 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
598 * Returns the DSN, or zero if the capability does not exist.
600 u64 pci_get_dsn(struct pci_dev *dev)
606 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
611 * The Device Serial Number is two dwords offset 4 bytes from the
612 * capability position. The specification says that the first dword is
613 * the lower half, and the second dword is the upper half.
616 pci_read_config_dword(dev, pos, &dword);
618 pci_read_config_dword(dev, pos + 4, &dword);
619 dsn |= ((u64)dword) << 32;
623 EXPORT_SYMBOL_GPL(pci_get_dsn);
625 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
627 int rc, ttl = PCI_FIND_CAP_TTL;
630 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
631 mask = HT_3BIT_CAP_MASK;
633 mask = HT_5BIT_CAP_MASK;
635 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
636 PCI_CAP_ID_HT, &ttl);
638 rc = pci_read_config_byte(dev, pos + 3, &cap);
639 if (rc != PCIBIOS_SUCCESSFUL)
642 if ((cap & mask) == ht_cap)
645 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
646 pos + PCI_CAP_LIST_NEXT,
647 PCI_CAP_ID_HT, &ttl);
654 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
655 * @dev: PCI device to query
656 * @pos: Position from which to continue searching
657 * @ht_cap: HyperTransport capability code
659 * To be used in conjunction with pci_find_ht_capability() to search for
660 * all capabilities matching @ht_cap. @pos should always be a value returned
661 * from pci_find_ht_capability().
663 * NB. To be 100% safe against broken PCI devices, the caller should take
664 * steps to avoid an infinite loop.
666 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap)
668 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
670 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
673 * pci_find_ht_capability - query a device's HyperTransport capabilities
674 * @dev: PCI device to query
675 * @ht_cap: HyperTransport capability code
677 * Tell if a device supports a given HyperTransport capability.
678 * Returns an address within the device's PCI configuration space
679 * or 0 in case the device does not support the request capability.
680 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
681 * which has a HyperTransport capability matching @ht_cap.
683 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
687 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
689 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
693 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
696 * pci_find_parent_resource - return resource region of parent bus of given
698 * @dev: PCI device structure contains resources to be searched
699 * @res: child resource record for which parent is sought
701 * For given resource region of given device, return the resource region of
702 * parent bus the given region is contained in.
704 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
705 struct resource *res)
707 const struct pci_bus *bus = dev->bus;
711 pci_bus_for_each_resource(bus, r, i) {
714 if (resource_contains(r, res)) {
717 * If the window is prefetchable but the BAR is
718 * not, the allocator made a mistake.
720 if (r->flags & IORESOURCE_PREFETCH &&
721 !(res->flags & IORESOURCE_PREFETCH))
725 * If we're below a transparent bridge, there may
726 * be both a positively-decoded aperture and a
727 * subtractively-decoded region that contain the BAR.
728 * We want the positively-decoded one, so this depends
729 * on pci_bus_for_each_resource() giving us those
737 EXPORT_SYMBOL(pci_find_parent_resource);
740 * pci_find_resource - Return matching PCI device resource
741 * @dev: PCI device to query
742 * @res: Resource to look for
744 * Goes over standard PCI resources (BARs) and checks if the given resource
745 * is partially or fully contained in any of them. In that case the
746 * matching resource is returned, %NULL otherwise.
748 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
752 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
753 struct resource *r = &dev->resource[i];
755 if (r->start && resource_contains(r, res))
761 EXPORT_SYMBOL(pci_find_resource);
764 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
765 * @dev: the PCI device to operate on
766 * @pos: config space offset of status word
767 * @mask: mask of bit(s) to care about in status word
769 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
771 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
775 /* Wait for Transaction Pending bit clean */
776 for (i = 0; i < 4; i++) {
779 msleep((1 << (i - 1)) * 100);
781 pci_read_config_word(dev, pos, &status);
782 if (!(status & mask))
789 static int pci_acs_enable;
792 * pci_request_acs - ask for ACS to be enabled if supported
794 void pci_request_acs(void)
799 static const char *disable_acs_redir_param;
802 * pci_disable_acs_redir - disable ACS redirect capabilities
803 * @dev: the PCI device
805 * For only devices specified in the disable_acs_redir parameter.
807 static void pci_disable_acs_redir(struct pci_dev *dev)
814 if (!disable_acs_redir_param)
817 p = disable_acs_redir_param;
819 ret = pci_dev_str_match(dev, p, &p);
821 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
822 disable_acs_redir_param);
825 } else if (ret == 1) {
830 if (*p != ';' && *p != ',') {
831 /* End of param or invalid format */
840 if (!pci_dev_specific_disable_acs_redir(dev))
845 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
849 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
851 /* P2P Request & Completion Redirect */
852 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
854 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
856 pci_info(dev, "disabled ACS redirect\n");
860 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
861 * @dev: the PCI device
863 static void pci_std_enable_acs(struct pci_dev *dev)
873 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
874 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
876 /* Source Validation */
877 ctrl |= (cap & PCI_ACS_SV);
879 /* P2P Request Redirect */
880 ctrl |= (cap & PCI_ACS_RR);
882 /* P2P Completion Redirect */
883 ctrl |= (cap & PCI_ACS_CR);
885 /* Upstream Forwarding */
886 ctrl |= (cap & PCI_ACS_UF);
888 /* Enable Translation Blocking for external devices */
889 if (dev->external_facing || dev->untrusted)
890 ctrl |= (cap & PCI_ACS_TB);
892 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
896 * pci_enable_acs - enable ACS if hardware support it
897 * @dev: the PCI device
899 static void pci_enable_acs(struct pci_dev *dev)
902 goto disable_acs_redir;
904 if (!pci_dev_specific_enable_acs(dev))
905 goto disable_acs_redir;
907 pci_std_enable_acs(dev);
911 * Note: pci_disable_acs_redir() must be called even if ACS was not
912 * enabled by the kernel because it may have been enabled by
913 * platform firmware. So if we are told to disable it, we should
914 * always disable it after setting the kernel's default
917 pci_disable_acs_redir(dev);
921 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
922 * @dev: PCI device to have its BARs restored
924 * Restore the BAR values for a given device, so as to make it
925 * accessible by its driver.
927 static void pci_restore_bars(struct pci_dev *dev)
931 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
932 pci_update_resource(dev, i);
935 static const struct pci_platform_pm_ops *pci_platform_pm;
937 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
939 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
940 !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
942 pci_platform_pm = ops;
946 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
948 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
951 static inline int platform_pci_set_power_state(struct pci_dev *dev,
954 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
957 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
959 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
962 static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
964 if (pci_platform_pm && pci_platform_pm->refresh_state)
965 pci_platform_pm->refresh_state(dev);
968 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
970 return pci_platform_pm ?
971 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
974 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
976 return pci_platform_pm ?
977 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
980 static inline bool platform_pci_need_resume(struct pci_dev *dev)
982 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
985 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
987 if (pci_platform_pm && pci_platform_pm->bridge_d3)
988 return pci_platform_pm->bridge_d3(dev);
993 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
995 * @dev: PCI device to handle.
996 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
999 * -EINVAL if the requested state is invalid.
1000 * -EIO if device does not support PCI PM or its PM capabilities register has a
1001 * wrong version, or device doesn't support the requested state.
1002 * 0 if device already is in the requested state.
1003 * 0 if device's power state has been successfully changed.
1005 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
1008 bool need_restore = false;
1010 /* Check if we're already there */
1011 if (dev->current_state == state)
1017 if (state < PCI_D0 || state > PCI_D3hot)
1021 * Validate transition: We can enter D0 from any state, but if
1022 * we're already in a low-power state, we can only go deeper. E.g.,
1023 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1024 * we'd have to go from D3 to D0, then to D1.
1026 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
1027 && dev->current_state > state) {
1028 pci_err(dev, "invalid power transition (from %s to %s)\n",
1029 pci_power_name(dev->current_state),
1030 pci_power_name(state));
1034 /* Check if this device supports the desired state */
1035 if ((state == PCI_D1 && !dev->d1_support)
1036 || (state == PCI_D2 && !dev->d2_support))
1039 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1040 if (pmcsr == (u16) ~0) {
1041 pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n",
1042 pci_power_name(dev->current_state),
1043 pci_power_name(state));
1048 * If we're (effectively) in D3, force entire word to 0.
1049 * This doesn't affect PME_Status, disables PME_En, and
1050 * sets PowerState to 0.
1052 switch (dev->current_state) {
1056 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
1061 case PCI_UNKNOWN: /* Boot-up */
1062 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
1063 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
1064 need_restore = true;
1065 fallthrough; /* force to D0 */
1071 /* Enter specified state */
1072 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1075 * Mandatory power management transition delays; see PCI PM 1.1
1078 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1079 pci_dev_d3_sleep(dev);
1080 else if (state == PCI_D2 || dev->current_state == PCI_D2)
1081 udelay(PCI_PM_D2_DELAY);
1083 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1084 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1085 if (dev->current_state != state)
1086 pci_info_ratelimited(dev, "refused to change power state from %s to %s\n",
1087 pci_power_name(dev->current_state),
1088 pci_power_name(state));
1091 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1092 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1093 * from D3hot to D0 _may_ perform an internal reset, thereby
1094 * going to "D0 Uninitialized" rather than "D0 Initialized".
1095 * For example, at least some versions of the 3c905B and the
1096 * 3c556B exhibit this behaviour.
1098 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1099 * devices in a D3hot state at boot. Consequently, we need to
1100 * restore at least the BARs so that the device will be
1101 * accessible to its driver.
1104 pci_restore_bars(dev);
1107 pcie_aspm_pm_state_change(dev->bus->self);
1113 * pci_update_current_state - Read power state of given device and cache it
1114 * @dev: PCI device to handle.
1115 * @state: State to cache in case the device doesn't have the PM capability
1117 * The power state is read from the PMCSR register, which however is
1118 * inaccessible in D3cold. The platform firmware is therefore queried first
1119 * to detect accessibility of the register. In case the platform firmware
1120 * reports an incorrect state or the device isn't power manageable by the
1121 * platform at all, we try to detect D3cold by testing accessibility of the
1122 * vendor ID in config space.
1124 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1126 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
1127 !pci_device_is_present(dev)) {
1128 dev->current_state = PCI_D3cold;
1129 } else if (dev->pm_cap) {
1132 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1133 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1135 dev->current_state = state;
1140 * pci_refresh_power_state - Refresh the given device's power state data
1141 * @dev: Target PCI device.
1143 * Ask the platform to refresh the devices power state information and invoke
1144 * pci_update_current_state() to update its current PCI power state.
1146 void pci_refresh_power_state(struct pci_dev *dev)
1148 if (platform_pci_power_manageable(dev))
1149 platform_pci_refresh_power_state(dev);
1151 pci_update_current_state(dev, dev->current_state);
1155 * pci_platform_power_transition - Use platform to change device power state
1156 * @dev: PCI device to handle.
1157 * @state: State to put the device into.
1159 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1163 if (platform_pci_power_manageable(dev)) {
1164 error = platform_pci_set_power_state(dev, state);
1166 pci_update_current_state(dev, state);
1170 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
1171 dev->current_state = PCI_D0;
1175 EXPORT_SYMBOL_GPL(pci_platform_power_transition);
1177 static int pci_resume_one(struct pci_dev *pci_dev, void *ign)
1179 pm_request_resume(&pci_dev->dev);
1184 * pci_resume_bus - Walk given bus and runtime resume devices on it
1185 * @bus: Top bus of the subtree to walk.
1187 void pci_resume_bus(struct pci_bus *bus)
1190 pci_walk_bus(bus, pci_resume_one, NULL);
1193 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1199 * After reset, the device should not silently discard config
1200 * requests, but it may still indicate that it needs more time by
1201 * responding to them with CRS completions. The Root Port will
1202 * generally synthesize ~0 data to complete the read (except when
1203 * CRS SV is enabled and the read was for the Vendor ID; in that
1204 * case it synthesizes 0x0001 data).
1206 * Wait for the device to return a non-CRS completion. Read the
1207 * Command register instead of Vendor ID so we don't have to
1208 * contend with the CRS SV value.
1210 pci_read_config_dword(dev, PCI_COMMAND, &id);
1212 if (delay > timeout) {
1213 pci_warn(dev, "not ready %dms after %s; giving up\n",
1214 delay - 1, reset_type);
1219 pci_info(dev, "not ready %dms after %s; waiting\n",
1220 delay - 1, reset_type);
1224 pci_read_config_dword(dev, PCI_COMMAND, &id);
1228 pci_info(dev, "ready %dms after %s\n", delay - 1,
1235 * pci_power_up - Put the given device into D0
1236 * @dev: PCI device to power up
1238 int pci_power_up(struct pci_dev *dev)
1240 pci_platform_power_transition(dev, PCI_D0);
1243 * Mandatory power management transition delays are handled in
1244 * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the
1245 * corresponding bridge.
1247 if (dev->runtime_d3cold) {
1249 * When powering on a bridge from D3cold, the whole hierarchy
1250 * may be powered on into D0uninitialized state, resume them to
1251 * give them a chance to suspend again
1253 pci_resume_bus(dev->subordinate);
1256 return pci_raw_set_power_state(dev, PCI_D0);
1260 * __pci_dev_set_current_state - Set current state of a PCI device
1261 * @dev: Device to handle
1262 * @data: pointer to state to be set
1264 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1266 pci_power_t state = *(pci_power_t *)data;
1268 dev->current_state = state;
1273 * pci_bus_set_current_state - Walk given bus and set current state of devices
1274 * @bus: Top bus of the subtree to walk.
1275 * @state: state to be set
1277 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1280 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1284 * pci_set_power_state - Set the power state of a PCI device
1285 * @dev: PCI device to handle.
1286 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1288 * Transition a device to a new power state, using the platform firmware and/or
1289 * the device's PCI PM registers.
1292 * -EINVAL if the requested state is invalid.
1293 * -EIO if device does not support PCI PM or its PM capabilities register has a
1294 * wrong version, or device doesn't support the requested state.
1295 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1296 * 0 if device already is in the requested state.
1297 * 0 if the transition is to D3 but D3 is not supported.
1298 * 0 if device's power state has been successfully changed.
1300 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1304 /* Bound the state we're entering */
1305 if (state > PCI_D3cold)
1307 else if (state < PCI_D0)
1309 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1312 * If the device or the parent bridge do not support PCI
1313 * PM, ignore the request if we're doing anything other
1314 * than putting it into D0 (which would only happen on
1319 /* Check if we're already there */
1320 if (dev->current_state == state)
1323 if (state == PCI_D0)
1324 return pci_power_up(dev);
1327 * This device is quirked not to be put into D3, so don't put it in
1330 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1334 * To put device in D3cold, we put device into D3hot in native
1335 * way, then put device into D3cold with platform ops
1337 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
1340 if (pci_platform_power_transition(dev, state))
1343 /* Powering off a bridge may power off the whole hierarchy */
1344 if (state == PCI_D3cold)
1345 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1349 EXPORT_SYMBOL(pci_set_power_state);
1352 * pci_choose_state - Choose the power state of a PCI device
1353 * @dev: PCI device to be suspended
1354 * @state: target sleep state for the whole system. This is the value
1355 * that is passed to suspend() function.
1357 * Returns PCI power state suitable for given device and given system
1360 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
1367 ret = platform_pci_choose_state(dev);
1368 if (ret != PCI_POWER_ERROR)
1371 switch (state.event) {
1374 case PM_EVENT_FREEZE:
1375 case PM_EVENT_PRETHAW:
1376 /* REVISIT both freeze and pre-thaw "should" use D0 */
1377 case PM_EVENT_SUSPEND:
1378 case PM_EVENT_HIBERNATE:
1381 pci_info(dev, "unrecognized suspend event %d\n",
1387 EXPORT_SYMBOL(pci_choose_state);
1389 #define PCI_EXP_SAVE_REGS 7
1391 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1392 u16 cap, bool extended)
1394 struct pci_cap_saved_state *tmp;
1396 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1397 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1403 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1405 return _pci_find_saved_cap(dev, cap, false);
1408 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1410 return _pci_find_saved_cap(dev, cap, true);
1413 static int pci_save_pcie_state(struct pci_dev *dev)
1416 struct pci_cap_saved_state *save_state;
1419 if (!pci_is_pcie(dev))
1422 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1424 pci_err(dev, "buffer not found in %s\n", __func__);
1428 cap = (u16 *)&save_state->cap.data[0];
1429 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1430 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1431 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1432 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1433 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1434 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1435 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1440 static void pci_restore_pcie_state(struct pci_dev *dev)
1443 struct pci_cap_saved_state *save_state;
1446 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1450 cap = (u16 *)&save_state->cap.data[0];
1451 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1452 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1453 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1454 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1455 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1456 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1457 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1460 static int pci_save_pcix_state(struct pci_dev *dev)
1463 struct pci_cap_saved_state *save_state;
1465 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1469 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1471 pci_err(dev, "buffer not found in %s\n", __func__);
1475 pci_read_config_word(dev, pos + PCI_X_CMD,
1476 (u16 *)save_state->cap.data);
1481 static void pci_restore_pcix_state(struct pci_dev *dev)
1484 struct pci_cap_saved_state *save_state;
1487 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1488 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1489 if (!save_state || !pos)
1491 cap = (u16 *)&save_state->cap.data[0];
1493 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1496 static void pci_save_ltr_state(struct pci_dev *dev)
1499 struct pci_cap_saved_state *save_state;
1502 if (!pci_is_pcie(dev))
1505 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1509 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1511 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1515 cap = (u16 *)&save_state->cap.data[0];
1516 pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++);
1517 pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++);
1520 static void pci_restore_ltr_state(struct pci_dev *dev)
1522 struct pci_cap_saved_state *save_state;
1526 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1527 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1528 if (!save_state || !ltr)
1531 cap = (u16 *)&save_state->cap.data[0];
1532 pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++);
1533 pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++);
1537 * pci_save_state - save the PCI configuration space of a device before
1539 * @dev: PCI device that we're dealing with
1541 int pci_save_state(struct pci_dev *dev)
1544 /* XXX: 100% dword access ok here? */
1545 for (i = 0; i < 16; i++) {
1546 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1547 pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
1548 i * 4, dev->saved_config_space[i]);
1550 dev->state_saved = true;
1552 i = pci_save_pcie_state(dev);
1556 i = pci_save_pcix_state(dev);
1560 pci_save_ltr_state(dev);
1561 pci_save_dpc_state(dev);
1562 pci_save_aer_state(dev);
1563 pci_save_ptm_state(dev);
1564 return pci_save_vc_state(dev);
1566 EXPORT_SYMBOL(pci_save_state);
1568 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1569 u32 saved_val, int retry, bool force)
1573 pci_read_config_dword(pdev, offset, &val);
1574 if (!force && val == saved_val)
1578 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1579 offset, val, saved_val);
1580 pci_write_config_dword(pdev, offset, saved_val);
1584 pci_read_config_dword(pdev, offset, &val);
1585 if (val == saved_val)
1592 static void pci_restore_config_space_range(struct pci_dev *pdev,
1593 int start, int end, int retry,
1598 for (index = end; index >= start; index--)
1599 pci_restore_config_dword(pdev, 4 * index,
1600 pdev->saved_config_space[index],
1604 static void pci_restore_config_space(struct pci_dev *pdev)
1606 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1607 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1608 /* Restore BARs before the command register. */
1609 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1610 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1611 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1612 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1615 * Force rewriting of prefetch registers to avoid S3 resume
1616 * issues on Intel PCI bridges that occur when these
1617 * registers are not explicitly written.
1619 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1620 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1622 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1626 static void pci_restore_rebar_state(struct pci_dev *pdev)
1628 unsigned int pos, nbars, i;
1631 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1635 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1636 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
1637 PCI_REBAR_CTRL_NBAR_SHIFT;
1639 for (i = 0; i < nbars; i++, pos += 8) {
1640 struct resource *res;
1643 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1644 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1645 res = pdev->resource + bar_idx;
1646 size = pci_rebar_bytes_to_size(resource_size(res));
1647 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1648 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
1649 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1654 * pci_restore_state - Restore the saved state of a PCI device
1655 * @dev: PCI device that we're dealing with
1657 void pci_restore_state(struct pci_dev *dev)
1659 if (!dev->state_saved)
1663 * Restore max latencies (in the LTR capability) before enabling
1664 * LTR itself (in the PCIe capability).
1666 pci_restore_ltr_state(dev);
1668 pci_restore_pcie_state(dev);
1669 pci_restore_pasid_state(dev);
1670 pci_restore_pri_state(dev);
1671 pci_restore_ats_state(dev);
1672 pci_restore_vc_state(dev);
1673 pci_restore_rebar_state(dev);
1674 pci_restore_dpc_state(dev);
1675 pci_restore_ptm_state(dev);
1677 pci_aer_clear_status(dev);
1678 pci_restore_aer_state(dev);
1680 pci_restore_config_space(dev);
1682 pci_restore_pcix_state(dev);
1683 pci_restore_msi_state(dev);
1685 /* Restore ACS and IOV configuration state */
1686 pci_enable_acs(dev);
1687 pci_restore_iov_state(dev);
1689 dev->state_saved = false;
1691 EXPORT_SYMBOL(pci_restore_state);
1693 struct pci_saved_state {
1694 u32 config_space[16];
1695 struct pci_cap_saved_data cap[];
1699 * pci_store_saved_state - Allocate and return an opaque struct containing
1700 * the device saved state.
1701 * @dev: PCI device that we're dealing with
1703 * Return NULL if no state or error.
1705 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1707 struct pci_saved_state *state;
1708 struct pci_cap_saved_state *tmp;
1709 struct pci_cap_saved_data *cap;
1712 if (!dev->state_saved)
1715 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1717 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1718 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1720 state = kzalloc(size, GFP_KERNEL);
1724 memcpy(state->config_space, dev->saved_config_space,
1725 sizeof(state->config_space));
1728 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1729 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1730 memcpy(cap, &tmp->cap, len);
1731 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1733 /* Empty cap_save terminates list */
1737 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1740 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1741 * @dev: PCI device that we're dealing with
1742 * @state: Saved state returned from pci_store_saved_state()
1744 int pci_load_saved_state(struct pci_dev *dev,
1745 struct pci_saved_state *state)
1747 struct pci_cap_saved_data *cap;
1749 dev->state_saved = false;
1754 memcpy(dev->saved_config_space, state->config_space,
1755 sizeof(state->config_space));
1759 struct pci_cap_saved_state *tmp;
1761 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1762 if (!tmp || tmp->cap.size != cap->size)
1765 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1766 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1767 sizeof(struct pci_cap_saved_data) + cap->size);
1770 dev->state_saved = true;
1773 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1776 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1777 * and free the memory allocated for it.
1778 * @dev: PCI device that we're dealing with
1779 * @state: Pointer to saved state returned from pci_store_saved_state()
1781 int pci_load_and_free_saved_state(struct pci_dev *dev,
1782 struct pci_saved_state **state)
1784 int ret = pci_load_saved_state(dev, *state);
1789 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1791 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1793 return pci_enable_resources(dev, bars);
1796 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1799 struct pci_dev *bridge;
1803 err = pci_set_power_state(dev, PCI_D0);
1804 if (err < 0 && err != -EIO)
1807 bridge = pci_upstream_bridge(dev);
1809 pcie_aspm_powersave_config_link(bridge);
1811 err = pcibios_enable_device(dev, bars);
1814 pci_fixup_device(pci_fixup_enable, dev);
1816 if (dev->msi_enabled || dev->msix_enabled)
1819 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1821 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1822 if (cmd & PCI_COMMAND_INTX_DISABLE)
1823 pci_write_config_word(dev, PCI_COMMAND,
1824 cmd & ~PCI_COMMAND_INTX_DISABLE);
1831 * pci_reenable_device - Resume abandoned device
1832 * @dev: PCI device to be resumed
1834 * NOTE: This function is a backend of pci_default_resume() and is not supposed
1835 * to be called by normal code, write proper resume handler and use it instead.
1837 int pci_reenable_device(struct pci_dev *dev)
1839 if (pci_is_enabled(dev))
1840 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1843 EXPORT_SYMBOL(pci_reenable_device);
1845 static void pci_enable_bridge(struct pci_dev *dev)
1847 struct pci_dev *bridge;
1850 bridge = pci_upstream_bridge(dev);
1852 pci_enable_bridge(bridge);
1854 if (pci_is_enabled(dev)) {
1855 if (!dev->is_busmaster)
1856 pci_set_master(dev);
1860 retval = pci_enable_device(dev);
1862 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1864 pci_set_master(dev);
1867 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1869 struct pci_dev *bridge;
1873 if (atomic_inc_return(&dev->enable_cnt) > 1) {
1874 pci_update_current_state(dev, dev->current_state);
1875 return 0; /* already enabled */
1878 bridge = pci_upstream_bridge(dev);
1880 pci_enable_bridge(bridge);
1882 /* only skip sriov related */
1883 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1884 if (dev->resource[i].flags & flags)
1886 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1887 if (dev->resource[i].flags & flags)
1890 err = do_pci_enable_device(dev, bars);
1892 atomic_dec(&dev->enable_cnt);
1897 * pci_enable_device_io - Initialize a device for use with IO space
1898 * @dev: PCI device to be initialized
1900 * Initialize device before it's used by a driver. Ask low-level code
1901 * to enable I/O resources. Wake up the device if it was suspended.
1902 * Beware, this function can fail.
1904 int pci_enable_device_io(struct pci_dev *dev)
1906 return pci_enable_device_flags(dev, IORESOURCE_IO);
1908 EXPORT_SYMBOL(pci_enable_device_io);
1911 * pci_enable_device_mem - Initialize a device for use with Memory space
1912 * @dev: PCI device to be initialized
1914 * Initialize device before it's used by a driver. Ask low-level code
1915 * to enable Memory resources. Wake up the device if it was suspended.
1916 * Beware, this function can fail.
1918 int pci_enable_device_mem(struct pci_dev *dev)
1920 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1922 EXPORT_SYMBOL(pci_enable_device_mem);
1925 * pci_enable_device - Initialize device before it's used by a driver.
1926 * @dev: PCI device to be initialized
1928 * Initialize device before it's used by a driver. Ask low-level code
1929 * to enable I/O and memory. Wake up the device if it was suspended.
1930 * Beware, this function can fail.
1932 * Note we don't actually enable the device many times if we call
1933 * this function repeatedly (we just increment the count).
1935 int pci_enable_device(struct pci_dev *dev)
1937 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1939 EXPORT_SYMBOL(pci_enable_device);
1942 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
1943 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
1944 * there's no need to track it separately. pci_devres is initialized
1945 * when a device is enabled using managed PCI device enable interface.
1948 unsigned int enabled:1;
1949 unsigned int pinned:1;
1950 unsigned int orig_intx:1;
1951 unsigned int restore_intx:1;
1956 static void pcim_release(struct device *gendev, void *res)
1958 struct pci_dev *dev = to_pci_dev(gendev);
1959 struct pci_devres *this = res;
1962 if (dev->msi_enabled)
1963 pci_disable_msi(dev);
1964 if (dev->msix_enabled)
1965 pci_disable_msix(dev);
1967 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1968 if (this->region_mask & (1 << i))
1969 pci_release_region(dev, i);
1974 if (this->restore_intx)
1975 pci_intx(dev, this->orig_intx);
1977 if (this->enabled && !this->pinned)
1978 pci_disable_device(dev);
1981 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1983 struct pci_devres *dr, *new_dr;
1985 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1989 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1992 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1995 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1997 if (pci_is_managed(pdev))
1998 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2003 * pcim_enable_device - Managed pci_enable_device()
2004 * @pdev: PCI device to be initialized
2006 * Managed pci_enable_device().
2008 int pcim_enable_device(struct pci_dev *pdev)
2010 struct pci_devres *dr;
2013 dr = get_pci_dr(pdev);
2019 rc = pci_enable_device(pdev);
2021 pdev->is_managed = 1;
2026 EXPORT_SYMBOL(pcim_enable_device);
2029 * pcim_pin_device - Pin managed PCI device
2030 * @pdev: PCI device to pin
2032 * Pin managed PCI device @pdev. Pinned device won't be disabled on
2033 * driver detach. @pdev must have been enabled with
2034 * pcim_enable_device().
2036 void pcim_pin_device(struct pci_dev *pdev)
2038 struct pci_devres *dr;
2040 dr = find_pci_dr(pdev);
2041 WARN_ON(!dr || !dr->enabled);
2045 EXPORT_SYMBOL(pcim_pin_device);
2048 * pcibios_add_device - provide arch specific hooks when adding device dev
2049 * @dev: the PCI device being added
2051 * Permits the platform to provide architecture specific functionality when
2052 * devices are added. This is the default implementation. Architecture
2053 * implementations can override this.
2055 int __weak pcibios_add_device(struct pci_dev *dev)
2061 * pcibios_release_device - provide arch specific hooks when releasing
2063 * @dev: the PCI device being released
2065 * Permits the platform to provide architecture specific functionality when
2066 * devices are released. This is the default implementation. Architecture
2067 * implementations can override this.
2069 void __weak pcibios_release_device(struct pci_dev *dev) {}
2072 * pcibios_disable_device - disable arch specific PCI resources for device dev
2073 * @dev: the PCI device to disable
2075 * Disables architecture specific PCI resources for the device. This
2076 * is the default implementation. Architecture implementations can
2079 void __weak pcibios_disable_device(struct pci_dev *dev) {}
2082 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2083 * @irq: ISA IRQ to penalize
2084 * @active: IRQ active or not
2086 * Permits the platform to provide architecture-specific functionality when
2087 * penalizing ISA IRQs. This is the default implementation. Architecture
2088 * implementations can override this.
2090 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
2092 static void do_pci_disable_device(struct pci_dev *dev)
2096 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2097 if (pci_command & PCI_COMMAND_MASTER) {
2098 pci_command &= ~PCI_COMMAND_MASTER;
2099 pci_write_config_word(dev, PCI_COMMAND, pci_command);
2102 pcibios_disable_device(dev);
2106 * pci_disable_enabled_device - Disable device without updating enable_cnt
2107 * @dev: PCI device to disable
2109 * NOTE: This function is a backend of PCI power management routines and is
2110 * not supposed to be called drivers.
2112 void pci_disable_enabled_device(struct pci_dev *dev)
2114 if (pci_is_enabled(dev))
2115 do_pci_disable_device(dev);
2119 * pci_disable_device - Disable PCI device after use
2120 * @dev: PCI device to be disabled
2122 * Signal to the system that the PCI device is not in use by the system
2123 * anymore. This only involves disabling PCI bus-mastering, if active.
2125 * Note we don't actually disable the device until all callers of
2126 * pci_enable_device() have called pci_disable_device().
2128 void pci_disable_device(struct pci_dev *dev)
2130 struct pci_devres *dr;
2132 dr = find_pci_dr(dev);
2136 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2137 "disabling already-disabled device");
2139 if (atomic_dec_return(&dev->enable_cnt) != 0)
2142 do_pci_disable_device(dev);
2144 dev->is_busmaster = 0;
2146 EXPORT_SYMBOL(pci_disable_device);
2149 * pcibios_set_pcie_reset_state - set reset state for device dev
2150 * @dev: the PCIe device reset
2151 * @state: Reset state to enter into
2153 * Set the PCIe reset state for the device. This is the default
2154 * implementation. Architecture implementations can override this.
2156 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2157 enum pcie_reset_state state)
2163 * pci_set_pcie_reset_state - set reset state for device dev
2164 * @dev: the PCIe device reset
2165 * @state: Reset state to enter into
2167 * Sets the PCI reset state for the device.
2169 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2171 return pcibios_set_pcie_reset_state(dev, state);
2173 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
2175 void pcie_clear_device_status(struct pci_dev *dev)
2179 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2180 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2184 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2185 * @dev: PCIe root port or event collector.
2187 void pcie_clear_root_pme_status(struct pci_dev *dev)
2189 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2193 * pci_check_pme_status - Check if given device has generated PME.
2194 * @dev: Device to check.
2196 * Check the PME status of the device and if set, clear it and clear PME enable
2197 * (if set). Return 'true' if PME status and PME enable were both set or
2198 * 'false' otherwise.
2200 bool pci_check_pme_status(struct pci_dev *dev)
2209 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2210 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2211 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2214 /* Clear PME status. */
2215 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2216 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2217 /* Disable PME to avoid interrupt flood. */
2218 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2222 pci_write_config_word(dev, pmcsr_pos, pmcsr);
2228 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2229 * @dev: Device to handle.
2230 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2232 * Check if @dev has generated PME and queue a resume request for it in that
2235 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2237 if (pme_poll_reset && dev->pme_poll)
2238 dev->pme_poll = false;
2240 if (pci_check_pme_status(dev)) {
2241 pci_wakeup_event(dev);
2242 pm_request_resume(&dev->dev);
2248 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2249 * @bus: Top bus of the subtree to walk.
2251 void pci_pme_wakeup_bus(struct pci_bus *bus)
2254 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2259 * pci_pme_capable - check the capability of PCI device to generate PME#
2260 * @dev: PCI device to handle.
2261 * @state: PCI state from which device will issue PME#.
2263 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2268 return !!(dev->pme_support & (1 << state));
2270 EXPORT_SYMBOL(pci_pme_capable);
2272 static void pci_pme_list_scan(struct work_struct *work)
2274 struct pci_pme_device *pme_dev, *n;
2276 mutex_lock(&pci_pme_list_mutex);
2277 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
2278 if (pme_dev->dev->pme_poll) {
2279 struct pci_dev *bridge;
2281 bridge = pme_dev->dev->bus->self;
2283 * If bridge is in low power state, the
2284 * configuration space of subordinate devices
2285 * may be not accessible
2287 if (bridge && bridge->current_state != PCI_D0)
2290 * If the device is in D3cold it should not be
2293 if (pme_dev->dev->current_state == PCI_D3cold)
2296 pci_pme_wakeup(pme_dev->dev, NULL);
2298 list_del(&pme_dev->list);
2302 if (!list_empty(&pci_pme_list))
2303 queue_delayed_work(system_freezable_wq, &pci_pme_work,
2304 msecs_to_jiffies(PME_TIMEOUT));
2305 mutex_unlock(&pci_pme_list_mutex);
2308 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2312 if (!dev->pme_support)
2315 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2316 /* Clear PME_Status by writing 1 to it and enable PME# */
2317 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2319 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2321 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2325 * pci_pme_restore - Restore PME configuration after config space restore.
2326 * @dev: PCI device to update.
2328 void pci_pme_restore(struct pci_dev *dev)
2332 if (!dev->pme_support)
2335 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2336 if (dev->wakeup_prepared) {
2337 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2338 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2340 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2341 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2343 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2347 * pci_pme_active - enable or disable PCI device's PME# function
2348 * @dev: PCI device to handle.
2349 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2351 * The caller must verify that the device is capable of generating PME# before
2352 * calling this function with @enable equal to 'true'.
2354 void pci_pme_active(struct pci_dev *dev, bool enable)
2356 __pci_pme_active(dev, enable);
2359 * PCI (as opposed to PCIe) PME requires that the device have
2360 * its PME# line hooked up correctly. Not all hardware vendors
2361 * do this, so the PME never gets delivered and the device
2362 * remains asleep. The easiest way around this is to
2363 * periodically walk the list of suspended devices and check
2364 * whether any have their PME flag set. The assumption is that
2365 * we'll wake up often enough anyway that this won't be a huge
2366 * hit, and the power savings from the devices will still be a
2369 * Although PCIe uses in-band PME message instead of PME# line
2370 * to report PME, PME does not work for some PCIe devices in
2371 * reality. For example, there are devices that set their PME
2372 * status bits, but don't really bother to send a PME message;
2373 * there are PCI Express Root Ports that don't bother to
2374 * trigger interrupts when they receive PME messages from the
2375 * devices below. So PME poll is used for PCIe devices too.
2378 if (dev->pme_poll) {
2379 struct pci_pme_device *pme_dev;
2381 pme_dev = kmalloc(sizeof(struct pci_pme_device),
2384 pci_warn(dev, "can't enable PME#\n");
2388 mutex_lock(&pci_pme_list_mutex);
2389 list_add(&pme_dev->list, &pci_pme_list);
2390 if (list_is_singular(&pci_pme_list))
2391 queue_delayed_work(system_freezable_wq,
2393 msecs_to_jiffies(PME_TIMEOUT));
2394 mutex_unlock(&pci_pme_list_mutex);
2396 mutex_lock(&pci_pme_list_mutex);
2397 list_for_each_entry(pme_dev, &pci_pme_list, list) {
2398 if (pme_dev->dev == dev) {
2399 list_del(&pme_dev->list);
2404 mutex_unlock(&pci_pme_list_mutex);
2408 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2410 EXPORT_SYMBOL(pci_pme_active);
2413 * __pci_enable_wake - enable PCI device as wakeup event source
2414 * @dev: PCI device affected
2415 * @state: PCI state from which device will issue wakeup events
2416 * @enable: True to enable event generation; false to disable
2418 * This enables the device as a wakeup event source, or disables it.
2419 * When such events involves platform-specific hooks, those hooks are
2420 * called automatically by this routine.
2422 * Devices with legacy power management (no standard PCI PM capabilities)
2423 * always require such platform hooks.
2426 * 0 is returned on success
2427 * -EINVAL is returned if device is not supposed to wake up the system
2428 * Error code depending on the platform is returned if both the platform and
2429 * the native mechanism fail to enable the generation of wake-up events
2431 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2436 * Bridges that are not power-manageable directly only signal
2437 * wakeup on behalf of subordinate devices which is set up
2438 * elsewhere, so skip them. However, bridges that are
2439 * power-manageable may signal wakeup for themselves (for example,
2440 * on a hotplug event) and they need to be covered here.
2442 if (!pci_power_manageable(dev))
2445 /* Don't do the same thing twice in a row for one device. */
2446 if (!!enable == !!dev->wakeup_prepared)
2450 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2451 * Anderson we should be doing PME# wake enable followed by ACPI wake
2452 * enable. To disable wake-up we call the platform first, for symmetry.
2458 if (pci_pme_capable(dev, state))
2459 pci_pme_active(dev, true);
2462 error = platform_pci_set_wakeup(dev, true);
2466 dev->wakeup_prepared = true;
2468 platform_pci_set_wakeup(dev, false);
2469 pci_pme_active(dev, false);
2470 dev->wakeup_prepared = false;
2477 * pci_enable_wake - change wakeup settings for a PCI device
2478 * @pci_dev: Target device
2479 * @state: PCI state from which device will issue wakeup events
2480 * @enable: Whether or not to enable event generation
2482 * If @enable is set, check device_may_wakeup() for the device before calling
2483 * __pci_enable_wake() for it.
2485 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2487 if (enable && !device_may_wakeup(&pci_dev->dev))
2490 return __pci_enable_wake(pci_dev, state, enable);
2492 EXPORT_SYMBOL(pci_enable_wake);
2495 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2496 * @dev: PCI device to prepare
2497 * @enable: True to enable wake-up event generation; false to disable
2499 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2500 * and this function allows them to set that up cleanly - pci_enable_wake()
2501 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2502 * ordering constraints.
2504 * This function only returns error code if the device is not allowed to wake
2505 * up the system from sleep or it is not capable of generating PME# from both
2506 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2508 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2510 return pci_pme_capable(dev, PCI_D3cold) ?
2511 pci_enable_wake(dev, PCI_D3cold, enable) :
2512 pci_enable_wake(dev, PCI_D3hot, enable);
2514 EXPORT_SYMBOL(pci_wake_from_d3);
2517 * pci_target_state - find an appropriate low power state for a given PCI dev
2519 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2521 * Use underlying platform code to find a supported low power state for @dev.
2522 * If the platform can't manage @dev, return the deepest state from which it
2523 * can generate wake events, based on any available PME info.
2525 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2527 pci_power_t target_state = PCI_D3hot;
2529 if (platform_pci_power_manageable(dev)) {
2531 * Call the platform to find the target state for the device.
2533 pci_power_t state = platform_pci_choose_state(dev);
2536 case PCI_POWER_ERROR:
2541 if (pci_no_d1d2(dev))
2545 target_state = state;
2548 return target_state;
2552 target_state = PCI_D0;
2555 * If the device is in D3cold even though it's not power-manageable by
2556 * the platform, it may have been powered down by non-standard means.
2557 * Best to let it slumber.
2559 if (dev->current_state == PCI_D3cold)
2560 target_state = PCI_D3cold;
2564 * Find the deepest state from which the device can generate
2567 if (dev->pme_support) {
2569 && !(dev->pme_support & (1 << target_state)))
2574 return target_state;
2578 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2579 * into a sleep state
2580 * @dev: Device to handle.
2582 * Choose the power state appropriate for the device depending on whether
2583 * it can wake up the system and/or is power manageable by the platform
2584 * (PCI_D3hot is the default) and put the device into that state.
2586 int pci_prepare_to_sleep(struct pci_dev *dev)
2588 bool wakeup = device_may_wakeup(&dev->dev);
2589 pci_power_t target_state = pci_target_state(dev, wakeup);
2592 if (target_state == PCI_POWER_ERROR)
2596 * There are systems (for example, Intel mobile chips since Coffee
2597 * Lake) where the power drawn while suspended can be significantly
2598 * reduced by disabling PTM on PCIe root ports as this allows the
2599 * port to enter a lower-power PM state and the SoC to reach a
2600 * lower-power idle state as a whole.
2602 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2603 pci_disable_ptm(dev);
2605 pci_enable_wake(dev, target_state, wakeup);
2607 error = pci_set_power_state(dev, target_state);
2610 pci_enable_wake(dev, target_state, false);
2611 pci_restore_ptm_state(dev);
2616 EXPORT_SYMBOL(pci_prepare_to_sleep);
2619 * pci_back_from_sleep - turn PCI device on during system-wide transition
2620 * into working state
2621 * @dev: Device to handle.
2623 * Disable device's system wake-up capability and put it into D0.
2625 int pci_back_from_sleep(struct pci_dev *dev)
2627 pci_enable_wake(dev, PCI_D0, false);
2628 return pci_set_power_state(dev, PCI_D0);
2630 EXPORT_SYMBOL(pci_back_from_sleep);
2633 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2634 * @dev: PCI device being suspended.
2636 * Prepare @dev to generate wake-up events at run time and put it into a low
2639 int pci_finish_runtime_suspend(struct pci_dev *dev)
2641 pci_power_t target_state;
2644 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2645 if (target_state == PCI_POWER_ERROR)
2648 dev->runtime_d3cold = target_state == PCI_D3cold;
2651 * There are systems (for example, Intel mobile chips since Coffee
2652 * Lake) where the power drawn while suspended can be significantly
2653 * reduced by disabling PTM on PCIe root ports as this allows the
2654 * port to enter a lower-power PM state and the SoC to reach a
2655 * lower-power idle state as a whole.
2657 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2658 pci_disable_ptm(dev);
2660 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2662 error = pci_set_power_state(dev, target_state);
2665 pci_enable_wake(dev, target_state, false);
2666 pci_restore_ptm_state(dev);
2667 dev->runtime_d3cold = false;
2674 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2675 * @dev: Device to check.
2677 * Return true if the device itself is capable of generating wake-up events
2678 * (through the platform or using the native PCIe PME) or if the device supports
2679 * PME and one of its upstream bridges can generate wake-up events.
2681 bool pci_dev_run_wake(struct pci_dev *dev)
2683 struct pci_bus *bus = dev->bus;
2685 if (!dev->pme_support)
2688 /* PME-capable in principle, but not from the target power state */
2689 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2692 if (device_can_wakeup(&dev->dev))
2695 while (bus->parent) {
2696 struct pci_dev *bridge = bus->self;
2698 if (device_can_wakeup(&bridge->dev))
2704 /* We have reached the root bus. */
2706 return device_can_wakeup(bus->bridge);
2710 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2713 * pci_dev_need_resume - Check if it is necessary to resume the device.
2714 * @pci_dev: Device to check.
2716 * Return 'true' if the device is not runtime-suspended or it has to be
2717 * reconfigured due to wakeup settings difference between system and runtime
2718 * suspend, or the current power state of it is not suitable for the upcoming
2719 * (system-wide) transition.
2721 bool pci_dev_need_resume(struct pci_dev *pci_dev)
2723 struct device *dev = &pci_dev->dev;
2724 pci_power_t target_state;
2726 if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2729 target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2732 * If the earlier platform check has not triggered, D3cold is just power
2733 * removal on top of D3hot, so no need to resume the device in that
2736 return target_state != pci_dev->current_state &&
2737 target_state != PCI_D3cold &&
2738 pci_dev->current_state != PCI_D3hot;
2742 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2743 * @pci_dev: Device to check.
2745 * If the device is suspended and it is not configured for system wakeup,
2746 * disable PME for it to prevent it from waking up the system unnecessarily.
2748 * Note that if the device's power state is D3cold and the platform check in
2749 * pci_dev_need_resume() has not triggered, the device's configuration need not
2752 void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2754 struct device *dev = &pci_dev->dev;
2756 spin_lock_irq(&dev->power.lock);
2758 if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2759 pci_dev->current_state < PCI_D3cold)
2760 __pci_pme_active(pci_dev, false);
2762 spin_unlock_irq(&dev->power.lock);
2766 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2767 * @pci_dev: Device to handle.
2769 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2770 * it might have been disabled during the prepare phase of system suspend if
2771 * the device was not configured for system wakeup.
2773 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2775 struct device *dev = &pci_dev->dev;
2777 if (!pci_dev_run_wake(pci_dev))
2780 spin_lock_irq(&dev->power.lock);
2782 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2783 __pci_pme_active(pci_dev, true);
2785 spin_unlock_irq(&dev->power.lock);
2788 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2790 struct device *dev = &pdev->dev;
2791 struct device *parent = dev->parent;
2794 pm_runtime_get_sync(parent);
2795 pm_runtime_get_noresume(dev);
2797 * pdev->current_state is set to PCI_D3cold during suspending,
2798 * so wait until suspending completes
2800 pm_runtime_barrier(dev);
2802 * Only need to resume devices in D3cold, because config
2803 * registers are still accessible for devices suspended but
2806 if (pdev->current_state == PCI_D3cold)
2807 pm_runtime_resume(dev);
2810 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2812 struct device *dev = &pdev->dev;
2813 struct device *parent = dev->parent;
2815 pm_runtime_put(dev);
2817 pm_runtime_put_sync(parent);
2820 static const struct dmi_system_id bridge_d3_blacklist[] = {
2824 * Gigabyte X299 root port is not marked as hotplug capable
2825 * which allows Linux to power manage it. However, this
2826 * confuses the BIOS SMI handler so don't power manage root
2827 * ports on that system.
2829 .ident = "X299 DESIGNARE EX-CF",
2831 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
2832 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2840 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2841 * @bridge: Bridge to check
2843 * This function checks if it is possible to move the bridge to D3.
2844 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2846 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2848 if (!pci_is_pcie(bridge))
2851 switch (pci_pcie_type(bridge)) {
2852 case PCI_EXP_TYPE_ROOT_PORT:
2853 case PCI_EXP_TYPE_UPSTREAM:
2854 case PCI_EXP_TYPE_DOWNSTREAM:
2855 if (pci_bridge_d3_disable)
2859 * Hotplug ports handled by firmware in System Management Mode
2860 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2862 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
2865 if (pci_bridge_d3_force)
2868 /* Even the oldest 2010 Thunderbolt controller supports D3. */
2869 if (bridge->is_thunderbolt)
2872 /* Platform might know better if the bridge supports D3 */
2873 if (platform_pci_bridge_d3(bridge))
2877 * Hotplug ports handled natively by the OS were not validated
2878 * by vendors for runtime D3 at least until 2018 because there
2879 * was no OS support.
2881 if (bridge->is_hotplug_bridge)
2884 if (dmi_check_system(bridge_d3_blacklist))
2888 * It should be safe to put PCIe ports from 2015 or newer
2891 if (dmi_get_bios_year() >= 2015)
2899 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2901 bool *d3cold_ok = data;
2903 if (/* The device needs to be allowed to go D3cold ... */
2904 dev->no_d3cold || !dev->d3cold_allowed ||
2906 /* ... and if it is wakeup capable to do so from D3cold. */
2907 (device_may_wakeup(&dev->dev) &&
2908 !pci_pme_capable(dev, PCI_D3cold)) ||
2910 /* If it is a bridge it must be allowed to go to D3. */
2911 !pci_power_manageable(dev))
2919 * pci_bridge_d3_update - Update bridge D3 capabilities
2920 * @dev: PCI device which is changed
2922 * Update upstream bridge PM capabilities accordingly depending on if the
2923 * device PM configuration was changed or the device is being removed. The
2924 * change is also propagated upstream.
2926 void pci_bridge_d3_update(struct pci_dev *dev)
2928 bool remove = !device_is_registered(&dev->dev);
2929 struct pci_dev *bridge;
2930 bool d3cold_ok = true;
2932 bridge = pci_upstream_bridge(dev);
2933 if (!bridge || !pci_bridge_d3_possible(bridge))
2937 * If D3 is currently allowed for the bridge, removing one of its
2938 * children won't change that.
2940 if (remove && bridge->bridge_d3)
2944 * If D3 is currently allowed for the bridge and a child is added or
2945 * changed, disallowance of D3 can only be caused by that child, so
2946 * we only need to check that single device, not any of its siblings.
2948 * If D3 is currently not allowed for the bridge, checking the device
2949 * first may allow us to skip checking its siblings.
2952 pci_dev_check_d3cold(dev, &d3cold_ok);
2955 * If D3 is currently not allowed for the bridge, this may be caused
2956 * either by the device being changed/removed or any of its siblings,
2957 * so we need to go through all children to find out if one of them
2958 * continues to block D3.
2960 if (d3cold_ok && !bridge->bridge_d3)
2961 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2964 if (bridge->bridge_d3 != d3cold_ok) {
2965 bridge->bridge_d3 = d3cold_ok;
2966 /* Propagate change to upstream bridges */
2967 pci_bridge_d3_update(bridge);
2972 * pci_d3cold_enable - Enable D3cold for device
2973 * @dev: PCI device to handle
2975 * This function can be used in drivers to enable D3cold from the device
2976 * they handle. It also updates upstream PCI bridge PM capabilities
2979 void pci_d3cold_enable(struct pci_dev *dev)
2981 if (dev->no_d3cold) {
2982 dev->no_d3cold = false;
2983 pci_bridge_d3_update(dev);
2986 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2989 * pci_d3cold_disable - Disable D3cold for device
2990 * @dev: PCI device to handle
2992 * This function can be used in drivers to disable D3cold from the device
2993 * they handle. It also updates upstream PCI bridge PM capabilities
2996 void pci_d3cold_disable(struct pci_dev *dev)
2998 if (!dev->no_d3cold) {
2999 dev->no_d3cold = true;
3000 pci_bridge_d3_update(dev);
3003 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
3006 * pci_pm_init - Initialize PM functions of given PCI device
3007 * @dev: PCI device to handle.
3009 void pci_pm_init(struct pci_dev *dev)
3015 pm_runtime_forbid(&dev->dev);
3016 pm_runtime_set_active(&dev->dev);
3017 pm_runtime_enable(&dev->dev);
3018 device_enable_async_suspend(&dev->dev);
3019 dev->wakeup_prepared = false;
3022 dev->pme_support = 0;
3024 /* find PCI PM capability in list */
3025 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3028 /* Check device's ability to generate PME# */
3029 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3031 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
3032 pci_err(dev, "unsupported PM cap regs version (%u)\n",
3033 pmc & PCI_PM_CAP_VER_MASK);
3038 dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
3039 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3040 dev->bridge_d3 = pci_bridge_d3_possible(dev);
3041 dev->d3cold_allowed = true;
3043 dev->d1_support = false;
3044 dev->d2_support = false;
3045 if (!pci_no_d1d2(dev)) {
3046 if (pmc & PCI_PM_CAP_D1)
3047 dev->d1_support = true;
3048 if (pmc & PCI_PM_CAP_D2)
3049 dev->d2_support = true;
3051 if (dev->d1_support || dev->d2_support)
3052 pci_info(dev, "supports%s%s\n",
3053 dev->d1_support ? " D1" : "",
3054 dev->d2_support ? " D2" : "");
3057 pmc &= PCI_PM_CAP_PME_MASK;
3059 pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3060 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
3061 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
3062 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
3063 (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
3064 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
3065 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
3066 dev->pme_poll = true;
3068 * Make device's PM flags reflect the wake-up capability, but
3069 * let the user space enable it to wake up the system as needed.
3071 device_set_wakeup_capable(&dev->dev, true);
3072 /* Disable the PME# generation functionality */
3073 pci_pme_active(dev, false);
3076 pci_read_config_word(dev, PCI_STATUS, &status);
3077 if (status & PCI_STATUS_IMM_READY)
3081 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3083 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
3087 case PCI_EA_P_VF_MEM:
3088 flags |= IORESOURCE_MEM;
3090 case PCI_EA_P_MEM_PREFETCH:
3091 case PCI_EA_P_VF_MEM_PREFETCH:
3092 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
3095 flags |= IORESOURCE_IO;
3104 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3107 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
3108 return &dev->resource[bei];
3109 #ifdef CONFIG_PCI_IOV
3110 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
3111 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
3112 return &dev->resource[PCI_IOV_RESOURCES +
3113 bei - PCI_EA_BEI_VF_BAR0];
3115 else if (bei == PCI_EA_BEI_ROM)
3116 return &dev->resource[PCI_ROM_RESOURCE];
3121 /* Read an Enhanced Allocation (EA) entry */
3122 static int pci_ea_read(struct pci_dev *dev, int offset)
3124 struct resource *res;
3125 int ent_size, ent_offset = offset;
3126 resource_size_t start, end;
3127 unsigned long flags;
3128 u32 dw0, bei, base, max_offset;
3130 bool support_64 = (sizeof(resource_size_t) >= 8);
3132 pci_read_config_dword(dev, ent_offset, &dw0);
3135 /* Entry size field indicates DWORDs after 1st */
3136 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
3138 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
3141 bei = (dw0 & PCI_EA_BEI) >> 4;
3142 prop = (dw0 & PCI_EA_PP) >> 8;
3145 * If the Property is in the reserved range, try the Secondary
3148 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
3149 prop = (dw0 & PCI_EA_SP) >> 16;
3150 if (prop > PCI_EA_P_BRIDGE_IO)
3153 res = pci_ea_get_resource(dev, bei, prop);
3155 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3159 flags = pci_ea_flags(dev, prop);
3161 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3166 pci_read_config_dword(dev, ent_offset, &base);
3167 start = (base & PCI_EA_FIELD_MASK);
3170 /* Read MaxOffset */
3171 pci_read_config_dword(dev, ent_offset, &max_offset);
3174 /* Read Base MSBs (if 64-bit entry) */
3175 if (base & PCI_EA_IS_64) {
3178 pci_read_config_dword(dev, ent_offset, &base_upper);
3181 flags |= IORESOURCE_MEM_64;
3183 /* entry starts above 32-bit boundary, can't use */
3184 if (!support_64 && base_upper)
3188 start |= ((u64)base_upper << 32);
3191 end = start + (max_offset | 0x03);
3193 /* Read MaxOffset MSBs (if 64-bit entry) */
3194 if (max_offset & PCI_EA_IS_64) {
3195 u32 max_offset_upper;
3197 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3200 flags |= IORESOURCE_MEM_64;
3202 /* entry too big, can't use */
3203 if (!support_64 && max_offset_upper)
3207 end += ((u64)max_offset_upper << 32);
3211 pci_err(dev, "EA Entry crosses address boundary\n");
3215 if (ent_size != ent_offset - offset) {
3216 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3217 ent_size, ent_offset - offset);
3221 res->name = pci_name(dev);
3226 if (bei <= PCI_EA_BEI_BAR5)
3227 pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3229 else if (bei == PCI_EA_BEI_ROM)
3230 pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3232 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3233 pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3234 bei - PCI_EA_BEI_VF_BAR0, res, prop);
3236 pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3240 return offset + ent_size;
3243 /* Enhanced Allocation Initialization */
3244 void pci_ea_init(struct pci_dev *dev)
3251 /* find PCI EA capability in list */
3252 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3256 /* determine the number of entries */
3257 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3259 num_ent &= PCI_EA_NUM_ENT_MASK;
3261 offset = ea + PCI_EA_FIRST_ENT;
3263 /* Skip DWORD 2 for type 1 functions */
3264 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3267 /* parse each EA entry */
3268 for (i = 0; i < num_ent; ++i)
3269 offset = pci_ea_read(dev, offset);
3272 static void pci_add_saved_cap(struct pci_dev *pci_dev,
3273 struct pci_cap_saved_state *new_cap)
3275 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
3279 * _pci_add_cap_save_buffer - allocate buffer for saving given
3280 * capability registers
3281 * @dev: the PCI device
3282 * @cap: the capability to allocate the buffer for
3283 * @extended: Standard or Extended capability ID
3284 * @size: requested size of the buffer
3286 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3287 bool extended, unsigned int size)
3290 struct pci_cap_saved_state *save_state;
3293 pos = pci_find_ext_capability(dev, cap);
3295 pos = pci_find_capability(dev, cap);
3300 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
3304 save_state->cap.cap_nr = cap;
3305 save_state->cap.cap_extended = extended;
3306 save_state->cap.size = size;
3307 pci_add_saved_cap(dev, save_state);
3312 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3314 return _pci_add_cap_save_buffer(dev, cap, false, size);
3317 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3319 return _pci_add_cap_save_buffer(dev, cap, true, size);
3323 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3324 * @dev: the PCI device
3326 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3330 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3331 PCI_EXP_SAVE_REGS * sizeof(u16));
3333 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3335 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3337 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3339 error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3342 pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3344 pci_allocate_vc_save_buffers(dev);
3347 void pci_free_cap_save_buffers(struct pci_dev *dev)
3349 struct pci_cap_saved_state *tmp;
3350 struct hlist_node *n;
3352 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3357 * pci_configure_ari - enable or disable ARI forwarding
3358 * @dev: the PCI device
3360 * If @dev and its upstream bridge both support ARI, enable ARI in the
3361 * bridge. Otherwise, disable ARI in the bridge.
3363 void pci_configure_ari(struct pci_dev *dev)
3366 struct pci_dev *bridge;
3368 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3371 bridge = dev->bus->self;
3375 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3376 if (!(cap & PCI_EXP_DEVCAP2_ARI))
3379 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3380 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3381 PCI_EXP_DEVCTL2_ARI);
3382 bridge->ari_enabled = 1;
3384 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3385 PCI_EXP_DEVCTL2_ARI);
3386 bridge->ari_enabled = 0;
3390 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3395 pos = pdev->acs_cap;
3400 * Except for egress control, capabilities are either required
3401 * or only required if controllable. Features missing from the
3402 * capability field can therefore be assumed as hard-wired enabled.
3404 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3405 acs_flags &= (cap | PCI_ACS_EC);
3407 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3408 return (ctrl & acs_flags) == acs_flags;
3412 * pci_acs_enabled - test ACS against required flags for a given device
3413 * @pdev: device to test
3414 * @acs_flags: required PCI ACS flags
3416 * Return true if the device supports the provided flags. Automatically
3417 * filters out flags that are not implemented on multifunction devices.
3419 * Note that this interface checks the effective ACS capabilities of the
3420 * device rather than the actual capabilities. For instance, most single
3421 * function endpoints are not required to support ACS because they have no
3422 * opportunity for peer-to-peer access. We therefore return 'true'
3423 * regardless of whether the device exposes an ACS capability. This makes
3424 * it much easier for callers of this function to ignore the actual type
3425 * or topology of the device when testing ACS support.
3427 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3431 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3436 * Conventional PCI and PCI-X devices never support ACS, either
3437 * effectively or actually. The shared bus topology implies that
3438 * any device on the bus can receive or snoop DMA.
3440 if (!pci_is_pcie(pdev))
3443 switch (pci_pcie_type(pdev)) {
3445 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3446 * but since their primary interface is PCI/X, we conservatively
3447 * handle them as we would a non-PCIe device.
3449 case PCI_EXP_TYPE_PCIE_BRIDGE:
3451 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3452 * applicable... must never implement an ACS Extended Capability...".
3453 * This seems arbitrary, but we take a conservative interpretation
3454 * of this statement.
3456 case PCI_EXP_TYPE_PCI_BRIDGE:
3457 case PCI_EXP_TYPE_RC_EC:
3460 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3461 * implement ACS in order to indicate their peer-to-peer capabilities,
3462 * regardless of whether they are single- or multi-function devices.
3464 case PCI_EXP_TYPE_DOWNSTREAM:
3465 case PCI_EXP_TYPE_ROOT_PORT:
3466 return pci_acs_flags_enabled(pdev, acs_flags);
3468 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3469 * implemented by the remaining PCIe types to indicate peer-to-peer
3470 * capabilities, but only when they are part of a multifunction
3471 * device. The footnote for section 6.12 indicates the specific
3472 * PCIe types included here.
3474 case PCI_EXP_TYPE_ENDPOINT:
3475 case PCI_EXP_TYPE_UPSTREAM:
3476 case PCI_EXP_TYPE_LEG_END:
3477 case PCI_EXP_TYPE_RC_END:
3478 if (!pdev->multifunction)
3481 return pci_acs_flags_enabled(pdev, acs_flags);
3485 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3486 * to single function devices with the exception of downstream ports.
3492 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3493 * @start: starting downstream device
3494 * @end: ending upstream device or NULL to search to the root bus
3495 * @acs_flags: required flags
3497 * Walk up a device tree from start to end testing PCI ACS support. If
3498 * any step along the way does not support the required flags, return false.
3500 bool pci_acs_path_enabled(struct pci_dev *start,
3501 struct pci_dev *end, u16 acs_flags)
3503 struct pci_dev *pdev, *parent = start;
3508 if (!pci_acs_enabled(pdev, acs_flags))
3511 if (pci_is_root_bus(pdev->bus))
3512 return (end == NULL);
3514 parent = pdev->bus->self;
3515 } while (pdev != end);
3521 * pci_acs_init - Initialize ACS if hardware supports it
3522 * @dev: the PCI device
3524 void pci_acs_init(struct pci_dev *dev)
3526 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3529 * Attempt to enable ACS regardless of capability because some Root
3530 * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3531 * the standard ACS capability but still support ACS via those
3534 pci_enable_acs(dev);
3538 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3542 * Helper to find the position of the ctrl register for a BAR.
3543 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3544 * Returns -ENOENT if no ctrl register for the BAR could be found.
3546 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3548 unsigned int pos, nbars, i;
3551 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3555 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3556 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3557 PCI_REBAR_CTRL_NBAR_SHIFT;
3559 for (i = 0; i < nbars; i++, pos += 8) {
3562 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3563 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3572 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3574 * @bar: BAR to query
3576 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3577 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3579 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3584 pos = pci_rebar_find_pos(pdev, bar);
3588 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3589 cap &= PCI_REBAR_CAP_SIZES;
3591 /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3592 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
3593 bar == 0 && cap == 0x7000)
3598 EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
3601 * pci_rebar_get_current_size - get the current size of a BAR
3603 * @bar: BAR to set size to
3605 * Read the size of a BAR from the resizable BAR config.
3606 * Returns size if found or negative error code.
3608 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3613 pos = pci_rebar_find_pos(pdev, bar);
3617 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3618 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
3622 * pci_rebar_set_size - set a new size for a BAR
3624 * @bar: BAR to set size to
3625 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3627 * Set the new size of a BAR as defined in the spec.
3628 * Returns zero if resizing was successful, error code otherwise.
3630 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3635 pos = pci_rebar_find_pos(pdev, bar);
3639 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3640 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3641 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
3642 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3647 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3648 * @dev: the PCI device
3649 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3650 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3651 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3652 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3654 * Return 0 if all upstream bridges support AtomicOp routing, egress
3655 * blocking is disabled on all upstream ports, and the root port supports
3656 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3657 * AtomicOp completion), or negative otherwise.
3659 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3661 struct pci_bus *bus = dev->bus;
3662 struct pci_dev *bridge;
3665 if (!pci_is_pcie(dev))
3669 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3670 * AtomicOp requesters. For now, we only support endpoints as
3671 * requesters and root ports as completers. No endpoints as
3672 * completers, and no peer-to-peer.
3675 switch (pci_pcie_type(dev)) {
3676 case PCI_EXP_TYPE_ENDPOINT:
3677 case PCI_EXP_TYPE_LEG_END:
3678 case PCI_EXP_TYPE_RC_END:
3684 while (bus->parent) {
3687 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3689 switch (pci_pcie_type(bridge)) {
3690 /* Ensure switch ports support AtomicOp routing */
3691 case PCI_EXP_TYPE_UPSTREAM:
3692 case PCI_EXP_TYPE_DOWNSTREAM:
3693 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3697 /* Ensure root port supports all the sizes we care about */
3698 case PCI_EXP_TYPE_ROOT_PORT:
3699 if ((cap & cap_mask) != cap_mask)
3704 /* Ensure upstream ports don't block AtomicOps on egress */
3705 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3706 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3708 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3715 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3716 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3719 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3722 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3723 * @dev: the PCI device
3724 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3726 * Perform INTx swizzling for a device behind one level of bridge. This is
3727 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3728 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3729 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3730 * the PCI Express Base Specification, Revision 2.1)
3732 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3736 if (pci_ari_enabled(dev->bus))
3739 slot = PCI_SLOT(dev->devfn);
3741 return (((pin - 1) + slot) % 4) + 1;
3744 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3752 while (!pci_is_root_bus(dev->bus)) {
3753 pin = pci_swizzle_interrupt_pin(dev, pin);
3754 dev = dev->bus->self;
3761 * pci_common_swizzle - swizzle INTx all the way to root bridge
3762 * @dev: the PCI device
3763 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3765 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3766 * bridges all the way up to a PCI root bus.
3768 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3772 while (!pci_is_root_bus(dev->bus)) {
3773 pin = pci_swizzle_interrupt_pin(dev, pin);
3774 dev = dev->bus->self;
3777 return PCI_SLOT(dev->devfn);
3779 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3782 * pci_release_region - Release a PCI bar
3783 * @pdev: PCI device whose resources were previously reserved by
3784 * pci_request_region()
3785 * @bar: BAR to release
3787 * Releases the PCI I/O and memory resources previously reserved by a
3788 * successful call to pci_request_region(). Call this function only
3789 * after all use of the PCI regions has ceased.
3791 void pci_release_region(struct pci_dev *pdev, int bar)
3793 struct pci_devres *dr;
3795 if (pci_resource_len(pdev, bar) == 0)
3797 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3798 release_region(pci_resource_start(pdev, bar),
3799 pci_resource_len(pdev, bar));
3800 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3801 release_mem_region(pci_resource_start(pdev, bar),
3802 pci_resource_len(pdev, bar));
3804 dr = find_pci_dr(pdev);
3806 dr->region_mask &= ~(1 << bar);
3808 EXPORT_SYMBOL(pci_release_region);
3811 * __pci_request_region - Reserved PCI I/O and memory resource
3812 * @pdev: PCI device whose resources are to be reserved
3813 * @bar: BAR to be reserved
3814 * @res_name: Name to be associated with resource.
3815 * @exclusive: whether the region access is exclusive or not
3817 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3818 * being reserved by owner @res_name. Do not access any
3819 * address inside the PCI regions unless this call returns
3822 * If @exclusive is set, then the region is marked so that userspace
3823 * is explicitly not allowed to map the resource via /dev/mem or
3824 * sysfs MMIO access.
3826 * Returns 0 on success, or %EBUSY on error. A warning
3827 * message is also printed on failure.
3829 static int __pci_request_region(struct pci_dev *pdev, int bar,
3830 const char *res_name, int exclusive)
3832 struct pci_devres *dr;
3834 if (pci_resource_len(pdev, bar) == 0)
3837 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3838 if (!request_region(pci_resource_start(pdev, bar),
3839 pci_resource_len(pdev, bar), res_name))
3841 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3842 if (!__request_mem_region(pci_resource_start(pdev, bar),
3843 pci_resource_len(pdev, bar), res_name,
3848 dr = find_pci_dr(pdev);
3850 dr->region_mask |= 1 << bar;
3855 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3856 &pdev->resource[bar]);
3861 * pci_request_region - Reserve PCI I/O and memory resource
3862 * @pdev: PCI device whose resources are to be reserved
3863 * @bar: BAR to be reserved
3864 * @res_name: Name to be associated with resource
3866 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3867 * being reserved by owner @res_name. Do not access any
3868 * address inside the PCI regions unless this call returns
3871 * Returns 0 on success, or %EBUSY on error. A warning
3872 * message is also printed on failure.
3874 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3876 return __pci_request_region(pdev, bar, res_name, 0);
3878 EXPORT_SYMBOL(pci_request_region);
3881 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3882 * @pdev: PCI device whose resources were previously reserved
3883 * @bars: Bitmask of BARs to be released
3885 * Release selected PCI I/O and memory resources previously reserved.
3886 * Call this function only after all use of the PCI regions has ceased.
3888 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3892 for (i = 0; i < PCI_STD_NUM_BARS; i++)
3893 if (bars & (1 << i))
3894 pci_release_region(pdev, i);
3896 EXPORT_SYMBOL(pci_release_selected_regions);
3898 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3899 const char *res_name, int excl)
3903 for (i = 0; i < PCI_STD_NUM_BARS; i++)
3904 if (bars & (1 << i))
3905 if (__pci_request_region(pdev, i, res_name, excl))
3911 if (bars & (1 << i))
3912 pci_release_region(pdev, i);
3919 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3920 * @pdev: PCI device whose resources are to be reserved
3921 * @bars: Bitmask of BARs to be requested
3922 * @res_name: Name to be associated with resource
3924 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3925 const char *res_name)
3927 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3929 EXPORT_SYMBOL(pci_request_selected_regions);
3931 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3932 const char *res_name)
3934 return __pci_request_selected_regions(pdev, bars, res_name,
3935 IORESOURCE_EXCLUSIVE);
3937 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3940 * pci_release_regions - Release reserved PCI I/O and memory resources
3941 * @pdev: PCI device whose resources were previously reserved by
3942 * pci_request_regions()
3944 * Releases all PCI I/O and memory resources previously reserved by a
3945 * successful call to pci_request_regions(). Call this function only
3946 * after all use of the PCI regions has ceased.
3949 void pci_release_regions(struct pci_dev *pdev)
3951 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
3953 EXPORT_SYMBOL(pci_release_regions);
3956 * pci_request_regions - Reserve PCI I/O and memory resources
3957 * @pdev: PCI device whose resources are to be reserved
3958 * @res_name: Name to be associated with resource.
3960 * Mark all PCI regions associated with PCI device @pdev as
3961 * being reserved by owner @res_name. Do not access any
3962 * address inside the PCI regions unless this call returns
3965 * Returns 0 on success, or %EBUSY on error. A warning
3966 * message is also printed on failure.
3968 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3970 return pci_request_selected_regions(pdev,
3971 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
3973 EXPORT_SYMBOL(pci_request_regions);
3976 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
3977 * @pdev: PCI device whose resources are to be reserved
3978 * @res_name: Name to be associated with resource.
3980 * Mark all PCI regions associated with PCI device @pdev as being reserved
3981 * by owner @res_name. Do not access any address inside the PCI regions
3982 * unless this call returns successfully.
3984 * pci_request_regions_exclusive() will mark the region so that /dev/mem
3985 * and the sysfs MMIO access will not be allowed.
3987 * Returns 0 on success, or %EBUSY on error. A warning message is also
3988 * printed on failure.
3990 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3992 return pci_request_selected_regions_exclusive(pdev,
3993 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
3995 EXPORT_SYMBOL(pci_request_regions_exclusive);
3998 * Record the PCI IO range (expressed as CPU physical address + size).
3999 * Return a negative value if an error has occurred, zero otherwise
4001 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
4002 resource_size_t size)
4006 struct logic_pio_hwaddr *range;
4008 if (!size || addr + size < addr)
4011 range = kzalloc(sizeof(*range), GFP_ATOMIC);
4015 range->fwnode = fwnode;
4017 range->hw_start = addr;
4018 range->flags = LOGIC_PIO_CPU_MMIO;
4020 ret = logic_pio_register_range(range);
4024 /* Ignore duplicates due to deferred probing */
4032 phys_addr_t pci_pio_to_address(unsigned long pio)
4034 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
4037 if (pio >= MMIO_UPPER_LIMIT)
4040 address = logic_pio_to_hwaddr(pio);
4046 unsigned long __weak pci_address_to_pio(phys_addr_t address)
4049 return logic_pio_trans_cpuaddr(address);
4051 if (address > IO_SPACE_LIMIT)
4052 return (unsigned long)-1;
4054 return (unsigned long) address;
4059 * pci_remap_iospace - Remap the memory mapped I/O space
4060 * @res: Resource describing the I/O space
4061 * @phys_addr: physical address of range to be mapped
4063 * Remap the memory mapped I/O space described by the @res and the CPU
4064 * physical address @phys_addr into virtual address space. Only
4065 * architectures that have memory mapped IO functions defined (and the
4066 * PCI_IOBASE value defined) should call this function.
4068 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
4070 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4071 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4073 if (!(res->flags & IORESOURCE_IO))
4076 if (res->end > IO_SPACE_LIMIT)
4079 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
4080 pgprot_device(PAGE_KERNEL));
4083 * This architecture does not have memory mapped I/O space,
4084 * so this function should never be called
4086 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4090 EXPORT_SYMBOL(pci_remap_iospace);
4093 * pci_unmap_iospace - Unmap the memory mapped I/O space
4094 * @res: resource to be unmapped
4096 * Unmap the CPU virtual address @res from virtual address space. Only
4097 * architectures that have memory mapped IO functions defined (and the
4098 * PCI_IOBASE value defined) should call this function.
4100 void pci_unmap_iospace(struct resource *res)
4102 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4103 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4105 unmap_kernel_range(vaddr, resource_size(res));
4108 EXPORT_SYMBOL(pci_unmap_iospace);
4110 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4112 struct resource **res = ptr;
4114 pci_unmap_iospace(*res);
4118 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4119 * @dev: Generic device to remap IO address for
4120 * @res: Resource describing the I/O space
4121 * @phys_addr: physical address of range to be mapped
4123 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4126 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4127 phys_addr_t phys_addr)
4129 const struct resource **ptr;
4132 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4136 error = pci_remap_iospace(res, phys_addr);
4141 devres_add(dev, ptr);
4146 EXPORT_SYMBOL(devm_pci_remap_iospace);
4149 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4150 * @dev: Generic device to remap IO address for
4151 * @offset: Resource address to map
4152 * @size: Size of map
4154 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4157 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4158 resource_size_t offset,
4159 resource_size_t size)
4161 void __iomem **ptr, *addr;
4163 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4167 addr = pci_remap_cfgspace(offset, size);
4170 devres_add(dev, ptr);
4176 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4179 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4180 * @dev: generic device to handle the resource for
4181 * @res: configuration space resource to be handled
4183 * Checks that a resource is a valid memory region, requests the memory
4184 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4185 * proper PCI configuration space memory attributes are guaranteed.
4187 * All operations are managed and will be undone on driver detach.
4189 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4190 * on failure. Usage example::
4192 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4193 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4195 * return PTR_ERR(base);
4197 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4198 struct resource *res)
4200 resource_size_t size;
4202 void __iomem *dest_ptr;
4206 if (!res || resource_type(res) != IORESOURCE_MEM) {
4207 dev_err(dev, "invalid resource\n");
4208 return IOMEM_ERR_PTR(-EINVAL);
4211 size = resource_size(res);
4214 name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),
4217 name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
4219 return IOMEM_ERR_PTR(-ENOMEM);
4221 if (!devm_request_mem_region(dev, res->start, size, name)) {
4222 dev_err(dev, "can't request region for resource %pR\n", res);
4223 return IOMEM_ERR_PTR(-EBUSY);
4226 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4228 dev_err(dev, "ioremap failed for resource %pR\n", res);
4229 devm_release_mem_region(dev, res->start, size);
4230 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4235 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4237 static void __pci_set_master(struct pci_dev *dev, bool enable)
4241 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4243 cmd = old_cmd | PCI_COMMAND_MASTER;
4245 cmd = old_cmd & ~PCI_COMMAND_MASTER;
4246 if (cmd != old_cmd) {
4247 pci_dbg(dev, "%s bus mastering\n",
4248 enable ? "enabling" : "disabling");
4249 pci_write_config_word(dev, PCI_COMMAND, cmd);
4251 dev->is_busmaster = enable;
4255 * pcibios_setup - process "pci=" kernel boot arguments
4256 * @str: string used to pass in "pci=" kernel boot arguments
4258 * Process kernel boot arguments. This is the default implementation.
4259 * Architecture specific implementations can override this as necessary.
4261 char * __weak __init pcibios_setup(char *str)
4267 * pcibios_set_master - enable PCI bus-mastering for device dev
4268 * @dev: the PCI device to enable
4270 * Enables PCI bus-mastering for the device. This is the default
4271 * implementation. Architecture specific implementations can override
4272 * this if necessary.
4274 void __weak pcibios_set_master(struct pci_dev *dev)
4278 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4279 if (pci_is_pcie(dev))
4282 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4284 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4285 else if (lat > pcibios_max_latency)
4286 lat = pcibios_max_latency;
4290 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4294 * pci_set_master - enables bus-mastering for device dev
4295 * @dev: the PCI device to enable
4297 * Enables bus-mastering on the device and calls pcibios_set_master()
4298 * to do the needed arch specific settings.
4300 void pci_set_master(struct pci_dev *dev)
4302 __pci_set_master(dev, true);
4303 pcibios_set_master(dev);
4305 EXPORT_SYMBOL(pci_set_master);
4308 * pci_clear_master - disables bus-mastering for device dev
4309 * @dev: the PCI device to disable
4311 void pci_clear_master(struct pci_dev *dev)
4313 __pci_set_master(dev, false);
4315 EXPORT_SYMBOL(pci_clear_master);
4318 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4319 * @dev: the PCI device for which MWI is to be enabled
4321 * Helper function for pci_set_mwi.
4322 * Originally copied from drivers/net/acenic.c.
4323 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4325 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4327 int pci_set_cacheline_size(struct pci_dev *dev)
4331 if (!pci_cache_line_size)
4334 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4335 equal to or multiple of the right value. */
4336 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4337 if (cacheline_size >= pci_cache_line_size &&
4338 (cacheline_size % pci_cache_line_size) == 0)
4341 /* Write the correct value. */
4342 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4344 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4345 if (cacheline_size == pci_cache_line_size)
4348 pci_dbg(dev, "cache line size of %d is not supported\n",
4349 pci_cache_line_size << 2);
4353 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4356 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4357 * @dev: the PCI device for which MWI is enabled
4359 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4361 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4363 int pci_set_mwi(struct pci_dev *dev)
4365 #ifdef PCI_DISABLE_MWI
4371 rc = pci_set_cacheline_size(dev);
4375 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4376 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4377 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4378 cmd |= PCI_COMMAND_INVALIDATE;
4379 pci_write_config_word(dev, PCI_COMMAND, cmd);
4384 EXPORT_SYMBOL(pci_set_mwi);
4387 * pcim_set_mwi - a device-managed pci_set_mwi()
4388 * @dev: the PCI device for which MWI is enabled
4390 * Managed pci_set_mwi().
4392 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4394 int pcim_set_mwi(struct pci_dev *dev)
4396 struct pci_devres *dr;
4398 dr = find_pci_dr(dev);
4403 return pci_set_mwi(dev);
4405 EXPORT_SYMBOL(pcim_set_mwi);
4408 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4409 * @dev: the PCI device for which MWI is enabled
4411 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4412 * Callers are not required to check the return value.
4414 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4416 int pci_try_set_mwi(struct pci_dev *dev)
4418 #ifdef PCI_DISABLE_MWI
4421 return pci_set_mwi(dev);
4424 EXPORT_SYMBOL(pci_try_set_mwi);
4427 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4428 * @dev: the PCI device to disable
4430 * Disables PCI Memory-Write-Invalidate transaction on the device
4432 void pci_clear_mwi(struct pci_dev *dev)
4434 #ifndef PCI_DISABLE_MWI
4437 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4438 if (cmd & PCI_COMMAND_INVALIDATE) {
4439 cmd &= ~PCI_COMMAND_INVALIDATE;
4440 pci_write_config_word(dev, PCI_COMMAND, cmd);
4444 EXPORT_SYMBOL(pci_clear_mwi);
4447 * pci_intx - enables/disables PCI INTx for device dev
4448 * @pdev: the PCI device to operate on
4449 * @enable: boolean: whether to enable or disable PCI INTx
4451 * Enables/disables PCI INTx for device @pdev
4453 void pci_intx(struct pci_dev *pdev, int enable)
4455 u16 pci_command, new;
4457 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4460 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4462 new = pci_command | PCI_COMMAND_INTX_DISABLE;
4464 if (new != pci_command) {
4465 struct pci_devres *dr;
4467 pci_write_config_word(pdev, PCI_COMMAND, new);
4469 dr = find_pci_dr(pdev);
4470 if (dr && !dr->restore_intx) {
4471 dr->restore_intx = 1;
4472 dr->orig_intx = !enable;
4476 EXPORT_SYMBOL_GPL(pci_intx);
4478 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4480 struct pci_bus *bus = dev->bus;
4481 bool mask_updated = true;
4482 u32 cmd_status_dword;
4483 u16 origcmd, newcmd;
4484 unsigned long flags;
4488 * We do a single dword read to retrieve both command and status.
4489 * Document assumptions that make this possible.
4491 BUILD_BUG_ON(PCI_COMMAND % 4);
4492 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4494 raw_spin_lock_irqsave(&pci_lock, flags);
4496 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4498 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4501 * Check interrupt status register to see whether our device
4502 * triggered the interrupt (when masking) or the next IRQ is
4503 * already pending (when unmasking).
4505 if (mask != irq_pending) {
4506 mask_updated = false;
4510 origcmd = cmd_status_dword;
4511 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4513 newcmd |= PCI_COMMAND_INTX_DISABLE;
4514 if (newcmd != origcmd)
4515 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4518 raw_spin_unlock_irqrestore(&pci_lock, flags);
4520 return mask_updated;
4524 * pci_check_and_mask_intx - mask INTx on pending interrupt
4525 * @dev: the PCI device to operate on
4527 * Check if the device dev has its INTx line asserted, mask it and return
4528 * true in that case. False is returned if no interrupt was pending.
4530 bool pci_check_and_mask_intx(struct pci_dev *dev)
4532 return pci_check_and_set_intx_mask(dev, true);
4534 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4537 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4538 * @dev: the PCI device to operate on
4540 * Check if the device dev has its INTx line asserted, unmask it if not and
4541 * return true. False is returned and the mask remains active if there was
4542 * still an interrupt pending.
4544 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4546 return pci_check_and_set_intx_mask(dev, false);
4548 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4551 * pci_wait_for_pending_transaction - wait for pending transaction
4552 * @dev: the PCI device to operate on
4554 * Return 0 if transaction is pending 1 otherwise.
4556 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4558 if (!pci_is_pcie(dev))
4561 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4562 PCI_EXP_DEVSTA_TRPND);
4564 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4567 * pcie_has_flr - check if a device supports function level resets
4568 * @dev: device to check
4570 * Returns true if the device advertises support for PCIe function level
4573 bool pcie_has_flr(struct pci_dev *dev)
4577 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4580 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
4581 return cap & PCI_EXP_DEVCAP_FLR;
4583 EXPORT_SYMBOL_GPL(pcie_has_flr);
4586 * pcie_flr - initiate a PCIe function level reset
4587 * @dev: device to reset
4589 * Initiate a function level reset on @dev. The caller should ensure the
4590 * device supports FLR before calling this function, e.g. by using the
4591 * pcie_has_flr() helper.
4593 int pcie_flr(struct pci_dev *dev)
4595 if (!pci_wait_for_pending_transaction(dev))
4596 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4598 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4604 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4605 * 100ms, but may silently discard requests while the FLR is in
4606 * progress. Wait 100ms before trying to access the device.
4610 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4612 EXPORT_SYMBOL_GPL(pcie_flr);
4614 static int pci_af_flr(struct pci_dev *dev, int probe)
4619 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4623 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4626 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4627 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4634 * Wait for Transaction Pending bit to clear. A word-aligned test
4635 * is used, so we use the control offset rather than status and shift
4636 * the test bit to match.
4638 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4639 PCI_AF_STATUS_TP << 8))
4640 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4642 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4648 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4649 * updated 27 July 2006; a device must complete an FLR within
4650 * 100ms, but may silently discard requests while the FLR is in
4651 * progress. Wait 100ms before trying to access the device.
4655 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4659 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4660 * @dev: Device to reset.
4661 * @probe: If set, only check if the device can be reset this way.
4663 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4664 * unset, it will be reinitialized internally when going from PCI_D3hot to
4665 * PCI_D0. If that's the case and the device is not in a low-power state
4666 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4668 * NOTE: This causes the caller to sleep for twice the device power transition
4669 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4670 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4671 * Moreover, only devices in D0 can be reset by this function.
4673 static int pci_pm_reset(struct pci_dev *dev, int probe)
4677 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4680 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4681 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4687 if (dev->current_state != PCI_D0)
4690 csr &= ~PCI_PM_CTRL_STATE_MASK;
4692 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4693 pci_dev_d3_sleep(dev);
4695 csr &= ~PCI_PM_CTRL_STATE_MASK;
4697 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4698 pci_dev_d3_sleep(dev);
4700 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
4704 * pcie_wait_for_link_delay - Wait until link is active or inactive
4705 * @pdev: Bridge device
4706 * @active: waiting for active or inactive?
4707 * @delay: Delay to wait after link has become active (in ms)
4709 * Use this to wait till link becomes active or inactive.
4711 static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
4719 * Some controllers might not implement link active reporting. In this
4720 * case, we wait for 1000 ms + any delay requested by the caller.
4722 if (!pdev->link_active_reporting) {
4723 msleep(timeout + delay);
4728 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4729 * after which we should expect an link active if the reset was
4730 * successful. If so, software must wait a minimum 100ms before sending
4731 * configuration requests to devices downstream this port.
4733 * If the link fails to activate, either the device was physically
4734 * removed or the link is permanently failed.
4739 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4740 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4751 return ret == active;
4755 * pcie_wait_for_link - Wait until link is active or inactive
4756 * @pdev: Bridge device
4757 * @active: waiting for active or inactive?
4759 * Use this to wait till link becomes active or inactive.
4761 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4763 return pcie_wait_for_link_delay(pdev, active, 100);
4767 * Find maximum D3cold delay required by all the devices on the bus. The
4768 * spec says 100 ms, but firmware can lower it and we allow drivers to
4769 * increase it as well.
4771 * Called with @pci_bus_sem locked for reading.
4773 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
4775 const struct pci_dev *pdev;
4776 int min_delay = 100;
4779 list_for_each_entry(pdev, &bus->devices, bus_list) {
4780 if (pdev->d3cold_delay < min_delay)
4781 min_delay = pdev->d3cold_delay;
4782 if (pdev->d3cold_delay > max_delay)
4783 max_delay = pdev->d3cold_delay;
4786 return max(min_delay, max_delay);
4790 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4793 * Handle necessary delays before access to the devices on the secondary
4794 * side of the bridge are permitted after D3cold to D0 transition.
4796 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
4797 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4800 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)
4802 struct pci_dev *child;
4805 if (pci_dev_is_disconnected(dev))
4808 if (!pci_is_bridge(dev) || !dev->bridge_d3)
4811 down_read(&pci_bus_sem);
4814 * We only deal with devices that are present currently on the bus.
4815 * For any hot-added devices the access delay is handled in pciehp
4816 * board_added(). In case of ACPI hotplug the firmware is expected
4817 * to configure the devices before OS is notified.
4819 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
4820 up_read(&pci_bus_sem);
4824 /* Take d3cold_delay requirements into account */
4825 delay = pci_bus_max_d3cold_delay(dev->subordinate);
4827 up_read(&pci_bus_sem);
4831 child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
4833 up_read(&pci_bus_sem);
4836 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4837 * accessing the device after reset (that is 1000 ms + 100 ms). In
4838 * practice this should not be needed because we don't do power
4839 * management for them (see pci_bridge_d3_possible()).
4841 if (!pci_is_pcie(dev)) {
4842 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
4843 msleep(1000 + delay);
4848 * For PCIe downstream and root ports that do not support speeds
4849 * greater than 5 GT/s need to wait minimum 100 ms. For higher
4850 * speeds (gen3) we need to wait first for the data link layer to
4853 * However, 100 ms is the minimum and the PCIe spec says the
4854 * software must allow at least 1s before it can determine that the
4855 * device that did not respond is a broken device. There is
4856 * evidence that 100 ms is not always enough, for example certain
4857 * Titan Ridge xHCI controller does not always respond to
4858 * configuration requests if we only wait for 100 ms (see
4859 * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
4861 * Therefore we wait for 100 ms and check for the device presence.
4862 * If it is still not present give it an additional 100 ms.
4864 if (!pcie_downstream_port(dev))
4867 if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
4868 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
4871 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
4873 if (!pcie_wait_for_link_delay(dev, true, delay)) {
4874 /* Did not train, no need to wait any further */
4875 pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
4880 if (!pci_device_is_present(child)) {
4881 pci_dbg(child, "waiting additional %d ms to become accessible\n", delay);
4886 void pci_reset_secondary_bus(struct pci_dev *dev)
4890 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4891 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4892 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4895 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4896 * this to 2ms to ensure that we meet the minimum requirement.
4900 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
4901 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4904 * Trhfa for conventional PCI is 2^25 clock cycles.
4905 * Assuming a minimum 33MHz clock this results in a 1s
4906 * delay before we can consider subordinate devices to
4907 * be re-initialized. PCIe has some ways to shorten this,
4908 * but we don't make use of them yet.
4913 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4915 pci_reset_secondary_bus(dev);
4919 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
4920 * @dev: Bridge device
4922 * Use the bridge control register to assert reset on the secondary bus.
4923 * Devices on the secondary bus are left in power-on state.
4925 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
4927 pcibios_reset_secondary_bus(dev);
4929 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
4931 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
4933 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4935 struct pci_dev *pdev;
4937 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4938 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4941 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4948 return pci_bridge_secondary_bus_reset(dev->bus->self);
4951 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
4955 if (!hotplug || !try_module_get(hotplug->owner))
4958 if (hotplug->ops->reset_slot)
4959 rc = hotplug->ops->reset_slot(hotplug, probe);
4961 module_put(hotplug->owner);
4966 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
4968 if (dev->multifunction || dev->subordinate || !dev->slot ||
4969 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4972 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
4975 static void pci_dev_lock(struct pci_dev *dev)
4977 pci_cfg_access_lock(dev);
4978 /* block PM suspend, driver probe, etc. */
4979 device_lock(&dev->dev);
4982 /* Return 1 on successful lock, 0 on contention */
4983 static int pci_dev_trylock(struct pci_dev *dev)
4985 if (pci_cfg_access_trylock(dev)) {
4986 if (device_trylock(&dev->dev))
4988 pci_cfg_access_unlock(dev);
4994 static void pci_dev_unlock(struct pci_dev *dev)
4996 device_unlock(&dev->dev);
4997 pci_cfg_access_unlock(dev);
5000 static void pci_dev_save_and_disable(struct pci_dev *dev)
5002 const struct pci_error_handlers *err_handler =
5003 dev->driver ? dev->driver->err_handler : NULL;
5006 * dev->driver->err_handler->reset_prepare() is protected against
5007 * races with ->remove() by the device lock, which must be held by
5010 if (err_handler && err_handler->reset_prepare)
5011 err_handler->reset_prepare(dev);
5014 * Wake-up device prior to save. PM registers default to D0 after
5015 * reset and a simple register restore doesn't reliably return
5016 * to a non-D0 state anyway.
5018 pci_set_power_state(dev, PCI_D0);
5020 pci_save_state(dev);
5022 * Disable the device by clearing the Command register, except for
5023 * INTx-disable which is set. This not only disables MMIO and I/O port
5024 * BARs, but also prevents the device from being Bus Master, preventing
5025 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
5026 * compliant devices, INTx-disable prevents legacy interrupts.
5028 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
5031 static void pci_dev_restore(struct pci_dev *dev)
5033 const struct pci_error_handlers *err_handler =
5034 dev->driver ? dev->driver->err_handler : NULL;
5036 pci_restore_state(dev);
5039 * dev->driver->err_handler->reset_done() is protected against
5040 * races with ->remove() by the device lock, which must be held by
5043 if (err_handler && err_handler->reset_done)
5044 err_handler->reset_done(dev);
5048 * __pci_reset_function_locked - reset a PCI device function while holding
5049 * the @dev mutex lock.
5050 * @dev: PCI device to reset
5052 * Some devices allow an individual function to be reset without affecting
5053 * other functions in the same device. The PCI device must be responsive
5054 * to PCI config space in order to use this function.
5056 * The device function is presumed to be unused and the caller is holding
5057 * the device mutex lock when this function is called.
5059 * Resetting the device will make the contents of PCI configuration space
5060 * random, so any caller of this must be prepared to reinitialise the
5061 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5064 * Returns 0 if the device function was successfully reset or negative if the
5065 * device doesn't support resetting a single function.
5067 int __pci_reset_function_locked(struct pci_dev *dev)
5074 * A reset method returns -ENOTTY if it doesn't support this device
5075 * and we should try the next method.
5077 * If it returns 0 (success), we're finished. If it returns any
5078 * other error, we're also finished: this indicates that further
5079 * reset mechanisms might be broken on the device.
5081 rc = pci_dev_specific_reset(dev, 0);
5084 if (pcie_has_flr(dev)) {
5089 rc = pci_af_flr(dev, 0);
5092 rc = pci_pm_reset(dev, 0);
5095 rc = pci_dev_reset_slot_function(dev, 0);
5098 return pci_parent_bus_reset(dev, 0);
5100 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
5103 * pci_probe_reset_function - check whether the device can be safely reset
5104 * @dev: PCI device to reset
5106 * Some devices allow an individual function to be reset without affecting
5107 * other functions in the same device. The PCI device must be responsive
5108 * to PCI config space in order to use this function.
5110 * Returns 0 if the device function can be reset or negative if the
5111 * device doesn't support resetting a single function.
5113 int pci_probe_reset_function(struct pci_dev *dev)
5119 rc = pci_dev_specific_reset(dev, 1);
5122 if (pcie_has_flr(dev))
5124 rc = pci_af_flr(dev, 1);
5127 rc = pci_pm_reset(dev, 1);
5130 rc = pci_dev_reset_slot_function(dev, 1);
5134 return pci_parent_bus_reset(dev, 1);
5138 * pci_reset_function - quiesce and reset a PCI device function
5139 * @dev: PCI device to reset
5141 * Some devices allow an individual function to be reset without affecting
5142 * other functions in the same device. The PCI device must be responsive
5143 * to PCI config space in order to use this function.
5145 * This function does not just reset the PCI portion of a device, but
5146 * clears all the state associated with the device. This function differs
5147 * from __pci_reset_function_locked() in that it saves and restores device state
5148 * over the reset and takes the PCI device lock.
5150 * Returns 0 if the device function was successfully reset or negative if the
5151 * device doesn't support resetting a single function.
5153 int pci_reset_function(struct pci_dev *dev)
5161 pci_dev_save_and_disable(dev);
5163 rc = __pci_reset_function_locked(dev);
5165 pci_dev_restore(dev);
5166 pci_dev_unlock(dev);
5170 EXPORT_SYMBOL_GPL(pci_reset_function);
5173 * pci_reset_function_locked - quiesce and reset a PCI device function
5174 * @dev: PCI device to reset
5176 * Some devices allow an individual function to be reset without affecting
5177 * other functions in the same device. The PCI device must be responsive
5178 * to PCI config space in order to use this function.
5180 * This function does not just reset the PCI portion of a device, but
5181 * clears all the state associated with the device. This function differs
5182 * from __pci_reset_function_locked() in that it saves and restores device state
5183 * over the reset. It also differs from pci_reset_function() in that it
5184 * requires the PCI device lock to be held.
5186 * Returns 0 if the device function was successfully reset or negative if the
5187 * device doesn't support resetting a single function.
5189 int pci_reset_function_locked(struct pci_dev *dev)
5196 pci_dev_save_and_disable(dev);
5198 rc = __pci_reset_function_locked(dev);
5200 pci_dev_restore(dev);
5204 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
5207 * pci_try_reset_function - quiesce and reset a PCI device function
5208 * @dev: PCI device to reset
5210 * Same as above, except return -EAGAIN if unable to lock device.
5212 int pci_try_reset_function(struct pci_dev *dev)
5219 if (!pci_dev_trylock(dev))
5222 pci_dev_save_and_disable(dev);
5223 rc = __pci_reset_function_locked(dev);
5224 pci_dev_restore(dev);
5225 pci_dev_unlock(dev);
5229 EXPORT_SYMBOL_GPL(pci_try_reset_function);
5231 /* Do any devices on or below this bus prevent a bus reset? */
5232 static bool pci_bus_resetable(struct pci_bus *bus)
5234 struct pci_dev *dev;
5237 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5240 list_for_each_entry(dev, &bus->devices, bus_list) {
5241 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5242 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5249 /* Lock devices from the top of the tree down */
5250 static void pci_bus_lock(struct pci_bus *bus)
5252 struct pci_dev *dev;
5254 list_for_each_entry(dev, &bus->devices, bus_list) {
5256 if (dev->subordinate)
5257 pci_bus_lock(dev->subordinate);
5261 /* Unlock devices from the bottom of the tree up */
5262 static void pci_bus_unlock(struct pci_bus *bus)
5264 struct pci_dev *dev;
5266 list_for_each_entry(dev, &bus->devices, bus_list) {
5267 if (dev->subordinate)
5268 pci_bus_unlock(dev->subordinate);
5269 pci_dev_unlock(dev);
5273 /* Return 1 on successful lock, 0 on contention */
5274 static int pci_bus_trylock(struct pci_bus *bus)
5276 struct pci_dev *dev;
5278 list_for_each_entry(dev, &bus->devices, bus_list) {
5279 if (!pci_dev_trylock(dev))
5281 if (dev->subordinate) {
5282 if (!pci_bus_trylock(dev->subordinate)) {
5283 pci_dev_unlock(dev);
5291 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5292 if (dev->subordinate)
5293 pci_bus_unlock(dev->subordinate);
5294 pci_dev_unlock(dev);
5299 /* Do any devices on or below this slot prevent a bus reset? */
5300 static bool pci_slot_resetable(struct pci_slot *slot)
5302 struct pci_dev *dev;
5304 if (slot->bus->self &&
5305 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5308 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5309 if (!dev->slot || dev->slot != slot)
5311 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5312 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5319 /* Lock devices from the top of the tree down */
5320 static void pci_slot_lock(struct pci_slot *slot)
5322 struct pci_dev *dev;
5324 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5325 if (!dev->slot || dev->slot != slot)
5328 if (dev->subordinate)
5329 pci_bus_lock(dev->subordinate);
5333 /* Unlock devices from the bottom of the tree up */
5334 static void pci_slot_unlock(struct pci_slot *slot)
5336 struct pci_dev *dev;
5338 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5339 if (!dev->slot || dev->slot != slot)
5341 if (dev->subordinate)
5342 pci_bus_unlock(dev->subordinate);
5343 pci_dev_unlock(dev);
5347 /* Return 1 on successful lock, 0 on contention */
5348 static int pci_slot_trylock(struct pci_slot *slot)
5350 struct pci_dev *dev;
5352 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5353 if (!dev->slot || dev->slot != slot)
5355 if (!pci_dev_trylock(dev))
5357 if (dev->subordinate) {
5358 if (!pci_bus_trylock(dev->subordinate)) {
5359 pci_dev_unlock(dev);
5367 list_for_each_entry_continue_reverse(dev,
5368 &slot->bus->devices, bus_list) {
5369 if (!dev->slot || dev->slot != slot)
5371 if (dev->subordinate)
5372 pci_bus_unlock(dev->subordinate);
5373 pci_dev_unlock(dev);
5379 * Save and disable devices from the top of the tree down while holding
5380 * the @dev mutex lock for the entire tree.
5382 static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5384 struct pci_dev *dev;
5386 list_for_each_entry(dev, &bus->devices, bus_list) {
5387 pci_dev_save_and_disable(dev);
5388 if (dev->subordinate)
5389 pci_bus_save_and_disable_locked(dev->subordinate);
5394 * Restore devices from top of the tree down while holding @dev mutex lock
5395 * for the entire tree. Parent bridges need to be restored before we can
5396 * get to subordinate devices.
5398 static void pci_bus_restore_locked(struct pci_bus *bus)
5400 struct pci_dev *dev;
5402 list_for_each_entry(dev, &bus->devices, bus_list) {
5403 pci_dev_restore(dev);
5404 if (dev->subordinate)
5405 pci_bus_restore_locked(dev->subordinate);
5410 * Save and disable devices from the top of the tree down while holding
5411 * the @dev mutex lock for the entire tree.
5413 static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
5415 struct pci_dev *dev;
5417 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5418 if (!dev->slot || dev->slot != slot)
5420 pci_dev_save_and_disable(dev);
5421 if (dev->subordinate)
5422 pci_bus_save_and_disable_locked(dev->subordinate);
5427 * Restore devices from top of the tree down while holding @dev mutex lock
5428 * for the entire tree. Parent bridges need to be restored before we can
5429 * get to subordinate devices.
5431 static void pci_slot_restore_locked(struct pci_slot *slot)
5433 struct pci_dev *dev;
5435 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5436 if (!dev->slot || dev->slot != slot)
5438 pci_dev_restore(dev);
5439 if (dev->subordinate)
5440 pci_bus_restore_locked(dev->subordinate);
5444 static int pci_slot_reset(struct pci_slot *slot, int probe)
5448 if (!slot || !pci_slot_resetable(slot))
5452 pci_slot_lock(slot);
5456 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5459 pci_slot_unlock(slot);
5465 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5466 * @slot: PCI slot to probe
5468 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5470 int pci_probe_reset_slot(struct pci_slot *slot)
5472 return pci_slot_reset(slot, 1);
5474 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5477 * __pci_reset_slot - Try to reset a PCI slot
5478 * @slot: PCI slot to reset
5480 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5481 * independent of other slots. For instance, some slots may support slot power
5482 * control. In the case of a 1:1 bus to slot architecture, this function may
5483 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5484 * Generally a slot reset should be attempted before a bus reset. All of the
5485 * function of the slot and any subordinate buses behind the slot are reset
5486 * through this function. PCI config space of all devices in the slot and
5487 * behind the slot is saved before and restored after reset.
5489 * Same as above except return -EAGAIN if the slot cannot be locked
5491 static int __pci_reset_slot(struct pci_slot *slot)
5495 rc = pci_slot_reset(slot, 1);
5499 if (pci_slot_trylock(slot)) {
5500 pci_slot_save_and_disable_locked(slot);
5502 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
5503 pci_slot_restore_locked(slot);
5504 pci_slot_unlock(slot);
5511 static int pci_bus_reset(struct pci_bus *bus, int probe)
5515 if (!bus->self || !pci_bus_resetable(bus))
5525 ret = pci_bridge_secondary_bus_reset(bus->self);
5527 pci_bus_unlock(bus);
5533 * pci_bus_error_reset - reset the bridge's subordinate bus
5534 * @bridge: The parent device that connects to the bus to reset
5536 * This function will first try to reset the slots on this bus if the method is
5537 * available. If slot reset fails or is not available, this will fall back to a
5538 * secondary bus reset.
5540 int pci_bus_error_reset(struct pci_dev *bridge)
5542 struct pci_bus *bus = bridge->subordinate;
5543 struct pci_slot *slot;
5548 mutex_lock(&pci_slot_mutex);
5549 if (list_empty(&bus->slots))
5552 list_for_each_entry(slot, &bus->slots, list)
5553 if (pci_probe_reset_slot(slot))
5556 list_for_each_entry(slot, &bus->slots, list)
5557 if (pci_slot_reset(slot, 0))
5560 mutex_unlock(&pci_slot_mutex);
5563 mutex_unlock(&pci_slot_mutex);
5564 return pci_bus_reset(bridge->subordinate, 0);
5568 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5569 * @bus: PCI bus to probe
5571 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5573 int pci_probe_reset_bus(struct pci_bus *bus)
5575 return pci_bus_reset(bus, 1);
5577 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
5580 * __pci_reset_bus - Try to reset a PCI bus
5581 * @bus: top level PCI bus to reset
5583 * Same as above except return -EAGAIN if the bus cannot be locked
5585 static int __pci_reset_bus(struct pci_bus *bus)
5589 rc = pci_bus_reset(bus, 1);
5593 if (pci_bus_trylock(bus)) {
5594 pci_bus_save_and_disable_locked(bus);
5596 rc = pci_bridge_secondary_bus_reset(bus->self);
5597 pci_bus_restore_locked(bus);
5598 pci_bus_unlock(bus);
5606 * pci_reset_bus - Try to reset a PCI bus
5607 * @pdev: top level PCI device to reset via slot/bus
5609 * Same as above except return -EAGAIN if the bus cannot be locked
5611 int pci_reset_bus(struct pci_dev *pdev)
5613 return (!pci_probe_reset_slot(pdev->slot)) ?
5614 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
5616 EXPORT_SYMBOL_GPL(pci_reset_bus);
5619 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5620 * @dev: PCI device to query
5622 * Returns mmrbc: maximum designed memory read count in bytes or
5623 * appropriate error value.
5625 int pcix_get_max_mmrbc(struct pci_dev *dev)
5630 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5634 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5637 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5639 EXPORT_SYMBOL(pcix_get_max_mmrbc);
5642 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5643 * @dev: PCI device to query
5645 * Returns mmrbc: maximum memory read count in bytes or appropriate error
5648 int pcix_get_mmrbc(struct pci_dev *dev)
5653 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5657 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5660 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5662 EXPORT_SYMBOL(pcix_get_mmrbc);
5665 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5666 * @dev: PCI device to query
5667 * @mmrbc: maximum memory read count in bytes
5668 * valid values are 512, 1024, 2048, 4096
5670 * If possible sets maximum memory read byte count, some bridges have errata
5671 * that prevent this.
5673 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5679 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5682 v = ffs(mmrbc) - 10;
5684 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5688 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5691 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5694 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5697 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5699 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5702 cmd &= ~PCI_X_CMD_MAX_READ;
5704 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5709 EXPORT_SYMBOL(pcix_set_mmrbc);
5712 * pcie_get_readrq - get PCI Express read request size
5713 * @dev: PCI device to query
5715 * Returns maximum memory read request in bytes or appropriate error value.
5717 int pcie_get_readrq(struct pci_dev *dev)
5721 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5723 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5725 EXPORT_SYMBOL(pcie_get_readrq);
5728 * pcie_set_readrq - set PCI Express maximum memory read request
5729 * @dev: PCI device to query
5730 * @rq: maximum memory read count in bytes
5731 * valid values are 128, 256, 512, 1024, 2048, 4096
5733 * If possible sets maximum memory read request in bytes
5735 int pcie_set_readrq(struct pci_dev *dev, int rq)
5740 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5744 * If using the "performance" PCIe config, we clamp the read rq
5745 * size to the max packet size to keep the host bridge from
5746 * generating requests larger than we can cope with.
5748 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5749 int mps = pcie_get_mps(dev);
5755 v = (ffs(rq) - 8) << 12;
5757 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5758 PCI_EXP_DEVCTL_READRQ, v);
5760 return pcibios_err_to_errno(ret);
5762 EXPORT_SYMBOL(pcie_set_readrq);
5765 * pcie_get_mps - get PCI Express maximum payload size
5766 * @dev: PCI device to query
5768 * Returns maximum payload size in bytes
5770 int pcie_get_mps(struct pci_dev *dev)
5774 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5776 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5778 EXPORT_SYMBOL(pcie_get_mps);
5781 * pcie_set_mps - set PCI Express maximum payload size
5782 * @dev: PCI device to query
5783 * @mps: maximum payload size in bytes
5784 * valid values are 128, 256, 512, 1024, 2048, 4096
5786 * If possible sets maximum payload size
5788 int pcie_set_mps(struct pci_dev *dev, int mps)
5793 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
5797 if (v > dev->pcie_mpss)
5801 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5802 PCI_EXP_DEVCTL_PAYLOAD, v);
5804 return pcibios_err_to_errno(ret);
5806 EXPORT_SYMBOL(pcie_set_mps);
5809 * pcie_bandwidth_available - determine minimum link settings of a PCIe
5810 * device and its bandwidth limitation
5811 * @dev: PCI device to query
5812 * @limiting_dev: storage for device causing the bandwidth limitation
5813 * @speed: storage for speed of limiting device
5814 * @width: storage for width of limiting device
5816 * Walk up the PCI device chain and find the point where the minimum
5817 * bandwidth is available. Return the bandwidth available there and (if
5818 * limiting_dev, speed, and width pointers are supplied) information about
5819 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
5822 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
5823 enum pci_bus_speed *speed,
5824 enum pcie_link_width *width)
5827 enum pci_bus_speed next_speed;
5828 enum pcie_link_width next_width;
5832 *speed = PCI_SPEED_UNKNOWN;
5834 *width = PCIE_LNK_WIDTH_UNKNOWN;
5839 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
5841 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
5842 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
5843 PCI_EXP_LNKSTA_NLW_SHIFT;
5845 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
5847 /* Check if current device limits the total bandwidth */
5848 if (!bw || next_bw <= bw) {
5852 *limiting_dev = dev;
5854 *speed = next_speed;
5856 *width = next_width;
5859 dev = pci_upstream_bridge(dev);
5864 EXPORT_SYMBOL(pcie_bandwidth_available);
5867 * pcie_get_speed_cap - query for the PCI device's link speed capability
5868 * @dev: PCI device to query
5870 * Query the PCI device speed capability. Return the maximum link speed
5871 * supported by the device.
5873 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
5875 u32 lnkcap2, lnkcap;
5878 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
5879 * implementation note there recommends using the Supported Link
5880 * Speeds Vector in Link Capabilities 2 when supported.
5882 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
5883 * should use the Supported Link Speeds field in Link Capabilities,
5884 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
5886 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
5888 /* PCIe r3.0-compliant */
5890 return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
5892 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5893 if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
5894 return PCIE_SPEED_5_0GT;
5895 else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
5896 return PCIE_SPEED_2_5GT;
5898 return PCI_SPEED_UNKNOWN;
5900 EXPORT_SYMBOL(pcie_get_speed_cap);
5903 * pcie_get_width_cap - query for the PCI device's link width capability
5904 * @dev: PCI device to query
5906 * Query the PCI device width capability. Return the maximum link width
5907 * supported by the device.
5909 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
5913 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5915 return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
5917 return PCIE_LNK_WIDTH_UNKNOWN;
5919 EXPORT_SYMBOL(pcie_get_width_cap);
5922 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
5924 * @speed: storage for link speed
5925 * @width: storage for link width
5927 * Calculate a PCI device's link bandwidth by querying for its link speed
5928 * and width, multiplying them, and applying encoding overhead. The result
5929 * is in Mb/s, i.e., megabits/second of raw bandwidth.
5931 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
5932 enum pcie_link_width *width)
5934 *speed = pcie_get_speed_cap(dev);
5935 *width = pcie_get_width_cap(dev);
5937 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
5940 return *width * PCIE_SPEED2MBS_ENC(*speed);
5944 * __pcie_print_link_status - Report the PCI device's link speed and width
5945 * @dev: PCI device to query
5946 * @verbose: Print info even when enough bandwidth is available
5948 * If the available bandwidth at the device is less than the device is
5949 * capable of, report the device's maximum possible bandwidth and the
5950 * upstream link that limits its performance. If @verbose, always print
5951 * the available bandwidth, even if the device isn't constrained.
5953 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
5955 enum pcie_link_width width, width_cap;
5956 enum pci_bus_speed speed, speed_cap;
5957 struct pci_dev *limiting_dev = NULL;
5958 u32 bw_avail, bw_cap;
5960 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
5961 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
5963 if (bw_avail >= bw_cap && verbose)
5964 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
5965 bw_cap / 1000, bw_cap % 1000,
5966 pci_speed_string(speed_cap), width_cap);
5967 else if (bw_avail < bw_cap)
5968 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
5969 bw_avail / 1000, bw_avail % 1000,
5970 pci_speed_string(speed), width,
5971 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
5972 bw_cap / 1000, bw_cap % 1000,
5973 pci_speed_string(speed_cap), width_cap);
5977 * pcie_print_link_status - Report the PCI device's link speed and width
5978 * @dev: PCI device to query
5980 * Report the available bandwidth at the device.
5982 void pcie_print_link_status(struct pci_dev *dev)
5984 __pcie_print_link_status(dev, true);
5986 EXPORT_SYMBOL(pcie_print_link_status);
5989 * pci_select_bars - Make BAR mask from the type of resource
5990 * @dev: the PCI device for which BAR mask is made
5991 * @flags: resource type mask to be selected
5993 * This helper routine makes bar mask from the type of resource.
5995 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
5998 for (i = 0; i < PCI_NUM_RESOURCES; i++)
5999 if (pci_resource_flags(dev, i) & flags)
6003 EXPORT_SYMBOL(pci_select_bars);
6005 /* Some architectures require additional programming to enable VGA */
6006 static arch_set_vga_state_t arch_set_vga_state;
6008 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
6010 arch_set_vga_state = func; /* NULL disables */
6013 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
6014 unsigned int command_bits, u32 flags)
6016 if (arch_set_vga_state)
6017 return arch_set_vga_state(dev, decode, command_bits,
6023 * pci_set_vga_state - set VGA decode state on device and parents if requested
6024 * @dev: the PCI device
6025 * @decode: true = enable decoding, false = disable decoding
6026 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6027 * @flags: traverse ancestors and change bridges
6028 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6030 int pci_set_vga_state(struct pci_dev *dev, bool decode,
6031 unsigned int command_bits, u32 flags)
6033 struct pci_bus *bus;
6034 struct pci_dev *bridge;
6038 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
6040 /* ARCH specific VGA enables */
6041 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6045 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
6046 pci_read_config_word(dev, PCI_COMMAND, &cmd);
6048 cmd |= command_bits;
6050 cmd &= ~command_bits;
6051 pci_write_config_word(dev, PCI_COMMAND, cmd);
6054 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
6061 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6064 cmd |= PCI_BRIDGE_CTL_VGA;
6066 cmd &= ~PCI_BRIDGE_CTL_VGA;
6067 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
6076 bool pci_pr3_present(struct pci_dev *pdev)
6078 struct acpi_device *adev;
6083 adev = ACPI_COMPANION(&pdev->dev);
6087 return adev->power.flags.power_resources &&
6088 acpi_has_method(adev->handle, "_PR3");
6090 EXPORT_SYMBOL_GPL(pci_pr3_present);
6094 * pci_add_dma_alias - Add a DMA devfn alias for a device
6095 * @dev: the PCI device for which alias is added
6096 * @devfn_from: alias slot and function
6097 * @nr_devfns: number of subsequent devfns to alias
6099 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6100 * which is used to program permissible bus-devfn source addresses for DMA
6101 * requests in an IOMMU. These aliases factor into IOMMU group creation
6102 * and are useful for devices generating DMA requests beyond or different
6103 * from their logical bus-devfn. Examples include device quirks where the
6104 * device simply uses the wrong devfn, as well as non-transparent bridges
6105 * where the alias may be a proxy for devices in another domain.
6107 * IOMMU group creation is performed during device discovery or addition,
6108 * prior to any potential DMA mapping and therefore prior to driver probing
6109 * (especially for userspace assigned devices where IOMMU group definition
6110 * cannot be left as a userspace activity). DMA aliases should therefore
6111 * be configured via quirks, such as the PCI fixup header quirk.
6113 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns)
6117 nr_devfns = min(nr_devfns, (unsigned) MAX_NR_DEVFNS - devfn_from);
6118 devfn_to = devfn_from + nr_devfns - 1;
6120 if (!dev->dma_alias_mask)
6121 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6122 if (!dev->dma_alias_mask) {
6123 pci_warn(dev, "Unable to allocate DMA alias mask\n");
6127 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6130 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6131 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
6132 else if (nr_devfns > 1)
6133 pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6134 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
6135 PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
6138 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
6140 return (dev1->dma_alias_mask &&
6141 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
6142 (dev2->dma_alias_mask &&
6143 test_bit(dev1->devfn, dev2->dma_alias_mask)) ||
6144 pci_real_dma_dev(dev1) == dev2 ||
6145 pci_real_dma_dev(dev2) == dev1;
6148 bool pci_device_is_present(struct pci_dev *pdev)
6152 if (pci_dev_is_disconnected(pdev))
6154 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
6156 EXPORT_SYMBOL_GPL(pci_device_is_present);
6158 void pci_ignore_hotplug(struct pci_dev *dev)
6160 struct pci_dev *bridge = dev->bus->self;
6162 dev->ignore_hotplug = 1;
6163 /* Propagate the "ignore hotplug" setting to the parent bridge. */
6165 bridge->ignore_hotplug = 1;
6167 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
6170 * pci_real_dma_dev - Get PCI DMA device for PCI device
6171 * @dev: the PCI device that may have a PCI DMA alias
6173 * Permits the platform to provide architecture-specific functionality to
6174 * devices needing to alias DMA to another PCI device on another PCI bus. If
6175 * the PCI device is on the same bus, it is recommended to use
6176 * pci_add_dma_alias(). This is the default implementation. Architecture
6177 * implementations can override this.
6179 struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6184 resource_size_t __weak pcibios_default_alignment(void)
6190 * Arches that don't want to expose struct resource to userland as-is in
6191 * sysfs and /proc can implement their own pci_resource_to_user().
6193 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6194 const struct resource *rsrc,
6195 resource_size_t *start, resource_size_t *end)
6197 *start = rsrc->start;
6201 static char *resource_alignment_param;
6202 static DEFINE_SPINLOCK(resource_alignment_lock);
6205 * pci_specified_resource_alignment - get resource alignment specified by user.
6206 * @dev: the PCI device to get
6207 * @resize: whether or not to change resources' size when reassigning alignment
6209 * RETURNS: Resource alignment if it is specified.
6210 * Zero if it is not specified.
6212 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6215 int align_order, count;
6216 resource_size_t align = pcibios_default_alignment();
6220 spin_lock(&resource_alignment_lock);
6221 p = resource_alignment_param;
6224 if (pci_has_flag(PCI_PROBE_ONLY)) {
6226 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6232 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
6235 if (align_order > 63) {
6236 pr_err("PCI: Invalid requested alignment (order %d)\n",
6238 align_order = PAGE_SHIFT;
6241 align_order = PAGE_SHIFT;
6244 ret = pci_dev_str_match(dev, p, &p);
6247 align = 1ULL << align_order;
6249 } else if (ret < 0) {
6250 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6255 if (*p != ';' && *p != ',') {
6256 /* End of param or invalid format */
6262 spin_unlock(&resource_alignment_lock);
6266 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6267 resource_size_t align, bool resize)
6269 struct resource *r = &dev->resource[bar];
6270 resource_size_t size;
6272 if (!(r->flags & IORESOURCE_MEM))
6275 if (r->flags & IORESOURCE_PCI_FIXED) {
6276 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
6277 bar, r, (unsigned long long)align);
6281 size = resource_size(r);
6286 * Increase the alignment of the resource. There are two ways we
6289 * 1) Increase the size of the resource. BARs are aligned on their
6290 * size, so when we reallocate space for this resource, we'll
6291 * allocate it with the larger alignment. This also prevents
6292 * assignment of any other BARs inside the alignment region, so
6293 * if we're requesting page alignment, this means no other BARs
6294 * will share the page.
6296 * The disadvantage is that this makes the resource larger than
6297 * the hardware BAR, which may break drivers that compute things
6298 * based on the resource size, e.g., to find registers at a
6299 * fixed offset before the end of the BAR.
6301 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6302 * set r->start to the desired alignment. By itself this
6303 * doesn't prevent other BARs being put inside the alignment
6304 * region, but if we realign *every* resource of every device in
6305 * the system, none of them will share an alignment region.
6307 * When the user has requested alignment for only some devices via
6308 * the "pci=resource_alignment" argument, "resize" is true and we
6309 * use the first method. Otherwise we assume we're aligning all
6310 * devices and we use the second.
6313 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
6314 bar, r, (unsigned long long)align);
6320 r->flags &= ~IORESOURCE_SIZEALIGN;
6321 r->flags |= IORESOURCE_STARTALIGN;
6323 r->end = r->start + size - 1;
6325 r->flags |= IORESOURCE_UNSET;
6329 * This function disables memory decoding and releases memory resources
6330 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6331 * It also rounds up size to specified alignment.
6332 * Later on, the kernel will assign page-aligned memory resource back
6335 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6339 resource_size_t align;
6341 bool resize = false;
6344 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6345 * 3.4.1.11. Their resources are allocated from the space
6346 * described by the VF BARx register in the PF's SR-IOV capability.
6347 * We can't influence their alignment here.
6352 /* check if specified PCI is target device to reassign */
6353 align = pci_specified_resource_alignment(dev, &resize);
6357 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6358 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6359 pci_warn(dev, "Can't reassign resources to host bridge\n");
6363 pci_read_config_word(dev, PCI_COMMAND, &command);
6364 command &= ~PCI_COMMAND_MEMORY;
6365 pci_write_config_word(dev, PCI_COMMAND, command);
6367 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
6368 pci_request_resource_alignment(dev, i, align, resize);
6371 * Need to disable bridge's resource window,
6372 * to enable the kernel to reassign new resource
6375 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6376 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6377 r = &dev->resource[i];
6378 if (!(r->flags & IORESOURCE_MEM))
6380 r->flags |= IORESOURCE_UNSET;
6381 r->end = resource_size(r) - 1;
6384 pci_disable_bridge_window(dev);
6388 static ssize_t resource_alignment_show(struct bus_type *bus, char *buf)
6392 spin_lock(&resource_alignment_lock);
6393 if (resource_alignment_param)
6394 count = scnprintf(buf, PAGE_SIZE, "%s", resource_alignment_param);
6395 spin_unlock(&resource_alignment_lock);
6398 * When set by the command line, resource_alignment_param will not
6399 * have a trailing line feed, which is ugly. So conditionally add
6402 if (count >= 2 && buf[count - 2] != '\n' && count < PAGE_SIZE - 1) {
6403 buf[count - 1] = '\n';
6410 static ssize_t resource_alignment_store(struct bus_type *bus,
6411 const char *buf, size_t count)
6413 char *param = kstrndup(buf, count, GFP_KERNEL);
6418 spin_lock(&resource_alignment_lock);
6419 kfree(resource_alignment_param);
6420 resource_alignment_param = param;
6421 spin_unlock(&resource_alignment_lock);
6425 static BUS_ATTR_RW(resource_alignment);
6427 static int __init pci_resource_alignment_sysfs_init(void)
6429 return bus_create_file(&pci_bus_type,
6430 &bus_attr_resource_alignment);
6432 late_initcall(pci_resource_alignment_sysfs_init);
6434 static void pci_no_domains(void)
6436 #ifdef CONFIG_PCI_DOMAINS
6437 pci_domains_supported = 0;
6441 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6442 static atomic_t __domain_nr = ATOMIC_INIT(-1);
6444 static int pci_get_new_domain_nr(void)
6446 return atomic_inc_return(&__domain_nr);
6449 static int of_pci_bus_find_domain_nr(struct device *parent)
6451 static int use_dt_domains = -1;
6455 domain = of_get_pci_domain_nr(parent->of_node);
6458 * Check DT domain and use_dt_domains values.
6460 * If DT domain property is valid (domain >= 0) and
6461 * use_dt_domains != 0, the DT assignment is valid since this means
6462 * we have not previously allocated a domain number by using
6463 * pci_get_new_domain_nr(); we should also update use_dt_domains to
6464 * 1, to indicate that we have just assigned a domain number from
6467 * If DT domain property value is not valid (ie domain < 0), and we
6468 * have not previously assigned a domain number from DT
6469 * (use_dt_domains != 1) we should assign a domain number by
6472 * pci_get_new_domain_nr()
6474 * API and update the use_dt_domains value to keep track of method we
6475 * are using to assign domain numbers (use_dt_domains = 0).
6477 * All other combinations imply we have a platform that is trying
6478 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
6479 * which is a recipe for domain mishandling and it is prevented by
6480 * invalidating the domain value (domain = -1) and printing a
6481 * corresponding error.
6483 if (domain >= 0 && use_dt_domains) {
6485 } else if (domain < 0 && use_dt_domains != 1) {
6487 domain = pci_get_new_domain_nr();
6490 pr_err("Node %pOF has ", parent->of_node);
6491 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
6498 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
6500 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
6501 acpi_pci_bus_find_domain_nr(bus);
6506 * pci_ext_cfg_avail - can we access extended PCI config space?
6508 * Returns 1 if we can access PCI extended config space (offsets
6509 * greater than 0xff). This is the default implementation. Architecture
6510 * implementations can override this.
6512 int __weak pci_ext_cfg_avail(void)
6517 void __weak pci_fixup_cardbus(struct pci_bus *bus)
6520 EXPORT_SYMBOL(pci_fixup_cardbus);
6522 static int __init pci_setup(char *str)
6525 char *k = strchr(str, ',');
6528 if (*str && (str = pcibios_setup(str)) && *str) {
6529 if (!strcmp(str, "nomsi")) {
6531 } else if (!strncmp(str, "noats", 5)) {
6532 pr_info("PCIe: ATS is disabled\n");
6533 pcie_ats_disabled = true;
6534 } else if (!strcmp(str, "noaer")) {
6536 } else if (!strcmp(str, "earlydump")) {
6537 pci_early_dump = true;
6538 } else if (!strncmp(str, "realloc=", 8)) {
6539 pci_realloc_get_opt(str + 8);
6540 } else if (!strncmp(str, "realloc", 7)) {
6541 pci_realloc_get_opt("on");
6542 } else if (!strcmp(str, "nodomains")) {
6544 } else if (!strncmp(str, "noari", 5)) {
6545 pcie_ari_disabled = true;
6546 } else if (!strncmp(str, "cbiosize=", 9)) {
6547 pci_cardbus_io_size = memparse(str + 9, &str);
6548 } else if (!strncmp(str, "cbmemsize=", 10)) {
6549 pci_cardbus_mem_size = memparse(str + 10, &str);
6550 } else if (!strncmp(str, "resource_alignment=", 19)) {
6551 resource_alignment_param = str + 19;
6552 } else if (!strncmp(str, "ecrc=", 5)) {
6553 pcie_ecrc_get_policy(str + 5);
6554 } else if (!strncmp(str, "hpiosize=", 9)) {
6555 pci_hotplug_io_size = memparse(str + 9, &str);
6556 } else if (!strncmp(str, "hpmmiosize=", 11)) {
6557 pci_hotplug_mmio_size = memparse(str + 11, &str);
6558 } else if (!strncmp(str, "hpmmioprefsize=", 15)) {
6559 pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
6560 } else if (!strncmp(str, "hpmemsize=", 10)) {
6561 pci_hotplug_mmio_size = memparse(str + 10, &str);
6562 pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
6563 } else if (!strncmp(str, "hpbussize=", 10)) {
6564 pci_hotplug_bus_size =
6565 simple_strtoul(str + 10, &str, 0);
6566 if (pci_hotplug_bus_size > 0xff)
6567 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
6568 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
6569 pcie_bus_config = PCIE_BUS_TUNE_OFF;
6570 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
6571 pcie_bus_config = PCIE_BUS_SAFE;
6572 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
6573 pcie_bus_config = PCIE_BUS_PERFORMANCE;
6574 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
6575 pcie_bus_config = PCIE_BUS_PEER2PEER;
6576 } else if (!strncmp(str, "pcie_scan_all", 13)) {
6577 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
6578 } else if (!strncmp(str, "disable_acs_redir=", 18)) {
6579 disable_acs_redir_param = str + 18;
6581 pr_err("PCI: Unknown option `%s'\n", str);
6588 early_param("pci", pci_setup);
6591 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6592 * in pci_setup(), above, to point to data in the __initdata section which
6593 * will be freed after the init sequence is complete. We can't allocate memory
6594 * in pci_setup() because some architectures do not have any memory allocation
6595 * service available during an early_param() call. So we allocate memory and
6596 * copy the variable here before the init section is freed.
6599 static int __init pci_realloc_setup_params(void)
6601 resource_alignment_param = kstrdup(resource_alignment_param,
6603 disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
6607 pure_initcall(pci_realloc_setup_params);