1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
17 #include <linux/of_pci.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pci-aspm.h>
27 #include <linux/pm_wakeup.h>
28 #include <linux/interrupt.h>
29 #include <linux/device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/pci_hotplug.h>
32 #include <linux/vmalloc.h>
33 #include <linux/pci-ats.h>
34 #include <asm/setup.h>
36 #include <linux/aer.h>
39 const char *pci_power_names[] = {
40 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
42 EXPORT_SYMBOL_GPL(pci_power_names);
44 int isa_dma_bridge_buggy;
45 EXPORT_SYMBOL(isa_dma_bridge_buggy);
48 EXPORT_SYMBOL(pci_pci_problems);
50 unsigned int pci_pm_d3_delay;
52 static void pci_pme_list_scan(struct work_struct *work);
54 static LIST_HEAD(pci_pme_list);
55 static DEFINE_MUTEX(pci_pme_list_mutex);
56 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
58 struct pci_pme_device {
59 struct list_head list;
63 #define PME_TIMEOUT 1000 /* How long between PME checks */
65 static void pci_dev_d3_sleep(struct pci_dev *dev)
67 unsigned int delay = dev->d3_delay;
69 if (delay < pci_pm_d3_delay)
70 delay = pci_pm_d3_delay;
76 #ifdef CONFIG_PCI_DOMAINS
77 int pci_domains_supported = 1;
80 #define DEFAULT_CARDBUS_IO_SIZE (256)
81 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
82 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
83 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
84 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
86 #define DEFAULT_HOTPLUG_IO_SIZE (256)
87 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
88 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
89 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
90 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
92 #define DEFAULT_HOTPLUG_BUS_SIZE 1
93 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
95 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
98 * The default CLS is used if arch didn't set CLS explicitly and not
99 * all pci devices agree on the same value. Arch can override either
100 * the dfl or actual value as it sees fit. Don't forget this is
101 * measured in 32-bit words, not bytes.
103 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
104 u8 pci_cache_line_size;
107 * If we set up a device for bus mastering, we need to check the latency
108 * timer as certain BIOSes forget to set it properly.
110 unsigned int pcibios_max_latency = 255;
112 /* If set, the PCIe ARI capability will not be used. */
113 static bool pcie_ari_disabled;
115 /* Disable bridge_d3 for all PCIe ports */
116 static bool pci_bridge_d3_disable;
117 /* Force bridge_d3 for all PCIe ports */
118 static bool pci_bridge_d3_force;
120 static int __init pcie_port_pm_setup(char *str)
122 if (!strcmp(str, "off"))
123 pci_bridge_d3_disable = true;
124 else if (!strcmp(str, "force"))
125 pci_bridge_d3_force = true;
128 __setup("pcie_port_pm=", pcie_port_pm_setup);
130 /* Time to wait after a reset for device to become responsive */
131 #define PCIE_RESET_READY_POLL_MS 60000
134 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
135 * @bus: pointer to PCI bus structure to search
137 * Given a PCI bus, returns the highest PCI bus number present in the set
138 * including the given PCI bus and its list of child PCI buses.
140 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
143 unsigned char max, n;
145 max = bus->busn_res.end;
146 list_for_each_entry(tmp, &bus->children, node) {
147 n = pci_bus_max_busnr(tmp);
153 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
155 #ifdef CONFIG_HAS_IOMEM
156 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
158 struct resource *res = &pdev->resource[bar];
161 * Make sure the BAR is actually a memory resource, not an IO resource
163 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
164 pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
167 return ioremap_nocache(res->start, resource_size(res));
169 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
171 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
174 * Make sure the BAR is actually a memory resource, not an IO resource
176 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
180 return ioremap_wc(pci_resource_start(pdev, bar),
181 pci_resource_len(pdev, bar));
183 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
187 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
188 u8 pos, int cap, int *ttl)
193 pci_bus_read_config_byte(bus, devfn, pos, &pos);
199 pci_bus_read_config_word(bus, devfn, pos, &ent);
211 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
214 int ttl = PCI_FIND_CAP_TTL;
216 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
219 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
221 return __pci_find_next_cap(dev->bus, dev->devfn,
222 pos + PCI_CAP_LIST_NEXT, cap);
224 EXPORT_SYMBOL_GPL(pci_find_next_capability);
226 static int __pci_bus_find_cap_start(struct pci_bus *bus,
227 unsigned int devfn, u8 hdr_type)
231 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
232 if (!(status & PCI_STATUS_CAP_LIST))
236 case PCI_HEADER_TYPE_NORMAL:
237 case PCI_HEADER_TYPE_BRIDGE:
238 return PCI_CAPABILITY_LIST;
239 case PCI_HEADER_TYPE_CARDBUS:
240 return PCI_CB_CAPABILITY_LIST;
247 * pci_find_capability - query for devices' capabilities
248 * @dev: PCI device to query
249 * @cap: capability code
251 * Tell if a device supports a given PCI capability.
252 * Returns the address of the requested capability structure within the
253 * device's PCI configuration space or 0 in case the device does not
254 * support it. Possible values for @cap:
256 * %PCI_CAP_ID_PM Power Management
257 * %PCI_CAP_ID_AGP Accelerated Graphics Port
258 * %PCI_CAP_ID_VPD Vital Product Data
259 * %PCI_CAP_ID_SLOTID Slot Identification
260 * %PCI_CAP_ID_MSI Message Signalled Interrupts
261 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
262 * %PCI_CAP_ID_PCIX PCI-X
263 * %PCI_CAP_ID_EXP PCI Express
265 int pci_find_capability(struct pci_dev *dev, int cap)
269 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
271 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
275 EXPORT_SYMBOL(pci_find_capability);
278 * pci_bus_find_capability - query for devices' capabilities
279 * @bus: the PCI bus to query
280 * @devfn: PCI device to query
281 * @cap: capability code
283 * Like pci_find_capability() but works for pci devices that do not have a
284 * pci_dev structure set up yet.
286 * Returns the address of the requested capability structure within the
287 * device's PCI configuration space or 0 in case the device does not
290 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
295 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
297 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
299 pos = __pci_find_next_cap(bus, devfn, pos, cap);
303 EXPORT_SYMBOL(pci_bus_find_capability);
306 * pci_find_next_ext_capability - Find an extended capability
307 * @dev: PCI device to query
308 * @start: address at which to start looking (0 to start at beginning of list)
309 * @cap: capability code
311 * Returns the address of the next matching extended capability structure
312 * within the device's PCI configuration space or 0 if the device does
313 * not support it. Some capabilities can occur several times, e.g., the
314 * vendor-specific capability, and this provides a way to find them all.
316 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
320 int pos = PCI_CFG_SPACE_SIZE;
322 /* minimum 8 bytes per capability */
323 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
325 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
331 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
335 * If we have no capabilities, this is indicated by cap ID,
336 * cap version and next pointer all being 0.
342 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
345 pos = PCI_EXT_CAP_NEXT(header);
346 if (pos < PCI_CFG_SPACE_SIZE)
349 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
355 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
358 * pci_find_ext_capability - Find an extended capability
359 * @dev: PCI device to query
360 * @cap: capability code
362 * Returns the address of the requested extended capability structure
363 * within the device's PCI configuration space or 0 if the device does
364 * not support it. Possible values for @cap:
366 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
367 * %PCI_EXT_CAP_ID_VC Virtual Channel
368 * %PCI_EXT_CAP_ID_DSN Device Serial Number
369 * %PCI_EXT_CAP_ID_PWR Power Budgeting
371 int pci_find_ext_capability(struct pci_dev *dev, int cap)
373 return pci_find_next_ext_capability(dev, 0, cap);
375 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
377 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
379 int rc, ttl = PCI_FIND_CAP_TTL;
382 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
383 mask = HT_3BIT_CAP_MASK;
385 mask = HT_5BIT_CAP_MASK;
387 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
388 PCI_CAP_ID_HT, &ttl);
390 rc = pci_read_config_byte(dev, pos + 3, &cap);
391 if (rc != PCIBIOS_SUCCESSFUL)
394 if ((cap & mask) == ht_cap)
397 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
398 pos + PCI_CAP_LIST_NEXT,
399 PCI_CAP_ID_HT, &ttl);
405 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
406 * @dev: PCI device to query
407 * @pos: Position from which to continue searching
408 * @ht_cap: Hypertransport capability code
410 * To be used in conjunction with pci_find_ht_capability() to search for
411 * all capabilities matching @ht_cap. @pos should always be a value returned
412 * from pci_find_ht_capability().
414 * NB. To be 100% safe against broken PCI devices, the caller should take
415 * steps to avoid an infinite loop.
417 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
419 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
421 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
424 * pci_find_ht_capability - query a device's Hypertransport capabilities
425 * @dev: PCI device to query
426 * @ht_cap: Hypertransport capability code
428 * Tell if a device supports a given Hypertransport capability.
429 * Returns an address within the device's PCI configuration space
430 * or 0 in case the device does not support the request capability.
431 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
432 * which has a Hypertransport capability matching @ht_cap.
434 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
438 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
440 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
444 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
447 * pci_find_parent_resource - return resource region of parent bus of given region
448 * @dev: PCI device structure contains resources to be searched
449 * @res: child resource record for which parent is sought
451 * For given resource region of given device, return the resource
452 * region of parent bus the given region is contained in.
454 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
455 struct resource *res)
457 const struct pci_bus *bus = dev->bus;
461 pci_bus_for_each_resource(bus, r, i) {
464 if (resource_contains(r, res)) {
467 * If the window is prefetchable but the BAR is
468 * not, the allocator made a mistake.
470 if (r->flags & IORESOURCE_PREFETCH &&
471 !(res->flags & IORESOURCE_PREFETCH))
475 * If we're below a transparent bridge, there may
476 * be both a positively-decoded aperture and a
477 * subtractively-decoded region that contain the BAR.
478 * We want the positively-decoded one, so this depends
479 * on pci_bus_for_each_resource() giving us those
487 EXPORT_SYMBOL(pci_find_parent_resource);
490 * pci_find_resource - Return matching PCI device resource
491 * @dev: PCI device to query
492 * @res: Resource to look for
494 * Goes over standard PCI resources (BARs) and checks if the given resource
495 * is partially or fully contained in any of them. In that case the
496 * matching resource is returned, %NULL otherwise.
498 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
502 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
503 struct resource *r = &dev->resource[i];
505 if (r->start && resource_contains(r, res))
511 EXPORT_SYMBOL(pci_find_resource);
514 * pci_find_pcie_root_port - return PCIe Root Port
515 * @dev: PCI device to query
517 * Traverse up the parent chain and return the PCIe Root Port PCI Device
518 * for a given PCI Device.
520 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
522 struct pci_dev *bridge, *highest_pcie_bridge = dev;
524 bridge = pci_upstream_bridge(dev);
525 while (bridge && pci_is_pcie(bridge)) {
526 highest_pcie_bridge = bridge;
527 bridge = pci_upstream_bridge(bridge);
530 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
533 return highest_pcie_bridge;
535 EXPORT_SYMBOL(pci_find_pcie_root_port);
538 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
539 * @dev: the PCI device to operate on
540 * @pos: config space offset of status word
541 * @mask: mask of bit(s) to care about in status word
543 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
545 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
549 /* Wait for Transaction Pending bit clean */
550 for (i = 0; i < 4; i++) {
553 msleep((1 << (i - 1)) * 100);
555 pci_read_config_word(dev, pos, &status);
556 if (!(status & mask))
564 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
565 * @dev: PCI device to have its BARs restored
567 * Restore the BAR values for a given device, so as to make it
568 * accessible by its driver.
570 static void pci_restore_bars(struct pci_dev *dev)
574 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
575 pci_update_resource(dev, i);
578 static const struct pci_platform_pm_ops *pci_platform_pm;
580 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
582 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
583 !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
585 pci_platform_pm = ops;
589 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
591 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
594 static inline int platform_pci_set_power_state(struct pci_dev *dev,
597 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
600 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
602 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
605 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
607 return pci_platform_pm ?
608 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
611 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
613 return pci_platform_pm ?
614 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
617 static inline bool platform_pci_need_resume(struct pci_dev *dev)
619 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
623 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
625 * @dev: PCI device to handle.
626 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
629 * -EINVAL if the requested state is invalid.
630 * -EIO if device does not support PCI PM or its PM capabilities register has a
631 * wrong version, or device doesn't support the requested state.
632 * 0 if device already is in the requested state.
633 * 0 if device's power state has been successfully changed.
635 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
638 bool need_restore = false;
640 /* Check if we're already there */
641 if (dev->current_state == state)
647 if (state < PCI_D0 || state > PCI_D3hot)
650 /* Validate current state:
651 * Can enter D0 from any state, but if we can only go deeper
652 * to sleep if we're already in a low power state
654 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
655 && dev->current_state > state) {
656 pci_err(dev, "invalid power transition (from state %d to %d)\n",
657 dev->current_state, state);
661 /* check if this device supports the desired state */
662 if ((state == PCI_D1 && !dev->d1_support)
663 || (state == PCI_D2 && !dev->d2_support))
666 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
668 /* If we're (effectively) in D3, force entire word to 0.
669 * This doesn't affect PME_Status, disables PME_En, and
670 * sets PowerState to 0.
672 switch (dev->current_state) {
676 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
681 case PCI_UNKNOWN: /* Boot-up */
682 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
683 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
685 /* Fall-through: force to D0 */
691 /* enter specified state */
692 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
694 /* Mandatory power management transition delays */
695 /* see PCI PM 1.1 5.6.1 table 18 */
696 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
697 pci_dev_d3_sleep(dev);
698 else if (state == PCI_D2 || dev->current_state == PCI_D2)
699 udelay(PCI_PM_D2_DELAY);
701 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
702 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
703 if (dev->current_state != state && printk_ratelimit())
704 pci_info(dev, "Refused to change power state, currently in D%d\n",
708 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
709 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
710 * from D3hot to D0 _may_ perform an internal reset, thereby
711 * going to "D0 Uninitialized" rather than "D0 Initialized".
712 * For example, at least some versions of the 3c905B and the
713 * 3c556B exhibit this behaviour.
715 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
716 * devices in a D3hot state at boot. Consequently, we need to
717 * restore at least the BARs so that the device will be
718 * accessible to its driver.
721 pci_restore_bars(dev);
724 pcie_aspm_pm_state_change(dev->bus->self);
730 * pci_update_current_state - Read power state of given device and cache it
731 * @dev: PCI device to handle.
732 * @state: State to cache in case the device doesn't have the PM capability
734 * The power state is read from the PMCSR register, which however is
735 * inaccessible in D3cold. The platform firmware is therefore queried first
736 * to detect accessibility of the register. In case the platform firmware
737 * reports an incorrect state or the device isn't power manageable by the
738 * platform at all, we try to detect D3cold by testing accessibility of the
739 * vendor ID in config space.
741 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
743 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
744 !pci_device_is_present(dev)) {
745 dev->current_state = PCI_D3cold;
746 } else if (dev->pm_cap) {
749 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
750 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
752 dev->current_state = state;
757 * pci_power_up - Put the given device into D0 forcibly
758 * @dev: PCI device to power up
760 void pci_power_up(struct pci_dev *dev)
762 if (platform_pci_power_manageable(dev))
763 platform_pci_set_power_state(dev, PCI_D0);
765 pci_raw_set_power_state(dev, PCI_D0);
766 pci_update_current_state(dev, PCI_D0);
770 * pci_platform_power_transition - Use platform to change device power state
771 * @dev: PCI device to handle.
772 * @state: State to put the device into.
774 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
778 if (platform_pci_power_manageable(dev)) {
779 error = platform_pci_set_power_state(dev, state);
781 pci_update_current_state(dev, state);
785 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
786 dev->current_state = PCI_D0;
792 * pci_wakeup - Wake up a PCI device
793 * @pci_dev: Device to handle.
794 * @ign: ignored parameter
796 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
798 pci_wakeup_event(pci_dev);
799 pm_request_resume(&pci_dev->dev);
804 * pci_wakeup_bus - Walk given bus and wake up devices on it
805 * @bus: Top bus of the subtree to walk.
807 static void pci_wakeup_bus(struct pci_bus *bus)
810 pci_walk_bus(bus, pci_wakeup, NULL);
814 * __pci_start_power_transition - Start power transition of a PCI device
815 * @dev: PCI device to handle.
816 * @state: State to put the device into.
818 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
820 if (state == PCI_D0) {
821 pci_platform_power_transition(dev, PCI_D0);
823 * Mandatory power management transition delays, see
824 * PCI Express Base Specification Revision 2.0 Section
825 * 6.6.1: Conventional Reset. Do not delay for
826 * devices powered on/off by corresponding bridge,
827 * because have already delayed for the bridge.
829 if (dev->runtime_d3cold) {
830 if (dev->d3cold_delay)
831 msleep(dev->d3cold_delay);
833 * When powering on a bridge from D3cold, the
834 * whole hierarchy may be powered on into
835 * D0uninitialized state, resume them to give
836 * them a chance to suspend again
838 pci_wakeup_bus(dev->subordinate);
844 * __pci_dev_set_current_state - Set current state of a PCI device
845 * @dev: Device to handle
846 * @data: pointer to state to be set
848 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
850 pci_power_t state = *(pci_power_t *)data;
852 dev->current_state = state;
857 * __pci_bus_set_current_state - Walk given bus and set current state of devices
858 * @bus: Top bus of the subtree to walk.
859 * @state: state to be set
861 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
864 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
868 * __pci_complete_power_transition - Complete power transition of a PCI device
869 * @dev: PCI device to handle.
870 * @state: State to put the device into.
872 * This function should not be called directly by device drivers.
874 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
880 ret = pci_platform_power_transition(dev, state);
881 /* Power off the bridge may power off the whole hierarchy */
882 if (!ret && state == PCI_D3cold)
883 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
886 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
889 * pci_set_power_state - Set the power state of a PCI device
890 * @dev: PCI device to handle.
891 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
893 * Transition a device to a new power state, using the platform firmware and/or
894 * the device's PCI PM registers.
897 * -EINVAL if the requested state is invalid.
898 * -EIO if device does not support PCI PM or its PM capabilities register has a
899 * wrong version, or device doesn't support the requested state.
900 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
901 * 0 if device already is in the requested state.
902 * 0 if the transition is to D3 but D3 is not supported.
903 * 0 if device's power state has been successfully changed.
905 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
909 /* bound the state we're entering */
910 if (state > PCI_D3cold)
912 else if (state < PCI_D0)
914 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
916 * If the device or the parent bridge do not support PCI PM,
917 * ignore the request if we're doing anything other than putting
918 * it into D0 (which would only happen on boot).
922 /* Check if we're already there */
923 if (dev->current_state == state)
926 __pci_start_power_transition(dev, state);
928 /* This device is quirked not to be put into D3, so
929 don't put it in D3 */
930 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
934 * To put device in D3cold, we put device into D3hot in native
935 * way, then put device into D3cold with platform ops
937 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
940 if (!__pci_complete_power_transition(dev, state))
945 EXPORT_SYMBOL(pci_set_power_state);
948 * pci_choose_state - Choose the power state of a PCI device
949 * @dev: PCI device to be suspended
950 * @state: target sleep state for the whole system. This is the value
951 * that is passed to suspend() function.
953 * Returns PCI power state suitable for given device and given system
957 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
964 ret = platform_pci_choose_state(dev);
965 if (ret != PCI_POWER_ERROR)
968 switch (state.event) {
971 case PM_EVENT_FREEZE:
972 case PM_EVENT_PRETHAW:
973 /* REVISIT both freeze and pre-thaw "should" use D0 */
974 case PM_EVENT_SUSPEND:
975 case PM_EVENT_HIBERNATE:
978 pci_info(dev, "unrecognized suspend event %d\n",
984 EXPORT_SYMBOL(pci_choose_state);
986 #define PCI_EXP_SAVE_REGS 7
988 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
989 u16 cap, bool extended)
991 struct pci_cap_saved_state *tmp;
993 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
994 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1000 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1002 return _pci_find_saved_cap(dev, cap, false);
1005 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1007 return _pci_find_saved_cap(dev, cap, true);
1010 static int pci_save_pcie_state(struct pci_dev *dev)
1013 struct pci_cap_saved_state *save_state;
1016 if (!pci_is_pcie(dev))
1019 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1021 pci_err(dev, "buffer not found in %s\n", __func__);
1025 cap = (u16 *)&save_state->cap.data[0];
1026 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1027 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1028 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1029 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1030 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1031 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1032 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1037 static void pci_restore_pcie_state(struct pci_dev *dev)
1040 struct pci_cap_saved_state *save_state;
1043 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1047 cap = (u16 *)&save_state->cap.data[0];
1048 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1049 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1050 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1051 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1052 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1053 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1054 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1058 static int pci_save_pcix_state(struct pci_dev *dev)
1061 struct pci_cap_saved_state *save_state;
1063 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1067 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1069 pci_err(dev, "buffer not found in %s\n", __func__);
1073 pci_read_config_word(dev, pos + PCI_X_CMD,
1074 (u16 *)save_state->cap.data);
1079 static void pci_restore_pcix_state(struct pci_dev *dev)
1082 struct pci_cap_saved_state *save_state;
1085 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1086 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1087 if (!save_state || !pos)
1089 cap = (u16 *)&save_state->cap.data[0];
1091 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1096 * pci_save_state - save the PCI configuration space of a device before suspending
1097 * @dev: - PCI device that we're dealing with
1099 int pci_save_state(struct pci_dev *dev)
1102 /* XXX: 100% dword access ok here? */
1103 for (i = 0; i < 16; i++)
1104 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1105 dev->state_saved = true;
1107 i = pci_save_pcie_state(dev);
1111 i = pci_save_pcix_state(dev);
1115 return pci_save_vc_state(dev);
1117 EXPORT_SYMBOL(pci_save_state);
1119 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1120 u32 saved_val, int retry)
1124 pci_read_config_dword(pdev, offset, &val);
1125 if (val == saved_val)
1129 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1130 offset, val, saved_val);
1131 pci_write_config_dword(pdev, offset, saved_val);
1135 pci_read_config_dword(pdev, offset, &val);
1136 if (val == saved_val)
1143 static void pci_restore_config_space_range(struct pci_dev *pdev,
1144 int start, int end, int retry)
1148 for (index = end; index >= start; index--)
1149 pci_restore_config_dword(pdev, 4 * index,
1150 pdev->saved_config_space[index],
1154 static void pci_restore_config_space(struct pci_dev *pdev)
1156 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1157 pci_restore_config_space_range(pdev, 10, 15, 0);
1158 /* Restore BARs before the command register. */
1159 pci_restore_config_space_range(pdev, 4, 9, 10);
1160 pci_restore_config_space_range(pdev, 0, 3, 0);
1162 pci_restore_config_space_range(pdev, 0, 15, 0);
1167 * pci_restore_state - Restore the saved state of a PCI device
1168 * @dev: - PCI device that we're dealing with
1170 void pci_restore_state(struct pci_dev *dev)
1172 if (!dev->state_saved)
1175 /* PCI Express register must be restored first */
1176 pci_restore_pcie_state(dev);
1177 pci_restore_pasid_state(dev);
1178 pci_restore_pri_state(dev);
1179 pci_restore_ats_state(dev);
1180 pci_restore_vc_state(dev);
1182 pci_cleanup_aer_error_status_regs(dev);
1184 pci_restore_config_space(dev);
1186 pci_restore_pcix_state(dev);
1187 pci_restore_msi_state(dev);
1189 /* Restore ACS and IOV configuration state */
1190 pci_enable_acs(dev);
1191 pci_restore_iov_state(dev);
1193 dev->state_saved = false;
1195 EXPORT_SYMBOL(pci_restore_state);
1197 struct pci_saved_state {
1198 u32 config_space[16];
1199 struct pci_cap_saved_data cap[0];
1203 * pci_store_saved_state - Allocate and return an opaque struct containing
1204 * the device saved state.
1205 * @dev: PCI device that we're dealing with
1207 * Return NULL if no state or error.
1209 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1211 struct pci_saved_state *state;
1212 struct pci_cap_saved_state *tmp;
1213 struct pci_cap_saved_data *cap;
1216 if (!dev->state_saved)
1219 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1221 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1222 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1224 state = kzalloc(size, GFP_KERNEL);
1228 memcpy(state->config_space, dev->saved_config_space,
1229 sizeof(state->config_space));
1232 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1233 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1234 memcpy(cap, &tmp->cap, len);
1235 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1237 /* Empty cap_save terminates list */
1241 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1244 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1245 * @dev: PCI device that we're dealing with
1246 * @state: Saved state returned from pci_store_saved_state()
1248 int pci_load_saved_state(struct pci_dev *dev,
1249 struct pci_saved_state *state)
1251 struct pci_cap_saved_data *cap;
1253 dev->state_saved = false;
1258 memcpy(dev->saved_config_space, state->config_space,
1259 sizeof(state->config_space));
1263 struct pci_cap_saved_state *tmp;
1265 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1266 if (!tmp || tmp->cap.size != cap->size)
1269 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1270 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1271 sizeof(struct pci_cap_saved_data) + cap->size);
1274 dev->state_saved = true;
1277 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1280 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1281 * and free the memory allocated for it.
1282 * @dev: PCI device that we're dealing with
1283 * @state: Pointer to saved state returned from pci_store_saved_state()
1285 int pci_load_and_free_saved_state(struct pci_dev *dev,
1286 struct pci_saved_state **state)
1288 int ret = pci_load_saved_state(dev, *state);
1293 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1295 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1297 return pci_enable_resources(dev, bars);
1300 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1303 struct pci_dev *bridge;
1307 err = pci_set_power_state(dev, PCI_D0);
1308 if (err < 0 && err != -EIO)
1311 bridge = pci_upstream_bridge(dev);
1313 pcie_aspm_powersave_config_link(bridge);
1315 err = pcibios_enable_device(dev, bars);
1318 pci_fixup_device(pci_fixup_enable, dev);
1320 if (dev->msi_enabled || dev->msix_enabled)
1323 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1325 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1326 if (cmd & PCI_COMMAND_INTX_DISABLE)
1327 pci_write_config_word(dev, PCI_COMMAND,
1328 cmd & ~PCI_COMMAND_INTX_DISABLE);
1335 * pci_reenable_device - Resume abandoned device
1336 * @dev: PCI device to be resumed
1338 * Note this function is a backend of pci_default_resume and is not supposed
1339 * to be called by normal code, write proper resume handler and use it instead.
1341 int pci_reenable_device(struct pci_dev *dev)
1343 if (pci_is_enabled(dev))
1344 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1347 EXPORT_SYMBOL(pci_reenable_device);
1349 static void pci_enable_bridge(struct pci_dev *dev)
1351 struct pci_dev *bridge;
1354 bridge = pci_upstream_bridge(dev);
1356 pci_enable_bridge(bridge);
1358 if (pci_is_enabled(dev)) {
1359 if (!dev->is_busmaster)
1360 pci_set_master(dev);
1364 retval = pci_enable_device(dev);
1366 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1368 pci_set_master(dev);
1371 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1373 struct pci_dev *bridge;
1378 * Power state could be unknown at this point, either due to a fresh
1379 * boot or a device removal call. So get the current power state
1380 * so that things like MSI message writing will behave as expected
1381 * (e.g. if the device really is in D0 at enable time).
1385 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1386 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1389 if (atomic_inc_return(&dev->enable_cnt) > 1)
1390 return 0; /* already enabled */
1392 bridge = pci_upstream_bridge(dev);
1394 pci_enable_bridge(bridge);
1396 /* only skip sriov related */
1397 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1398 if (dev->resource[i].flags & flags)
1400 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1401 if (dev->resource[i].flags & flags)
1404 err = do_pci_enable_device(dev, bars);
1406 atomic_dec(&dev->enable_cnt);
1411 * pci_enable_device_io - Initialize a device for use with IO space
1412 * @dev: PCI device to be initialized
1414 * Initialize device before it's used by a driver. Ask low-level code
1415 * to enable I/O resources. Wake up the device if it was suspended.
1416 * Beware, this function can fail.
1418 int pci_enable_device_io(struct pci_dev *dev)
1420 return pci_enable_device_flags(dev, IORESOURCE_IO);
1422 EXPORT_SYMBOL(pci_enable_device_io);
1425 * pci_enable_device_mem - Initialize a device for use with Memory space
1426 * @dev: PCI device to be initialized
1428 * Initialize device before it's used by a driver. Ask low-level code
1429 * to enable Memory resources. Wake up the device if it was suspended.
1430 * Beware, this function can fail.
1432 int pci_enable_device_mem(struct pci_dev *dev)
1434 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1436 EXPORT_SYMBOL(pci_enable_device_mem);
1439 * pci_enable_device - Initialize device before it's used by a driver.
1440 * @dev: PCI device to be initialized
1442 * Initialize device before it's used by a driver. Ask low-level code
1443 * to enable I/O and memory. Wake up the device if it was suspended.
1444 * Beware, this function can fail.
1446 * Note we don't actually enable the device many times if we call
1447 * this function repeatedly (we just increment the count).
1449 int pci_enable_device(struct pci_dev *dev)
1451 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1453 EXPORT_SYMBOL(pci_enable_device);
1456 * Managed PCI resources. This manages device on/off, intx/msi/msix
1457 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1458 * there's no need to track it separately. pci_devres is initialized
1459 * when a device is enabled using managed PCI device enable interface.
1462 unsigned int enabled:1;
1463 unsigned int pinned:1;
1464 unsigned int orig_intx:1;
1465 unsigned int restore_intx:1;
1470 static void pcim_release(struct device *gendev, void *res)
1472 struct pci_dev *dev = to_pci_dev(gendev);
1473 struct pci_devres *this = res;
1476 if (dev->msi_enabled)
1477 pci_disable_msi(dev);
1478 if (dev->msix_enabled)
1479 pci_disable_msix(dev);
1481 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1482 if (this->region_mask & (1 << i))
1483 pci_release_region(dev, i);
1488 if (this->restore_intx)
1489 pci_intx(dev, this->orig_intx);
1491 if (this->enabled && !this->pinned)
1492 pci_disable_device(dev);
1495 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1497 struct pci_devres *dr, *new_dr;
1499 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1503 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1506 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1509 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1511 if (pci_is_managed(pdev))
1512 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1517 * pcim_enable_device - Managed pci_enable_device()
1518 * @pdev: PCI device to be initialized
1520 * Managed pci_enable_device().
1522 int pcim_enable_device(struct pci_dev *pdev)
1524 struct pci_devres *dr;
1527 dr = get_pci_dr(pdev);
1533 rc = pci_enable_device(pdev);
1535 pdev->is_managed = 1;
1540 EXPORT_SYMBOL(pcim_enable_device);
1543 * pcim_pin_device - Pin managed PCI device
1544 * @pdev: PCI device to pin
1546 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1547 * driver detach. @pdev must have been enabled with
1548 * pcim_enable_device().
1550 void pcim_pin_device(struct pci_dev *pdev)
1552 struct pci_devres *dr;
1554 dr = find_pci_dr(pdev);
1555 WARN_ON(!dr || !dr->enabled);
1559 EXPORT_SYMBOL(pcim_pin_device);
1562 * pcibios_add_device - provide arch specific hooks when adding device dev
1563 * @dev: the PCI device being added
1565 * Permits the platform to provide architecture specific functionality when
1566 * devices are added. This is the default implementation. Architecture
1567 * implementations can override this.
1569 int __weak pcibios_add_device(struct pci_dev *dev)
1575 * pcibios_release_device - provide arch specific hooks when releasing device dev
1576 * @dev: the PCI device being released
1578 * Permits the platform to provide architecture specific functionality when
1579 * devices are released. This is the default implementation. Architecture
1580 * implementations can override this.
1582 void __weak pcibios_release_device(struct pci_dev *dev) {}
1585 * pcibios_disable_device - disable arch specific PCI resources for device dev
1586 * @dev: the PCI device to disable
1588 * Disables architecture specific PCI resources for the device. This
1589 * is the default implementation. Architecture implementations can
1592 void __weak pcibios_disable_device(struct pci_dev *dev) {}
1595 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1596 * @irq: ISA IRQ to penalize
1597 * @active: IRQ active or not
1599 * Permits the platform to provide architecture-specific functionality when
1600 * penalizing ISA IRQs. This is the default implementation. Architecture
1601 * implementations can override this.
1603 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1605 static void do_pci_disable_device(struct pci_dev *dev)
1609 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1610 if (pci_command & PCI_COMMAND_MASTER) {
1611 pci_command &= ~PCI_COMMAND_MASTER;
1612 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1615 pcibios_disable_device(dev);
1619 * pci_disable_enabled_device - Disable device without updating enable_cnt
1620 * @dev: PCI device to disable
1622 * NOTE: This function is a backend of PCI power management routines and is
1623 * not supposed to be called drivers.
1625 void pci_disable_enabled_device(struct pci_dev *dev)
1627 if (pci_is_enabled(dev))
1628 do_pci_disable_device(dev);
1632 * pci_disable_device - Disable PCI device after use
1633 * @dev: PCI device to be disabled
1635 * Signal to the system that the PCI device is not in use by the system
1636 * anymore. This only involves disabling PCI bus-mastering, if active.
1638 * Note we don't actually disable the device until all callers of
1639 * pci_enable_device() have called pci_disable_device().
1641 void pci_disable_device(struct pci_dev *dev)
1643 struct pci_devres *dr;
1645 dr = find_pci_dr(dev);
1649 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1650 "disabling already-disabled device");
1652 if (atomic_dec_return(&dev->enable_cnt) != 0)
1655 do_pci_disable_device(dev);
1657 dev->is_busmaster = 0;
1659 EXPORT_SYMBOL(pci_disable_device);
1662 * pcibios_set_pcie_reset_state - set reset state for device dev
1663 * @dev: the PCIe device reset
1664 * @state: Reset state to enter into
1667 * Sets the PCIe reset state for the device. This is the default
1668 * implementation. Architecture implementations can override this.
1670 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1671 enum pcie_reset_state state)
1677 * pci_set_pcie_reset_state - set reset state for device dev
1678 * @dev: the PCIe device reset
1679 * @state: Reset state to enter into
1682 * Sets the PCI reset state for the device.
1684 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1686 return pcibios_set_pcie_reset_state(dev, state);
1688 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1691 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
1692 * @dev: PCIe root port or event collector.
1694 void pcie_clear_root_pme_status(struct pci_dev *dev)
1696 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
1700 * pci_check_pme_status - Check if given device has generated PME.
1701 * @dev: Device to check.
1703 * Check the PME status of the device and if set, clear it and clear PME enable
1704 * (if set). Return 'true' if PME status and PME enable were both set or
1705 * 'false' otherwise.
1707 bool pci_check_pme_status(struct pci_dev *dev)
1716 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1717 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1718 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1721 /* Clear PME status. */
1722 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1723 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1724 /* Disable PME to avoid interrupt flood. */
1725 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1729 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1735 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1736 * @dev: Device to handle.
1737 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1739 * Check if @dev has generated PME and queue a resume request for it in that
1742 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1744 if (pme_poll_reset && dev->pme_poll)
1745 dev->pme_poll = false;
1747 if (pci_check_pme_status(dev)) {
1748 pci_wakeup_event(dev);
1749 pm_request_resume(&dev->dev);
1755 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1756 * @bus: Top bus of the subtree to walk.
1758 void pci_pme_wakeup_bus(struct pci_bus *bus)
1761 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1766 * pci_pme_capable - check the capability of PCI device to generate PME#
1767 * @dev: PCI device to handle.
1768 * @state: PCI state from which device will issue PME#.
1770 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1775 return !!(dev->pme_support & (1 << state));
1777 EXPORT_SYMBOL(pci_pme_capable);
1779 static void pci_pme_list_scan(struct work_struct *work)
1781 struct pci_pme_device *pme_dev, *n;
1783 mutex_lock(&pci_pme_list_mutex);
1784 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1785 if (pme_dev->dev->pme_poll) {
1786 struct pci_dev *bridge;
1788 bridge = pme_dev->dev->bus->self;
1790 * If bridge is in low power state, the
1791 * configuration space of subordinate devices
1792 * may be not accessible
1794 if (bridge && bridge->current_state != PCI_D0)
1796 pci_pme_wakeup(pme_dev->dev, NULL);
1798 list_del(&pme_dev->list);
1802 if (!list_empty(&pci_pme_list))
1803 queue_delayed_work(system_freezable_wq, &pci_pme_work,
1804 msecs_to_jiffies(PME_TIMEOUT));
1805 mutex_unlock(&pci_pme_list_mutex);
1808 static void __pci_pme_active(struct pci_dev *dev, bool enable)
1812 if (!dev->pme_support)
1815 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1816 /* Clear PME_Status by writing 1 to it and enable PME# */
1817 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1819 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1821 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1825 * pci_pme_restore - Restore PME configuration after config space restore.
1826 * @dev: PCI device to update.
1828 void pci_pme_restore(struct pci_dev *dev)
1832 if (!dev->pme_support)
1835 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1836 if (dev->wakeup_prepared) {
1837 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
1838 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
1840 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1841 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1843 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1847 * pci_pme_active - enable or disable PCI device's PME# function
1848 * @dev: PCI device to handle.
1849 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1851 * The caller must verify that the device is capable of generating PME# before
1852 * calling this function with @enable equal to 'true'.
1854 void pci_pme_active(struct pci_dev *dev, bool enable)
1856 __pci_pme_active(dev, enable);
1859 * PCI (as opposed to PCIe) PME requires that the device have
1860 * its PME# line hooked up correctly. Not all hardware vendors
1861 * do this, so the PME never gets delivered and the device
1862 * remains asleep. The easiest way around this is to
1863 * periodically walk the list of suspended devices and check
1864 * whether any have their PME flag set. The assumption is that
1865 * we'll wake up often enough anyway that this won't be a huge
1866 * hit, and the power savings from the devices will still be a
1869 * Although PCIe uses in-band PME message instead of PME# line
1870 * to report PME, PME does not work for some PCIe devices in
1871 * reality. For example, there are devices that set their PME
1872 * status bits, but don't really bother to send a PME message;
1873 * there are PCI Express Root Ports that don't bother to
1874 * trigger interrupts when they receive PME messages from the
1875 * devices below. So PME poll is used for PCIe devices too.
1878 if (dev->pme_poll) {
1879 struct pci_pme_device *pme_dev;
1881 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1884 pci_warn(dev, "can't enable PME#\n");
1888 mutex_lock(&pci_pme_list_mutex);
1889 list_add(&pme_dev->list, &pci_pme_list);
1890 if (list_is_singular(&pci_pme_list))
1891 queue_delayed_work(system_freezable_wq,
1893 msecs_to_jiffies(PME_TIMEOUT));
1894 mutex_unlock(&pci_pme_list_mutex);
1896 mutex_lock(&pci_pme_list_mutex);
1897 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1898 if (pme_dev->dev == dev) {
1899 list_del(&pme_dev->list);
1904 mutex_unlock(&pci_pme_list_mutex);
1908 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
1910 EXPORT_SYMBOL(pci_pme_active);
1913 * pci_enable_wake - enable PCI device as wakeup event source
1914 * @dev: PCI device affected
1915 * @state: PCI state from which device will issue wakeup events
1916 * @enable: True to enable event generation; false to disable
1918 * This enables the device as a wakeup event source, or disables it.
1919 * When such events involves platform-specific hooks, those hooks are
1920 * called automatically by this routine.
1922 * Devices with legacy power management (no standard PCI PM capabilities)
1923 * always require such platform hooks.
1926 * 0 is returned on success
1927 * -EINVAL is returned if device is not supposed to wake up the system
1928 * Error code depending on the platform is returned if both the platform and
1929 * the native mechanism fail to enable the generation of wake-up events
1931 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
1936 * Bridges can only signal wakeup on behalf of subordinate devices,
1937 * but that is set up elsewhere, so skip them.
1939 if (pci_has_subordinate(dev))
1942 /* Don't do the same thing twice in a row for one device. */
1943 if (!!enable == !!dev->wakeup_prepared)
1947 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1948 * Anderson we should be doing PME# wake enable followed by ACPI wake
1949 * enable. To disable wake-up we call the platform first, for symmetry.
1955 if (pci_pme_capable(dev, state))
1956 pci_pme_active(dev, true);
1959 error = platform_pci_set_wakeup(dev, true);
1963 dev->wakeup_prepared = true;
1965 platform_pci_set_wakeup(dev, false);
1966 pci_pme_active(dev, false);
1967 dev->wakeup_prepared = false;
1972 EXPORT_SYMBOL(pci_enable_wake);
1975 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1976 * @dev: PCI device to prepare
1977 * @enable: True to enable wake-up event generation; false to disable
1979 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1980 * and this function allows them to set that up cleanly - pci_enable_wake()
1981 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1982 * ordering constraints.
1984 * This function only returns error code if the device is not capable of
1985 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1986 * enable wake-up power for it.
1988 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1990 return pci_pme_capable(dev, PCI_D3cold) ?
1991 pci_enable_wake(dev, PCI_D3cold, enable) :
1992 pci_enable_wake(dev, PCI_D3hot, enable);
1994 EXPORT_SYMBOL(pci_wake_from_d3);
1997 * pci_target_state - find an appropriate low power state for a given PCI dev
1999 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2001 * Use underlying platform code to find a supported low power state for @dev.
2002 * If the platform can't manage @dev, return the deepest state from which it
2003 * can generate wake events, based on any available PME info.
2005 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2007 pci_power_t target_state = PCI_D3hot;
2009 if (platform_pci_power_manageable(dev)) {
2011 * Call the platform to choose the target state of the device
2012 * and enable wake-up from this state if supported.
2014 pci_power_t state = platform_pci_choose_state(dev);
2017 case PCI_POWER_ERROR:
2022 if (pci_no_d1d2(dev))
2025 target_state = state;
2028 return target_state;
2032 target_state = PCI_D0;
2035 * If the device is in D3cold even though it's not power-manageable by
2036 * the platform, it may have been powered down by non-standard means.
2037 * Best to let it slumber.
2039 if (dev->current_state == PCI_D3cold)
2040 target_state = PCI_D3cold;
2044 * Find the deepest state from which the device can generate
2045 * wake-up events, make it the target state and enable device
2048 if (dev->pme_support) {
2050 && !(dev->pme_support & (1 << target_state)))
2055 return target_state;
2059 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2060 * @dev: Device to handle.
2062 * Choose the power state appropriate for the device depending on whether
2063 * it can wake up the system and/or is power manageable by the platform
2064 * (PCI_D3hot is the default) and put the device into that state.
2066 int pci_prepare_to_sleep(struct pci_dev *dev)
2068 bool wakeup = device_may_wakeup(&dev->dev);
2069 pci_power_t target_state = pci_target_state(dev, wakeup);
2072 if (target_state == PCI_POWER_ERROR)
2075 pci_enable_wake(dev, target_state, wakeup);
2077 error = pci_set_power_state(dev, target_state);
2080 pci_enable_wake(dev, target_state, false);
2084 EXPORT_SYMBOL(pci_prepare_to_sleep);
2087 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2088 * @dev: Device to handle.
2090 * Disable device's system wake-up capability and put it into D0.
2092 int pci_back_from_sleep(struct pci_dev *dev)
2094 pci_enable_wake(dev, PCI_D0, false);
2095 return pci_set_power_state(dev, PCI_D0);
2097 EXPORT_SYMBOL(pci_back_from_sleep);
2100 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2101 * @dev: PCI device being suspended.
2103 * Prepare @dev to generate wake-up events at run time and put it into a low
2106 int pci_finish_runtime_suspend(struct pci_dev *dev)
2108 pci_power_t target_state;
2111 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2112 if (target_state == PCI_POWER_ERROR)
2115 dev->runtime_d3cold = target_state == PCI_D3cold;
2117 pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2119 error = pci_set_power_state(dev, target_state);
2122 pci_enable_wake(dev, target_state, false);
2123 dev->runtime_d3cold = false;
2130 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2131 * @dev: Device to check.
2133 * Return true if the device itself is capable of generating wake-up events
2134 * (through the platform or using the native PCIe PME) or if the device supports
2135 * PME and one of its upstream bridges can generate wake-up events.
2137 bool pci_dev_run_wake(struct pci_dev *dev)
2139 struct pci_bus *bus = dev->bus;
2141 if (device_can_wakeup(&dev->dev))
2144 if (!dev->pme_support)
2147 /* PME-capable in principle, but not from the target power state */
2148 if (!pci_pme_capable(dev, pci_target_state(dev, false)))
2151 while (bus->parent) {
2152 struct pci_dev *bridge = bus->self;
2154 if (device_can_wakeup(&bridge->dev))
2160 /* We have reached the root bus. */
2162 return device_can_wakeup(bus->bridge);
2166 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2169 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2170 * @pci_dev: Device to check.
2172 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2173 * reconfigured due to wakeup settings difference between system and runtime
2174 * suspend and the current power state of it is suitable for the upcoming
2175 * (system) transition.
2177 * If the device is not configured for system wakeup, disable PME for it before
2178 * returning 'true' to prevent it from waking up the system unnecessarily.
2180 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2182 struct device *dev = &pci_dev->dev;
2183 bool wakeup = device_may_wakeup(dev);
2185 if (!pm_runtime_suspended(dev)
2186 || pci_target_state(pci_dev, wakeup) != pci_dev->current_state
2187 || platform_pci_need_resume(pci_dev))
2191 * At this point the device is good to go unless it's been configured
2192 * to generate PME at the runtime suspend time, but it is not supposed
2193 * to wake up the system. In that case, simply disable PME for it
2194 * (it will have to be re-enabled on exit from system resume).
2196 * If the device's power state is D3cold and the platform check above
2197 * hasn't triggered, the device's configuration is suitable and we don't
2198 * need to manipulate it at all.
2200 spin_lock_irq(&dev->power.lock);
2202 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2204 __pci_pme_active(pci_dev, false);
2206 spin_unlock_irq(&dev->power.lock);
2211 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2212 * @pci_dev: Device to handle.
2214 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2215 * it might have been disabled during the prepare phase of system suspend if
2216 * the device was not configured for system wakeup.
2218 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2220 struct device *dev = &pci_dev->dev;
2222 if (!pci_dev_run_wake(pci_dev))
2225 spin_lock_irq(&dev->power.lock);
2227 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2228 __pci_pme_active(pci_dev, true);
2230 spin_unlock_irq(&dev->power.lock);
2233 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2235 struct device *dev = &pdev->dev;
2236 struct device *parent = dev->parent;
2239 pm_runtime_get_sync(parent);
2240 pm_runtime_get_noresume(dev);
2242 * pdev->current_state is set to PCI_D3cold during suspending,
2243 * so wait until suspending completes
2245 pm_runtime_barrier(dev);
2247 * Only need to resume devices in D3cold, because config
2248 * registers are still accessible for devices suspended but
2251 if (pdev->current_state == PCI_D3cold)
2252 pm_runtime_resume(dev);
2255 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2257 struct device *dev = &pdev->dev;
2258 struct device *parent = dev->parent;
2260 pm_runtime_put(dev);
2262 pm_runtime_put_sync(parent);
2266 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2267 * @bridge: Bridge to check
2269 * This function checks if it is possible to move the bridge to D3.
2270 * Currently we only allow D3 for recent enough PCIe ports.
2272 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2276 if (!pci_is_pcie(bridge))
2279 switch (pci_pcie_type(bridge)) {
2280 case PCI_EXP_TYPE_ROOT_PORT:
2281 case PCI_EXP_TYPE_UPSTREAM:
2282 case PCI_EXP_TYPE_DOWNSTREAM:
2283 if (pci_bridge_d3_disable)
2287 * Hotplug interrupts cannot be delivered if the link is down,
2288 * so parents of a hotplug port must stay awake. In addition,
2289 * hotplug ports handled by firmware in System Management Mode
2290 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2291 * For simplicity, disallow in general for now.
2293 if (bridge->is_hotplug_bridge)
2296 if (pci_bridge_d3_force)
2300 * It should be safe to put PCIe ports from 2015 or newer
2303 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
2313 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2315 bool *d3cold_ok = data;
2317 if (/* The device needs to be allowed to go D3cold ... */
2318 dev->no_d3cold || !dev->d3cold_allowed ||
2320 /* ... and if it is wakeup capable to do so from D3cold. */
2321 (device_may_wakeup(&dev->dev) &&
2322 !pci_pme_capable(dev, PCI_D3cold)) ||
2324 /* If it is a bridge it must be allowed to go to D3. */
2325 !pci_power_manageable(dev))
2333 * pci_bridge_d3_update - Update bridge D3 capabilities
2334 * @dev: PCI device which is changed
2336 * Update upstream bridge PM capabilities accordingly depending on if the
2337 * device PM configuration was changed or the device is being removed. The
2338 * change is also propagated upstream.
2340 void pci_bridge_d3_update(struct pci_dev *dev)
2342 bool remove = !device_is_registered(&dev->dev);
2343 struct pci_dev *bridge;
2344 bool d3cold_ok = true;
2346 bridge = pci_upstream_bridge(dev);
2347 if (!bridge || !pci_bridge_d3_possible(bridge))
2351 * If D3 is currently allowed for the bridge, removing one of its
2352 * children won't change that.
2354 if (remove && bridge->bridge_d3)
2358 * If D3 is currently allowed for the bridge and a child is added or
2359 * changed, disallowance of D3 can only be caused by that child, so
2360 * we only need to check that single device, not any of its siblings.
2362 * If D3 is currently not allowed for the bridge, checking the device
2363 * first may allow us to skip checking its siblings.
2366 pci_dev_check_d3cold(dev, &d3cold_ok);
2369 * If D3 is currently not allowed for the bridge, this may be caused
2370 * either by the device being changed/removed or any of its siblings,
2371 * so we need to go through all children to find out if one of them
2372 * continues to block D3.
2374 if (d3cold_ok && !bridge->bridge_d3)
2375 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2378 if (bridge->bridge_d3 != d3cold_ok) {
2379 bridge->bridge_d3 = d3cold_ok;
2380 /* Propagate change to upstream bridges */
2381 pci_bridge_d3_update(bridge);
2386 * pci_d3cold_enable - Enable D3cold for device
2387 * @dev: PCI device to handle
2389 * This function can be used in drivers to enable D3cold from the device
2390 * they handle. It also updates upstream PCI bridge PM capabilities
2393 void pci_d3cold_enable(struct pci_dev *dev)
2395 if (dev->no_d3cold) {
2396 dev->no_d3cold = false;
2397 pci_bridge_d3_update(dev);
2400 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2403 * pci_d3cold_disable - Disable D3cold for device
2404 * @dev: PCI device to handle
2406 * This function can be used in drivers to disable D3cold from the device
2407 * they handle. It also updates upstream PCI bridge PM capabilities
2410 void pci_d3cold_disable(struct pci_dev *dev)
2412 if (!dev->no_d3cold) {
2413 dev->no_d3cold = true;
2414 pci_bridge_d3_update(dev);
2417 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2420 * pci_pm_init - Initialize PM functions of given PCI device
2421 * @dev: PCI device to handle.
2423 void pci_pm_init(struct pci_dev *dev)
2428 pm_runtime_forbid(&dev->dev);
2429 pm_runtime_set_active(&dev->dev);
2430 pm_runtime_enable(&dev->dev);
2431 device_enable_async_suspend(&dev->dev);
2432 dev->wakeup_prepared = false;
2435 dev->pme_support = 0;
2437 /* find PCI PM capability in list */
2438 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2441 /* Check device's ability to generate PME# */
2442 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2444 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2445 pci_err(dev, "unsupported PM cap regs version (%u)\n",
2446 pmc & PCI_PM_CAP_VER_MASK);
2451 dev->d3_delay = PCI_PM_D3_WAIT;
2452 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2453 dev->bridge_d3 = pci_bridge_d3_possible(dev);
2454 dev->d3cold_allowed = true;
2456 dev->d1_support = false;
2457 dev->d2_support = false;
2458 if (!pci_no_d1d2(dev)) {
2459 if (pmc & PCI_PM_CAP_D1)
2460 dev->d1_support = true;
2461 if (pmc & PCI_PM_CAP_D2)
2462 dev->d2_support = true;
2464 if (dev->d1_support || dev->d2_support)
2465 pci_printk(KERN_DEBUG, dev, "supports%s%s\n",
2466 dev->d1_support ? " D1" : "",
2467 dev->d2_support ? " D2" : "");
2470 pmc &= PCI_PM_CAP_PME_MASK;
2472 pci_printk(KERN_DEBUG, dev, "PME# supported from%s%s%s%s%s\n",
2473 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2474 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2475 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2476 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2477 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2478 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2479 dev->pme_poll = true;
2481 * Make device's PM flags reflect the wake-up capability, but
2482 * let the user space enable it to wake up the system as needed.
2484 device_set_wakeup_capable(&dev->dev, true);
2485 /* Disable the PME# generation functionality */
2486 pci_pme_active(dev, false);
2490 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2492 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
2496 case PCI_EA_P_VF_MEM:
2497 flags |= IORESOURCE_MEM;
2499 case PCI_EA_P_MEM_PREFETCH:
2500 case PCI_EA_P_VF_MEM_PREFETCH:
2501 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2504 flags |= IORESOURCE_IO;
2513 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2516 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2517 return &dev->resource[bei];
2518 #ifdef CONFIG_PCI_IOV
2519 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2520 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2521 return &dev->resource[PCI_IOV_RESOURCES +
2522 bei - PCI_EA_BEI_VF_BAR0];
2524 else if (bei == PCI_EA_BEI_ROM)
2525 return &dev->resource[PCI_ROM_RESOURCE];
2530 /* Read an Enhanced Allocation (EA) entry */
2531 static int pci_ea_read(struct pci_dev *dev, int offset)
2533 struct resource *res;
2534 int ent_size, ent_offset = offset;
2535 resource_size_t start, end;
2536 unsigned long flags;
2537 u32 dw0, bei, base, max_offset;
2539 bool support_64 = (sizeof(resource_size_t) >= 8);
2541 pci_read_config_dword(dev, ent_offset, &dw0);
2544 /* Entry size field indicates DWORDs after 1st */
2545 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2547 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2550 bei = (dw0 & PCI_EA_BEI) >> 4;
2551 prop = (dw0 & PCI_EA_PP) >> 8;
2554 * If the Property is in the reserved range, try the Secondary
2557 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2558 prop = (dw0 & PCI_EA_SP) >> 16;
2559 if (prop > PCI_EA_P_BRIDGE_IO)
2562 res = pci_ea_get_resource(dev, bei, prop);
2564 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
2568 flags = pci_ea_flags(dev, prop);
2570 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
2575 pci_read_config_dword(dev, ent_offset, &base);
2576 start = (base & PCI_EA_FIELD_MASK);
2579 /* Read MaxOffset */
2580 pci_read_config_dword(dev, ent_offset, &max_offset);
2583 /* Read Base MSBs (if 64-bit entry) */
2584 if (base & PCI_EA_IS_64) {
2587 pci_read_config_dword(dev, ent_offset, &base_upper);
2590 flags |= IORESOURCE_MEM_64;
2592 /* entry starts above 32-bit boundary, can't use */
2593 if (!support_64 && base_upper)
2597 start |= ((u64)base_upper << 32);
2600 end = start + (max_offset | 0x03);
2602 /* Read MaxOffset MSBs (if 64-bit entry) */
2603 if (max_offset & PCI_EA_IS_64) {
2604 u32 max_offset_upper;
2606 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2609 flags |= IORESOURCE_MEM_64;
2611 /* entry too big, can't use */
2612 if (!support_64 && max_offset_upper)
2616 end += ((u64)max_offset_upper << 32);
2620 pci_err(dev, "EA Entry crosses address boundary\n");
2624 if (ent_size != ent_offset - offset) {
2625 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
2626 ent_size, ent_offset - offset);
2630 res->name = pci_name(dev);
2635 if (bei <= PCI_EA_BEI_BAR5)
2636 pci_printk(KERN_DEBUG, dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2638 else if (bei == PCI_EA_BEI_ROM)
2639 pci_printk(KERN_DEBUG, dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2641 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2642 pci_printk(KERN_DEBUG, dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2643 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2645 pci_printk(KERN_DEBUG, dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2649 return offset + ent_size;
2652 /* Enhanced Allocation Initialization */
2653 void pci_ea_init(struct pci_dev *dev)
2660 /* find PCI EA capability in list */
2661 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2665 /* determine the number of entries */
2666 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2668 num_ent &= PCI_EA_NUM_ENT_MASK;
2670 offset = ea + PCI_EA_FIRST_ENT;
2672 /* Skip DWORD 2 for type 1 functions */
2673 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2676 /* parse each EA entry */
2677 for (i = 0; i < num_ent; ++i)
2678 offset = pci_ea_read(dev, offset);
2681 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2682 struct pci_cap_saved_state *new_cap)
2684 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2688 * _pci_add_cap_save_buffer - allocate buffer for saving given
2689 * capability registers
2690 * @dev: the PCI device
2691 * @cap: the capability to allocate the buffer for
2692 * @extended: Standard or Extended capability ID
2693 * @size: requested size of the buffer
2695 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2696 bool extended, unsigned int size)
2699 struct pci_cap_saved_state *save_state;
2702 pos = pci_find_ext_capability(dev, cap);
2704 pos = pci_find_capability(dev, cap);
2709 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2713 save_state->cap.cap_nr = cap;
2714 save_state->cap.cap_extended = extended;
2715 save_state->cap.size = size;
2716 pci_add_saved_cap(dev, save_state);
2721 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2723 return _pci_add_cap_save_buffer(dev, cap, false, size);
2726 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2728 return _pci_add_cap_save_buffer(dev, cap, true, size);
2732 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2733 * @dev: the PCI device
2735 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2739 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2740 PCI_EXP_SAVE_REGS * sizeof(u16));
2742 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
2744 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2746 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
2748 pci_allocate_vc_save_buffers(dev);
2751 void pci_free_cap_save_buffers(struct pci_dev *dev)
2753 struct pci_cap_saved_state *tmp;
2754 struct hlist_node *n;
2756 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2761 * pci_configure_ari - enable or disable ARI forwarding
2762 * @dev: the PCI device
2764 * If @dev and its upstream bridge both support ARI, enable ARI in the
2765 * bridge. Otherwise, disable ARI in the bridge.
2767 void pci_configure_ari(struct pci_dev *dev)
2770 struct pci_dev *bridge;
2772 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2775 bridge = dev->bus->self;
2779 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2780 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2783 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2784 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2785 PCI_EXP_DEVCTL2_ARI);
2786 bridge->ari_enabled = 1;
2788 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2789 PCI_EXP_DEVCTL2_ARI);
2790 bridge->ari_enabled = 0;
2794 static int pci_acs_enable;
2797 * pci_request_acs - ask for ACS to be enabled if supported
2799 void pci_request_acs(void)
2805 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2806 * @dev: the PCI device
2808 static void pci_std_enable_acs(struct pci_dev *dev)
2814 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2818 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2819 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2821 /* Source Validation */
2822 ctrl |= (cap & PCI_ACS_SV);
2824 /* P2P Request Redirect */
2825 ctrl |= (cap & PCI_ACS_RR);
2827 /* P2P Completion Redirect */
2828 ctrl |= (cap & PCI_ACS_CR);
2830 /* Upstream Forwarding */
2831 ctrl |= (cap & PCI_ACS_UF);
2833 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2837 * pci_enable_acs - enable ACS if hardware support it
2838 * @dev: the PCI device
2840 void pci_enable_acs(struct pci_dev *dev)
2842 if (!pci_acs_enable)
2845 if (!pci_dev_specific_enable_acs(dev))
2848 pci_std_enable_acs(dev);
2851 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2856 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2861 * Except for egress control, capabilities are either required
2862 * or only required if controllable. Features missing from the
2863 * capability field can therefore be assumed as hard-wired enabled.
2865 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2866 acs_flags &= (cap | PCI_ACS_EC);
2868 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2869 return (ctrl & acs_flags) == acs_flags;
2873 * pci_acs_enabled - test ACS against required flags for a given device
2874 * @pdev: device to test
2875 * @acs_flags: required PCI ACS flags
2877 * Return true if the device supports the provided flags. Automatically
2878 * filters out flags that are not implemented on multifunction devices.
2880 * Note that this interface checks the effective ACS capabilities of the
2881 * device rather than the actual capabilities. For instance, most single
2882 * function endpoints are not required to support ACS because they have no
2883 * opportunity for peer-to-peer access. We therefore return 'true'
2884 * regardless of whether the device exposes an ACS capability. This makes
2885 * it much easier for callers of this function to ignore the actual type
2886 * or topology of the device when testing ACS support.
2888 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2892 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2897 * Conventional PCI and PCI-X devices never support ACS, either
2898 * effectively or actually. The shared bus topology implies that
2899 * any device on the bus can receive or snoop DMA.
2901 if (!pci_is_pcie(pdev))
2904 switch (pci_pcie_type(pdev)) {
2906 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2907 * but since their primary interface is PCI/X, we conservatively
2908 * handle them as we would a non-PCIe device.
2910 case PCI_EXP_TYPE_PCIE_BRIDGE:
2912 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2913 * applicable... must never implement an ACS Extended Capability...".
2914 * This seems arbitrary, but we take a conservative interpretation
2915 * of this statement.
2917 case PCI_EXP_TYPE_PCI_BRIDGE:
2918 case PCI_EXP_TYPE_RC_EC:
2921 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2922 * implement ACS in order to indicate their peer-to-peer capabilities,
2923 * regardless of whether they are single- or multi-function devices.
2925 case PCI_EXP_TYPE_DOWNSTREAM:
2926 case PCI_EXP_TYPE_ROOT_PORT:
2927 return pci_acs_flags_enabled(pdev, acs_flags);
2929 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2930 * implemented by the remaining PCIe types to indicate peer-to-peer
2931 * capabilities, but only when they are part of a multifunction
2932 * device. The footnote for section 6.12 indicates the specific
2933 * PCIe types included here.
2935 case PCI_EXP_TYPE_ENDPOINT:
2936 case PCI_EXP_TYPE_UPSTREAM:
2937 case PCI_EXP_TYPE_LEG_END:
2938 case PCI_EXP_TYPE_RC_END:
2939 if (!pdev->multifunction)
2942 return pci_acs_flags_enabled(pdev, acs_flags);
2946 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2947 * to single function devices with the exception of downstream ports.
2953 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2954 * @start: starting downstream device
2955 * @end: ending upstream device or NULL to search to the root bus
2956 * @acs_flags: required flags
2958 * Walk up a device tree from start to end testing PCI ACS support. If
2959 * any step along the way does not support the required flags, return false.
2961 bool pci_acs_path_enabled(struct pci_dev *start,
2962 struct pci_dev *end, u16 acs_flags)
2964 struct pci_dev *pdev, *parent = start;
2969 if (!pci_acs_enabled(pdev, acs_flags))
2972 if (pci_is_root_bus(pdev->bus))
2973 return (end == NULL);
2975 parent = pdev->bus->self;
2976 } while (pdev != end);
2982 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
2986 * Helper to find the position of the ctrl register for a BAR.
2987 * Returns -ENOTSUPP if resizable BARs are not supported at all.
2988 * Returns -ENOENT if no ctrl register for the BAR could be found.
2990 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
2992 unsigned int pos, nbars, i;
2995 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
2999 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3000 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3001 PCI_REBAR_CTRL_NBAR_SHIFT;
3003 for (i = 0; i < nbars; i++, pos += 8) {
3006 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3007 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3016 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3018 * @bar: BAR to query
3020 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3021 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3023 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3028 pos = pci_rebar_find_pos(pdev, bar);
3032 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3033 return (cap & PCI_REBAR_CAP_SIZES) >> 4;
3037 * pci_rebar_get_current_size - get the current size of a BAR
3039 * @bar: BAR to set size to
3041 * Read the size of a BAR from the resizable BAR config.
3042 * Returns size if found or negative error code.
3044 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3049 pos = pci_rebar_find_pos(pdev, bar);
3053 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3054 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> 8;
3058 * pci_rebar_set_size - set a new size for a BAR
3060 * @bar: BAR to set size to
3061 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3063 * Set the new size of a BAR as defined in the spec.
3064 * Returns zero if resizing was successful, error code otherwise.
3066 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3071 pos = pci_rebar_find_pos(pdev, bar);
3075 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3076 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3078 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3083 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3084 * @dev: the PCI device
3085 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3086 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3087 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3088 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3090 * Return 0 if all upstream bridges support AtomicOp routing, egress
3091 * blocking is disabled on all upstream ports, and the root port supports
3092 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3093 * AtomicOp completion), or negative otherwise.
3095 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3097 struct pci_bus *bus = dev->bus;
3098 struct pci_dev *bridge;
3101 if (!pci_is_pcie(dev))
3105 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3106 * AtomicOp requesters. For now, we only support endpoints as
3107 * requesters and root ports as completers. No endpoints as
3108 * completers, and no peer-to-peer.
3111 switch (pci_pcie_type(dev)) {
3112 case PCI_EXP_TYPE_ENDPOINT:
3113 case PCI_EXP_TYPE_LEG_END:
3114 case PCI_EXP_TYPE_RC_END:
3120 while (bus->parent) {
3123 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3125 switch (pci_pcie_type(bridge)) {
3126 /* Ensure switch ports support AtomicOp routing */
3127 case PCI_EXP_TYPE_UPSTREAM:
3128 case PCI_EXP_TYPE_DOWNSTREAM:
3129 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3133 /* Ensure root port supports all the sizes we care about */
3134 case PCI_EXP_TYPE_ROOT_PORT:
3135 if ((cap & cap_mask) != cap_mask)
3140 /* Ensure upstream ports don't block AtomicOps on egress */
3141 if (!bridge->has_secondary_link) {
3142 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3144 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3151 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3152 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3155 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3158 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3159 * @dev: the PCI device
3160 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3162 * Perform INTx swizzling for a device behind one level of bridge. This is
3163 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3164 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3165 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3166 * the PCI Express Base Specification, Revision 2.1)
3168 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3172 if (pci_ari_enabled(dev->bus))
3175 slot = PCI_SLOT(dev->devfn);
3177 return (((pin - 1) + slot) % 4) + 1;
3180 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3188 while (!pci_is_root_bus(dev->bus)) {
3189 pin = pci_swizzle_interrupt_pin(dev, pin);
3190 dev = dev->bus->self;
3197 * pci_common_swizzle - swizzle INTx all the way to root bridge
3198 * @dev: the PCI device
3199 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3201 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3202 * bridges all the way up to a PCI root bus.
3204 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3208 while (!pci_is_root_bus(dev->bus)) {
3209 pin = pci_swizzle_interrupt_pin(dev, pin);
3210 dev = dev->bus->self;
3213 return PCI_SLOT(dev->devfn);
3215 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3218 * pci_release_region - Release a PCI bar
3219 * @pdev: PCI device whose resources were previously reserved by pci_request_region
3220 * @bar: BAR to release
3222 * Releases the PCI I/O and memory resources previously reserved by a
3223 * successful call to pci_request_region. Call this function only
3224 * after all use of the PCI regions has ceased.
3226 void pci_release_region(struct pci_dev *pdev, int bar)
3228 struct pci_devres *dr;
3230 if (pci_resource_len(pdev, bar) == 0)
3232 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3233 release_region(pci_resource_start(pdev, bar),
3234 pci_resource_len(pdev, bar));
3235 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3236 release_mem_region(pci_resource_start(pdev, bar),
3237 pci_resource_len(pdev, bar));
3239 dr = find_pci_dr(pdev);
3241 dr->region_mask &= ~(1 << bar);
3243 EXPORT_SYMBOL(pci_release_region);
3246 * __pci_request_region - Reserved PCI I/O and memory resource
3247 * @pdev: PCI device whose resources are to be reserved
3248 * @bar: BAR to be reserved
3249 * @res_name: Name to be associated with resource.
3250 * @exclusive: whether the region access is exclusive or not
3252 * Mark the PCI region associated with PCI device @pdev BR @bar as
3253 * being reserved by owner @res_name. Do not access any
3254 * address inside the PCI regions unless this call returns
3257 * If @exclusive is set, then the region is marked so that userspace
3258 * is explicitly not allowed to map the resource via /dev/mem or
3259 * sysfs MMIO access.
3261 * Returns 0 on success, or %EBUSY on error. A warning
3262 * message is also printed on failure.
3264 static int __pci_request_region(struct pci_dev *pdev, int bar,
3265 const char *res_name, int exclusive)
3267 struct pci_devres *dr;
3269 if (pci_resource_len(pdev, bar) == 0)
3272 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3273 if (!request_region(pci_resource_start(pdev, bar),
3274 pci_resource_len(pdev, bar), res_name))
3276 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3277 if (!__request_mem_region(pci_resource_start(pdev, bar),
3278 pci_resource_len(pdev, bar), res_name,
3283 dr = find_pci_dr(pdev);
3285 dr->region_mask |= 1 << bar;
3290 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3291 &pdev->resource[bar]);
3296 * pci_request_region - Reserve PCI I/O and memory resource
3297 * @pdev: PCI device whose resources are to be reserved
3298 * @bar: BAR to be reserved
3299 * @res_name: Name to be associated with resource
3301 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3302 * being reserved by owner @res_name. Do not access any
3303 * address inside the PCI regions unless this call returns
3306 * Returns 0 on success, or %EBUSY on error. A warning
3307 * message is also printed on failure.
3309 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3311 return __pci_request_region(pdev, bar, res_name, 0);
3313 EXPORT_SYMBOL(pci_request_region);
3316 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3317 * @pdev: PCI device whose resources are to be reserved
3318 * @bar: BAR to be reserved
3319 * @res_name: Name to be associated with resource.
3321 * Mark the PCI region associated with PCI device @pdev BR @bar as
3322 * being reserved by owner @res_name. Do not access any
3323 * address inside the PCI regions unless this call returns
3326 * Returns 0 on success, or %EBUSY on error. A warning
3327 * message is also printed on failure.
3329 * The key difference that _exclusive makes it that userspace is
3330 * explicitly not allowed to map the resource via /dev/mem or
3333 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3334 const char *res_name)
3336 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3338 EXPORT_SYMBOL(pci_request_region_exclusive);
3341 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3342 * @pdev: PCI device whose resources were previously reserved
3343 * @bars: Bitmask of BARs to be released
3345 * Release selected PCI I/O and memory resources previously reserved.
3346 * Call this function only after all use of the PCI regions has ceased.
3348 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3352 for (i = 0; i < 6; i++)
3353 if (bars & (1 << i))
3354 pci_release_region(pdev, i);
3356 EXPORT_SYMBOL(pci_release_selected_regions);
3358 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3359 const char *res_name, int excl)
3363 for (i = 0; i < 6; i++)
3364 if (bars & (1 << i))
3365 if (__pci_request_region(pdev, i, res_name, excl))
3371 if (bars & (1 << i))
3372 pci_release_region(pdev, i);
3379 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3380 * @pdev: PCI device whose resources are to be reserved
3381 * @bars: Bitmask of BARs to be requested
3382 * @res_name: Name to be associated with resource
3384 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3385 const char *res_name)
3387 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3389 EXPORT_SYMBOL(pci_request_selected_regions);
3391 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3392 const char *res_name)
3394 return __pci_request_selected_regions(pdev, bars, res_name,
3395 IORESOURCE_EXCLUSIVE);
3397 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3400 * pci_release_regions - Release reserved PCI I/O and memory resources
3401 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3403 * Releases all PCI I/O and memory resources previously reserved by a
3404 * successful call to pci_request_regions. Call this function only
3405 * after all use of the PCI regions has ceased.
3408 void pci_release_regions(struct pci_dev *pdev)
3410 pci_release_selected_regions(pdev, (1 << 6) - 1);
3412 EXPORT_SYMBOL(pci_release_regions);
3415 * pci_request_regions - Reserved PCI I/O and memory resources
3416 * @pdev: PCI device whose resources are to be reserved
3417 * @res_name: Name to be associated with resource.
3419 * Mark all PCI regions associated with PCI device @pdev as
3420 * being reserved by owner @res_name. Do not access any
3421 * address inside the PCI regions unless this call returns
3424 * Returns 0 on success, or %EBUSY on error. A warning
3425 * message is also printed on failure.
3427 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3429 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3431 EXPORT_SYMBOL(pci_request_regions);
3434 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3435 * @pdev: PCI device whose resources are to be reserved
3436 * @res_name: Name to be associated with resource.
3438 * Mark all PCI regions associated with PCI device @pdev as
3439 * being reserved by owner @res_name. Do not access any
3440 * address inside the PCI regions unless this call returns
3443 * pci_request_regions_exclusive() will mark the region so that
3444 * /dev/mem and the sysfs MMIO access will not be allowed.
3446 * Returns 0 on success, or %EBUSY on error. A warning
3447 * message is also printed on failure.
3449 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3451 return pci_request_selected_regions_exclusive(pdev,
3452 ((1 << 6) - 1), res_name);
3454 EXPORT_SYMBOL(pci_request_regions_exclusive);
3457 * Record the PCI IO range (expressed as CPU physical address + size).
3458 * Return a negative value if an error has occured, zero otherwise
3460 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
3461 resource_size_t size)
3465 struct logic_pio_hwaddr *range;
3467 if (!size || addr + size < addr)
3470 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3474 range->fwnode = fwnode;
3476 range->hw_start = addr;
3477 range->flags = LOGIC_PIO_CPU_MMIO;
3479 ret = logic_pio_register_range(range);
3487 phys_addr_t pci_pio_to_address(unsigned long pio)
3489 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3492 if (pio >= MMIO_UPPER_LIMIT)
3495 address = logic_pio_to_hwaddr(pio);
3501 unsigned long __weak pci_address_to_pio(phys_addr_t address)
3504 return logic_pio_trans_cpuaddr(address);
3506 if (address > IO_SPACE_LIMIT)
3507 return (unsigned long)-1;
3509 return (unsigned long) address;
3514 * pci_remap_iospace - Remap the memory mapped I/O space
3515 * @res: Resource describing the I/O space
3516 * @phys_addr: physical address of range to be mapped
3518 * Remap the memory mapped I/O space described by the @res
3519 * and the CPU physical address @phys_addr into virtual address space.
3520 * Only architectures that have memory mapped IO functions defined
3521 * (and the PCI_IOBASE value defined) should call this function.
3523 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3525 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3526 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3528 if (!(res->flags & IORESOURCE_IO))
3531 if (res->end > IO_SPACE_LIMIT)
3534 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3535 pgprot_device(PAGE_KERNEL));
3537 /* this architecture does not have memory mapped I/O space,
3538 so this function should never be called */
3539 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3543 EXPORT_SYMBOL(pci_remap_iospace);
3546 * pci_unmap_iospace - Unmap the memory mapped I/O space
3547 * @res: resource to be unmapped
3549 * Unmap the CPU virtual address @res from virtual address space.
3550 * Only architectures that have memory mapped IO functions defined
3551 * (and the PCI_IOBASE value defined) should call this function.
3553 void pci_unmap_iospace(struct resource *res)
3555 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3556 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3558 unmap_kernel_range(vaddr, resource_size(res));
3561 EXPORT_SYMBOL(pci_unmap_iospace);
3564 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
3565 * @dev: Generic device to remap IO address for
3566 * @offset: Resource address to map
3567 * @size: Size of map
3569 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
3572 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
3573 resource_size_t offset,
3574 resource_size_t size)
3576 void __iomem **ptr, *addr;
3578 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
3582 addr = pci_remap_cfgspace(offset, size);
3585 devres_add(dev, ptr);
3591 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
3594 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
3595 * @dev: generic device to handle the resource for
3596 * @res: configuration space resource to be handled
3598 * Checks that a resource is a valid memory region, requests the memory
3599 * region and ioremaps with pci_remap_cfgspace() API that ensures the
3600 * proper PCI configuration space memory attributes are guaranteed.
3602 * All operations are managed and will be undone on driver detach.
3604 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
3605 * on failure. Usage example::
3607 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3608 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
3610 * return PTR_ERR(base);
3612 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
3613 struct resource *res)
3615 resource_size_t size;
3617 void __iomem *dest_ptr;
3621 if (!res || resource_type(res) != IORESOURCE_MEM) {
3622 dev_err(dev, "invalid resource\n");
3623 return IOMEM_ERR_PTR(-EINVAL);
3626 size = resource_size(res);
3627 name = res->name ?: dev_name(dev);
3629 if (!devm_request_mem_region(dev, res->start, size, name)) {
3630 dev_err(dev, "can't request region for resource %pR\n", res);
3631 return IOMEM_ERR_PTR(-EBUSY);
3634 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
3636 dev_err(dev, "ioremap failed for resource %pR\n", res);
3637 devm_release_mem_region(dev, res->start, size);
3638 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
3643 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
3645 static void __pci_set_master(struct pci_dev *dev, bool enable)
3649 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3651 cmd = old_cmd | PCI_COMMAND_MASTER;
3653 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3654 if (cmd != old_cmd) {
3655 pci_dbg(dev, "%s bus mastering\n",
3656 enable ? "enabling" : "disabling");
3657 pci_write_config_word(dev, PCI_COMMAND, cmd);
3659 dev->is_busmaster = enable;
3663 * pcibios_setup - process "pci=" kernel boot arguments
3664 * @str: string used to pass in "pci=" kernel boot arguments
3666 * Process kernel boot arguments. This is the default implementation.
3667 * Architecture specific implementations can override this as necessary.
3669 char * __weak __init pcibios_setup(char *str)
3675 * pcibios_set_master - enable PCI bus-mastering for device dev
3676 * @dev: the PCI device to enable
3678 * Enables PCI bus-mastering for the device. This is the default
3679 * implementation. Architecture specific implementations can override
3680 * this if necessary.
3682 void __weak pcibios_set_master(struct pci_dev *dev)
3686 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3687 if (pci_is_pcie(dev))
3690 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
3692 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
3693 else if (lat > pcibios_max_latency)
3694 lat = pcibios_max_latency;
3698 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
3702 * pci_set_master - enables bus-mastering for device dev
3703 * @dev: the PCI device to enable
3705 * Enables bus-mastering on the device and calls pcibios_set_master()
3706 * to do the needed arch specific settings.
3708 void pci_set_master(struct pci_dev *dev)
3710 __pci_set_master(dev, true);
3711 pcibios_set_master(dev);
3713 EXPORT_SYMBOL(pci_set_master);
3716 * pci_clear_master - disables bus-mastering for device dev
3717 * @dev: the PCI device to disable
3719 void pci_clear_master(struct pci_dev *dev)
3721 __pci_set_master(dev, false);
3723 EXPORT_SYMBOL(pci_clear_master);
3726 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3727 * @dev: the PCI device for which MWI is to be enabled
3729 * Helper function for pci_set_mwi.
3730 * Originally copied from drivers/net/acenic.c.
3731 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3733 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3735 int pci_set_cacheline_size(struct pci_dev *dev)
3739 if (!pci_cache_line_size)
3742 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3743 equal to or multiple of the right value. */
3744 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3745 if (cacheline_size >= pci_cache_line_size &&
3746 (cacheline_size % pci_cache_line_size) == 0)
3749 /* Write the correct value. */
3750 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
3752 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3753 if (cacheline_size == pci_cache_line_size)
3756 pci_printk(KERN_DEBUG, dev, "cache line size of %d is not supported\n",
3757 pci_cache_line_size << 2);
3761 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
3764 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3765 * @dev: the PCI device for which MWI is enabled
3767 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3769 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3771 int pci_set_mwi(struct pci_dev *dev)
3773 #ifdef PCI_DISABLE_MWI
3779 rc = pci_set_cacheline_size(dev);
3783 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3784 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
3785 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
3786 cmd |= PCI_COMMAND_INVALIDATE;
3787 pci_write_config_word(dev, PCI_COMMAND, cmd);
3792 EXPORT_SYMBOL(pci_set_mwi);
3795 * pcim_set_mwi - a device-managed pci_set_mwi()
3796 * @dev: the PCI device for which MWI is enabled
3798 * Managed pci_set_mwi().
3800 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3802 int pcim_set_mwi(struct pci_dev *dev)
3804 struct pci_devres *dr;
3806 dr = find_pci_dr(dev);
3811 return pci_set_mwi(dev);
3813 EXPORT_SYMBOL(pcim_set_mwi);
3816 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3817 * @dev: the PCI device for which MWI is enabled
3819 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3820 * Callers are not required to check the return value.
3822 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3824 int pci_try_set_mwi(struct pci_dev *dev)
3826 #ifdef PCI_DISABLE_MWI
3829 return pci_set_mwi(dev);
3832 EXPORT_SYMBOL(pci_try_set_mwi);
3835 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3836 * @dev: the PCI device to disable
3838 * Disables PCI Memory-Write-Invalidate transaction on the device
3840 void pci_clear_mwi(struct pci_dev *dev)
3842 #ifndef PCI_DISABLE_MWI
3845 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3846 if (cmd & PCI_COMMAND_INVALIDATE) {
3847 cmd &= ~PCI_COMMAND_INVALIDATE;
3848 pci_write_config_word(dev, PCI_COMMAND, cmd);
3852 EXPORT_SYMBOL(pci_clear_mwi);
3855 * pci_intx - enables/disables PCI INTx for device dev
3856 * @pdev: the PCI device to operate on
3857 * @enable: boolean: whether to enable or disable PCI INTx
3859 * Enables/disables PCI INTx for device dev
3861 void pci_intx(struct pci_dev *pdev, int enable)
3863 u16 pci_command, new;
3865 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3868 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3870 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3872 if (new != pci_command) {
3873 struct pci_devres *dr;
3875 pci_write_config_word(pdev, PCI_COMMAND, new);
3877 dr = find_pci_dr(pdev);
3878 if (dr && !dr->restore_intx) {
3879 dr->restore_intx = 1;
3880 dr->orig_intx = !enable;
3884 EXPORT_SYMBOL_GPL(pci_intx);
3886 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3888 struct pci_bus *bus = dev->bus;
3889 bool mask_updated = true;
3890 u32 cmd_status_dword;
3891 u16 origcmd, newcmd;
3892 unsigned long flags;
3896 * We do a single dword read to retrieve both command and status.
3897 * Document assumptions that make this possible.
3899 BUILD_BUG_ON(PCI_COMMAND % 4);
3900 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3902 raw_spin_lock_irqsave(&pci_lock, flags);
3904 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3906 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3909 * Check interrupt status register to see whether our device
3910 * triggered the interrupt (when masking) or the next IRQ is
3911 * already pending (when unmasking).
3913 if (mask != irq_pending) {
3914 mask_updated = false;
3918 origcmd = cmd_status_dword;
3919 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3921 newcmd |= PCI_COMMAND_INTX_DISABLE;
3922 if (newcmd != origcmd)
3923 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3926 raw_spin_unlock_irqrestore(&pci_lock, flags);
3928 return mask_updated;
3932 * pci_check_and_mask_intx - mask INTx on pending interrupt
3933 * @dev: the PCI device to operate on
3935 * Check if the device dev has its INTx line asserted, mask it and
3936 * return true in that case. False is returned if no interrupt was
3939 bool pci_check_and_mask_intx(struct pci_dev *dev)
3941 return pci_check_and_set_intx_mask(dev, true);
3943 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3946 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3947 * @dev: the PCI device to operate on
3949 * Check if the device dev has its INTx line asserted, unmask it if not
3950 * and return true. False is returned and the mask remains active if
3951 * there was still an interrupt pending.
3953 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3955 return pci_check_and_set_intx_mask(dev, false);
3957 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3960 * pci_wait_for_pending_transaction - waits for pending transaction
3961 * @dev: the PCI device to operate on
3963 * Return 0 if transaction is pending 1 otherwise.
3965 int pci_wait_for_pending_transaction(struct pci_dev *dev)
3967 if (!pci_is_pcie(dev))
3970 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
3971 PCI_EXP_DEVSTA_TRPND);
3973 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3975 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
3981 * After reset, the device should not silently discard config
3982 * requests, but it may still indicate that it needs more time by
3983 * responding to them with CRS completions. The Root Port will
3984 * generally synthesize ~0 data to complete the read (except when
3985 * CRS SV is enabled and the read was for the Vendor ID; in that
3986 * case it synthesizes 0x0001 data).
3988 * Wait for the device to return a non-CRS completion. Read the
3989 * Command register instead of Vendor ID so we don't have to
3990 * contend with the CRS SV value.
3992 pci_read_config_dword(dev, PCI_COMMAND, &id);
3994 if (delay > timeout) {
3995 pci_warn(dev, "not ready %dms after %s; giving up\n",
3996 delay - 1, reset_type);
4001 pci_info(dev, "not ready %dms after %s; waiting\n",
4002 delay - 1, reset_type);
4006 pci_read_config_dword(dev, PCI_COMMAND, &id);
4010 pci_info(dev, "ready %dms after %s\n", delay - 1,
4017 * pcie_has_flr - check if a device supports function level resets
4018 * @dev: device to check
4020 * Returns true if the device advertises support for PCIe function level
4023 static bool pcie_has_flr(struct pci_dev *dev)
4027 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4030 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
4031 return cap & PCI_EXP_DEVCAP_FLR;
4035 * pcie_flr - initiate a PCIe function level reset
4036 * @dev: device to reset
4038 * Initiate a function level reset on @dev. The caller should ensure the
4039 * device supports FLR before calling this function, e.g. by using the
4040 * pcie_has_flr() helper.
4042 int pcie_flr(struct pci_dev *dev)
4044 if (!pci_wait_for_pending_transaction(dev))
4045 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4047 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4050 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4051 * 100ms, but may silently discard requests while the FLR is in
4052 * progress. Wait 100ms before trying to access the device.
4056 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4058 EXPORT_SYMBOL_GPL(pcie_flr);
4060 static int pci_af_flr(struct pci_dev *dev, int probe)
4065 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4069 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4072 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4073 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4080 * Wait for Transaction Pending bit to clear. A word-aligned test
4081 * is used, so we use the conrol offset rather than status and shift
4082 * the test bit to match.
4084 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4085 PCI_AF_STATUS_TP << 8))
4086 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4088 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4091 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4092 * updated 27 July 2006; a device must complete an FLR within
4093 * 100ms, but may silently discard requests while the FLR is in
4094 * progress. Wait 100ms before trying to access the device.
4098 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4102 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4103 * @dev: Device to reset.
4104 * @probe: If set, only check if the device can be reset this way.
4106 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4107 * unset, it will be reinitialized internally when going from PCI_D3hot to
4108 * PCI_D0. If that's the case and the device is not in a low-power state
4109 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4111 * NOTE: This causes the caller to sleep for twice the device power transition
4112 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4113 * by default (i.e. unless the @dev's d3_delay field has a different value).
4114 * Moreover, only devices in D0 can be reset by this function.
4116 static int pci_pm_reset(struct pci_dev *dev, int probe)
4120 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4123 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4124 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4130 if (dev->current_state != PCI_D0)
4133 csr &= ~PCI_PM_CTRL_STATE_MASK;
4135 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4136 pci_dev_d3_sleep(dev);
4138 csr &= ~PCI_PM_CTRL_STATE_MASK;
4140 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4141 pci_dev_d3_sleep(dev);
4143 return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS);
4146 void pci_reset_secondary_bus(struct pci_dev *dev)
4150 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4151 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4152 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4155 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4156 * this to 2ms to ensure that we meet the minimum requirement.
4160 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
4161 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4164 * Trhfa for conventional PCI is 2^25 clock cycles.
4165 * Assuming a minimum 33MHz clock this results in a 1s
4166 * delay before we can consider subordinate devices to
4167 * be re-initialized. PCIe has some ways to shorten this,
4168 * but we don't make use of them yet.
4173 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4175 pci_reset_secondary_bus(dev);
4179 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
4180 * @dev: Bridge device
4182 * Use the bridge control register to assert reset on the secondary bus.
4183 * Devices on the secondary bus are left in power-on state.
4185 int pci_reset_bridge_secondary_bus(struct pci_dev *dev)
4187 pcibios_reset_secondary_bus(dev);
4189 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
4191 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
4193 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4195 struct pci_dev *pdev;
4197 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4198 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4201 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4208 pci_reset_bridge_secondary_bus(dev->bus->self);
4213 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
4217 if (!hotplug || !try_module_get(hotplug->ops->owner))
4220 if (hotplug->ops->reset_slot)
4221 rc = hotplug->ops->reset_slot(hotplug, probe);
4223 module_put(hotplug->ops->owner);
4228 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
4230 struct pci_dev *pdev;
4232 if (dev->subordinate || !dev->slot ||
4233 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4236 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4237 if (pdev != dev && pdev->slot == dev->slot)
4240 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
4243 static void pci_dev_lock(struct pci_dev *dev)
4245 pci_cfg_access_lock(dev);
4246 /* block PM suspend, driver probe, etc. */
4247 device_lock(&dev->dev);
4250 /* Return 1 on successful lock, 0 on contention */
4251 static int pci_dev_trylock(struct pci_dev *dev)
4253 if (pci_cfg_access_trylock(dev)) {
4254 if (device_trylock(&dev->dev))
4256 pci_cfg_access_unlock(dev);
4262 static void pci_dev_unlock(struct pci_dev *dev)
4264 device_unlock(&dev->dev);
4265 pci_cfg_access_unlock(dev);
4268 static void pci_dev_save_and_disable(struct pci_dev *dev)
4270 const struct pci_error_handlers *err_handler =
4271 dev->driver ? dev->driver->err_handler : NULL;
4274 * dev->driver->err_handler->reset_prepare() is protected against
4275 * races with ->remove() by the device lock, which must be held by
4278 if (err_handler && err_handler->reset_prepare)
4279 err_handler->reset_prepare(dev);
4282 * Wake-up device prior to save. PM registers default to D0 after
4283 * reset and a simple register restore doesn't reliably return
4284 * to a non-D0 state anyway.
4286 pci_set_power_state(dev, PCI_D0);
4288 pci_save_state(dev);
4290 * Disable the device by clearing the Command register, except for
4291 * INTx-disable which is set. This not only disables MMIO and I/O port
4292 * BARs, but also prevents the device from being Bus Master, preventing
4293 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4294 * compliant devices, INTx-disable prevents legacy interrupts.
4296 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4299 static void pci_dev_restore(struct pci_dev *dev)
4301 const struct pci_error_handlers *err_handler =
4302 dev->driver ? dev->driver->err_handler : NULL;
4304 pci_restore_state(dev);
4307 * dev->driver->err_handler->reset_done() is protected against
4308 * races with ->remove() by the device lock, which must be held by
4311 if (err_handler && err_handler->reset_done)
4312 err_handler->reset_done(dev);
4316 * __pci_reset_function_locked - reset a PCI device function while holding
4317 * the @dev mutex lock.
4318 * @dev: PCI device to reset
4320 * Some devices allow an individual function to be reset without affecting
4321 * other functions in the same device. The PCI device must be responsive
4322 * to PCI config space in order to use this function.
4324 * The device function is presumed to be unused and the caller is holding
4325 * the device mutex lock when this function is called.
4326 * Resetting the device will make the contents of PCI configuration space
4327 * random, so any caller of this must be prepared to reinitialise the
4328 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4331 * Returns 0 if the device function was successfully reset or negative if the
4332 * device doesn't support resetting a single function.
4334 int __pci_reset_function_locked(struct pci_dev *dev)
4341 * A reset method returns -ENOTTY if it doesn't support this device
4342 * and we should try the next method.
4344 * If it returns 0 (success), we're finished. If it returns any
4345 * other error, we're also finished: this indicates that further
4346 * reset mechanisms might be broken on the device.
4348 rc = pci_dev_specific_reset(dev, 0);
4351 if (pcie_has_flr(dev)) {
4356 rc = pci_af_flr(dev, 0);
4359 rc = pci_pm_reset(dev, 0);
4362 rc = pci_dev_reset_slot_function(dev, 0);
4365 return pci_parent_bus_reset(dev, 0);
4367 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4370 * pci_probe_reset_function - check whether the device can be safely reset
4371 * @dev: PCI device to reset
4373 * Some devices allow an individual function to be reset without affecting
4374 * other functions in the same device. The PCI device must be responsive
4375 * to PCI config space in order to use this function.
4377 * Returns 0 if the device function can be reset or negative if the
4378 * device doesn't support resetting a single function.
4380 int pci_probe_reset_function(struct pci_dev *dev)
4386 rc = pci_dev_specific_reset(dev, 1);
4389 if (pcie_has_flr(dev))
4391 rc = pci_af_flr(dev, 1);
4394 rc = pci_pm_reset(dev, 1);
4397 rc = pci_dev_reset_slot_function(dev, 1);
4401 return pci_parent_bus_reset(dev, 1);
4405 * pci_reset_function - quiesce and reset a PCI device function
4406 * @dev: PCI device to reset
4408 * Some devices allow an individual function to be reset without affecting
4409 * other functions in the same device. The PCI device must be responsive
4410 * to PCI config space in order to use this function.
4412 * This function does not just reset the PCI portion of a device, but
4413 * clears all the state associated with the device. This function differs
4414 * from __pci_reset_function_locked() in that it saves and restores device state
4415 * over the reset and takes the PCI device lock.
4417 * Returns 0 if the device function was successfully reset or negative if the
4418 * device doesn't support resetting a single function.
4420 int pci_reset_function(struct pci_dev *dev)
4428 pci_dev_save_and_disable(dev);
4430 rc = __pci_reset_function_locked(dev);
4432 pci_dev_restore(dev);
4433 pci_dev_unlock(dev);
4437 EXPORT_SYMBOL_GPL(pci_reset_function);
4440 * pci_reset_function_locked - quiesce and reset a PCI device function
4441 * @dev: PCI device to reset
4443 * Some devices allow an individual function to be reset without affecting
4444 * other functions in the same device. The PCI device must be responsive
4445 * to PCI config space in order to use this function.
4447 * This function does not just reset the PCI portion of a device, but
4448 * clears all the state associated with the device. This function differs
4449 * from __pci_reset_function_locked() in that it saves and restores device state
4450 * over the reset. It also differs from pci_reset_function() in that it
4451 * requires the PCI device lock to be held.
4453 * Returns 0 if the device function was successfully reset or negative if the
4454 * device doesn't support resetting a single function.
4456 int pci_reset_function_locked(struct pci_dev *dev)
4463 pci_dev_save_and_disable(dev);
4465 rc = __pci_reset_function_locked(dev);
4467 pci_dev_restore(dev);
4471 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
4474 * pci_try_reset_function - quiesce and reset a PCI device function
4475 * @dev: PCI device to reset
4477 * Same as above, except return -EAGAIN if unable to lock device.
4479 int pci_try_reset_function(struct pci_dev *dev)
4486 if (!pci_dev_trylock(dev))
4489 pci_dev_save_and_disable(dev);
4490 rc = __pci_reset_function_locked(dev);
4491 pci_dev_restore(dev);
4492 pci_dev_unlock(dev);
4496 EXPORT_SYMBOL_GPL(pci_try_reset_function);
4498 /* Do any devices on or below this bus prevent a bus reset? */
4499 static bool pci_bus_resetable(struct pci_bus *bus)
4501 struct pci_dev *dev;
4504 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4507 list_for_each_entry(dev, &bus->devices, bus_list) {
4508 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4509 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4516 /* Lock devices from the top of the tree down */
4517 static void pci_bus_lock(struct pci_bus *bus)
4519 struct pci_dev *dev;
4521 list_for_each_entry(dev, &bus->devices, bus_list) {
4523 if (dev->subordinate)
4524 pci_bus_lock(dev->subordinate);
4528 /* Unlock devices from the bottom of the tree up */
4529 static void pci_bus_unlock(struct pci_bus *bus)
4531 struct pci_dev *dev;
4533 list_for_each_entry(dev, &bus->devices, bus_list) {
4534 if (dev->subordinate)
4535 pci_bus_unlock(dev->subordinate);
4536 pci_dev_unlock(dev);
4540 /* Return 1 on successful lock, 0 on contention */
4541 static int pci_bus_trylock(struct pci_bus *bus)
4543 struct pci_dev *dev;
4545 list_for_each_entry(dev, &bus->devices, bus_list) {
4546 if (!pci_dev_trylock(dev))
4548 if (dev->subordinate) {
4549 if (!pci_bus_trylock(dev->subordinate)) {
4550 pci_dev_unlock(dev);
4558 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
4559 if (dev->subordinate)
4560 pci_bus_unlock(dev->subordinate);
4561 pci_dev_unlock(dev);
4566 /* Do any devices on or below this slot prevent a bus reset? */
4567 static bool pci_slot_resetable(struct pci_slot *slot)
4569 struct pci_dev *dev;
4571 if (slot->bus->self &&
4572 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4575 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4576 if (!dev->slot || dev->slot != slot)
4578 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4579 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4586 /* Lock devices from the top of the tree down */
4587 static void pci_slot_lock(struct pci_slot *slot)
4589 struct pci_dev *dev;
4591 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4592 if (!dev->slot || dev->slot != slot)
4595 if (dev->subordinate)
4596 pci_bus_lock(dev->subordinate);
4600 /* Unlock devices from the bottom of the tree up */
4601 static void pci_slot_unlock(struct pci_slot *slot)
4603 struct pci_dev *dev;
4605 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4606 if (!dev->slot || dev->slot != slot)
4608 if (dev->subordinate)
4609 pci_bus_unlock(dev->subordinate);
4610 pci_dev_unlock(dev);
4614 /* Return 1 on successful lock, 0 on contention */
4615 static int pci_slot_trylock(struct pci_slot *slot)
4617 struct pci_dev *dev;
4619 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4620 if (!dev->slot || dev->slot != slot)
4622 if (!pci_dev_trylock(dev))
4624 if (dev->subordinate) {
4625 if (!pci_bus_trylock(dev->subordinate)) {
4626 pci_dev_unlock(dev);
4634 list_for_each_entry_continue_reverse(dev,
4635 &slot->bus->devices, bus_list) {
4636 if (!dev->slot || dev->slot != slot)
4638 if (dev->subordinate)
4639 pci_bus_unlock(dev->subordinate);
4640 pci_dev_unlock(dev);
4645 /* Save and disable devices from the top of the tree down */
4646 static void pci_bus_save_and_disable(struct pci_bus *bus)
4648 struct pci_dev *dev;
4650 list_for_each_entry(dev, &bus->devices, bus_list) {
4652 pci_dev_save_and_disable(dev);
4653 pci_dev_unlock(dev);
4654 if (dev->subordinate)
4655 pci_bus_save_and_disable(dev->subordinate);
4660 * Restore devices from top of the tree down - parent bridges need to be
4661 * restored before we can get to subordinate devices.
4663 static void pci_bus_restore(struct pci_bus *bus)
4665 struct pci_dev *dev;
4667 list_for_each_entry(dev, &bus->devices, bus_list) {
4669 pci_dev_restore(dev);
4670 pci_dev_unlock(dev);
4671 if (dev->subordinate)
4672 pci_bus_restore(dev->subordinate);
4676 /* Save and disable devices from the top of the tree down */
4677 static void pci_slot_save_and_disable(struct pci_slot *slot)
4679 struct pci_dev *dev;
4681 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4682 if (!dev->slot || dev->slot != slot)
4684 pci_dev_save_and_disable(dev);
4685 if (dev->subordinate)
4686 pci_bus_save_and_disable(dev->subordinate);
4691 * Restore devices from top of the tree down - parent bridges need to be
4692 * restored before we can get to subordinate devices.
4694 static void pci_slot_restore(struct pci_slot *slot)
4696 struct pci_dev *dev;
4698 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4699 if (!dev->slot || dev->slot != slot)
4702 pci_dev_restore(dev);
4703 pci_dev_unlock(dev);
4704 if (dev->subordinate)
4705 pci_bus_restore(dev->subordinate);
4709 static int pci_slot_reset(struct pci_slot *slot, int probe)
4713 if (!slot || !pci_slot_resetable(slot))
4717 pci_slot_lock(slot);
4721 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
4724 pci_slot_unlock(slot);
4730 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4731 * @slot: PCI slot to probe
4733 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4735 int pci_probe_reset_slot(struct pci_slot *slot)
4737 return pci_slot_reset(slot, 1);
4739 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
4742 * pci_reset_slot - reset a PCI slot
4743 * @slot: PCI slot to reset
4745 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4746 * independent of other slots. For instance, some slots may support slot power
4747 * control. In the case of a 1:1 bus to slot architecture, this function may
4748 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4749 * Generally a slot reset should be attempted before a bus reset. All of the
4750 * function of the slot and any subordinate buses behind the slot are reset
4751 * through this function. PCI config space of all devices in the slot and
4752 * behind the slot is saved before and restored after reset.
4754 * Return 0 on success, non-zero on error.
4756 int pci_reset_slot(struct pci_slot *slot)
4760 rc = pci_slot_reset(slot, 1);
4764 pci_slot_save_and_disable(slot);
4766 rc = pci_slot_reset(slot, 0);
4768 pci_slot_restore(slot);
4772 EXPORT_SYMBOL_GPL(pci_reset_slot);
4775 * pci_try_reset_slot - Try to reset a PCI slot
4776 * @slot: PCI slot to reset
4778 * Same as above except return -EAGAIN if the slot cannot be locked
4780 int pci_try_reset_slot(struct pci_slot *slot)
4784 rc = pci_slot_reset(slot, 1);
4788 pci_slot_save_and_disable(slot);
4790 if (pci_slot_trylock(slot)) {
4792 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
4793 pci_slot_unlock(slot);
4797 pci_slot_restore(slot);
4801 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
4803 static int pci_bus_reset(struct pci_bus *bus, int probe)
4805 if (!bus->self || !pci_bus_resetable(bus))
4815 pci_reset_bridge_secondary_bus(bus->self);
4817 pci_bus_unlock(bus);
4823 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4824 * @bus: PCI bus to probe
4826 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4828 int pci_probe_reset_bus(struct pci_bus *bus)
4830 return pci_bus_reset(bus, 1);
4832 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
4835 * pci_reset_bus - reset a PCI bus
4836 * @bus: top level PCI bus to reset
4838 * Do a bus reset on the given bus and any subordinate buses, saving
4839 * and restoring state of all devices.
4841 * Return 0 on success, non-zero on error.
4843 int pci_reset_bus(struct pci_bus *bus)
4847 rc = pci_bus_reset(bus, 1);
4851 pci_bus_save_and_disable(bus);
4853 rc = pci_bus_reset(bus, 0);
4855 pci_bus_restore(bus);
4859 EXPORT_SYMBOL_GPL(pci_reset_bus);
4862 * pci_try_reset_bus - Try to reset a PCI bus
4863 * @bus: top level PCI bus to reset
4865 * Same as above except return -EAGAIN if the bus cannot be locked
4867 int pci_try_reset_bus(struct pci_bus *bus)
4871 rc = pci_bus_reset(bus, 1);
4875 pci_bus_save_and_disable(bus);
4877 if (pci_bus_trylock(bus)) {
4879 pci_reset_bridge_secondary_bus(bus->self);
4880 pci_bus_unlock(bus);
4884 pci_bus_restore(bus);
4888 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
4891 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4892 * @dev: PCI device to query
4894 * Returns mmrbc: maximum designed memory read count in bytes
4895 * or appropriate error value.
4897 int pcix_get_max_mmrbc(struct pci_dev *dev)
4902 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4906 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4909 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
4911 EXPORT_SYMBOL(pcix_get_max_mmrbc);
4914 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4915 * @dev: PCI device to query
4917 * Returns mmrbc: maximum memory read count in bytes
4918 * or appropriate error value.
4920 int pcix_get_mmrbc(struct pci_dev *dev)
4925 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4929 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4932 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
4934 EXPORT_SYMBOL(pcix_get_mmrbc);
4937 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4938 * @dev: PCI device to query
4939 * @mmrbc: maximum memory read count in bytes
4940 * valid values are 512, 1024, 2048, 4096
4942 * If possible sets maximum memory read byte count, some bridges have erratas
4943 * that prevent this.
4945 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
4951 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
4954 v = ffs(mmrbc) - 10;
4956 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4960 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4963 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
4966 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4969 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
4971 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
4974 cmd &= ~PCI_X_CMD_MAX_READ;
4976 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
4981 EXPORT_SYMBOL(pcix_set_mmrbc);
4984 * pcie_get_readrq - get PCI Express read request size
4985 * @dev: PCI device to query
4987 * Returns maximum memory read request in bytes
4988 * or appropriate error value.
4990 int pcie_get_readrq(struct pci_dev *dev)
4994 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4996 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4998 EXPORT_SYMBOL(pcie_get_readrq);
5001 * pcie_set_readrq - set PCI Express maximum memory read request
5002 * @dev: PCI device to query
5003 * @rq: maximum memory read count in bytes
5004 * valid values are 128, 256, 512, 1024, 2048, 4096
5006 * If possible sets maximum memory read request in bytes
5008 int pcie_set_readrq(struct pci_dev *dev, int rq)
5012 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5016 * If using the "performance" PCIe config, we clamp the
5017 * read rq size to the max packet size to prevent the
5018 * host bridge generating requests larger than we can
5021 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5022 int mps = pcie_get_mps(dev);
5028 v = (ffs(rq) - 8) << 12;
5030 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5031 PCI_EXP_DEVCTL_READRQ, v);
5033 EXPORT_SYMBOL(pcie_set_readrq);
5036 * pcie_get_mps - get PCI Express maximum payload size
5037 * @dev: PCI device to query
5039 * Returns maximum payload size in bytes
5041 int pcie_get_mps(struct pci_dev *dev)
5045 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5047 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5049 EXPORT_SYMBOL(pcie_get_mps);
5052 * pcie_set_mps - set PCI Express maximum payload size
5053 * @dev: PCI device to query
5054 * @mps: maximum payload size in bytes
5055 * valid values are 128, 256, 512, 1024, 2048, 4096
5057 * If possible sets maximum payload size
5059 int pcie_set_mps(struct pci_dev *dev, int mps)
5063 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
5067 if (v > dev->pcie_mpss)
5071 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5072 PCI_EXP_DEVCTL_PAYLOAD, v);
5074 EXPORT_SYMBOL(pcie_set_mps);
5077 * pcie_get_minimum_link - determine minimum link settings of a PCI device
5078 * @dev: PCI device to query
5079 * @speed: storage for minimum speed
5080 * @width: storage for minimum width
5082 * This function will walk up the PCI device chain and determine the minimum
5083 * link width and speed of the device.
5085 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
5086 enum pcie_link_width *width)
5090 *speed = PCI_SPEED_UNKNOWN;
5091 *width = PCIE_LNK_WIDTH_UNKNOWN;
5095 enum pci_bus_speed next_speed;
5096 enum pcie_link_width next_width;
5098 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
5102 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
5103 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
5104 PCI_EXP_LNKSTA_NLW_SHIFT;
5106 if (next_speed < *speed)
5107 *speed = next_speed;
5109 if (next_width < *width)
5110 *width = next_width;
5112 dev = dev->bus->self;
5117 EXPORT_SYMBOL(pcie_get_minimum_link);
5120 * pcie_bandwidth_available - determine minimum link settings of a PCIe
5121 * device and its bandwidth limitation
5122 * @dev: PCI device to query
5123 * @limiting_dev: storage for device causing the bandwidth limitation
5124 * @speed: storage for speed of limiting device
5125 * @width: storage for width of limiting device
5127 * Walk up the PCI device chain and find the point where the minimum
5128 * bandwidth is available. Return the bandwidth available there and (if
5129 * limiting_dev, speed, and width pointers are supplied) information about
5130 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
5133 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
5134 enum pci_bus_speed *speed,
5135 enum pcie_link_width *width)
5138 enum pci_bus_speed next_speed;
5139 enum pcie_link_width next_width;
5143 *speed = PCI_SPEED_UNKNOWN;
5145 *width = PCIE_LNK_WIDTH_UNKNOWN;
5150 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
5152 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
5153 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
5154 PCI_EXP_LNKSTA_NLW_SHIFT;
5156 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
5158 /* Check if current device limits the total bandwidth */
5159 if (!bw || next_bw <= bw) {
5163 *limiting_dev = dev;
5165 *speed = next_speed;
5167 *width = next_width;
5170 dev = pci_upstream_bridge(dev);
5175 EXPORT_SYMBOL(pcie_bandwidth_available);
5178 * pcie_get_speed_cap - query for the PCI device's link speed capability
5179 * @dev: PCI device to query
5181 * Query the PCI device speed capability. Return the maximum link speed
5182 * supported by the device.
5184 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
5186 u32 lnkcap2, lnkcap;
5189 * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link
5190 * Speeds Vector in Link Capabilities 2 when supported, falling
5191 * back to Max Link Speed in Link Capabilities otherwise.
5193 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
5194 if (lnkcap2) { /* PCIe r3.0-compliant */
5195 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
5196 return PCIE_SPEED_16_0GT;
5197 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
5198 return PCIE_SPEED_8_0GT;
5199 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
5200 return PCIE_SPEED_5_0GT;
5201 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
5202 return PCIE_SPEED_2_5GT;
5203 return PCI_SPEED_UNKNOWN;
5206 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5208 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
5209 return PCIE_SPEED_16_0GT;
5210 else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
5211 return PCIE_SPEED_8_0GT;
5212 else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
5213 return PCIE_SPEED_5_0GT;
5214 else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
5215 return PCIE_SPEED_2_5GT;
5218 return PCI_SPEED_UNKNOWN;
5222 * pcie_get_width_cap - query for the PCI device's link width capability
5223 * @dev: PCI device to query
5225 * Query the PCI device width capability. Return the maximum link width
5226 * supported by the device.
5228 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
5232 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5234 return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
5236 return PCIE_LNK_WIDTH_UNKNOWN;
5240 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
5242 * @speed: storage for link speed
5243 * @width: storage for link width
5245 * Calculate a PCI device's link bandwidth by querying for its link speed
5246 * and width, multiplying them, and applying encoding overhead. The result
5247 * is in Mb/s, i.e., megabits/second of raw bandwidth.
5249 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
5250 enum pcie_link_width *width)
5252 *speed = pcie_get_speed_cap(dev);
5253 *width = pcie_get_width_cap(dev);
5255 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
5258 return *width * PCIE_SPEED2MBS_ENC(*speed);
5262 * pcie_print_link_status - Report the PCI device's link speed and width
5263 * @dev: PCI device to query
5265 * Report the available bandwidth at the device. If this is less than the
5266 * device is capable of, report the device's maximum possible bandwidth and
5267 * the upstream link that limits its performance to less than that.
5269 void pcie_print_link_status(struct pci_dev *dev)
5271 enum pcie_link_width width, width_cap;
5272 enum pci_bus_speed speed, speed_cap;
5273 struct pci_dev *limiting_dev = NULL;
5274 u32 bw_avail, bw_cap;
5276 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
5277 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
5279 if (bw_avail >= bw_cap)
5280 pci_info(dev, "%u.%03u Gb/s available bandwidth (%s x%d link)\n",
5281 bw_cap / 1000, bw_cap % 1000,
5282 PCIE_SPEED2STR(speed_cap), width_cap);
5284 pci_info(dev, "%u.%03u Gb/s available bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
5285 bw_avail / 1000, bw_avail % 1000,
5286 PCIE_SPEED2STR(speed), width,
5287 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
5288 bw_cap / 1000, bw_cap % 1000,
5289 PCIE_SPEED2STR(speed_cap), width_cap);
5291 EXPORT_SYMBOL(pcie_print_link_status);
5294 * pci_select_bars - Make BAR mask from the type of resource
5295 * @dev: the PCI device for which BAR mask is made
5296 * @flags: resource type mask to be selected
5298 * This helper routine makes bar mask from the type of resource.
5300 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
5303 for (i = 0; i < PCI_NUM_RESOURCES; i++)
5304 if (pci_resource_flags(dev, i) & flags)
5308 EXPORT_SYMBOL(pci_select_bars);
5310 /* Some architectures require additional programming to enable VGA */
5311 static arch_set_vga_state_t arch_set_vga_state;
5313 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
5315 arch_set_vga_state = func; /* NULL disables */
5318 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
5319 unsigned int command_bits, u32 flags)
5321 if (arch_set_vga_state)
5322 return arch_set_vga_state(dev, decode, command_bits,
5328 * pci_set_vga_state - set VGA decode state on device and parents if requested
5329 * @dev: the PCI device
5330 * @decode: true = enable decoding, false = disable decoding
5331 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
5332 * @flags: traverse ancestors and change bridges
5333 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
5335 int pci_set_vga_state(struct pci_dev *dev, bool decode,
5336 unsigned int command_bits, u32 flags)
5338 struct pci_bus *bus;
5339 struct pci_dev *bridge;
5343 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
5345 /* ARCH specific VGA enables */
5346 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
5350 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
5351 pci_read_config_word(dev, PCI_COMMAND, &cmd);
5353 cmd |= command_bits;
5355 cmd &= ~command_bits;
5356 pci_write_config_word(dev, PCI_COMMAND, cmd);
5359 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
5366 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
5369 cmd |= PCI_BRIDGE_CTL_VGA;
5371 cmd &= ~PCI_BRIDGE_CTL_VGA;
5372 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
5381 * pci_add_dma_alias - Add a DMA devfn alias for a device
5382 * @dev: the PCI device for which alias is added
5383 * @devfn: alias slot and function
5385 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
5386 * It should be called early, preferably as PCI fixup header quirk.
5388 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
5390 if (!dev->dma_alias_mask)
5391 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
5392 sizeof(long), GFP_KERNEL);
5393 if (!dev->dma_alias_mask) {
5394 pci_warn(dev, "Unable to allocate DMA alias mask\n");
5398 set_bit(devfn, dev->dma_alias_mask);
5399 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
5400 PCI_SLOT(devfn), PCI_FUNC(devfn));
5403 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
5405 return (dev1->dma_alias_mask &&
5406 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
5407 (dev2->dma_alias_mask &&
5408 test_bit(dev1->devfn, dev2->dma_alias_mask));
5411 bool pci_device_is_present(struct pci_dev *pdev)
5415 if (pci_dev_is_disconnected(pdev))
5417 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
5419 EXPORT_SYMBOL_GPL(pci_device_is_present);
5421 void pci_ignore_hotplug(struct pci_dev *dev)
5423 struct pci_dev *bridge = dev->bus->self;
5425 dev->ignore_hotplug = 1;
5426 /* Propagate the "ignore hotplug" setting to the parent bridge. */
5428 bridge->ignore_hotplug = 1;
5430 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
5432 resource_size_t __weak pcibios_default_alignment(void)
5437 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
5438 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
5439 static DEFINE_SPINLOCK(resource_alignment_lock);
5442 * pci_specified_resource_alignment - get resource alignment specified by user.
5443 * @dev: the PCI device to get
5444 * @resize: whether or not to change resources' size when reassigning alignment
5446 * RETURNS: Resource alignment if it is specified.
5447 * Zero if it is not specified.
5449 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
5452 int seg, bus, slot, func, align_order, count;
5453 unsigned short vendor, device, subsystem_vendor, subsystem_device;
5454 resource_size_t align = pcibios_default_alignment();
5457 spin_lock(&resource_alignment_lock);
5458 p = resource_alignment_param;
5461 if (pci_has_flag(PCI_PROBE_ONLY)) {
5463 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
5469 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
5475 if (strncmp(p, "pci:", 4) == 0) {
5476 /* PCI vendor/device (subvendor/subdevice) ids are specified */
5478 if (sscanf(p, "%hx:%hx:%hx:%hx%n",
5479 &vendor, &device, &subsystem_vendor, &subsystem_device, &count) != 4) {
5480 if (sscanf(p, "%hx:%hx%n", &vendor, &device, &count) != 2) {
5481 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: pci:%s\n",
5485 subsystem_vendor = subsystem_device = 0;
5488 if ((!vendor || (vendor == dev->vendor)) &&
5489 (!device || (device == dev->device)) &&
5490 (!subsystem_vendor || (subsystem_vendor == dev->subsystem_vendor)) &&
5491 (!subsystem_device || (subsystem_device == dev->subsystem_device))) {
5493 if (align_order == -1)
5496 align = 1 << align_order;
5502 if (sscanf(p, "%x:%x:%x.%x%n",
5503 &seg, &bus, &slot, &func, &count) != 4) {
5505 if (sscanf(p, "%x:%x.%x%n",
5506 &bus, &slot, &func, &count) != 3) {
5507 /* Invalid format */
5508 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
5514 if (seg == pci_domain_nr(dev->bus) &&
5515 bus == dev->bus->number &&
5516 slot == PCI_SLOT(dev->devfn) &&
5517 func == PCI_FUNC(dev->devfn)) {
5519 if (align_order == -1)
5522 align = 1 << align_order;
5527 if (*p != ';' && *p != ',') {
5528 /* End of param or invalid format */
5534 spin_unlock(&resource_alignment_lock);
5538 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
5539 resource_size_t align, bool resize)
5541 struct resource *r = &dev->resource[bar];
5542 resource_size_t size;
5544 if (!(r->flags & IORESOURCE_MEM))
5547 if (r->flags & IORESOURCE_PCI_FIXED) {
5548 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
5549 bar, r, (unsigned long long)align);
5553 size = resource_size(r);
5558 * Increase the alignment of the resource. There are two ways we
5561 * 1) Increase the size of the resource. BARs are aligned on their
5562 * size, so when we reallocate space for this resource, we'll
5563 * allocate it with the larger alignment. This also prevents
5564 * assignment of any other BARs inside the alignment region, so
5565 * if we're requesting page alignment, this means no other BARs
5566 * will share the page.
5568 * The disadvantage is that this makes the resource larger than
5569 * the hardware BAR, which may break drivers that compute things
5570 * based on the resource size, e.g., to find registers at a
5571 * fixed offset before the end of the BAR.
5573 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
5574 * set r->start to the desired alignment. By itself this
5575 * doesn't prevent other BARs being put inside the alignment
5576 * region, but if we realign *every* resource of every device in
5577 * the system, none of them will share an alignment region.
5579 * When the user has requested alignment for only some devices via
5580 * the "pci=resource_alignment" argument, "resize" is true and we
5581 * use the first method. Otherwise we assume we're aligning all
5582 * devices and we use the second.
5585 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
5586 bar, r, (unsigned long long)align);
5592 r->flags &= ~IORESOURCE_SIZEALIGN;
5593 r->flags |= IORESOURCE_STARTALIGN;
5595 r->end = r->start + size - 1;
5597 r->flags |= IORESOURCE_UNSET;
5601 * This function disables memory decoding and releases memory resources
5602 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5603 * It also rounds up size to specified alignment.
5604 * Later on, the kernel will assign page-aligned memory resource back
5607 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
5611 resource_size_t align;
5613 bool resize = false;
5616 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
5617 * 3.4.1.11. Their resources are allocated from the space
5618 * described by the VF BARx register in the PF's SR-IOV capability.
5619 * We can't influence their alignment here.
5624 /* check if specified PCI is target device to reassign */
5625 align = pci_specified_resource_alignment(dev, &resize);
5629 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
5630 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
5631 pci_warn(dev, "Can't reassign resources to host bridge\n");
5635 pci_info(dev, "Disabling memory decoding and releasing memory resources\n");
5636 pci_read_config_word(dev, PCI_COMMAND, &command);
5637 command &= ~PCI_COMMAND_MEMORY;
5638 pci_write_config_word(dev, PCI_COMMAND, command);
5640 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
5641 pci_request_resource_alignment(dev, i, align, resize);
5644 * Need to disable bridge's resource window,
5645 * to enable the kernel to reassign new resource
5648 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
5649 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
5650 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
5651 r = &dev->resource[i];
5652 if (!(r->flags & IORESOURCE_MEM))
5654 r->flags |= IORESOURCE_UNSET;
5655 r->end = resource_size(r) - 1;
5658 pci_disable_bridge_window(dev);
5662 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
5664 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
5665 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
5666 spin_lock(&resource_alignment_lock);
5667 strncpy(resource_alignment_param, buf, count);
5668 resource_alignment_param[count] = '\0';
5669 spin_unlock(&resource_alignment_lock);
5673 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
5676 spin_lock(&resource_alignment_lock);
5677 count = snprintf(buf, size, "%s", resource_alignment_param);
5678 spin_unlock(&resource_alignment_lock);
5682 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
5684 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
5687 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
5688 const char *buf, size_t count)
5690 return pci_set_resource_alignment_param(buf, count);
5693 static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
5694 pci_resource_alignment_store);
5696 static int __init pci_resource_alignment_sysfs_init(void)
5698 return bus_create_file(&pci_bus_type,
5699 &bus_attr_resource_alignment);
5701 late_initcall(pci_resource_alignment_sysfs_init);
5703 static void pci_no_domains(void)
5705 #ifdef CONFIG_PCI_DOMAINS
5706 pci_domains_supported = 0;
5710 #ifdef CONFIG_PCI_DOMAINS
5711 static atomic_t __domain_nr = ATOMIC_INIT(-1);
5713 int pci_get_new_domain_nr(void)
5715 return atomic_inc_return(&__domain_nr);
5718 #ifdef CONFIG_PCI_DOMAINS_GENERIC
5719 static int of_pci_bus_find_domain_nr(struct device *parent)
5721 static int use_dt_domains = -1;
5725 domain = of_get_pci_domain_nr(parent->of_node);
5727 * Check DT domain and use_dt_domains values.
5729 * If DT domain property is valid (domain >= 0) and
5730 * use_dt_domains != 0, the DT assignment is valid since this means
5731 * we have not previously allocated a domain number by using
5732 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5733 * 1, to indicate that we have just assigned a domain number from
5736 * If DT domain property value is not valid (ie domain < 0), and we
5737 * have not previously assigned a domain number from DT
5738 * (use_dt_domains != 1) we should assign a domain number by
5741 * pci_get_new_domain_nr()
5743 * API and update the use_dt_domains value to keep track of method we
5744 * are using to assign domain numbers (use_dt_domains = 0).
5746 * All other combinations imply we have a platform that is trying
5747 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5748 * which is a recipe for domain mishandling and it is prevented by
5749 * invalidating the domain value (domain = -1) and printing a
5750 * corresponding error.
5752 if (domain >= 0 && use_dt_domains) {
5754 } else if (domain < 0 && use_dt_domains != 1) {
5756 domain = pci_get_new_domain_nr();
5759 pr_err("Node %pOF has ", parent->of_node);
5760 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
5767 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
5769 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
5770 acpi_pci_bus_find_domain_nr(bus);
5776 * pci_ext_cfg_avail - can we access extended PCI config space?
5778 * Returns 1 if we can access PCI extended config space (offsets
5779 * greater than 0xff). This is the default implementation. Architecture
5780 * implementations can override this.
5782 int __weak pci_ext_cfg_avail(void)
5787 void __weak pci_fixup_cardbus(struct pci_bus *bus)
5790 EXPORT_SYMBOL(pci_fixup_cardbus);
5792 static int __init pci_setup(char *str)
5795 char *k = strchr(str, ',');
5798 if (*str && (str = pcibios_setup(str)) && *str) {
5799 if (!strcmp(str, "nomsi")) {
5801 } else if (!strcmp(str, "noaer")) {
5803 } else if (!strncmp(str, "realloc=", 8)) {
5804 pci_realloc_get_opt(str + 8);
5805 } else if (!strncmp(str, "realloc", 7)) {
5806 pci_realloc_get_opt("on");
5807 } else if (!strcmp(str, "nodomains")) {
5809 } else if (!strncmp(str, "noari", 5)) {
5810 pcie_ari_disabled = true;
5811 } else if (!strncmp(str, "cbiosize=", 9)) {
5812 pci_cardbus_io_size = memparse(str + 9, &str);
5813 } else if (!strncmp(str, "cbmemsize=", 10)) {
5814 pci_cardbus_mem_size = memparse(str + 10, &str);
5815 } else if (!strncmp(str, "resource_alignment=", 19)) {
5816 pci_set_resource_alignment_param(str + 19,
5818 } else if (!strncmp(str, "ecrc=", 5)) {
5819 pcie_ecrc_get_policy(str + 5);
5820 } else if (!strncmp(str, "hpiosize=", 9)) {
5821 pci_hotplug_io_size = memparse(str + 9, &str);
5822 } else if (!strncmp(str, "hpmemsize=", 10)) {
5823 pci_hotplug_mem_size = memparse(str + 10, &str);
5824 } else if (!strncmp(str, "hpbussize=", 10)) {
5825 pci_hotplug_bus_size =
5826 simple_strtoul(str + 10, &str, 0);
5827 if (pci_hotplug_bus_size > 0xff)
5828 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
5829 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
5830 pcie_bus_config = PCIE_BUS_TUNE_OFF;
5831 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
5832 pcie_bus_config = PCIE_BUS_SAFE;
5833 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
5834 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5835 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
5836 pcie_bus_config = PCIE_BUS_PEER2PEER;
5837 } else if (!strncmp(str, "pcie_scan_all", 13)) {
5838 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
5840 printk(KERN_ERR "PCI: Unknown option `%s'\n",
5848 early_param("pci", pci_setup);