1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
33 #include <linux/aer.h>
36 DEFINE_MUTEX(pci_slot_mutex);
38 const char *pci_power_names[] = {
39 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
41 EXPORT_SYMBOL_GPL(pci_power_names);
43 int isa_dma_bridge_buggy;
44 EXPORT_SYMBOL(isa_dma_bridge_buggy);
47 EXPORT_SYMBOL(pci_pci_problems);
49 unsigned int pci_pm_d3hot_delay;
51 static void pci_pme_list_scan(struct work_struct *work);
53 static LIST_HEAD(pci_pme_list);
54 static DEFINE_MUTEX(pci_pme_list_mutex);
55 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
57 struct pci_pme_device {
58 struct list_head list;
62 #define PME_TIMEOUT 1000 /* How long between PME checks */
64 static void pci_dev_d3_sleep(struct pci_dev *dev)
66 unsigned int delay = dev->d3hot_delay;
68 if (delay < pci_pm_d3hot_delay)
69 delay = pci_pm_d3hot_delay;
75 #ifdef CONFIG_PCI_DOMAINS
76 int pci_domains_supported = 1;
79 #define DEFAULT_CARDBUS_IO_SIZE (256)
80 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
81 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
82 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
83 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
85 #define DEFAULT_HOTPLUG_IO_SIZE (256)
86 #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
87 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
88 /* hpiosize=nn can override this */
89 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
91 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
92 * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
93 * pci=hpmemsize=nnM overrides both
95 unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
96 unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
98 #define DEFAULT_HOTPLUG_BUS_SIZE 1
99 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
102 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
103 #ifdef CONFIG_PCIE_BUS_TUNE_OFF
104 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
105 #elif defined CONFIG_PCIE_BUS_SAFE
106 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
107 #elif defined CONFIG_PCIE_BUS_PERFORMANCE
108 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
109 #elif defined CONFIG_PCIE_BUS_PEER2PEER
110 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
112 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
116 * The default CLS is used if arch didn't set CLS explicitly and not
117 * all pci devices agree on the same value. Arch can override either
118 * the dfl or actual value as it sees fit. Don't forget this is
119 * measured in 32-bit words, not bytes.
121 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
122 u8 pci_cache_line_size;
125 * If we set up a device for bus mastering, we need to check the latency
126 * timer as certain BIOSes forget to set it properly.
128 unsigned int pcibios_max_latency = 255;
130 /* If set, the PCIe ARI capability will not be used. */
131 static bool pcie_ari_disabled;
133 /* If set, the PCIe ATS capability will not be used. */
134 static bool pcie_ats_disabled;
136 /* If set, the PCI config space of each device is printed during boot. */
139 bool pci_ats_disabled(void)
141 return pcie_ats_disabled;
143 EXPORT_SYMBOL_GPL(pci_ats_disabled);
145 /* Disable bridge_d3 for all PCIe ports */
146 static bool pci_bridge_d3_disable;
147 /* Force bridge_d3 for all PCIe ports */
148 static bool pci_bridge_d3_force;
150 static int __init pcie_port_pm_setup(char *str)
152 if (!strcmp(str, "off"))
153 pci_bridge_d3_disable = true;
154 else if (!strcmp(str, "force"))
155 pci_bridge_d3_force = true;
158 __setup("pcie_port_pm=", pcie_port_pm_setup);
160 /* Time to wait after a reset for device to become responsive */
161 #define PCIE_RESET_READY_POLL_MS 60000
164 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
165 * @bus: pointer to PCI bus structure to search
167 * Given a PCI bus, returns the highest PCI bus number present in the set
168 * including the given PCI bus and its list of child PCI buses.
170 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
173 unsigned char max, n;
175 max = bus->busn_res.end;
176 list_for_each_entry(tmp, &bus->children, node) {
177 n = pci_bus_max_busnr(tmp);
183 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
186 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
187 * @pdev: the PCI device
189 * Returns error bits set in PCI_STATUS and clears them.
191 int pci_status_get_and_clear_errors(struct pci_dev *pdev)
196 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
197 if (ret != PCIBIOS_SUCCESSFUL)
200 status &= PCI_STATUS_ERROR_BITS;
202 pci_write_config_word(pdev, PCI_STATUS, status);
206 EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
208 #ifdef CONFIG_HAS_IOMEM
209 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
211 struct resource *res = &pdev->resource[bar];
214 * Make sure the BAR is actually a memory resource, not an IO resource
216 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
217 pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
220 return ioremap(res->start, resource_size(res));
222 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
224 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
227 * Make sure the BAR is actually a memory resource, not an IO resource
229 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
233 return ioremap_wc(pci_resource_start(pdev, bar),
234 pci_resource_len(pdev, bar));
236 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
240 * pci_dev_str_match_path - test if a path string matches a device
241 * @dev: the PCI device to test
242 * @path: string to match the device against
243 * @endptr: pointer to the string after the match
245 * Test if a string (typically from a kernel parameter) formatted as a
246 * path of device/function addresses matches a PCI device. The string must
249 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
251 * A path for a device can be obtained using 'lspci -t'. Using a path
252 * is more robust against bus renumbering than using only a single bus,
253 * device and function address.
255 * Returns 1 if the string matches the device, 0 if it does not and
256 * a negative error code if it fails to parse the string.
258 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
262 int seg, bus, slot, func;
266 *endptr = strchrnul(path, ';');
268 wpath = kmemdup_nul(path, *endptr - path, GFP_KERNEL);
273 p = strrchr(wpath, '/');
276 ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
282 if (dev->devfn != PCI_DEVFN(slot, func)) {
288 * Note: we don't need to get a reference to the upstream
289 * bridge because we hold a reference to the top level
290 * device which should hold a reference to the bridge,
293 dev = pci_upstream_bridge(dev);
302 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
306 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
313 ret = (seg == pci_domain_nr(dev->bus) &&
314 bus == dev->bus->number &&
315 dev->devfn == PCI_DEVFN(slot, func));
323 * pci_dev_str_match - test if a string matches a device
324 * @dev: the PCI device to test
325 * @p: string to match the device against
326 * @endptr: pointer to the string after the match
328 * Test if a string (typically from a kernel parameter) matches a specified
329 * PCI device. The string may be of one of the following formats:
331 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
332 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
334 * The first format specifies a PCI bus/device/function address which
335 * may change if new hardware is inserted, if motherboard firmware changes,
336 * or due to changes caused in kernel parameters. If the domain is
337 * left unspecified, it is taken to be 0. In order to be robust against
338 * bus renumbering issues, a path of PCI device/function numbers may be used
339 * to address the specific device. The path for a device can be determined
340 * through the use of 'lspci -t'.
342 * The second format matches devices using IDs in the configuration
343 * space which may match multiple devices in the system. A value of 0
344 * for any field will match all devices. (Note: this differs from
345 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
346 * legacy reasons and convenience so users don't have to specify
347 * FFFFFFFFs on the command line.)
349 * Returns 1 if the string matches the device, 0 if it does not and
350 * a negative error code if the string cannot be parsed.
352 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
357 unsigned short vendor, device, subsystem_vendor, subsystem_device;
359 if (strncmp(p, "pci:", 4) == 0) {
360 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
362 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
363 &subsystem_vendor, &subsystem_device, &count);
365 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
369 subsystem_vendor = 0;
370 subsystem_device = 0;
375 if ((!vendor || vendor == dev->vendor) &&
376 (!device || device == dev->device) &&
377 (!subsystem_vendor ||
378 subsystem_vendor == dev->subsystem_vendor) &&
379 (!subsystem_device ||
380 subsystem_device == dev->subsystem_device))
384 * PCI Bus, Device, Function IDs are specified
385 * (optionally, may include a path of devfns following it)
387 ret = pci_dev_str_match_path(dev, p, &p);
402 static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
403 u8 pos, int cap, int *ttl)
408 pci_bus_read_config_byte(bus, devfn, pos, &pos);
414 pci_bus_read_config_word(bus, devfn, pos, &ent);
426 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
429 int ttl = PCI_FIND_CAP_TTL;
431 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
434 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
436 return __pci_find_next_cap(dev->bus, dev->devfn,
437 pos + PCI_CAP_LIST_NEXT, cap);
439 EXPORT_SYMBOL_GPL(pci_find_next_capability);
441 static u8 __pci_bus_find_cap_start(struct pci_bus *bus,
442 unsigned int devfn, u8 hdr_type)
446 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
447 if (!(status & PCI_STATUS_CAP_LIST))
451 case PCI_HEADER_TYPE_NORMAL:
452 case PCI_HEADER_TYPE_BRIDGE:
453 return PCI_CAPABILITY_LIST;
454 case PCI_HEADER_TYPE_CARDBUS:
455 return PCI_CB_CAPABILITY_LIST;
462 * pci_find_capability - query for devices' capabilities
463 * @dev: PCI device to query
464 * @cap: capability code
466 * Tell if a device supports a given PCI capability.
467 * Returns the address of the requested capability structure within the
468 * device's PCI configuration space or 0 in case the device does not
469 * support it. Possible values for @cap include:
471 * %PCI_CAP_ID_PM Power Management
472 * %PCI_CAP_ID_AGP Accelerated Graphics Port
473 * %PCI_CAP_ID_VPD Vital Product Data
474 * %PCI_CAP_ID_SLOTID Slot Identification
475 * %PCI_CAP_ID_MSI Message Signalled Interrupts
476 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
477 * %PCI_CAP_ID_PCIX PCI-X
478 * %PCI_CAP_ID_EXP PCI Express
480 u8 pci_find_capability(struct pci_dev *dev, int cap)
484 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
486 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
490 EXPORT_SYMBOL(pci_find_capability);
493 * pci_bus_find_capability - query for devices' capabilities
494 * @bus: the PCI bus to query
495 * @devfn: PCI device to query
496 * @cap: capability code
498 * Like pci_find_capability() but works for PCI devices that do not have a
499 * pci_dev structure set up yet.
501 * Returns the address of the requested capability structure within the
502 * device's PCI configuration space or 0 in case the device does not
505 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
509 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
511 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
513 pos = __pci_find_next_cap(bus, devfn, pos, cap);
517 EXPORT_SYMBOL(pci_bus_find_capability);
520 * pci_find_next_ext_capability - Find an extended capability
521 * @dev: PCI device to query
522 * @start: address at which to start looking (0 to start at beginning of list)
523 * @cap: capability code
525 * Returns the address of the next matching extended capability structure
526 * within the device's PCI configuration space or 0 if the device does
527 * not support it. Some capabilities can occur several times, e.g., the
528 * vendor-specific capability, and this provides a way to find them all.
530 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
534 u16 pos = PCI_CFG_SPACE_SIZE;
536 /* minimum 8 bytes per capability */
537 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
539 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
545 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
549 * If we have no capabilities, this is indicated by cap ID,
550 * cap version and next pointer all being 0.
556 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
559 pos = PCI_EXT_CAP_NEXT(header);
560 if (pos < PCI_CFG_SPACE_SIZE)
563 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
569 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
572 * pci_find_ext_capability - Find an extended capability
573 * @dev: PCI device to query
574 * @cap: capability code
576 * Returns the address of the requested extended capability structure
577 * within the device's PCI configuration space or 0 if the device does
578 * not support it. Possible values for @cap include:
580 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
581 * %PCI_EXT_CAP_ID_VC Virtual Channel
582 * %PCI_EXT_CAP_ID_DSN Device Serial Number
583 * %PCI_EXT_CAP_ID_PWR Power Budgeting
585 u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
587 return pci_find_next_ext_capability(dev, 0, cap);
589 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
592 * pci_get_dsn - Read and return the 8-byte Device Serial Number
593 * @dev: PCI device to query
595 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
598 * Returns the DSN, or zero if the capability does not exist.
600 u64 pci_get_dsn(struct pci_dev *dev)
606 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
611 * The Device Serial Number is two dwords offset 4 bytes from the
612 * capability position. The specification says that the first dword is
613 * the lower half, and the second dword is the upper half.
616 pci_read_config_dword(dev, pos, &dword);
618 pci_read_config_dword(dev, pos + 4, &dword);
619 dsn |= ((u64)dword) << 32;
623 EXPORT_SYMBOL_GPL(pci_get_dsn);
625 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
627 int rc, ttl = PCI_FIND_CAP_TTL;
630 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
631 mask = HT_3BIT_CAP_MASK;
633 mask = HT_5BIT_CAP_MASK;
635 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
636 PCI_CAP_ID_HT, &ttl);
638 rc = pci_read_config_byte(dev, pos + 3, &cap);
639 if (rc != PCIBIOS_SUCCESSFUL)
642 if ((cap & mask) == ht_cap)
645 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
646 pos + PCI_CAP_LIST_NEXT,
647 PCI_CAP_ID_HT, &ttl);
654 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
655 * @dev: PCI device to query
656 * @pos: Position from which to continue searching
657 * @ht_cap: HyperTransport capability code
659 * To be used in conjunction with pci_find_ht_capability() to search for
660 * all capabilities matching @ht_cap. @pos should always be a value returned
661 * from pci_find_ht_capability().
663 * NB. To be 100% safe against broken PCI devices, the caller should take
664 * steps to avoid an infinite loop.
666 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap)
668 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
670 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
673 * pci_find_ht_capability - query a device's HyperTransport capabilities
674 * @dev: PCI device to query
675 * @ht_cap: HyperTransport capability code
677 * Tell if a device supports a given HyperTransport capability.
678 * Returns an address within the device's PCI configuration space
679 * or 0 in case the device does not support the request capability.
680 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
681 * which has a HyperTransport capability matching @ht_cap.
683 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
687 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
689 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
693 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
696 * pci_find_vsec_capability - Find a vendor-specific extended capability
697 * @dev: PCI device to query
698 * @vendor: Vendor ID for which capability is defined
699 * @cap: Vendor-specific capability ID
701 * If @dev has Vendor ID @vendor, search for a VSEC capability with
702 * VSEC ID @cap. If found, return the capability offset in
703 * config space; otherwise return 0.
705 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap)
710 if (vendor != dev->vendor)
713 while ((vsec = pci_find_next_ext_capability(dev, vsec,
714 PCI_EXT_CAP_ID_VNDR))) {
715 if (pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER,
716 &header) == PCIBIOS_SUCCESSFUL &&
717 PCI_VNDR_HEADER_ID(header) == cap)
723 EXPORT_SYMBOL_GPL(pci_find_vsec_capability);
726 * pci_find_parent_resource - return resource region of parent bus of given
728 * @dev: PCI device structure contains resources to be searched
729 * @res: child resource record for which parent is sought
731 * For given resource region of given device, return the resource region of
732 * parent bus the given region is contained in.
734 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
735 struct resource *res)
737 const struct pci_bus *bus = dev->bus;
741 pci_bus_for_each_resource(bus, r, i) {
744 if (resource_contains(r, res)) {
747 * If the window is prefetchable but the BAR is
748 * not, the allocator made a mistake.
750 if (r->flags & IORESOURCE_PREFETCH &&
751 !(res->flags & IORESOURCE_PREFETCH))
755 * If we're below a transparent bridge, there may
756 * be both a positively-decoded aperture and a
757 * subtractively-decoded region that contain the BAR.
758 * We want the positively-decoded one, so this depends
759 * on pci_bus_for_each_resource() giving us those
767 EXPORT_SYMBOL(pci_find_parent_resource);
770 * pci_find_resource - Return matching PCI device resource
771 * @dev: PCI device to query
772 * @res: Resource to look for
774 * Goes over standard PCI resources (BARs) and checks if the given resource
775 * is partially or fully contained in any of them. In that case the
776 * matching resource is returned, %NULL otherwise.
778 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
782 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
783 struct resource *r = &dev->resource[i];
785 if (r->start && resource_contains(r, res))
791 EXPORT_SYMBOL(pci_find_resource);
794 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
795 * @dev: the PCI device to operate on
796 * @pos: config space offset of status word
797 * @mask: mask of bit(s) to care about in status word
799 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
801 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
805 /* Wait for Transaction Pending bit clean */
806 for (i = 0; i < 4; i++) {
809 msleep((1 << (i - 1)) * 100);
811 pci_read_config_word(dev, pos, &status);
812 if (!(status & mask))
819 static int pci_acs_enable;
822 * pci_request_acs - ask for ACS to be enabled if supported
824 void pci_request_acs(void)
829 static const char *disable_acs_redir_param;
832 * pci_disable_acs_redir - disable ACS redirect capabilities
833 * @dev: the PCI device
835 * For only devices specified in the disable_acs_redir parameter.
837 static void pci_disable_acs_redir(struct pci_dev *dev)
844 if (!disable_acs_redir_param)
847 p = disable_acs_redir_param;
849 ret = pci_dev_str_match(dev, p, &p);
851 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
852 disable_acs_redir_param);
855 } else if (ret == 1) {
860 if (*p != ';' && *p != ',') {
861 /* End of param or invalid format */
870 if (!pci_dev_specific_disable_acs_redir(dev))
875 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
879 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
881 /* P2P Request & Completion Redirect */
882 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
884 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
886 pci_info(dev, "disabled ACS redirect\n");
890 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
891 * @dev: the PCI device
893 static void pci_std_enable_acs(struct pci_dev *dev)
903 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
904 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
906 /* Source Validation */
907 ctrl |= (cap & PCI_ACS_SV);
909 /* P2P Request Redirect */
910 ctrl |= (cap & PCI_ACS_RR);
912 /* P2P Completion Redirect */
913 ctrl |= (cap & PCI_ACS_CR);
915 /* Upstream Forwarding */
916 ctrl |= (cap & PCI_ACS_UF);
918 /* Enable Translation Blocking for external devices */
919 if (dev->external_facing || dev->untrusted)
920 ctrl |= (cap & PCI_ACS_TB);
922 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
926 * pci_enable_acs - enable ACS if hardware support it
927 * @dev: the PCI device
929 static void pci_enable_acs(struct pci_dev *dev)
932 goto disable_acs_redir;
934 if (!pci_dev_specific_enable_acs(dev))
935 goto disable_acs_redir;
937 pci_std_enable_acs(dev);
941 * Note: pci_disable_acs_redir() must be called even if ACS was not
942 * enabled by the kernel because it may have been enabled by
943 * platform firmware. So if we are told to disable it, we should
944 * always disable it after setting the kernel's default
947 pci_disable_acs_redir(dev);
951 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
952 * @dev: PCI device to have its BARs restored
954 * Restore the BAR values for a given device, so as to make it
955 * accessible by its driver.
957 static void pci_restore_bars(struct pci_dev *dev)
961 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
962 pci_update_resource(dev, i);
965 static const struct pci_platform_pm_ops *pci_platform_pm;
967 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
969 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
970 !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
972 pci_platform_pm = ops;
976 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
978 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
981 static inline int platform_pci_set_power_state(struct pci_dev *dev,
984 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
987 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
989 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
992 static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
994 if (pci_platform_pm && pci_platform_pm->refresh_state)
995 pci_platform_pm->refresh_state(dev);
998 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
1000 return pci_platform_pm ?
1001 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
1004 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
1006 return pci_platform_pm ?
1007 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
1010 static inline bool platform_pci_need_resume(struct pci_dev *dev)
1012 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
1015 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
1017 if (pci_platform_pm && pci_platform_pm->bridge_d3)
1018 return pci_platform_pm->bridge_d3(dev);
1023 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
1025 * @dev: PCI device to handle.
1026 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1029 * -EINVAL if the requested state is invalid.
1030 * -EIO if device does not support PCI PM or its PM capabilities register has a
1031 * wrong version, or device doesn't support the requested state.
1032 * 0 if device already is in the requested state.
1033 * 0 if device's power state has been successfully changed.
1035 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
1038 bool need_restore = false;
1040 /* Check if we're already there */
1041 if (dev->current_state == state)
1047 if (state < PCI_D0 || state > PCI_D3hot)
1051 * Validate transition: We can enter D0 from any state, but if
1052 * we're already in a low-power state, we can only go deeper. E.g.,
1053 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1054 * we'd have to go from D3 to D0, then to D1.
1056 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
1057 && dev->current_state > state) {
1058 pci_err(dev, "invalid power transition (from %s to %s)\n",
1059 pci_power_name(dev->current_state),
1060 pci_power_name(state));
1064 /* Check if this device supports the desired state */
1065 if ((state == PCI_D1 && !dev->d1_support)
1066 || (state == PCI_D2 && !dev->d2_support))
1069 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1070 if (pmcsr == (u16) ~0) {
1071 pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n",
1072 pci_power_name(dev->current_state),
1073 pci_power_name(state));
1078 * If we're (effectively) in D3, force entire word to 0.
1079 * This doesn't affect PME_Status, disables PME_En, and
1080 * sets PowerState to 0.
1082 switch (dev->current_state) {
1086 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
1091 case PCI_UNKNOWN: /* Boot-up */
1092 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
1093 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
1094 need_restore = true;
1095 fallthrough; /* force to D0 */
1101 /* Enter specified state */
1102 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1105 * Mandatory power management transition delays; see PCI PM 1.1
1108 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1109 pci_dev_d3_sleep(dev);
1110 else if (state == PCI_D2 || dev->current_state == PCI_D2)
1111 udelay(PCI_PM_D2_DELAY);
1113 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1114 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1115 if (dev->current_state != state)
1116 pci_info_ratelimited(dev, "refused to change power state from %s to %s\n",
1117 pci_power_name(dev->current_state),
1118 pci_power_name(state));
1121 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1122 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1123 * from D3hot to D0 _may_ perform an internal reset, thereby
1124 * going to "D0 Uninitialized" rather than "D0 Initialized".
1125 * For example, at least some versions of the 3c905B and the
1126 * 3c556B exhibit this behaviour.
1128 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1129 * devices in a D3hot state at boot. Consequently, we need to
1130 * restore at least the BARs so that the device will be
1131 * accessible to its driver.
1134 pci_restore_bars(dev);
1137 pcie_aspm_pm_state_change(dev->bus->self);
1143 * pci_update_current_state - Read power state of given device and cache it
1144 * @dev: PCI device to handle.
1145 * @state: State to cache in case the device doesn't have the PM capability
1147 * The power state is read from the PMCSR register, which however is
1148 * inaccessible in D3cold. The platform firmware is therefore queried first
1149 * to detect accessibility of the register. In case the platform firmware
1150 * reports an incorrect state or the device isn't power manageable by the
1151 * platform at all, we try to detect D3cold by testing accessibility of the
1152 * vendor ID in config space.
1154 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1156 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
1157 !pci_device_is_present(dev)) {
1158 dev->current_state = PCI_D3cold;
1159 } else if (dev->pm_cap) {
1162 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1163 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1165 dev->current_state = state;
1170 * pci_refresh_power_state - Refresh the given device's power state data
1171 * @dev: Target PCI device.
1173 * Ask the platform to refresh the devices power state information and invoke
1174 * pci_update_current_state() to update its current PCI power state.
1176 void pci_refresh_power_state(struct pci_dev *dev)
1178 if (platform_pci_power_manageable(dev))
1179 platform_pci_refresh_power_state(dev);
1181 pci_update_current_state(dev, dev->current_state);
1185 * pci_platform_power_transition - Use platform to change device power state
1186 * @dev: PCI device to handle.
1187 * @state: State to put the device into.
1189 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1193 if (platform_pci_power_manageable(dev)) {
1194 error = platform_pci_set_power_state(dev, state);
1196 pci_update_current_state(dev, state);
1200 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
1201 dev->current_state = PCI_D0;
1205 EXPORT_SYMBOL_GPL(pci_platform_power_transition);
1207 static int pci_resume_one(struct pci_dev *pci_dev, void *ign)
1209 pm_request_resume(&pci_dev->dev);
1214 * pci_resume_bus - Walk given bus and runtime resume devices on it
1215 * @bus: Top bus of the subtree to walk.
1217 void pci_resume_bus(struct pci_bus *bus)
1220 pci_walk_bus(bus, pci_resume_one, NULL);
1223 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1229 * After reset, the device should not silently discard config
1230 * requests, but it may still indicate that it needs more time by
1231 * responding to them with CRS completions. The Root Port will
1232 * generally synthesize ~0 data to complete the read (except when
1233 * CRS SV is enabled and the read was for the Vendor ID; in that
1234 * case it synthesizes 0x0001 data).
1236 * Wait for the device to return a non-CRS completion. Read the
1237 * Command register instead of Vendor ID so we don't have to
1238 * contend with the CRS SV value.
1240 pci_read_config_dword(dev, PCI_COMMAND, &id);
1242 if (delay > timeout) {
1243 pci_warn(dev, "not ready %dms after %s; giving up\n",
1244 delay - 1, reset_type);
1249 pci_info(dev, "not ready %dms after %s; waiting\n",
1250 delay - 1, reset_type);
1254 pci_read_config_dword(dev, PCI_COMMAND, &id);
1258 pci_info(dev, "ready %dms after %s\n", delay - 1,
1265 * pci_power_up - Put the given device into D0
1266 * @dev: PCI device to power up
1268 int pci_power_up(struct pci_dev *dev)
1270 pci_platform_power_transition(dev, PCI_D0);
1273 * Mandatory power management transition delays are handled in
1274 * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the
1275 * corresponding bridge.
1277 if (dev->runtime_d3cold) {
1279 * When powering on a bridge from D3cold, the whole hierarchy
1280 * may be powered on into D0uninitialized state, resume them to
1281 * give them a chance to suspend again
1283 pci_resume_bus(dev->subordinate);
1286 return pci_raw_set_power_state(dev, PCI_D0);
1290 * __pci_dev_set_current_state - Set current state of a PCI device
1291 * @dev: Device to handle
1292 * @data: pointer to state to be set
1294 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1296 pci_power_t state = *(pci_power_t *)data;
1298 dev->current_state = state;
1303 * pci_bus_set_current_state - Walk given bus and set current state of devices
1304 * @bus: Top bus of the subtree to walk.
1305 * @state: state to be set
1307 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1310 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1314 * pci_set_power_state - Set the power state of a PCI device
1315 * @dev: PCI device to handle.
1316 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1318 * Transition a device to a new power state, using the platform firmware and/or
1319 * the device's PCI PM registers.
1322 * -EINVAL if the requested state is invalid.
1323 * -EIO if device does not support PCI PM or its PM capabilities register has a
1324 * wrong version, or device doesn't support the requested state.
1325 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1326 * 0 if device already is in the requested state.
1327 * 0 if the transition is to D3 but D3 is not supported.
1328 * 0 if device's power state has been successfully changed.
1330 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1334 /* Bound the state we're entering */
1335 if (state > PCI_D3cold)
1337 else if (state < PCI_D0)
1339 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1342 * If the device or the parent bridge do not support PCI
1343 * PM, ignore the request if we're doing anything other
1344 * than putting it into D0 (which would only happen on
1349 /* Check if we're already there */
1350 if (dev->current_state == state)
1353 if (state == PCI_D0)
1354 return pci_power_up(dev);
1357 * This device is quirked not to be put into D3, so don't put it in
1360 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1364 * To put device in D3cold, we put device into D3hot in native
1365 * way, then put device into D3cold with platform ops
1367 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
1370 if (pci_platform_power_transition(dev, state))
1373 /* Powering off a bridge may power off the whole hierarchy */
1374 if (state == PCI_D3cold)
1375 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1379 EXPORT_SYMBOL(pci_set_power_state);
1382 * pci_choose_state - Choose the power state of a PCI device
1383 * @dev: PCI device to be suspended
1384 * @state: target sleep state for the whole system. This is the value
1385 * that is passed to suspend() function.
1387 * Returns PCI power state suitable for given device and given system
1390 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
1397 ret = platform_pci_choose_state(dev);
1398 if (ret != PCI_POWER_ERROR)
1401 switch (state.event) {
1404 case PM_EVENT_FREEZE:
1405 case PM_EVENT_PRETHAW:
1406 /* REVISIT both freeze and pre-thaw "should" use D0 */
1407 case PM_EVENT_SUSPEND:
1408 case PM_EVENT_HIBERNATE:
1411 pci_info(dev, "unrecognized suspend event %d\n",
1417 EXPORT_SYMBOL(pci_choose_state);
1419 #define PCI_EXP_SAVE_REGS 7
1421 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1422 u16 cap, bool extended)
1424 struct pci_cap_saved_state *tmp;
1426 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1427 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1433 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1435 return _pci_find_saved_cap(dev, cap, false);
1438 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1440 return _pci_find_saved_cap(dev, cap, true);
1443 static int pci_save_pcie_state(struct pci_dev *dev)
1446 struct pci_cap_saved_state *save_state;
1449 if (!pci_is_pcie(dev))
1452 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1454 pci_err(dev, "buffer not found in %s\n", __func__);
1458 cap = (u16 *)&save_state->cap.data[0];
1459 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1460 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1461 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1462 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1463 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1464 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1465 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1470 static void pci_restore_pcie_state(struct pci_dev *dev)
1473 struct pci_cap_saved_state *save_state;
1476 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1480 cap = (u16 *)&save_state->cap.data[0];
1481 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1482 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1483 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1484 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1485 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1486 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1487 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1490 static int pci_save_pcix_state(struct pci_dev *dev)
1493 struct pci_cap_saved_state *save_state;
1495 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1499 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1501 pci_err(dev, "buffer not found in %s\n", __func__);
1505 pci_read_config_word(dev, pos + PCI_X_CMD,
1506 (u16 *)save_state->cap.data);
1511 static void pci_restore_pcix_state(struct pci_dev *dev)
1514 struct pci_cap_saved_state *save_state;
1517 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1518 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1519 if (!save_state || !pos)
1521 cap = (u16 *)&save_state->cap.data[0];
1523 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1526 static void pci_save_ltr_state(struct pci_dev *dev)
1529 struct pci_cap_saved_state *save_state;
1532 if (!pci_is_pcie(dev))
1535 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1539 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1541 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1545 cap = (u16 *)&save_state->cap.data[0];
1546 pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++);
1547 pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++);
1550 static void pci_restore_ltr_state(struct pci_dev *dev)
1552 struct pci_cap_saved_state *save_state;
1556 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1557 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1558 if (!save_state || !ltr)
1561 cap = (u16 *)&save_state->cap.data[0];
1562 pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++);
1563 pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++);
1567 * pci_save_state - save the PCI configuration space of a device before
1569 * @dev: PCI device that we're dealing with
1571 int pci_save_state(struct pci_dev *dev)
1574 /* XXX: 100% dword access ok here? */
1575 for (i = 0; i < 16; i++) {
1576 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1577 pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
1578 i * 4, dev->saved_config_space[i]);
1580 dev->state_saved = true;
1582 i = pci_save_pcie_state(dev);
1586 i = pci_save_pcix_state(dev);
1590 pci_save_ltr_state(dev);
1591 pci_save_dpc_state(dev);
1592 pci_save_aer_state(dev);
1593 pci_save_ptm_state(dev);
1594 return pci_save_vc_state(dev);
1596 EXPORT_SYMBOL(pci_save_state);
1598 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1599 u32 saved_val, int retry, bool force)
1603 pci_read_config_dword(pdev, offset, &val);
1604 if (!force && val == saved_val)
1608 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1609 offset, val, saved_val);
1610 pci_write_config_dword(pdev, offset, saved_val);
1614 pci_read_config_dword(pdev, offset, &val);
1615 if (val == saved_val)
1622 static void pci_restore_config_space_range(struct pci_dev *pdev,
1623 int start, int end, int retry,
1628 for (index = end; index >= start; index--)
1629 pci_restore_config_dword(pdev, 4 * index,
1630 pdev->saved_config_space[index],
1634 static void pci_restore_config_space(struct pci_dev *pdev)
1636 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1637 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1638 /* Restore BARs before the command register. */
1639 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1640 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1641 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1642 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1645 * Force rewriting of prefetch registers to avoid S3 resume
1646 * issues on Intel PCI bridges that occur when these
1647 * registers are not explicitly written.
1649 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1650 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1652 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1656 static void pci_restore_rebar_state(struct pci_dev *pdev)
1658 unsigned int pos, nbars, i;
1661 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1665 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1666 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
1667 PCI_REBAR_CTRL_NBAR_SHIFT;
1669 for (i = 0; i < nbars; i++, pos += 8) {
1670 struct resource *res;
1673 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1674 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1675 res = pdev->resource + bar_idx;
1676 size = pci_rebar_bytes_to_size(resource_size(res));
1677 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1678 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
1679 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1684 * pci_restore_state - Restore the saved state of a PCI device
1685 * @dev: PCI device that we're dealing with
1687 void pci_restore_state(struct pci_dev *dev)
1689 if (!dev->state_saved)
1693 * Restore max latencies (in the LTR capability) before enabling
1694 * LTR itself (in the PCIe capability).
1696 pci_restore_ltr_state(dev);
1698 pci_restore_pcie_state(dev);
1699 pci_restore_pasid_state(dev);
1700 pci_restore_pri_state(dev);
1701 pci_restore_ats_state(dev);
1702 pci_restore_vc_state(dev);
1703 pci_restore_rebar_state(dev);
1704 pci_restore_dpc_state(dev);
1705 pci_restore_ptm_state(dev);
1707 pci_aer_clear_status(dev);
1708 pci_restore_aer_state(dev);
1710 pci_restore_config_space(dev);
1712 pci_restore_pcix_state(dev);
1713 pci_restore_msi_state(dev);
1715 /* Restore ACS and IOV configuration state */
1716 pci_enable_acs(dev);
1717 pci_restore_iov_state(dev);
1719 dev->state_saved = false;
1721 EXPORT_SYMBOL(pci_restore_state);
1723 struct pci_saved_state {
1724 u32 config_space[16];
1725 struct pci_cap_saved_data cap[];
1729 * pci_store_saved_state - Allocate and return an opaque struct containing
1730 * the device saved state.
1731 * @dev: PCI device that we're dealing with
1733 * Return NULL if no state or error.
1735 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1737 struct pci_saved_state *state;
1738 struct pci_cap_saved_state *tmp;
1739 struct pci_cap_saved_data *cap;
1742 if (!dev->state_saved)
1745 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1747 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1748 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1750 state = kzalloc(size, GFP_KERNEL);
1754 memcpy(state->config_space, dev->saved_config_space,
1755 sizeof(state->config_space));
1758 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1759 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1760 memcpy(cap, &tmp->cap, len);
1761 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1763 /* Empty cap_save terminates list */
1767 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1770 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1771 * @dev: PCI device that we're dealing with
1772 * @state: Saved state returned from pci_store_saved_state()
1774 int pci_load_saved_state(struct pci_dev *dev,
1775 struct pci_saved_state *state)
1777 struct pci_cap_saved_data *cap;
1779 dev->state_saved = false;
1784 memcpy(dev->saved_config_space, state->config_space,
1785 sizeof(state->config_space));
1789 struct pci_cap_saved_state *tmp;
1791 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1792 if (!tmp || tmp->cap.size != cap->size)
1795 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1796 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1797 sizeof(struct pci_cap_saved_data) + cap->size);
1800 dev->state_saved = true;
1803 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1806 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1807 * and free the memory allocated for it.
1808 * @dev: PCI device that we're dealing with
1809 * @state: Pointer to saved state returned from pci_store_saved_state()
1811 int pci_load_and_free_saved_state(struct pci_dev *dev,
1812 struct pci_saved_state **state)
1814 int ret = pci_load_saved_state(dev, *state);
1819 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1821 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1823 return pci_enable_resources(dev, bars);
1826 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1829 struct pci_dev *bridge;
1833 err = pci_set_power_state(dev, PCI_D0);
1834 if (err < 0 && err != -EIO)
1837 bridge = pci_upstream_bridge(dev);
1839 pcie_aspm_powersave_config_link(bridge);
1841 err = pcibios_enable_device(dev, bars);
1844 pci_fixup_device(pci_fixup_enable, dev);
1846 if (dev->msi_enabled || dev->msix_enabled)
1849 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1851 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1852 if (cmd & PCI_COMMAND_INTX_DISABLE)
1853 pci_write_config_word(dev, PCI_COMMAND,
1854 cmd & ~PCI_COMMAND_INTX_DISABLE);
1861 * pci_reenable_device - Resume abandoned device
1862 * @dev: PCI device to be resumed
1864 * NOTE: This function is a backend of pci_default_resume() and is not supposed
1865 * to be called by normal code, write proper resume handler and use it instead.
1867 int pci_reenable_device(struct pci_dev *dev)
1869 if (pci_is_enabled(dev))
1870 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1873 EXPORT_SYMBOL(pci_reenable_device);
1875 static void pci_enable_bridge(struct pci_dev *dev)
1877 struct pci_dev *bridge;
1880 bridge = pci_upstream_bridge(dev);
1882 pci_enable_bridge(bridge);
1884 if (pci_is_enabled(dev)) {
1885 if (!dev->is_busmaster)
1886 pci_set_master(dev);
1890 retval = pci_enable_device(dev);
1892 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1894 pci_set_master(dev);
1897 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1899 struct pci_dev *bridge;
1904 * Power state could be unknown at this point, either due to a fresh
1905 * boot or a device removal call. So get the current power state
1906 * so that things like MSI message writing will behave as expected
1907 * (e.g. if the device really is in D0 at enable time).
1909 pci_update_current_state(dev, dev->current_state);
1911 if (atomic_inc_return(&dev->enable_cnt) > 1)
1912 return 0; /* already enabled */
1914 bridge = pci_upstream_bridge(dev);
1916 pci_enable_bridge(bridge);
1918 /* only skip sriov related */
1919 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1920 if (dev->resource[i].flags & flags)
1922 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1923 if (dev->resource[i].flags & flags)
1926 err = do_pci_enable_device(dev, bars);
1928 atomic_dec(&dev->enable_cnt);
1933 * pci_enable_device_io - Initialize a device for use with IO space
1934 * @dev: PCI device to be initialized
1936 * Initialize device before it's used by a driver. Ask low-level code
1937 * to enable I/O resources. Wake up the device if it was suspended.
1938 * Beware, this function can fail.
1940 int pci_enable_device_io(struct pci_dev *dev)
1942 return pci_enable_device_flags(dev, IORESOURCE_IO);
1944 EXPORT_SYMBOL(pci_enable_device_io);
1947 * pci_enable_device_mem - Initialize a device for use with Memory space
1948 * @dev: PCI device to be initialized
1950 * Initialize device before it's used by a driver. Ask low-level code
1951 * to enable Memory resources. Wake up the device if it was suspended.
1952 * Beware, this function can fail.
1954 int pci_enable_device_mem(struct pci_dev *dev)
1956 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1958 EXPORT_SYMBOL(pci_enable_device_mem);
1961 * pci_enable_device - Initialize device before it's used by a driver.
1962 * @dev: PCI device to be initialized
1964 * Initialize device before it's used by a driver. Ask low-level code
1965 * to enable I/O and memory. Wake up the device if it was suspended.
1966 * Beware, this function can fail.
1968 * Note we don't actually enable the device many times if we call
1969 * this function repeatedly (we just increment the count).
1971 int pci_enable_device(struct pci_dev *dev)
1973 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1975 EXPORT_SYMBOL(pci_enable_device);
1978 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
1979 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
1980 * there's no need to track it separately. pci_devres is initialized
1981 * when a device is enabled using managed PCI device enable interface.
1984 unsigned int enabled:1;
1985 unsigned int pinned:1;
1986 unsigned int orig_intx:1;
1987 unsigned int restore_intx:1;
1992 static void pcim_release(struct device *gendev, void *res)
1994 struct pci_dev *dev = to_pci_dev(gendev);
1995 struct pci_devres *this = res;
1998 if (dev->msi_enabled)
1999 pci_disable_msi(dev);
2000 if (dev->msix_enabled)
2001 pci_disable_msix(dev);
2003 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
2004 if (this->region_mask & (1 << i))
2005 pci_release_region(dev, i);
2010 if (this->restore_intx)
2011 pci_intx(dev, this->orig_intx);
2013 if (this->enabled && !this->pinned)
2014 pci_disable_device(dev);
2017 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
2019 struct pci_devres *dr, *new_dr;
2021 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
2025 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
2028 return devres_get(&pdev->dev, new_dr, NULL, NULL);
2031 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
2033 if (pci_is_managed(pdev))
2034 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2039 * pcim_enable_device - Managed pci_enable_device()
2040 * @pdev: PCI device to be initialized
2042 * Managed pci_enable_device().
2044 int pcim_enable_device(struct pci_dev *pdev)
2046 struct pci_devres *dr;
2049 dr = get_pci_dr(pdev);
2055 rc = pci_enable_device(pdev);
2057 pdev->is_managed = 1;
2062 EXPORT_SYMBOL(pcim_enable_device);
2065 * pcim_pin_device - Pin managed PCI device
2066 * @pdev: PCI device to pin
2068 * Pin managed PCI device @pdev. Pinned device won't be disabled on
2069 * driver detach. @pdev must have been enabled with
2070 * pcim_enable_device().
2072 void pcim_pin_device(struct pci_dev *pdev)
2074 struct pci_devres *dr;
2076 dr = find_pci_dr(pdev);
2077 WARN_ON(!dr || !dr->enabled);
2081 EXPORT_SYMBOL(pcim_pin_device);
2084 * pcibios_add_device - provide arch specific hooks when adding device dev
2085 * @dev: the PCI device being added
2087 * Permits the platform to provide architecture specific functionality when
2088 * devices are added. This is the default implementation. Architecture
2089 * implementations can override this.
2091 int __weak pcibios_add_device(struct pci_dev *dev)
2097 * pcibios_release_device - provide arch specific hooks when releasing
2099 * @dev: the PCI device being released
2101 * Permits the platform to provide architecture specific functionality when
2102 * devices are released. This is the default implementation. Architecture
2103 * implementations can override this.
2105 void __weak pcibios_release_device(struct pci_dev *dev) {}
2108 * pcibios_disable_device - disable arch specific PCI resources for device dev
2109 * @dev: the PCI device to disable
2111 * Disables architecture specific PCI resources for the device. This
2112 * is the default implementation. Architecture implementations can
2115 void __weak pcibios_disable_device(struct pci_dev *dev) {}
2118 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2119 * @irq: ISA IRQ to penalize
2120 * @active: IRQ active or not
2122 * Permits the platform to provide architecture-specific functionality when
2123 * penalizing ISA IRQs. This is the default implementation. Architecture
2124 * implementations can override this.
2126 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
2128 static void do_pci_disable_device(struct pci_dev *dev)
2132 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2133 if (pci_command & PCI_COMMAND_MASTER) {
2134 pci_command &= ~PCI_COMMAND_MASTER;
2135 pci_write_config_word(dev, PCI_COMMAND, pci_command);
2138 pcibios_disable_device(dev);
2142 * pci_disable_enabled_device - Disable device without updating enable_cnt
2143 * @dev: PCI device to disable
2145 * NOTE: This function is a backend of PCI power management routines and is
2146 * not supposed to be called drivers.
2148 void pci_disable_enabled_device(struct pci_dev *dev)
2150 if (pci_is_enabled(dev))
2151 do_pci_disable_device(dev);
2155 * pci_disable_device - Disable PCI device after use
2156 * @dev: PCI device to be disabled
2158 * Signal to the system that the PCI device is not in use by the system
2159 * anymore. This only involves disabling PCI bus-mastering, if active.
2161 * Note we don't actually disable the device until all callers of
2162 * pci_enable_device() have called pci_disable_device().
2164 void pci_disable_device(struct pci_dev *dev)
2166 struct pci_devres *dr;
2168 dr = find_pci_dr(dev);
2172 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2173 "disabling already-disabled device");
2175 if (atomic_dec_return(&dev->enable_cnt) != 0)
2178 do_pci_disable_device(dev);
2180 dev->is_busmaster = 0;
2182 EXPORT_SYMBOL(pci_disable_device);
2185 * pcibios_set_pcie_reset_state - set reset state for device dev
2186 * @dev: the PCIe device reset
2187 * @state: Reset state to enter into
2189 * Set the PCIe reset state for the device. This is the default
2190 * implementation. Architecture implementations can override this.
2192 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2193 enum pcie_reset_state state)
2199 * pci_set_pcie_reset_state - set reset state for device dev
2200 * @dev: the PCIe device reset
2201 * @state: Reset state to enter into
2203 * Sets the PCI reset state for the device.
2205 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2207 return pcibios_set_pcie_reset_state(dev, state);
2209 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
2211 void pcie_clear_device_status(struct pci_dev *dev)
2215 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2216 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2220 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2221 * @dev: PCIe root port or event collector.
2223 void pcie_clear_root_pme_status(struct pci_dev *dev)
2225 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2229 * pci_check_pme_status - Check if given device has generated PME.
2230 * @dev: Device to check.
2232 * Check the PME status of the device and if set, clear it and clear PME enable
2233 * (if set). Return 'true' if PME status and PME enable were both set or
2234 * 'false' otherwise.
2236 bool pci_check_pme_status(struct pci_dev *dev)
2245 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2246 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2247 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2250 /* Clear PME status. */
2251 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2252 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2253 /* Disable PME to avoid interrupt flood. */
2254 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2258 pci_write_config_word(dev, pmcsr_pos, pmcsr);
2264 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2265 * @dev: Device to handle.
2266 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2268 * Check if @dev has generated PME and queue a resume request for it in that
2271 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2273 if (pme_poll_reset && dev->pme_poll)
2274 dev->pme_poll = false;
2276 if (pci_check_pme_status(dev)) {
2277 pci_wakeup_event(dev);
2278 pm_request_resume(&dev->dev);
2284 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2285 * @bus: Top bus of the subtree to walk.
2287 void pci_pme_wakeup_bus(struct pci_bus *bus)
2290 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2295 * pci_pme_capable - check the capability of PCI device to generate PME#
2296 * @dev: PCI device to handle.
2297 * @state: PCI state from which device will issue PME#.
2299 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2304 return !!(dev->pme_support & (1 << state));
2306 EXPORT_SYMBOL(pci_pme_capable);
2308 static void pci_pme_list_scan(struct work_struct *work)
2310 struct pci_pme_device *pme_dev, *n;
2312 mutex_lock(&pci_pme_list_mutex);
2313 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
2314 if (pme_dev->dev->pme_poll) {
2315 struct pci_dev *bridge;
2317 bridge = pme_dev->dev->bus->self;
2319 * If bridge is in low power state, the
2320 * configuration space of subordinate devices
2321 * may be not accessible
2323 if (bridge && bridge->current_state != PCI_D0)
2326 * If the device is in D3cold it should not be
2329 if (pme_dev->dev->current_state == PCI_D3cold)
2332 pci_pme_wakeup(pme_dev->dev, NULL);
2334 list_del(&pme_dev->list);
2338 if (!list_empty(&pci_pme_list))
2339 queue_delayed_work(system_freezable_wq, &pci_pme_work,
2340 msecs_to_jiffies(PME_TIMEOUT));
2341 mutex_unlock(&pci_pme_list_mutex);
2344 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2348 if (!dev->pme_support)
2351 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2352 /* Clear PME_Status by writing 1 to it and enable PME# */
2353 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2355 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2357 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2361 * pci_pme_restore - Restore PME configuration after config space restore.
2362 * @dev: PCI device to update.
2364 void pci_pme_restore(struct pci_dev *dev)
2368 if (!dev->pme_support)
2371 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2372 if (dev->wakeup_prepared) {
2373 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2374 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2376 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2377 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2379 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2383 * pci_pme_active - enable or disable PCI device's PME# function
2384 * @dev: PCI device to handle.
2385 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2387 * The caller must verify that the device is capable of generating PME# before
2388 * calling this function with @enable equal to 'true'.
2390 void pci_pme_active(struct pci_dev *dev, bool enable)
2392 __pci_pme_active(dev, enable);
2395 * PCI (as opposed to PCIe) PME requires that the device have
2396 * its PME# line hooked up correctly. Not all hardware vendors
2397 * do this, so the PME never gets delivered and the device
2398 * remains asleep. The easiest way around this is to
2399 * periodically walk the list of suspended devices and check
2400 * whether any have their PME flag set. The assumption is that
2401 * we'll wake up often enough anyway that this won't be a huge
2402 * hit, and the power savings from the devices will still be a
2405 * Although PCIe uses in-band PME message instead of PME# line
2406 * to report PME, PME does not work for some PCIe devices in
2407 * reality. For example, there are devices that set their PME
2408 * status bits, but don't really bother to send a PME message;
2409 * there are PCI Express Root Ports that don't bother to
2410 * trigger interrupts when they receive PME messages from the
2411 * devices below. So PME poll is used for PCIe devices too.
2414 if (dev->pme_poll) {
2415 struct pci_pme_device *pme_dev;
2417 pme_dev = kmalloc(sizeof(struct pci_pme_device),
2420 pci_warn(dev, "can't enable PME#\n");
2424 mutex_lock(&pci_pme_list_mutex);
2425 list_add(&pme_dev->list, &pci_pme_list);
2426 if (list_is_singular(&pci_pme_list))
2427 queue_delayed_work(system_freezable_wq,
2429 msecs_to_jiffies(PME_TIMEOUT));
2430 mutex_unlock(&pci_pme_list_mutex);
2432 mutex_lock(&pci_pme_list_mutex);
2433 list_for_each_entry(pme_dev, &pci_pme_list, list) {
2434 if (pme_dev->dev == dev) {
2435 list_del(&pme_dev->list);
2440 mutex_unlock(&pci_pme_list_mutex);
2444 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2446 EXPORT_SYMBOL(pci_pme_active);
2449 * __pci_enable_wake - enable PCI device as wakeup event source
2450 * @dev: PCI device affected
2451 * @state: PCI state from which device will issue wakeup events
2452 * @enable: True to enable event generation; false to disable
2454 * This enables the device as a wakeup event source, or disables it.
2455 * When such events involves platform-specific hooks, those hooks are
2456 * called automatically by this routine.
2458 * Devices with legacy power management (no standard PCI PM capabilities)
2459 * always require such platform hooks.
2462 * 0 is returned on success
2463 * -EINVAL is returned if device is not supposed to wake up the system
2464 * Error code depending on the platform is returned if both the platform and
2465 * the native mechanism fail to enable the generation of wake-up events
2467 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2472 * Bridges that are not power-manageable directly only signal
2473 * wakeup on behalf of subordinate devices which is set up
2474 * elsewhere, so skip them. However, bridges that are
2475 * power-manageable may signal wakeup for themselves (for example,
2476 * on a hotplug event) and they need to be covered here.
2478 if (!pci_power_manageable(dev))
2481 /* Don't do the same thing twice in a row for one device. */
2482 if (!!enable == !!dev->wakeup_prepared)
2486 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2487 * Anderson we should be doing PME# wake enable followed by ACPI wake
2488 * enable. To disable wake-up we call the platform first, for symmetry.
2495 * Enable PME signaling if the device can signal PME from
2496 * D3cold regardless of whether or not it can signal PME from
2497 * the current target state, because that will allow it to
2498 * signal PME when the hierarchy above it goes into D3cold and
2499 * the device itself ends up in D3cold as a result of that.
2501 if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
2502 pci_pme_active(dev, true);
2505 error = platform_pci_set_wakeup(dev, true);
2509 dev->wakeup_prepared = true;
2511 platform_pci_set_wakeup(dev, false);
2512 pci_pme_active(dev, false);
2513 dev->wakeup_prepared = false;
2520 * pci_enable_wake - change wakeup settings for a PCI device
2521 * @pci_dev: Target device
2522 * @state: PCI state from which device will issue wakeup events
2523 * @enable: Whether or not to enable event generation
2525 * If @enable is set, check device_may_wakeup() for the device before calling
2526 * __pci_enable_wake() for it.
2528 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2530 if (enable && !device_may_wakeup(&pci_dev->dev))
2533 return __pci_enable_wake(pci_dev, state, enable);
2535 EXPORT_SYMBOL(pci_enable_wake);
2538 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2539 * @dev: PCI device to prepare
2540 * @enable: True to enable wake-up event generation; false to disable
2542 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2543 * and this function allows them to set that up cleanly - pci_enable_wake()
2544 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2545 * ordering constraints.
2547 * This function only returns error code if the device is not allowed to wake
2548 * up the system from sleep or it is not capable of generating PME# from both
2549 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2551 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2553 return pci_pme_capable(dev, PCI_D3cold) ?
2554 pci_enable_wake(dev, PCI_D3cold, enable) :
2555 pci_enable_wake(dev, PCI_D3hot, enable);
2557 EXPORT_SYMBOL(pci_wake_from_d3);
2560 * pci_target_state - find an appropriate low power state for a given PCI dev
2562 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2564 * Use underlying platform code to find a supported low power state for @dev.
2565 * If the platform can't manage @dev, return the deepest state from which it
2566 * can generate wake events, based on any available PME info.
2568 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2570 pci_power_t target_state = PCI_D3hot;
2572 if (platform_pci_power_manageable(dev)) {
2574 * Call the platform to find the target state for the device.
2576 pci_power_t state = platform_pci_choose_state(dev);
2579 case PCI_POWER_ERROR:
2584 if (pci_no_d1d2(dev))
2588 target_state = state;
2591 return target_state;
2595 target_state = PCI_D0;
2598 * If the device is in D3cold even though it's not power-manageable by
2599 * the platform, it may have been powered down by non-standard means.
2600 * Best to let it slumber.
2602 if (dev->current_state == PCI_D3cold)
2603 target_state = PCI_D3cold;
2605 if (wakeup && dev->pme_support) {
2606 pci_power_t state = target_state;
2609 * Find the deepest state from which the device can generate
2612 while (state && !(dev->pme_support & (1 << state)))
2617 else if (dev->pme_support & 1)
2621 return target_state;
2625 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2626 * into a sleep state
2627 * @dev: Device to handle.
2629 * Choose the power state appropriate for the device depending on whether
2630 * it can wake up the system and/or is power manageable by the platform
2631 * (PCI_D3hot is the default) and put the device into that state.
2633 int pci_prepare_to_sleep(struct pci_dev *dev)
2635 bool wakeup = device_may_wakeup(&dev->dev);
2636 pci_power_t target_state = pci_target_state(dev, wakeup);
2639 if (target_state == PCI_POWER_ERROR)
2643 * There are systems (for example, Intel mobile chips since Coffee
2644 * Lake) where the power drawn while suspended can be significantly
2645 * reduced by disabling PTM on PCIe root ports as this allows the
2646 * port to enter a lower-power PM state and the SoC to reach a
2647 * lower-power idle state as a whole.
2649 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2650 pci_disable_ptm(dev);
2652 pci_enable_wake(dev, target_state, wakeup);
2654 error = pci_set_power_state(dev, target_state);
2657 pci_enable_wake(dev, target_state, false);
2658 pci_restore_ptm_state(dev);
2663 EXPORT_SYMBOL(pci_prepare_to_sleep);
2666 * pci_back_from_sleep - turn PCI device on during system-wide transition
2667 * into working state
2668 * @dev: Device to handle.
2670 * Disable device's system wake-up capability and put it into D0.
2672 int pci_back_from_sleep(struct pci_dev *dev)
2674 pci_enable_wake(dev, PCI_D0, false);
2675 return pci_set_power_state(dev, PCI_D0);
2677 EXPORT_SYMBOL(pci_back_from_sleep);
2680 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2681 * @dev: PCI device being suspended.
2683 * Prepare @dev to generate wake-up events at run time and put it into a low
2686 int pci_finish_runtime_suspend(struct pci_dev *dev)
2688 pci_power_t target_state;
2691 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2692 if (target_state == PCI_POWER_ERROR)
2695 dev->runtime_d3cold = target_state == PCI_D3cold;
2698 * There are systems (for example, Intel mobile chips since Coffee
2699 * Lake) where the power drawn while suspended can be significantly
2700 * reduced by disabling PTM on PCIe root ports as this allows the
2701 * port to enter a lower-power PM state and the SoC to reach a
2702 * lower-power idle state as a whole.
2704 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2705 pci_disable_ptm(dev);
2707 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2709 error = pci_set_power_state(dev, target_state);
2712 pci_enable_wake(dev, target_state, false);
2713 pci_restore_ptm_state(dev);
2714 dev->runtime_d3cold = false;
2721 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2722 * @dev: Device to check.
2724 * Return true if the device itself is capable of generating wake-up events
2725 * (through the platform or using the native PCIe PME) or if the device supports
2726 * PME and one of its upstream bridges can generate wake-up events.
2728 bool pci_dev_run_wake(struct pci_dev *dev)
2730 struct pci_bus *bus = dev->bus;
2732 if (!dev->pme_support)
2735 /* PME-capable in principle, but not from the target power state */
2736 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2739 if (device_can_wakeup(&dev->dev))
2742 while (bus->parent) {
2743 struct pci_dev *bridge = bus->self;
2745 if (device_can_wakeup(&bridge->dev))
2751 /* We have reached the root bus. */
2753 return device_can_wakeup(bus->bridge);
2757 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2760 * pci_dev_need_resume - Check if it is necessary to resume the device.
2761 * @pci_dev: Device to check.
2763 * Return 'true' if the device is not runtime-suspended or it has to be
2764 * reconfigured due to wakeup settings difference between system and runtime
2765 * suspend, or the current power state of it is not suitable for the upcoming
2766 * (system-wide) transition.
2768 bool pci_dev_need_resume(struct pci_dev *pci_dev)
2770 struct device *dev = &pci_dev->dev;
2771 pci_power_t target_state;
2773 if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2776 target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2779 * If the earlier platform check has not triggered, D3cold is just power
2780 * removal on top of D3hot, so no need to resume the device in that
2783 return target_state != pci_dev->current_state &&
2784 target_state != PCI_D3cold &&
2785 pci_dev->current_state != PCI_D3hot;
2789 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2790 * @pci_dev: Device to check.
2792 * If the device is suspended and it is not configured for system wakeup,
2793 * disable PME for it to prevent it from waking up the system unnecessarily.
2795 * Note that if the device's power state is D3cold and the platform check in
2796 * pci_dev_need_resume() has not triggered, the device's configuration need not
2799 void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2801 struct device *dev = &pci_dev->dev;
2803 spin_lock_irq(&dev->power.lock);
2805 if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2806 pci_dev->current_state < PCI_D3cold)
2807 __pci_pme_active(pci_dev, false);
2809 spin_unlock_irq(&dev->power.lock);
2813 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2814 * @pci_dev: Device to handle.
2816 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2817 * it might have been disabled during the prepare phase of system suspend if
2818 * the device was not configured for system wakeup.
2820 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2822 struct device *dev = &pci_dev->dev;
2824 if (!pci_dev_run_wake(pci_dev))
2827 spin_lock_irq(&dev->power.lock);
2829 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2830 __pci_pme_active(pci_dev, true);
2832 spin_unlock_irq(&dev->power.lock);
2835 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2837 struct device *dev = &pdev->dev;
2838 struct device *parent = dev->parent;
2841 pm_runtime_get_sync(parent);
2842 pm_runtime_get_noresume(dev);
2844 * pdev->current_state is set to PCI_D3cold during suspending,
2845 * so wait until suspending completes
2847 pm_runtime_barrier(dev);
2849 * Only need to resume devices in D3cold, because config
2850 * registers are still accessible for devices suspended but
2853 if (pdev->current_state == PCI_D3cold)
2854 pm_runtime_resume(dev);
2857 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2859 struct device *dev = &pdev->dev;
2860 struct device *parent = dev->parent;
2862 pm_runtime_put(dev);
2864 pm_runtime_put_sync(parent);
2867 static const struct dmi_system_id bridge_d3_blacklist[] = {
2871 * Gigabyte X299 root port is not marked as hotplug capable
2872 * which allows Linux to power manage it. However, this
2873 * confuses the BIOS SMI handler so don't power manage root
2874 * ports on that system.
2876 .ident = "X299 DESIGNARE EX-CF",
2878 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
2879 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2887 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2888 * @bridge: Bridge to check
2890 * This function checks if it is possible to move the bridge to D3.
2891 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2893 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2895 if (!pci_is_pcie(bridge))
2898 switch (pci_pcie_type(bridge)) {
2899 case PCI_EXP_TYPE_ROOT_PORT:
2900 case PCI_EXP_TYPE_UPSTREAM:
2901 case PCI_EXP_TYPE_DOWNSTREAM:
2902 if (pci_bridge_d3_disable)
2906 * Hotplug ports handled by firmware in System Management Mode
2907 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2909 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
2912 if (pci_bridge_d3_force)
2915 /* Even the oldest 2010 Thunderbolt controller supports D3. */
2916 if (bridge->is_thunderbolt)
2919 /* Platform might know better if the bridge supports D3 */
2920 if (platform_pci_bridge_d3(bridge))
2924 * Hotplug ports handled natively by the OS were not validated
2925 * by vendors for runtime D3 at least until 2018 because there
2926 * was no OS support.
2928 if (bridge->is_hotplug_bridge)
2931 if (dmi_check_system(bridge_d3_blacklist))
2935 * It should be safe to put PCIe ports from 2015 or newer
2938 if (dmi_get_bios_year() >= 2015)
2946 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2948 bool *d3cold_ok = data;
2950 if (/* The device needs to be allowed to go D3cold ... */
2951 dev->no_d3cold || !dev->d3cold_allowed ||
2953 /* ... and if it is wakeup capable to do so from D3cold. */
2954 (device_may_wakeup(&dev->dev) &&
2955 !pci_pme_capable(dev, PCI_D3cold)) ||
2957 /* If it is a bridge it must be allowed to go to D3. */
2958 !pci_power_manageable(dev))
2966 * pci_bridge_d3_update - Update bridge D3 capabilities
2967 * @dev: PCI device which is changed
2969 * Update upstream bridge PM capabilities accordingly depending on if the
2970 * device PM configuration was changed or the device is being removed. The
2971 * change is also propagated upstream.
2973 void pci_bridge_d3_update(struct pci_dev *dev)
2975 bool remove = !device_is_registered(&dev->dev);
2976 struct pci_dev *bridge;
2977 bool d3cold_ok = true;
2979 bridge = pci_upstream_bridge(dev);
2980 if (!bridge || !pci_bridge_d3_possible(bridge))
2984 * If D3 is currently allowed for the bridge, removing one of its
2985 * children won't change that.
2987 if (remove && bridge->bridge_d3)
2991 * If D3 is currently allowed for the bridge and a child is added or
2992 * changed, disallowance of D3 can only be caused by that child, so
2993 * we only need to check that single device, not any of its siblings.
2995 * If D3 is currently not allowed for the bridge, checking the device
2996 * first may allow us to skip checking its siblings.
2999 pci_dev_check_d3cold(dev, &d3cold_ok);
3002 * If D3 is currently not allowed for the bridge, this may be caused
3003 * either by the device being changed/removed or any of its siblings,
3004 * so we need to go through all children to find out if one of them
3005 * continues to block D3.
3007 if (d3cold_ok && !bridge->bridge_d3)
3008 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
3011 if (bridge->bridge_d3 != d3cold_ok) {
3012 bridge->bridge_d3 = d3cold_ok;
3013 /* Propagate change to upstream bridges */
3014 pci_bridge_d3_update(bridge);
3019 * pci_d3cold_enable - Enable D3cold for device
3020 * @dev: PCI device to handle
3022 * This function can be used in drivers to enable D3cold from the device
3023 * they handle. It also updates upstream PCI bridge PM capabilities
3026 void pci_d3cold_enable(struct pci_dev *dev)
3028 if (dev->no_d3cold) {
3029 dev->no_d3cold = false;
3030 pci_bridge_d3_update(dev);
3033 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
3036 * pci_d3cold_disable - Disable D3cold for device
3037 * @dev: PCI device to handle
3039 * This function can be used in drivers to disable D3cold from the device
3040 * they handle. It also updates upstream PCI bridge PM capabilities
3043 void pci_d3cold_disable(struct pci_dev *dev)
3045 if (!dev->no_d3cold) {
3046 dev->no_d3cold = true;
3047 pci_bridge_d3_update(dev);
3050 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
3053 * pci_pm_init - Initialize PM functions of given PCI device
3054 * @dev: PCI device to handle.
3056 void pci_pm_init(struct pci_dev *dev)
3062 pm_runtime_forbid(&dev->dev);
3063 pm_runtime_set_active(&dev->dev);
3064 pm_runtime_enable(&dev->dev);
3065 device_enable_async_suspend(&dev->dev);
3066 dev->wakeup_prepared = false;
3069 dev->pme_support = 0;
3071 /* find PCI PM capability in list */
3072 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3075 /* Check device's ability to generate PME# */
3076 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3078 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
3079 pci_err(dev, "unsupported PM cap regs version (%u)\n",
3080 pmc & PCI_PM_CAP_VER_MASK);
3085 dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
3086 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3087 dev->bridge_d3 = pci_bridge_d3_possible(dev);
3088 dev->d3cold_allowed = true;
3090 dev->d1_support = false;
3091 dev->d2_support = false;
3092 if (!pci_no_d1d2(dev)) {
3093 if (pmc & PCI_PM_CAP_D1)
3094 dev->d1_support = true;
3095 if (pmc & PCI_PM_CAP_D2)
3096 dev->d2_support = true;
3098 if (dev->d1_support || dev->d2_support)
3099 pci_info(dev, "supports%s%s\n",
3100 dev->d1_support ? " D1" : "",
3101 dev->d2_support ? " D2" : "");
3104 pmc &= PCI_PM_CAP_PME_MASK;
3106 pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3107 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
3108 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
3109 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
3110 (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
3111 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
3112 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
3113 dev->pme_poll = true;
3115 * Make device's PM flags reflect the wake-up capability, but
3116 * let the user space enable it to wake up the system as needed.
3118 device_set_wakeup_capable(&dev->dev, true);
3119 /* Disable the PME# generation functionality */
3120 pci_pme_active(dev, false);
3123 pci_read_config_word(dev, PCI_STATUS, &status);
3124 if (status & PCI_STATUS_IMM_READY)
3128 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3130 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
3134 case PCI_EA_P_VF_MEM:
3135 flags |= IORESOURCE_MEM;
3137 case PCI_EA_P_MEM_PREFETCH:
3138 case PCI_EA_P_VF_MEM_PREFETCH:
3139 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
3142 flags |= IORESOURCE_IO;
3151 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3154 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
3155 return &dev->resource[bei];
3156 #ifdef CONFIG_PCI_IOV
3157 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
3158 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
3159 return &dev->resource[PCI_IOV_RESOURCES +
3160 bei - PCI_EA_BEI_VF_BAR0];
3162 else if (bei == PCI_EA_BEI_ROM)
3163 return &dev->resource[PCI_ROM_RESOURCE];
3168 /* Read an Enhanced Allocation (EA) entry */
3169 static int pci_ea_read(struct pci_dev *dev, int offset)
3171 struct resource *res;
3172 int ent_size, ent_offset = offset;
3173 resource_size_t start, end;
3174 unsigned long flags;
3175 u32 dw0, bei, base, max_offset;
3177 bool support_64 = (sizeof(resource_size_t) >= 8);
3179 pci_read_config_dword(dev, ent_offset, &dw0);
3182 /* Entry size field indicates DWORDs after 1st */
3183 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
3185 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
3188 bei = (dw0 & PCI_EA_BEI) >> 4;
3189 prop = (dw0 & PCI_EA_PP) >> 8;
3192 * If the Property is in the reserved range, try the Secondary
3195 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
3196 prop = (dw0 & PCI_EA_SP) >> 16;
3197 if (prop > PCI_EA_P_BRIDGE_IO)
3200 res = pci_ea_get_resource(dev, bei, prop);
3202 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3206 flags = pci_ea_flags(dev, prop);
3208 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3213 pci_read_config_dword(dev, ent_offset, &base);
3214 start = (base & PCI_EA_FIELD_MASK);
3217 /* Read MaxOffset */
3218 pci_read_config_dword(dev, ent_offset, &max_offset);
3221 /* Read Base MSBs (if 64-bit entry) */
3222 if (base & PCI_EA_IS_64) {
3225 pci_read_config_dword(dev, ent_offset, &base_upper);
3228 flags |= IORESOURCE_MEM_64;
3230 /* entry starts above 32-bit boundary, can't use */
3231 if (!support_64 && base_upper)
3235 start |= ((u64)base_upper << 32);
3238 end = start + (max_offset | 0x03);
3240 /* Read MaxOffset MSBs (if 64-bit entry) */
3241 if (max_offset & PCI_EA_IS_64) {
3242 u32 max_offset_upper;
3244 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3247 flags |= IORESOURCE_MEM_64;
3249 /* entry too big, can't use */
3250 if (!support_64 && max_offset_upper)
3254 end += ((u64)max_offset_upper << 32);
3258 pci_err(dev, "EA Entry crosses address boundary\n");
3262 if (ent_size != ent_offset - offset) {
3263 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3264 ent_size, ent_offset - offset);
3268 res->name = pci_name(dev);
3273 if (bei <= PCI_EA_BEI_BAR5)
3274 pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3276 else if (bei == PCI_EA_BEI_ROM)
3277 pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3279 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3280 pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3281 bei - PCI_EA_BEI_VF_BAR0, res, prop);
3283 pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3287 return offset + ent_size;
3290 /* Enhanced Allocation Initialization */
3291 void pci_ea_init(struct pci_dev *dev)
3298 /* find PCI EA capability in list */
3299 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3303 /* determine the number of entries */
3304 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3306 num_ent &= PCI_EA_NUM_ENT_MASK;
3308 offset = ea + PCI_EA_FIRST_ENT;
3310 /* Skip DWORD 2 for type 1 functions */
3311 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3314 /* parse each EA entry */
3315 for (i = 0; i < num_ent; ++i)
3316 offset = pci_ea_read(dev, offset);
3319 static void pci_add_saved_cap(struct pci_dev *pci_dev,
3320 struct pci_cap_saved_state *new_cap)
3322 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
3326 * _pci_add_cap_save_buffer - allocate buffer for saving given
3327 * capability registers
3328 * @dev: the PCI device
3329 * @cap: the capability to allocate the buffer for
3330 * @extended: Standard or Extended capability ID
3331 * @size: requested size of the buffer
3333 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3334 bool extended, unsigned int size)
3337 struct pci_cap_saved_state *save_state;
3340 pos = pci_find_ext_capability(dev, cap);
3342 pos = pci_find_capability(dev, cap);
3347 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
3351 save_state->cap.cap_nr = cap;
3352 save_state->cap.cap_extended = extended;
3353 save_state->cap.size = size;
3354 pci_add_saved_cap(dev, save_state);
3359 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3361 return _pci_add_cap_save_buffer(dev, cap, false, size);
3364 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3366 return _pci_add_cap_save_buffer(dev, cap, true, size);
3370 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3371 * @dev: the PCI device
3373 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3377 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3378 PCI_EXP_SAVE_REGS * sizeof(u16));
3380 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3382 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3384 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3386 error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3389 pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3391 pci_allocate_vc_save_buffers(dev);
3394 void pci_free_cap_save_buffers(struct pci_dev *dev)
3396 struct pci_cap_saved_state *tmp;
3397 struct hlist_node *n;
3399 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3404 * pci_configure_ari - enable or disable ARI forwarding
3405 * @dev: the PCI device
3407 * If @dev and its upstream bridge both support ARI, enable ARI in the
3408 * bridge. Otherwise, disable ARI in the bridge.
3410 void pci_configure_ari(struct pci_dev *dev)
3413 struct pci_dev *bridge;
3415 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3418 bridge = dev->bus->self;
3422 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3423 if (!(cap & PCI_EXP_DEVCAP2_ARI))
3426 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3427 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3428 PCI_EXP_DEVCTL2_ARI);
3429 bridge->ari_enabled = 1;
3431 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3432 PCI_EXP_DEVCTL2_ARI);
3433 bridge->ari_enabled = 0;
3437 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3442 pos = pdev->acs_cap;
3447 * Except for egress control, capabilities are either required
3448 * or only required if controllable. Features missing from the
3449 * capability field can therefore be assumed as hard-wired enabled.
3451 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3452 acs_flags &= (cap | PCI_ACS_EC);
3454 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3455 return (ctrl & acs_flags) == acs_flags;
3459 * pci_acs_enabled - test ACS against required flags for a given device
3460 * @pdev: device to test
3461 * @acs_flags: required PCI ACS flags
3463 * Return true if the device supports the provided flags. Automatically
3464 * filters out flags that are not implemented on multifunction devices.
3466 * Note that this interface checks the effective ACS capabilities of the
3467 * device rather than the actual capabilities. For instance, most single
3468 * function endpoints are not required to support ACS because they have no
3469 * opportunity for peer-to-peer access. We therefore return 'true'
3470 * regardless of whether the device exposes an ACS capability. This makes
3471 * it much easier for callers of this function to ignore the actual type
3472 * or topology of the device when testing ACS support.
3474 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3478 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3483 * Conventional PCI and PCI-X devices never support ACS, either
3484 * effectively or actually. The shared bus topology implies that
3485 * any device on the bus can receive or snoop DMA.
3487 if (!pci_is_pcie(pdev))
3490 switch (pci_pcie_type(pdev)) {
3492 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3493 * but since their primary interface is PCI/X, we conservatively
3494 * handle them as we would a non-PCIe device.
3496 case PCI_EXP_TYPE_PCIE_BRIDGE:
3498 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3499 * applicable... must never implement an ACS Extended Capability...".
3500 * This seems arbitrary, but we take a conservative interpretation
3501 * of this statement.
3503 case PCI_EXP_TYPE_PCI_BRIDGE:
3504 case PCI_EXP_TYPE_RC_EC:
3507 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3508 * implement ACS in order to indicate their peer-to-peer capabilities,
3509 * regardless of whether they are single- or multi-function devices.
3511 case PCI_EXP_TYPE_DOWNSTREAM:
3512 case PCI_EXP_TYPE_ROOT_PORT:
3513 return pci_acs_flags_enabled(pdev, acs_flags);
3515 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3516 * implemented by the remaining PCIe types to indicate peer-to-peer
3517 * capabilities, but only when they are part of a multifunction
3518 * device. The footnote for section 6.12 indicates the specific
3519 * PCIe types included here.
3521 case PCI_EXP_TYPE_ENDPOINT:
3522 case PCI_EXP_TYPE_UPSTREAM:
3523 case PCI_EXP_TYPE_LEG_END:
3524 case PCI_EXP_TYPE_RC_END:
3525 if (!pdev->multifunction)
3528 return pci_acs_flags_enabled(pdev, acs_flags);
3532 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3533 * to single function devices with the exception of downstream ports.
3539 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3540 * @start: starting downstream device
3541 * @end: ending upstream device or NULL to search to the root bus
3542 * @acs_flags: required flags
3544 * Walk up a device tree from start to end testing PCI ACS support. If
3545 * any step along the way does not support the required flags, return false.
3547 bool pci_acs_path_enabled(struct pci_dev *start,
3548 struct pci_dev *end, u16 acs_flags)
3550 struct pci_dev *pdev, *parent = start;
3555 if (!pci_acs_enabled(pdev, acs_flags))
3558 if (pci_is_root_bus(pdev->bus))
3559 return (end == NULL);
3561 parent = pdev->bus->self;
3562 } while (pdev != end);
3568 * pci_acs_init - Initialize ACS if hardware supports it
3569 * @dev: the PCI device
3571 void pci_acs_init(struct pci_dev *dev)
3573 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3576 * Attempt to enable ACS regardless of capability because some Root
3577 * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3578 * the standard ACS capability but still support ACS via those
3581 pci_enable_acs(dev);
3585 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3589 * Helper to find the position of the ctrl register for a BAR.
3590 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3591 * Returns -ENOENT if no ctrl register for the BAR could be found.
3593 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3595 unsigned int pos, nbars, i;
3598 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3602 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3603 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3604 PCI_REBAR_CTRL_NBAR_SHIFT;
3606 for (i = 0; i < nbars; i++, pos += 8) {
3609 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3610 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3619 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3621 * @bar: BAR to query
3623 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3624 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3626 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3631 pos = pci_rebar_find_pos(pdev, bar);
3635 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3636 cap &= PCI_REBAR_CAP_SIZES;
3638 /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3639 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
3640 bar == 0 && cap == 0x7000)
3645 EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
3648 * pci_rebar_get_current_size - get the current size of a BAR
3650 * @bar: BAR to set size to
3652 * Read the size of a BAR from the resizable BAR config.
3653 * Returns size if found or negative error code.
3655 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3660 pos = pci_rebar_find_pos(pdev, bar);
3664 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3665 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
3669 * pci_rebar_set_size - set a new size for a BAR
3671 * @bar: BAR to set size to
3672 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3674 * Set the new size of a BAR as defined in the spec.
3675 * Returns zero if resizing was successful, error code otherwise.
3677 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3682 pos = pci_rebar_find_pos(pdev, bar);
3686 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3687 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3688 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
3689 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3694 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3695 * @dev: the PCI device
3696 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3697 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3698 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3699 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3701 * Return 0 if all upstream bridges support AtomicOp routing, egress
3702 * blocking is disabled on all upstream ports, and the root port supports
3703 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3704 * AtomicOp completion), or negative otherwise.
3706 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3708 struct pci_bus *bus = dev->bus;
3709 struct pci_dev *bridge;
3712 if (!pci_is_pcie(dev))
3716 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3717 * AtomicOp requesters. For now, we only support endpoints as
3718 * requesters and root ports as completers. No endpoints as
3719 * completers, and no peer-to-peer.
3722 switch (pci_pcie_type(dev)) {
3723 case PCI_EXP_TYPE_ENDPOINT:
3724 case PCI_EXP_TYPE_LEG_END:
3725 case PCI_EXP_TYPE_RC_END:
3731 while (bus->parent) {
3734 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3736 switch (pci_pcie_type(bridge)) {
3737 /* Ensure switch ports support AtomicOp routing */
3738 case PCI_EXP_TYPE_UPSTREAM:
3739 case PCI_EXP_TYPE_DOWNSTREAM:
3740 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3744 /* Ensure root port supports all the sizes we care about */
3745 case PCI_EXP_TYPE_ROOT_PORT:
3746 if ((cap & cap_mask) != cap_mask)
3751 /* Ensure upstream ports don't block AtomicOps on egress */
3752 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3753 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3755 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3762 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3763 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3766 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3769 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3770 * @dev: the PCI device
3771 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3773 * Perform INTx swizzling for a device behind one level of bridge. This is
3774 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3775 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3776 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3777 * the PCI Express Base Specification, Revision 2.1)
3779 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3783 if (pci_ari_enabled(dev->bus))
3786 slot = PCI_SLOT(dev->devfn);
3788 return (((pin - 1) + slot) % 4) + 1;
3791 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3799 while (!pci_is_root_bus(dev->bus)) {
3800 pin = pci_swizzle_interrupt_pin(dev, pin);
3801 dev = dev->bus->self;
3808 * pci_common_swizzle - swizzle INTx all the way to root bridge
3809 * @dev: the PCI device
3810 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3812 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3813 * bridges all the way up to a PCI root bus.
3815 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3819 while (!pci_is_root_bus(dev->bus)) {
3820 pin = pci_swizzle_interrupt_pin(dev, pin);
3821 dev = dev->bus->self;
3824 return PCI_SLOT(dev->devfn);
3826 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3829 * pci_release_region - Release a PCI bar
3830 * @pdev: PCI device whose resources were previously reserved by
3831 * pci_request_region()
3832 * @bar: BAR to release
3834 * Releases the PCI I/O and memory resources previously reserved by a
3835 * successful call to pci_request_region(). Call this function only
3836 * after all use of the PCI regions has ceased.
3838 void pci_release_region(struct pci_dev *pdev, int bar)
3840 struct pci_devres *dr;
3842 if (pci_resource_len(pdev, bar) == 0)
3844 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3845 release_region(pci_resource_start(pdev, bar),
3846 pci_resource_len(pdev, bar));
3847 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3848 release_mem_region(pci_resource_start(pdev, bar),
3849 pci_resource_len(pdev, bar));
3851 dr = find_pci_dr(pdev);
3853 dr->region_mask &= ~(1 << bar);
3855 EXPORT_SYMBOL(pci_release_region);
3858 * __pci_request_region - Reserved PCI I/O and memory resource
3859 * @pdev: PCI device whose resources are to be reserved
3860 * @bar: BAR to be reserved
3861 * @res_name: Name to be associated with resource.
3862 * @exclusive: whether the region access is exclusive or not
3864 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3865 * being reserved by owner @res_name. Do not access any
3866 * address inside the PCI regions unless this call returns
3869 * If @exclusive is set, then the region is marked so that userspace
3870 * is explicitly not allowed to map the resource via /dev/mem or
3871 * sysfs MMIO access.
3873 * Returns 0 on success, or %EBUSY on error. A warning
3874 * message is also printed on failure.
3876 static int __pci_request_region(struct pci_dev *pdev, int bar,
3877 const char *res_name, int exclusive)
3879 struct pci_devres *dr;
3881 if (pci_resource_len(pdev, bar) == 0)
3884 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3885 if (!request_region(pci_resource_start(pdev, bar),
3886 pci_resource_len(pdev, bar), res_name))
3888 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3889 if (!__request_mem_region(pci_resource_start(pdev, bar),
3890 pci_resource_len(pdev, bar), res_name,
3895 dr = find_pci_dr(pdev);
3897 dr->region_mask |= 1 << bar;
3902 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3903 &pdev->resource[bar]);
3908 * pci_request_region - Reserve PCI I/O and memory resource
3909 * @pdev: PCI device whose resources are to be reserved
3910 * @bar: BAR to be reserved
3911 * @res_name: Name to be associated with resource
3913 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3914 * being reserved by owner @res_name. Do not access any
3915 * address inside the PCI regions unless this call returns
3918 * Returns 0 on success, or %EBUSY on error. A warning
3919 * message is also printed on failure.
3921 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3923 return __pci_request_region(pdev, bar, res_name, 0);
3925 EXPORT_SYMBOL(pci_request_region);
3928 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3929 * @pdev: PCI device whose resources were previously reserved
3930 * @bars: Bitmask of BARs to be released
3932 * Release selected PCI I/O and memory resources previously reserved.
3933 * Call this function only after all use of the PCI regions has ceased.
3935 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3939 for (i = 0; i < PCI_STD_NUM_BARS; i++)
3940 if (bars & (1 << i))
3941 pci_release_region(pdev, i);
3943 EXPORT_SYMBOL(pci_release_selected_regions);
3945 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3946 const char *res_name, int excl)
3950 for (i = 0; i < PCI_STD_NUM_BARS; i++)
3951 if (bars & (1 << i))
3952 if (__pci_request_region(pdev, i, res_name, excl))
3958 if (bars & (1 << i))
3959 pci_release_region(pdev, i);
3966 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3967 * @pdev: PCI device whose resources are to be reserved
3968 * @bars: Bitmask of BARs to be requested
3969 * @res_name: Name to be associated with resource
3971 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3972 const char *res_name)
3974 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3976 EXPORT_SYMBOL(pci_request_selected_regions);
3978 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3979 const char *res_name)
3981 return __pci_request_selected_regions(pdev, bars, res_name,
3982 IORESOURCE_EXCLUSIVE);
3984 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3987 * pci_release_regions - Release reserved PCI I/O and memory resources
3988 * @pdev: PCI device whose resources were previously reserved by
3989 * pci_request_regions()
3991 * Releases all PCI I/O and memory resources previously reserved by a
3992 * successful call to pci_request_regions(). Call this function only
3993 * after all use of the PCI regions has ceased.
3996 void pci_release_regions(struct pci_dev *pdev)
3998 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
4000 EXPORT_SYMBOL(pci_release_regions);
4003 * pci_request_regions - Reserve PCI I/O and memory resources
4004 * @pdev: PCI device whose resources are to be reserved
4005 * @res_name: Name to be associated with resource.
4007 * Mark all PCI regions associated with PCI device @pdev as
4008 * being reserved by owner @res_name. Do not access any
4009 * address inside the PCI regions unless this call returns
4012 * Returns 0 on success, or %EBUSY on error. A warning
4013 * message is also printed on failure.
4015 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
4017 return pci_request_selected_regions(pdev,
4018 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4020 EXPORT_SYMBOL(pci_request_regions);
4023 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4024 * @pdev: PCI device whose resources are to be reserved
4025 * @res_name: Name to be associated with resource.
4027 * Mark all PCI regions associated with PCI device @pdev as being reserved
4028 * by owner @res_name. Do not access any address inside the PCI regions
4029 * unless this call returns successfully.
4031 * pci_request_regions_exclusive() will mark the region so that /dev/mem
4032 * and the sysfs MMIO access will not be allowed.
4034 * Returns 0 on success, or %EBUSY on error. A warning message is also
4035 * printed on failure.
4037 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
4039 return pci_request_selected_regions_exclusive(pdev,
4040 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4042 EXPORT_SYMBOL(pci_request_regions_exclusive);
4045 * Record the PCI IO range (expressed as CPU physical address + size).
4046 * Return a negative value if an error has occurred, zero otherwise
4048 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
4049 resource_size_t size)
4053 struct logic_pio_hwaddr *range;
4055 if (!size || addr + size < addr)
4058 range = kzalloc(sizeof(*range), GFP_ATOMIC);
4062 range->fwnode = fwnode;
4064 range->hw_start = addr;
4065 range->flags = LOGIC_PIO_CPU_MMIO;
4067 ret = logic_pio_register_range(range);
4071 /* Ignore duplicates due to deferred probing */
4079 phys_addr_t pci_pio_to_address(unsigned long pio)
4081 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
4084 if (pio >= MMIO_UPPER_LIMIT)
4087 address = logic_pio_to_hwaddr(pio);
4092 EXPORT_SYMBOL_GPL(pci_pio_to_address);
4094 unsigned long __weak pci_address_to_pio(phys_addr_t address)
4097 return logic_pio_trans_cpuaddr(address);
4099 if (address > IO_SPACE_LIMIT)
4100 return (unsigned long)-1;
4102 return (unsigned long) address;
4107 * pci_remap_iospace - Remap the memory mapped I/O space
4108 * @res: Resource describing the I/O space
4109 * @phys_addr: physical address of range to be mapped
4111 * Remap the memory mapped I/O space described by the @res and the CPU
4112 * physical address @phys_addr into virtual address space. Only
4113 * architectures that have memory mapped IO functions defined (and the
4114 * PCI_IOBASE value defined) should call this function.
4116 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
4118 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4119 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4121 if (!(res->flags & IORESOURCE_IO))
4124 if (res->end > IO_SPACE_LIMIT)
4127 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
4128 pgprot_device(PAGE_KERNEL));
4131 * This architecture does not have memory mapped I/O space,
4132 * so this function should never be called
4134 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4138 EXPORT_SYMBOL(pci_remap_iospace);
4141 * pci_unmap_iospace - Unmap the memory mapped I/O space
4142 * @res: resource to be unmapped
4144 * Unmap the CPU virtual address @res from virtual address space. Only
4145 * architectures that have memory mapped IO functions defined (and the
4146 * PCI_IOBASE value defined) should call this function.
4148 void pci_unmap_iospace(struct resource *res)
4150 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4151 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4153 vunmap_range(vaddr, vaddr + resource_size(res));
4156 EXPORT_SYMBOL(pci_unmap_iospace);
4158 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4160 struct resource **res = ptr;
4162 pci_unmap_iospace(*res);
4166 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4167 * @dev: Generic device to remap IO address for
4168 * @res: Resource describing the I/O space
4169 * @phys_addr: physical address of range to be mapped
4171 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4174 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4175 phys_addr_t phys_addr)
4177 const struct resource **ptr;
4180 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4184 error = pci_remap_iospace(res, phys_addr);
4189 devres_add(dev, ptr);
4194 EXPORT_SYMBOL(devm_pci_remap_iospace);
4197 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4198 * @dev: Generic device to remap IO address for
4199 * @offset: Resource address to map
4200 * @size: Size of map
4202 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4205 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4206 resource_size_t offset,
4207 resource_size_t size)
4209 void __iomem **ptr, *addr;
4211 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4215 addr = pci_remap_cfgspace(offset, size);
4218 devres_add(dev, ptr);
4224 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4227 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4228 * @dev: generic device to handle the resource for
4229 * @res: configuration space resource to be handled
4231 * Checks that a resource is a valid memory region, requests the memory
4232 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4233 * proper PCI configuration space memory attributes are guaranteed.
4235 * All operations are managed and will be undone on driver detach.
4237 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4238 * on failure. Usage example::
4240 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4241 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4243 * return PTR_ERR(base);
4245 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4246 struct resource *res)
4248 resource_size_t size;
4250 void __iomem *dest_ptr;
4254 if (!res || resource_type(res) != IORESOURCE_MEM) {
4255 dev_err(dev, "invalid resource\n");
4256 return IOMEM_ERR_PTR(-EINVAL);
4259 size = resource_size(res);
4262 name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),
4265 name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
4267 return IOMEM_ERR_PTR(-ENOMEM);
4269 if (!devm_request_mem_region(dev, res->start, size, name)) {
4270 dev_err(dev, "can't request region for resource %pR\n", res);
4271 return IOMEM_ERR_PTR(-EBUSY);
4274 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4276 dev_err(dev, "ioremap failed for resource %pR\n", res);
4277 devm_release_mem_region(dev, res->start, size);
4278 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4283 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4285 static void __pci_set_master(struct pci_dev *dev, bool enable)
4289 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4291 cmd = old_cmd | PCI_COMMAND_MASTER;
4293 cmd = old_cmd & ~PCI_COMMAND_MASTER;
4294 if (cmd != old_cmd) {
4295 pci_dbg(dev, "%s bus mastering\n",
4296 enable ? "enabling" : "disabling");
4297 pci_write_config_word(dev, PCI_COMMAND, cmd);
4299 dev->is_busmaster = enable;
4303 * pcibios_setup - process "pci=" kernel boot arguments
4304 * @str: string used to pass in "pci=" kernel boot arguments
4306 * Process kernel boot arguments. This is the default implementation.
4307 * Architecture specific implementations can override this as necessary.
4309 char * __weak __init pcibios_setup(char *str)
4315 * pcibios_set_master - enable PCI bus-mastering for device dev
4316 * @dev: the PCI device to enable
4318 * Enables PCI bus-mastering for the device. This is the default
4319 * implementation. Architecture specific implementations can override
4320 * this if necessary.
4322 void __weak pcibios_set_master(struct pci_dev *dev)
4326 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4327 if (pci_is_pcie(dev))
4330 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4332 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4333 else if (lat > pcibios_max_latency)
4334 lat = pcibios_max_latency;
4338 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4342 * pci_set_master - enables bus-mastering for device dev
4343 * @dev: the PCI device to enable
4345 * Enables bus-mastering on the device and calls pcibios_set_master()
4346 * to do the needed arch specific settings.
4348 void pci_set_master(struct pci_dev *dev)
4350 __pci_set_master(dev, true);
4351 pcibios_set_master(dev);
4353 EXPORT_SYMBOL(pci_set_master);
4356 * pci_clear_master - disables bus-mastering for device dev
4357 * @dev: the PCI device to disable
4359 void pci_clear_master(struct pci_dev *dev)
4361 __pci_set_master(dev, false);
4363 EXPORT_SYMBOL(pci_clear_master);
4366 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4367 * @dev: the PCI device for which MWI is to be enabled
4369 * Helper function for pci_set_mwi.
4370 * Originally copied from drivers/net/acenic.c.
4371 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4373 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4375 int pci_set_cacheline_size(struct pci_dev *dev)
4379 if (!pci_cache_line_size)
4382 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4383 equal to or multiple of the right value. */
4384 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4385 if (cacheline_size >= pci_cache_line_size &&
4386 (cacheline_size % pci_cache_line_size) == 0)
4389 /* Write the correct value. */
4390 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4392 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4393 if (cacheline_size == pci_cache_line_size)
4396 pci_dbg(dev, "cache line size of %d is not supported\n",
4397 pci_cache_line_size << 2);
4401 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4404 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4405 * @dev: the PCI device for which MWI is enabled
4407 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4409 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4411 int pci_set_mwi(struct pci_dev *dev)
4413 #ifdef PCI_DISABLE_MWI
4419 rc = pci_set_cacheline_size(dev);
4423 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4424 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4425 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4426 cmd |= PCI_COMMAND_INVALIDATE;
4427 pci_write_config_word(dev, PCI_COMMAND, cmd);
4432 EXPORT_SYMBOL(pci_set_mwi);
4435 * pcim_set_mwi - a device-managed pci_set_mwi()
4436 * @dev: the PCI device for which MWI is enabled
4438 * Managed pci_set_mwi().
4440 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4442 int pcim_set_mwi(struct pci_dev *dev)
4444 struct pci_devres *dr;
4446 dr = find_pci_dr(dev);
4451 return pci_set_mwi(dev);
4453 EXPORT_SYMBOL(pcim_set_mwi);
4456 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4457 * @dev: the PCI device for which MWI is enabled
4459 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4460 * Callers are not required to check the return value.
4462 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4464 int pci_try_set_mwi(struct pci_dev *dev)
4466 #ifdef PCI_DISABLE_MWI
4469 return pci_set_mwi(dev);
4472 EXPORT_SYMBOL(pci_try_set_mwi);
4475 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4476 * @dev: the PCI device to disable
4478 * Disables PCI Memory-Write-Invalidate transaction on the device
4480 void pci_clear_mwi(struct pci_dev *dev)
4482 #ifndef PCI_DISABLE_MWI
4485 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4486 if (cmd & PCI_COMMAND_INVALIDATE) {
4487 cmd &= ~PCI_COMMAND_INVALIDATE;
4488 pci_write_config_word(dev, PCI_COMMAND, cmd);
4492 EXPORT_SYMBOL(pci_clear_mwi);
4495 * pci_disable_parity - disable parity checking for device
4496 * @dev: the PCI device to operate on
4498 * Disable parity checking for device @dev
4500 void pci_disable_parity(struct pci_dev *dev)
4504 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4505 if (cmd & PCI_COMMAND_PARITY) {
4506 cmd &= ~PCI_COMMAND_PARITY;
4507 pci_write_config_word(dev, PCI_COMMAND, cmd);
4512 * pci_intx - enables/disables PCI INTx for device dev
4513 * @pdev: the PCI device to operate on
4514 * @enable: boolean: whether to enable or disable PCI INTx
4516 * Enables/disables PCI INTx for device @pdev
4518 void pci_intx(struct pci_dev *pdev, int enable)
4520 u16 pci_command, new;
4522 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4525 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4527 new = pci_command | PCI_COMMAND_INTX_DISABLE;
4529 if (new != pci_command) {
4530 struct pci_devres *dr;
4532 pci_write_config_word(pdev, PCI_COMMAND, new);
4534 dr = find_pci_dr(pdev);
4535 if (dr && !dr->restore_intx) {
4536 dr->restore_intx = 1;
4537 dr->orig_intx = !enable;
4541 EXPORT_SYMBOL_GPL(pci_intx);
4543 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4545 struct pci_bus *bus = dev->bus;
4546 bool mask_updated = true;
4547 u32 cmd_status_dword;
4548 u16 origcmd, newcmd;
4549 unsigned long flags;
4553 * We do a single dword read to retrieve both command and status.
4554 * Document assumptions that make this possible.
4556 BUILD_BUG_ON(PCI_COMMAND % 4);
4557 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4559 raw_spin_lock_irqsave(&pci_lock, flags);
4561 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4563 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4566 * Check interrupt status register to see whether our device
4567 * triggered the interrupt (when masking) or the next IRQ is
4568 * already pending (when unmasking).
4570 if (mask != irq_pending) {
4571 mask_updated = false;
4575 origcmd = cmd_status_dword;
4576 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4578 newcmd |= PCI_COMMAND_INTX_DISABLE;
4579 if (newcmd != origcmd)
4580 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4583 raw_spin_unlock_irqrestore(&pci_lock, flags);
4585 return mask_updated;
4589 * pci_check_and_mask_intx - mask INTx on pending interrupt
4590 * @dev: the PCI device to operate on
4592 * Check if the device dev has its INTx line asserted, mask it and return
4593 * true in that case. False is returned if no interrupt was pending.
4595 bool pci_check_and_mask_intx(struct pci_dev *dev)
4597 return pci_check_and_set_intx_mask(dev, true);
4599 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4602 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4603 * @dev: the PCI device to operate on
4605 * Check if the device dev has its INTx line asserted, unmask it if not and
4606 * return true. False is returned and the mask remains active if there was
4607 * still an interrupt pending.
4609 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4611 return pci_check_and_set_intx_mask(dev, false);
4613 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4616 * pci_wait_for_pending_transaction - wait for pending transaction
4617 * @dev: the PCI device to operate on
4619 * Return 0 if transaction is pending 1 otherwise.
4621 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4623 if (!pci_is_pcie(dev))
4626 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4627 PCI_EXP_DEVSTA_TRPND);
4629 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4632 * pcie_has_flr - check if a device supports function level resets
4633 * @dev: device to check
4635 * Returns true if the device advertises support for PCIe function level
4638 bool pcie_has_flr(struct pci_dev *dev)
4642 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4645 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
4646 return cap & PCI_EXP_DEVCAP_FLR;
4648 EXPORT_SYMBOL_GPL(pcie_has_flr);
4651 * pcie_flr - initiate a PCIe function level reset
4652 * @dev: device to reset
4654 * Initiate a function level reset on @dev. The caller should ensure the
4655 * device supports FLR before calling this function, e.g. by using the
4656 * pcie_has_flr() helper.
4658 int pcie_flr(struct pci_dev *dev)
4660 if (!pci_wait_for_pending_transaction(dev))
4661 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4663 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4669 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4670 * 100ms, but may silently discard requests while the FLR is in
4671 * progress. Wait 100ms before trying to access the device.
4675 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4677 EXPORT_SYMBOL_GPL(pcie_flr);
4679 static int pci_af_flr(struct pci_dev *dev, int probe)
4684 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4688 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4691 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4692 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4699 * Wait for Transaction Pending bit to clear. A word-aligned test
4700 * is used, so we use the control offset rather than status and shift
4701 * the test bit to match.
4703 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4704 PCI_AF_STATUS_TP << 8))
4705 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4707 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4713 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4714 * updated 27 July 2006; a device must complete an FLR within
4715 * 100ms, but may silently discard requests while the FLR is in
4716 * progress. Wait 100ms before trying to access the device.
4720 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4724 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4725 * @dev: Device to reset.
4726 * @probe: If set, only check if the device can be reset this way.
4728 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4729 * unset, it will be reinitialized internally when going from PCI_D3hot to
4730 * PCI_D0. If that's the case and the device is not in a low-power state
4731 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4733 * NOTE: This causes the caller to sleep for twice the device power transition
4734 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4735 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4736 * Moreover, only devices in D0 can be reset by this function.
4738 static int pci_pm_reset(struct pci_dev *dev, int probe)
4742 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4745 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4746 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4752 if (dev->current_state != PCI_D0)
4755 csr &= ~PCI_PM_CTRL_STATE_MASK;
4757 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4758 pci_dev_d3_sleep(dev);
4760 csr &= ~PCI_PM_CTRL_STATE_MASK;
4762 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4763 pci_dev_d3_sleep(dev);
4765 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
4769 * pcie_wait_for_link_delay - Wait until link is active or inactive
4770 * @pdev: Bridge device
4771 * @active: waiting for active or inactive?
4772 * @delay: Delay to wait after link has become active (in ms)
4774 * Use this to wait till link becomes active or inactive.
4776 static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
4784 * Some controllers might not implement link active reporting. In this
4785 * case, we wait for 1000 ms + any delay requested by the caller.
4787 if (!pdev->link_active_reporting) {
4788 msleep(timeout + delay);
4793 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4794 * after which we should expect an link active if the reset was
4795 * successful. If so, software must wait a minimum 100ms before sending
4796 * configuration requests to devices downstream this port.
4798 * If the link fails to activate, either the device was physically
4799 * removed or the link is permanently failed.
4804 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4805 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4816 return ret == active;
4820 * pcie_wait_for_link - Wait until link is active or inactive
4821 * @pdev: Bridge device
4822 * @active: waiting for active or inactive?
4824 * Use this to wait till link becomes active or inactive.
4826 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4828 return pcie_wait_for_link_delay(pdev, active, 100);
4832 * Find maximum D3cold delay required by all the devices on the bus. The
4833 * spec says 100 ms, but firmware can lower it and we allow drivers to
4834 * increase it as well.
4836 * Called with @pci_bus_sem locked for reading.
4838 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
4840 const struct pci_dev *pdev;
4841 int min_delay = 100;
4844 list_for_each_entry(pdev, &bus->devices, bus_list) {
4845 if (pdev->d3cold_delay < min_delay)
4846 min_delay = pdev->d3cold_delay;
4847 if (pdev->d3cold_delay > max_delay)
4848 max_delay = pdev->d3cold_delay;
4851 return max(min_delay, max_delay);
4855 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4858 * Handle necessary delays before access to the devices on the secondary
4859 * side of the bridge are permitted after D3cold to D0 transition.
4861 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
4862 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4865 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)
4867 struct pci_dev *child;
4870 if (pci_dev_is_disconnected(dev))
4873 if (!pci_is_bridge(dev) || !dev->bridge_d3)
4876 down_read(&pci_bus_sem);
4879 * We only deal with devices that are present currently on the bus.
4880 * For any hot-added devices the access delay is handled in pciehp
4881 * board_added(). In case of ACPI hotplug the firmware is expected
4882 * to configure the devices before OS is notified.
4884 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
4885 up_read(&pci_bus_sem);
4889 /* Take d3cold_delay requirements into account */
4890 delay = pci_bus_max_d3cold_delay(dev->subordinate);
4892 up_read(&pci_bus_sem);
4896 child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
4898 up_read(&pci_bus_sem);
4901 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4902 * accessing the device after reset (that is 1000 ms + 100 ms). In
4903 * practice this should not be needed because we don't do power
4904 * management for them (see pci_bridge_d3_possible()).
4906 if (!pci_is_pcie(dev)) {
4907 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
4908 msleep(1000 + delay);
4913 * For PCIe downstream and root ports that do not support speeds
4914 * greater than 5 GT/s need to wait minimum 100 ms. For higher
4915 * speeds (gen3) we need to wait first for the data link layer to
4918 * However, 100 ms is the minimum and the PCIe spec says the
4919 * software must allow at least 1s before it can determine that the
4920 * device that did not respond is a broken device. There is
4921 * evidence that 100 ms is not always enough, for example certain
4922 * Titan Ridge xHCI controller does not always respond to
4923 * configuration requests if we only wait for 100 ms (see
4924 * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
4926 * Therefore we wait for 100 ms and check for the device presence.
4927 * If it is still not present give it an additional 100 ms.
4929 if (!pcie_downstream_port(dev))
4932 if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
4933 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
4936 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
4938 if (!pcie_wait_for_link_delay(dev, true, delay)) {
4939 /* Did not train, no need to wait any further */
4940 pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
4945 if (!pci_device_is_present(child)) {
4946 pci_dbg(child, "waiting additional %d ms to become accessible\n", delay);
4951 void pci_reset_secondary_bus(struct pci_dev *dev)
4955 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4956 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4957 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4960 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4961 * this to 2ms to ensure that we meet the minimum requirement.
4965 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
4966 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4969 * Trhfa for conventional PCI is 2^25 clock cycles.
4970 * Assuming a minimum 33MHz clock this results in a 1s
4971 * delay before we can consider subordinate devices to
4972 * be re-initialized. PCIe has some ways to shorten this,
4973 * but we don't make use of them yet.
4978 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4980 pci_reset_secondary_bus(dev);
4984 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
4985 * @dev: Bridge device
4987 * Use the bridge control register to assert reset on the secondary bus.
4988 * Devices on the secondary bus are left in power-on state.
4990 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
4992 pcibios_reset_secondary_bus(dev);
4994 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
4996 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
4998 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
5000 struct pci_dev *pdev;
5002 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
5003 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5006 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
5013 return pci_bridge_secondary_bus_reset(dev->bus->self);
5016 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
5020 if (!hotplug || !try_module_get(hotplug->owner))
5023 if (hotplug->ops->reset_slot)
5024 rc = hotplug->ops->reset_slot(hotplug, probe);
5026 module_put(hotplug->owner);
5031 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
5033 if (dev->multifunction || dev->subordinate || !dev->slot ||
5034 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5037 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
5040 static int pci_reset_bus_function(struct pci_dev *dev, int probe)
5044 rc = pci_dev_reset_slot_function(dev, probe);
5047 return pci_parent_bus_reset(dev, probe);
5050 static void pci_dev_lock(struct pci_dev *dev)
5052 pci_cfg_access_lock(dev);
5053 /* block PM suspend, driver probe, etc. */
5054 device_lock(&dev->dev);
5057 /* Return 1 on successful lock, 0 on contention */
5058 int pci_dev_trylock(struct pci_dev *dev)
5060 if (pci_cfg_access_trylock(dev)) {
5061 if (device_trylock(&dev->dev))
5063 pci_cfg_access_unlock(dev);
5068 EXPORT_SYMBOL_GPL(pci_dev_trylock);
5070 void pci_dev_unlock(struct pci_dev *dev)
5072 device_unlock(&dev->dev);
5073 pci_cfg_access_unlock(dev);
5075 EXPORT_SYMBOL_GPL(pci_dev_unlock);
5077 static void pci_dev_save_and_disable(struct pci_dev *dev)
5079 const struct pci_error_handlers *err_handler =
5080 dev->driver ? dev->driver->err_handler : NULL;
5083 * dev->driver->err_handler->reset_prepare() is protected against
5084 * races with ->remove() by the device lock, which must be held by
5087 if (err_handler && err_handler->reset_prepare)
5088 err_handler->reset_prepare(dev);
5091 * Wake-up device prior to save. PM registers default to D0 after
5092 * reset and a simple register restore doesn't reliably return
5093 * to a non-D0 state anyway.
5095 pci_set_power_state(dev, PCI_D0);
5097 pci_save_state(dev);
5099 * Disable the device by clearing the Command register, except for
5100 * INTx-disable which is set. This not only disables MMIO and I/O port
5101 * BARs, but also prevents the device from being Bus Master, preventing
5102 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
5103 * compliant devices, INTx-disable prevents legacy interrupts.
5105 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
5108 static void pci_dev_restore(struct pci_dev *dev)
5110 const struct pci_error_handlers *err_handler =
5111 dev->driver ? dev->driver->err_handler : NULL;
5113 pci_restore_state(dev);
5116 * dev->driver->err_handler->reset_done() is protected against
5117 * races with ->remove() by the device lock, which must be held by
5120 if (err_handler && err_handler->reset_done)
5121 err_handler->reset_done(dev);
5125 * __pci_reset_function_locked - reset a PCI device function while holding
5126 * the @dev mutex lock.
5127 * @dev: PCI device to reset
5129 * Some devices allow an individual function to be reset without affecting
5130 * other functions in the same device. The PCI device must be responsive
5131 * to PCI config space in order to use this function.
5133 * The device function is presumed to be unused and the caller is holding
5134 * the device mutex lock when this function is called.
5136 * Resetting the device will make the contents of PCI configuration space
5137 * random, so any caller of this must be prepared to reinitialise the
5138 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5141 * Returns 0 if the device function was successfully reset or negative if the
5142 * device doesn't support resetting a single function.
5144 int __pci_reset_function_locked(struct pci_dev *dev)
5151 * A reset method returns -ENOTTY if it doesn't support this device
5152 * and we should try the next method.
5154 * If it returns 0 (success), we're finished. If it returns any
5155 * other error, we're also finished: this indicates that further
5156 * reset mechanisms might be broken on the device.
5158 rc = pci_dev_specific_reset(dev, 0);
5161 if (pcie_has_flr(dev)) {
5166 rc = pci_af_flr(dev, 0);
5169 rc = pci_pm_reset(dev, 0);
5172 return pci_reset_bus_function(dev, 0);
5174 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
5177 * pci_probe_reset_function - check whether the device can be safely reset
5178 * @dev: PCI device to reset
5180 * Some devices allow an individual function to be reset without affecting
5181 * other functions in the same device. The PCI device must be responsive
5182 * to PCI config space in order to use this function.
5184 * Returns 0 if the device function can be reset or negative if the
5185 * device doesn't support resetting a single function.
5187 int pci_probe_reset_function(struct pci_dev *dev)
5193 rc = pci_dev_specific_reset(dev, 1);
5196 if (pcie_has_flr(dev))
5198 rc = pci_af_flr(dev, 1);
5201 rc = pci_pm_reset(dev, 1);
5205 return pci_reset_bus_function(dev, 1);
5209 * pci_reset_function - quiesce and reset a PCI device function
5210 * @dev: PCI device to reset
5212 * Some devices allow an individual function to be reset without affecting
5213 * other functions in the same device. The PCI device must be responsive
5214 * to PCI config space in order to use this function.
5216 * This function does not just reset the PCI portion of a device, but
5217 * clears all the state associated with the device. This function differs
5218 * from __pci_reset_function_locked() in that it saves and restores device state
5219 * over the reset and takes the PCI device lock.
5221 * Returns 0 if the device function was successfully reset or negative if the
5222 * device doesn't support resetting a single function.
5224 int pci_reset_function(struct pci_dev *dev)
5232 pci_dev_save_and_disable(dev);
5234 rc = __pci_reset_function_locked(dev);
5236 pci_dev_restore(dev);
5237 pci_dev_unlock(dev);
5241 EXPORT_SYMBOL_GPL(pci_reset_function);
5244 * pci_reset_function_locked - quiesce and reset a PCI device function
5245 * @dev: PCI device to reset
5247 * Some devices allow an individual function to be reset without affecting
5248 * other functions in the same device. The PCI device must be responsive
5249 * to PCI config space in order to use this function.
5251 * This function does not just reset the PCI portion of a device, but
5252 * clears all the state associated with the device. This function differs
5253 * from __pci_reset_function_locked() in that it saves and restores device state
5254 * over the reset. It also differs from pci_reset_function() in that it
5255 * requires the PCI device lock to be held.
5257 * Returns 0 if the device function was successfully reset or negative if the
5258 * device doesn't support resetting a single function.
5260 int pci_reset_function_locked(struct pci_dev *dev)
5267 pci_dev_save_and_disable(dev);
5269 rc = __pci_reset_function_locked(dev);
5271 pci_dev_restore(dev);
5275 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
5278 * pci_try_reset_function - quiesce and reset a PCI device function
5279 * @dev: PCI device to reset
5281 * Same as above, except return -EAGAIN if unable to lock device.
5283 int pci_try_reset_function(struct pci_dev *dev)
5290 if (!pci_dev_trylock(dev))
5293 pci_dev_save_and_disable(dev);
5294 rc = __pci_reset_function_locked(dev);
5295 pci_dev_restore(dev);
5296 pci_dev_unlock(dev);
5300 EXPORT_SYMBOL_GPL(pci_try_reset_function);
5302 /* Do any devices on or below this bus prevent a bus reset? */
5303 static bool pci_bus_resetable(struct pci_bus *bus)
5305 struct pci_dev *dev;
5308 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5311 list_for_each_entry(dev, &bus->devices, bus_list) {
5312 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5313 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5320 /* Lock devices from the top of the tree down */
5321 static void pci_bus_lock(struct pci_bus *bus)
5323 struct pci_dev *dev;
5325 list_for_each_entry(dev, &bus->devices, bus_list) {
5327 if (dev->subordinate)
5328 pci_bus_lock(dev->subordinate);
5332 /* Unlock devices from the bottom of the tree up */
5333 static void pci_bus_unlock(struct pci_bus *bus)
5335 struct pci_dev *dev;
5337 list_for_each_entry(dev, &bus->devices, bus_list) {
5338 if (dev->subordinate)
5339 pci_bus_unlock(dev->subordinate);
5340 pci_dev_unlock(dev);
5344 /* Return 1 on successful lock, 0 on contention */
5345 static int pci_bus_trylock(struct pci_bus *bus)
5347 struct pci_dev *dev;
5349 list_for_each_entry(dev, &bus->devices, bus_list) {
5350 if (!pci_dev_trylock(dev))
5352 if (dev->subordinate) {
5353 if (!pci_bus_trylock(dev->subordinate)) {
5354 pci_dev_unlock(dev);
5362 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5363 if (dev->subordinate)
5364 pci_bus_unlock(dev->subordinate);
5365 pci_dev_unlock(dev);
5370 /* Do any devices on or below this slot prevent a bus reset? */
5371 static bool pci_slot_resetable(struct pci_slot *slot)
5373 struct pci_dev *dev;
5375 if (slot->bus->self &&
5376 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5379 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5380 if (!dev->slot || dev->slot != slot)
5382 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5383 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5390 /* Lock devices from the top of the tree down */
5391 static void pci_slot_lock(struct pci_slot *slot)
5393 struct pci_dev *dev;
5395 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5396 if (!dev->slot || dev->slot != slot)
5399 if (dev->subordinate)
5400 pci_bus_lock(dev->subordinate);
5404 /* Unlock devices from the bottom of the tree up */
5405 static void pci_slot_unlock(struct pci_slot *slot)
5407 struct pci_dev *dev;
5409 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5410 if (!dev->slot || dev->slot != slot)
5412 if (dev->subordinate)
5413 pci_bus_unlock(dev->subordinate);
5414 pci_dev_unlock(dev);
5418 /* Return 1 on successful lock, 0 on contention */
5419 static int pci_slot_trylock(struct pci_slot *slot)
5421 struct pci_dev *dev;
5423 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5424 if (!dev->slot || dev->slot != slot)
5426 if (!pci_dev_trylock(dev))
5428 if (dev->subordinate) {
5429 if (!pci_bus_trylock(dev->subordinate)) {
5430 pci_dev_unlock(dev);
5438 list_for_each_entry_continue_reverse(dev,
5439 &slot->bus->devices, bus_list) {
5440 if (!dev->slot || dev->slot != slot)
5442 if (dev->subordinate)
5443 pci_bus_unlock(dev->subordinate);
5444 pci_dev_unlock(dev);
5450 * Save and disable devices from the top of the tree down while holding
5451 * the @dev mutex lock for the entire tree.
5453 static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5455 struct pci_dev *dev;
5457 list_for_each_entry(dev, &bus->devices, bus_list) {
5458 pci_dev_save_and_disable(dev);
5459 if (dev->subordinate)
5460 pci_bus_save_and_disable_locked(dev->subordinate);
5465 * Restore devices from top of the tree down while holding @dev mutex lock
5466 * for the entire tree. Parent bridges need to be restored before we can
5467 * get to subordinate devices.
5469 static void pci_bus_restore_locked(struct pci_bus *bus)
5471 struct pci_dev *dev;
5473 list_for_each_entry(dev, &bus->devices, bus_list) {
5474 pci_dev_restore(dev);
5475 if (dev->subordinate)
5476 pci_bus_restore_locked(dev->subordinate);
5481 * Save and disable devices from the top of the tree down while holding
5482 * the @dev mutex lock for the entire tree.
5484 static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
5486 struct pci_dev *dev;
5488 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5489 if (!dev->slot || dev->slot != slot)
5491 pci_dev_save_and_disable(dev);
5492 if (dev->subordinate)
5493 pci_bus_save_and_disable_locked(dev->subordinate);
5498 * Restore devices from top of the tree down while holding @dev mutex lock
5499 * for the entire tree. Parent bridges need to be restored before we can
5500 * get to subordinate devices.
5502 static void pci_slot_restore_locked(struct pci_slot *slot)
5504 struct pci_dev *dev;
5506 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5507 if (!dev->slot || dev->slot != slot)
5509 pci_dev_restore(dev);
5510 if (dev->subordinate)
5511 pci_bus_restore_locked(dev->subordinate);
5515 static int pci_slot_reset(struct pci_slot *slot, int probe)
5519 if (!slot || !pci_slot_resetable(slot))
5523 pci_slot_lock(slot);
5527 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5530 pci_slot_unlock(slot);
5536 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5537 * @slot: PCI slot to probe
5539 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5541 int pci_probe_reset_slot(struct pci_slot *slot)
5543 return pci_slot_reset(slot, 1);
5545 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5548 * __pci_reset_slot - Try to reset a PCI slot
5549 * @slot: PCI slot to reset
5551 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5552 * independent of other slots. For instance, some slots may support slot power
5553 * control. In the case of a 1:1 bus to slot architecture, this function may
5554 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5555 * Generally a slot reset should be attempted before a bus reset. All of the
5556 * function of the slot and any subordinate buses behind the slot are reset
5557 * through this function. PCI config space of all devices in the slot and
5558 * behind the slot is saved before and restored after reset.
5560 * Same as above except return -EAGAIN if the slot cannot be locked
5562 static int __pci_reset_slot(struct pci_slot *slot)
5566 rc = pci_slot_reset(slot, 1);
5570 if (pci_slot_trylock(slot)) {
5571 pci_slot_save_and_disable_locked(slot);
5573 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
5574 pci_slot_restore_locked(slot);
5575 pci_slot_unlock(slot);
5582 static int pci_bus_reset(struct pci_bus *bus, int probe)
5586 if (!bus->self || !pci_bus_resetable(bus))
5596 ret = pci_bridge_secondary_bus_reset(bus->self);
5598 pci_bus_unlock(bus);
5604 * pci_bus_error_reset - reset the bridge's subordinate bus
5605 * @bridge: The parent device that connects to the bus to reset
5607 * This function will first try to reset the slots on this bus if the method is
5608 * available. If slot reset fails or is not available, this will fall back to a
5609 * secondary bus reset.
5611 int pci_bus_error_reset(struct pci_dev *bridge)
5613 struct pci_bus *bus = bridge->subordinate;
5614 struct pci_slot *slot;
5619 mutex_lock(&pci_slot_mutex);
5620 if (list_empty(&bus->slots))
5623 list_for_each_entry(slot, &bus->slots, list)
5624 if (pci_probe_reset_slot(slot))
5627 list_for_each_entry(slot, &bus->slots, list)
5628 if (pci_slot_reset(slot, 0))
5631 mutex_unlock(&pci_slot_mutex);
5634 mutex_unlock(&pci_slot_mutex);
5635 return pci_bus_reset(bridge->subordinate, 0);
5639 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5640 * @bus: PCI bus to probe
5642 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5644 int pci_probe_reset_bus(struct pci_bus *bus)
5646 return pci_bus_reset(bus, 1);
5648 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
5651 * __pci_reset_bus - Try to reset a PCI bus
5652 * @bus: top level PCI bus to reset
5654 * Same as above except return -EAGAIN if the bus cannot be locked
5656 static int __pci_reset_bus(struct pci_bus *bus)
5660 rc = pci_bus_reset(bus, 1);
5664 if (pci_bus_trylock(bus)) {
5665 pci_bus_save_and_disable_locked(bus);
5667 rc = pci_bridge_secondary_bus_reset(bus->self);
5668 pci_bus_restore_locked(bus);
5669 pci_bus_unlock(bus);
5677 * pci_reset_bus - Try to reset a PCI bus
5678 * @pdev: top level PCI device to reset via slot/bus
5680 * Same as above except return -EAGAIN if the bus cannot be locked
5682 int pci_reset_bus(struct pci_dev *pdev)
5684 return (!pci_probe_reset_slot(pdev->slot)) ?
5685 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
5687 EXPORT_SYMBOL_GPL(pci_reset_bus);
5690 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5691 * @dev: PCI device to query
5693 * Returns mmrbc: maximum designed memory read count in bytes or
5694 * appropriate error value.
5696 int pcix_get_max_mmrbc(struct pci_dev *dev)
5701 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5705 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5708 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5710 EXPORT_SYMBOL(pcix_get_max_mmrbc);
5713 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5714 * @dev: PCI device to query
5716 * Returns mmrbc: maximum memory read count in bytes or appropriate error
5719 int pcix_get_mmrbc(struct pci_dev *dev)
5724 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5728 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5731 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5733 EXPORT_SYMBOL(pcix_get_mmrbc);
5736 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5737 * @dev: PCI device to query
5738 * @mmrbc: maximum memory read count in bytes
5739 * valid values are 512, 1024, 2048, 4096
5741 * If possible sets maximum memory read byte count, some bridges have errata
5742 * that prevent this.
5744 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5750 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5753 v = ffs(mmrbc) - 10;
5755 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5759 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5762 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5765 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5768 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5770 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5773 cmd &= ~PCI_X_CMD_MAX_READ;
5775 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5780 EXPORT_SYMBOL(pcix_set_mmrbc);
5783 * pcie_get_readrq - get PCI Express read request size
5784 * @dev: PCI device to query
5786 * Returns maximum memory read request in bytes or appropriate error value.
5788 int pcie_get_readrq(struct pci_dev *dev)
5792 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5794 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5796 EXPORT_SYMBOL(pcie_get_readrq);
5799 * pcie_set_readrq - set PCI Express maximum memory read request
5800 * @dev: PCI device to query
5801 * @rq: maximum memory read count in bytes
5802 * valid values are 128, 256, 512, 1024, 2048, 4096
5804 * If possible sets maximum memory read request in bytes
5806 int pcie_set_readrq(struct pci_dev *dev, int rq)
5811 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5815 * If using the "performance" PCIe config, we clamp the read rq
5816 * size to the max packet size to keep the host bridge from
5817 * generating requests larger than we can cope with.
5819 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5820 int mps = pcie_get_mps(dev);
5826 v = (ffs(rq) - 8) << 12;
5828 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5829 PCI_EXP_DEVCTL_READRQ, v);
5831 return pcibios_err_to_errno(ret);
5833 EXPORT_SYMBOL(pcie_set_readrq);
5836 * pcie_get_mps - get PCI Express maximum payload size
5837 * @dev: PCI device to query
5839 * Returns maximum payload size in bytes
5841 int pcie_get_mps(struct pci_dev *dev)
5845 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5847 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5849 EXPORT_SYMBOL(pcie_get_mps);
5852 * pcie_set_mps - set PCI Express maximum payload size
5853 * @dev: PCI device to query
5854 * @mps: maximum payload size in bytes
5855 * valid values are 128, 256, 512, 1024, 2048, 4096
5857 * If possible sets maximum payload size
5859 int pcie_set_mps(struct pci_dev *dev, int mps)
5864 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
5868 if (v > dev->pcie_mpss)
5872 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5873 PCI_EXP_DEVCTL_PAYLOAD, v);
5875 return pcibios_err_to_errno(ret);
5877 EXPORT_SYMBOL(pcie_set_mps);
5880 * pcie_bandwidth_available - determine minimum link settings of a PCIe
5881 * device and its bandwidth limitation
5882 * @dev: PCI device to query
5883 * @limiting_dev: storage for device causing the bandwidth limitation
5884 * @speed: storage for speed of limiting device
5885 * @width: storage for width of limiting device
5887 * Walk up the PCI device chain and find the point where the minimum
5888 * bandwidth is available. Return the bandwidth available there and (if
5889 * limiting_dev, speed, and width pointers are supplied) information about
5890 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
5893 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
5894 enum pci_bus_speed *speed,
5895 enum pcie_link_width *width)
5898 enum pci_bus_speed next_speed;
5899 enum pcie_link_width next_width;
5903 *speed = PCI_SPEED_UNKNOWN;
5905 *width = PCIE_LNK_WIDTH_UNKNOWN;
5910 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
5912 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
5913 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
5914 PCI_EXP_LNKSTA_NLW_SHIFT;
5916 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
5918 /* Check if current device limits the total bandwidth */
5919 if (!bw || next_bw <= bw) {
5923 *limiting_dev = dev;
5925 *speed = next_speed;
5927 *width = next_width;
5930 dev = pci_upstream_bridge(dev);
5935 EXPORT_SYMBOL(pcie_bandwidth_available);
5938 * pcie_get_speed_cap - query for the PCI device's link speed capability
5939 * @dev: PCI device to query
5941 * Query the PCI device speed capability. Return the maximum link speed
5942 * supported by the device.
5944 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
5946 u32 lnkcap2, lnkcap;
5949 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
5950 * implementation note there recommends using the Supported Link
5951 * Speeds Vector in Link Capabilities 2 when supported.
5953 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
5954 * should use the Supported Link Speeds field in Link Capabilities,
5955 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
5957 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
5959 /* PCIe r3.0-compliant */
5961 return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
5963 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5964 if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
5965 return PCIE_SPEED_5_0GT;
5966 else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
5967 return PCIE_SPEED_2_5GT;
5969 return PCI_SPEED_UNKNOWN;
5971 EXPORT_SYMBOL(pcie_get_speed_cap);
5974 * pcie_get_width_cap - query for the PCI device's link width capability
5975 * @dev: PCI device to query
5977 * Query the PCI device width capability. Return the maximum link width
5978 * supported by the device.
5980 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
5984 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5986 return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
5988 return PCIE_LNK_WIDTH_UNKNOWN;
5990 EXPORT_SYMBOL(pcie_get_width_cap);
5993 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
5995 * @speed: storage for link speed
5996 * @width: storage for link width
5998 * Calculate a PCI device's link bandwidth by querying for its link speed
5999 * and width, multiplying them, and applying encoding overhead. The result
6000 * is in Mb/s, i.e., megabits/second of raw bandwidth.
6002 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
6003 enum pcie_link_width *width)
6005 *speed = pcie_get_speed_cap(dev);
6006 *width = pcie_get_width_cap(dev);
6008 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
6011 return *width * PCIE_SPEED2MBS_ENC(*speed);
6015 * __pcie_print_link_status - Report the PCI device's link speed and width
6016 * @dev: PCI device to query
6017 * @verbose: Print info even when enough bandwidth is available
6019 * If the available bandwidth at the device is less than the device is
6020 * capable of, report the device's maximum possible bandwidth and the
6021 * upstream link that limits its performance. If @verbose, always print
6022 * the available bandwidth, even if the device isn't constrained.
6024 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
6026 enum pcie_link_width width, width_cap;
6027 enum pci_bus_speed speed, speed_cap;
6028 struct pci_dev *limiting_dev = NULL;
6029 u32 bw_avail, bw_cap;
6031 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
6032 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
6034 if (bw_avail >= bw_cap && verbose)
6035 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6036 bw_cap / 1000, bw_cap % 1000,
6037 pci_speed_string(speed_cap), width_cap);
6038 else if (bw_avail < bw_cap)
6039 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6040 bw_avail / 1000, bw_avail % 1000,
6041 pci_speed_string(speed), width,
6042 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
6043 bw_cap / 1000, bw_cap % 1000,
6044 pci_speed_string(speed_cap), width_cap);
6048 * pcie_print_link_status - Report the PCI device's link speed and width
6049 * @dev: PCI device to query
6051 * Report the available bandwidth at the device.
6053 void pcie_print_link_status(struct pci_dev *dev)
6055 __pcie_print_link_status(dev, true);
6057 EXPORT_SYMBOL(pcie_print_link_status);
6060 * pci_select_bars - Make BAR mask from the type of resource
6061 * @dev: the PCI device for which BAR mask is made
6062 * @flags: resource type mask to be selected
6064 * This helper routine makes bar mask from the type of resource.
6066 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
6069 for (i = 0; i < PCI_NUM_RESOURCES; i++)
6070 if (pci_resource_flags(dev, i) & flags)
6074 EXPORT_SYMBOL(pci_select_bars);
6076 /* Some architectures require additional programming to enable VGA */
6077 static arch_set_vga_state_t arch_set_vga_state;
6079 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
6081 arch_set_vga_state = func; /* NULL disables */
6084 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
6085 unsigned int command_bits, u32 flags)
6087 if (arch_set_vga_state)
6088 return arch_set_vga_state(dev, decode, command_bits,
6094 * pci_set_vga_state - set VGA decode state on device and parents if requested
6095 * @dev: the PCI device
6096 * @decode: true = enable decoding, false = disable decoding
6097 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6098 * @flags: traverse ancestors and change bridges
6099 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6101 int pci_set_vga_state(struct pci_dev *dev, bool decode,
6102 unsigned int command_bits, u32 flags)
6104 struct pci_bus *bus;
6105 struct pci_dev *bridge;
6109 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
6111 /* ARCH specific VGA enables */
6112 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6116 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
6117 pci_read_config_word(dev, PCI_COMMAND, &cmd);
6119 cmd |= command_bits;
6121 cmd &= ~command_bits;
6122 pci_write_config_word(dev, PCI_COMMAND, cmd);
6125 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
6132 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6135 cmd |= PCI_BRIDGE_CTL_VGA;
6137 cmd &= ~PCI_BRIDGE_CTL_VGA;
6138 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
6147 bool pci_pr3_present(struct pci_dev *pdev)
6149 struct acpi_device *adev;
6154 adev = ACPI_COMPANION(&pdev->dev);
6158 return adev->power.flags.power_resources &&
6159 acpi_has_method(adev->handle, "_PR3");
6161 EXPORT_SYMBOL_GPL(pci_pr3_present);
6165 * pci_add_dma_alias - Add a DMA devfn alias for a device
6166 * @dev: the PCI device for which alias is added
6167 * @devfn_from: alias slot and function
6168 * @nr_devfns: number of subsequent devfns to alias
6170 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6171 * which is used to program permissible bus-devfn source addresses for DMA
6172 * requests in an IOMMU. These aliases factor into IOMMU group creation
6173 * and are useful for devices generating DMA requests beyond or different
6174 * from their logical bus-devfn. Examples include device quirks where the
6175 * device simply uses the wrong devfn, as well as non-transparent bridges
6176 * where the alias may be a proxy for devices in another domain.
6178 * IOMMU group creation is performed during device discovery or addition,
6179 * prior to any potential DMA mapping and therefore prior to driver probing
6180 * (especially for userspace assigned devices where IOMMU group definition
6181 * cannot be left as a userspace activity). DMA aliases should therefore
6182 * be configured via quirks, such as the PCI fixup header quirk.
6184 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns)
6188 nr_devfns = min(nr_devfns, (unsigned) MAX_NR_DEVFNS - devfn_from);
6189 devfn_to = devfn_from + nr_devfns - 1;
6191 if (!dev->dma_alias_mask)
6192 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6193 if (!dev->dma_alias_mask) {
6194 pci_warn(dev, "Unable to allocate DMA alias mask\n");
6198 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6201 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6202 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
6203 else if (nr_devfns > 1)
6204 pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6205 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
6206 PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
6209 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
6211 return (dev1->dma_alias_mask &&
6212 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
6213 (dev2->dma_alias_mask &&
6214 test_bit(dev1->devfn, dev2->dma_alias_mask)) ||
6215 pci_real_dma_dev(dev1) == dev2 ||
6216 pci_real_dma_dev(dev2) == dev1;
6219 bool pci_device_is_present(struct pci_dev *pdev)
6223 if (pci_dev_is_disconnected(pdev))
6225 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
6227 EXPORT_SYMBOL_GPL(pci_device_is_present);
6229 void pci_ignore_hotplug(struct pci_dev *dev)
6231 struct pci_dev *bridge = dev->bus->self;
6233 dev->ignore_hotplug = 1;
6234 /* Propagate the "ignore hotplug" setting to the parent bridge. */
6236 bridge->ignore_hotplug = 1;
6238 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
6241 * pci_real_dma_dev - Get PCI DMA device for PCI device
6242 * @dev: the PCI device that may have a PCI DMA alias
6244 * Permits the platform to provide architecture-specific functionality to
6245 * devices needing to alias DMA to another PCI device on another PCI bus. If
6246 * the PCI device is on the same bus, it is recommended to use
6247 * pci_add_dma_alias(). This is the default implementation. Architecture
6248 * implementations can override this.
6250 struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6255 resource_size_t __weak pcibios_default_alignment(void)
6261 * Arches that don't want to expose struct resource to userland as-is in
6262 * sysfs and /proc can implement their own pci_resource_to_user().
6264 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6265 const struct resource *rsrc,
6266 resource_size_t *start, resource_size_t *end)
6268 *start = rsrc->start;
6272 static char *resource_alignment_param;
6273 static DEFINE_SPINLOCK(resource_alignment_lock);
6276 * pci_specified_resource_alignment - get resource alignment specified by user.
6277 * @dev: the PCI device to get
6278 * @resize: whether or not to change resources' size when reassigning alignment
6280 * RETURNS: Resource alignment if it is specified.
6281 * Zero if it is not specified.
6283 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6286 int align_order, count;
6287 resource_size_t align = pcibios_default_alignment();
6291 spin_lock(&resource_alignment_lock);
6292 p = resource_alignment_param;
6295 if (pci_has_flag(PCI_PROBE_ONLY)) {
6297 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6303 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
6306 if (align_order > 63) {
6307 pr_err("PCI: Invalid requested alignment (order %d)\n",
6309 align_order = PAGE_SHIFT;
6312 align_order = PAGE_SHIFT;
6315 ret = pci_dev_str_match(dev, p, &p);
6318 align = 1ULL << align_order;
6320 } else if (ret < 0) {
6321 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6326 if (*p != ';' && *p != ',') {
6327 /* End of param or invalid format */
6333 spin_unlock(&resource_alignment_lock);
6337 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6338 resource_size_t align, bool resize)
6340 struct resource *r = &dev->resource[bar];
6341 resource_size_t size;
6343 if (!(r->flags & IORESOURCE_MEM))
6346 if (r->flags & IORESOURCE_PCI_FIXED) {
6347 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
6348 bar, r, (unsigned long long)align);
6352 size = resource_size(r);
6357 * Increase the alignment of the resource. There are two ways we
6360 * 1) Increase the size of the resource. BARs are aligned on their
6361 * size, so when we reallocate space for this resource, we'll
6362 * allocate it with the larger alignment. This also prevents
6363 * assignment of any other BARs inside the alignment region, so
6364 * if we're requesting page alignment, this means no other BARs
6365 * will share the page.
6367 * The disadvantage is that this makes the resource larger than
6368 * the hardware BAR, which may break drivers that compute things
6369 * based on the resource size, e.g., to find registers at a
6370 * fixed offset before the end of the BAR.
6372 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6373 * set r->start to the desired alignment. By itself this
6374 * doesn't prevent other BARs being put inside the alignment
6375 * region, but if we realign *every* resource of every device in
6376 * the system, none of them will share an alignment region.
6378 * When the user has requested alignment for only some devices via
6379 * the "pci=resource_alignment" argument, "resize" is true and we
6380 * use the first method. Otherwise we assume we're aligning all
6381 * devices and we use the second.
6384 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
6385 bar, r, (unsigned long long)align);
6391 r->flags &= ~IORESOURCE_SIZEALIGN;
6392 r->flags |= IORESOURCE_STARTALIGN;
6394 r->end = r->start + size - 1;
6396 r->flags |= IORESOURCE_UNSET;
6400 * This function disables memory decoding and releases memory resources
6401 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6402 * It also rounds up size to specified alignment.
6403 * Later on, the kernel will assign page-aligned memory resource back
6406 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6410 resource_size_t align;
6412 bool resize = false;
6415 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6416 * 3.4.1.11. Their resources are allocated from the space
6417 * described by the VF BARx register in the PF's SR-IOV capability.
6418 * We can't influence their alignment here.
6423 /* check if specified PCI is target device to reassign */
6424 align = pci_specified_resource_alignment(dev, &resize);
6428 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6429 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6430 pci_warn(dev, "Can't reassign resources to host bridge\n");
6434 pci_read_config_word(dev, PCI_COMMAND, &command);
6435 command &= ~PCI_COMMAND_MEMORY;
6436 pci_write_config_word(dev, PCI_COMMAND, command);
6438 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
6439 pci_request_resource_alignment(dev, i, align, resize);
6442 * Need to disable bridge's resource window,
6443 * to enable the kernel to reassign new resource
6446 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6447 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6448 r = &dev->resource[i];
6449 if (!(r->flags & IORESOURCE_MEM))
6451 r->flags |= IORESOURCE_UNSET;
6452 r->end = resource_size(r) - 1;
6455 pci_disable_bridge_window(dev);
6459 static ssize_t resource_alignment_show(struct bus_type *bus, char *buf)
6463 spin_lock(&resource_alignment_lock);
6464 if (resource_alignment_param)
6465 count = sysfs_emit(buf, "%s\n", resource_alignment_param);
6466 spin_unlock(&resource_alignment_lock);
6471 static ssize_t resource_alignment_store(struct bus_type *bus,
6472 const char *buf, size_t count)
6474 char *param, *old, *end;
6476 if (count >= (PAGE_SIZE - 1))
6479 param = kstrndup(buf, count, GFP_KERNEL);
6483 end = strchr(param, '\n');
6487 spin_lock(&resource_alignment_lock);
6488 old = resource_alignment_param;
6489 if (strlen(param)) {
6490 resource_alignment_param = param;
6493 resource_alignment_param = NULL;
6495 spin_unlock(&resource_alignment_lock);
6502 static BUS_ATTR_RW(resource_alignment);
6504 static int __init pci_resource_alignment_sysfs_init(void)
6506 return bus_create_file(&pci_bus_type,
6507 &bus_attr_resource_alignment);
6509 late_initcall(pci_resource_alignment_sysfs_init);
6511 static void pci_no_domains(void)
6513 #ifdef CONFIG_PCI_DOMAINS
6514 pci_domains_supported = 0;
6518 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6519 static atomic_t __domain_nr = ATOMIC_INIT(-1);
6521 static int pci_get_new_domain_nr(void)
6523 return atomic_inc_return(&__domain_nr);
6526 static int of_pci_bus_find_domain_nr(struct device *parent)
6528 static int use_dt_domains = -1;
6532 domain = of_get_pci_domain_nr(parent->of_node);
6535 * Check DT domain and use_dt_domains values.
6537 * If DT domain property is valid (domain >= 0) and
6538 * use_dt_domains != 0, the DT assignment is valid since this means
6539 * we have not previously allocated a domain number by using
6540 * pci_get_new_domain_nr(); we should also update use_dt_domains to
6541 * 1, to indicate that we have just assigned a domain number from
6544 * If DT domain property value is not valid (ie domain < 0), and we
6545 * have not previously assigned a domain number from DT
6546 * (use_dt_domains != 1) we should assign a domain number by
6549 * pci_get_new_domain_nr()
6551 * API and update the use_dt_domains value to keep track of method we
6552 * are using to assign domain numbers (use_dt_domains = 0).
6554 * All other combinations imply we have a platform that is trying
6555 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
6556 * which is a recipe for domain mishandling and it is prevented by
6557 * invalidating the domain value (domain = -1) and printing a
6558 * corresponding error.
6560 if (domain >= 0 && use_dt_domains) {
6562 } else if (domain < 0 && use_dt_domains != 1) {
6564 domain = pci_get_new_domain_nr();
6567 pr_err("Node %pOF has ", parent->of_node);
6568 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
6575 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
6577 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
6578 acpi_pci_bus_find_domain_nr(bus);
6583 * pci_ext_cfg_avail - can we access extended PCI config space?
6585 * Returns 1 if we can access PCI extended config space (offsets
6586 * greater than 0xff). This is the default implementation. Architecture
6587 * implementations can override this.
6589 int __weak pci_ext_cfg_avail(void)
6594 void __weak pci_fixup_cardbus(struct pci_bus *bus)
6597 EXPORT_SYMBOL(pci_fixup_cardbus);
6599 static int __init pci_setup(char *str)
6602 char *k = strchr(str, ',');
6605 if (*str && (str = pcibios_setup(str)) && *str) {
6606 if (!strcmp(str, "nomsi")) {
6608 } else if (!strncmp(str, "noats", 5)) {
6609 pr_info("PCIe: ATS is disabled\n");
6610 pcie_ats_disabled = true;
6611 } else if (!strcmp(str, "noaer")) {
6613 } else if (!strcmp(str, "earlydump")) {
6614 pci_early_dump = true;
6615 } else if (!strncmp(str, "realloc=", 8)) {
6616 pci_realloc_get_opt(str + 8);
6617 } else if (!strncmp(str, "realloc", 7)) {
6618 pci_realloc_get_opt("on");
6619 } else if (!strcmp(str, "nodomains")) {
6621 } else if (!strncmp(str, "noari", 5)) {
6622 pcie_ari_disabled = true;
6623 } else if (!strncmp(str, "cbiosize=", 9)) {
6624 pci_cardbus_io_size = memparse(str + 9, &str);
6625 } else if (!strncmp(str, "cbmemsize=", 10)) {
6626 pci_cardbus_mem_size = memparse(str + 10, &str);
6627 } else if (!strncmp(str, "resource_alignment=", 19)) {
6628 resource_alignment_param = str + 19;
6629 } else if (!strncmp(str, "ecrc=", 5)) {
6630 pcie_ecrc_get_policy(str + 5);
6631 } else if (!strncmp(str, "hpiosize=", 9)) {
6632 pci_hotplug_io_size = memparse(str + 9, &str);
6633 } else if (!strncmp(str, "hpmmiosize=", 11)) {
6634 pci_hotplug_mmio_size = memparse(str + 11, &str);
6635 } else if (!strncmp(str, "hpmmioprefsize=", 15)) {
6636 pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
6637 } else if (!strncmp(str, "hpmemsize=", 10)) {
6638 pci_hotplug_mmio_size = memparse(str + 10, &str);
6639 pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
6640 } else if (!strncmp(str, "hpbussize=", 10)) {
6641 pci_hotplug_bus_size =
6642 simple_strtoul(str + 10, &str, 0);
6643 if (pci_hotplug_bus_size > 0xff)
6644 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
6645 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
6646 pcie_bus_config = PCIE_BUS_TUNE_OFF;
6647 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
6648 pcie_bus_config = PCIE_BUS_SAFE;
6649 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
6650 pcie_bus_config = PCIE_BUS_PERFORMANCE;
6651 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
6652 pcie_bus_config = PCIE_BUS_PEER2PEER;
6653 } else if (!strncmp(str, "pcie_scan_all", 13)) {
6654 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
6655 } else if (!strncmp(str, "disable_acs_redir=", 18)) {
6656 disable_acs_redir_param = str + 18;
6658 pr_err("PCI: Unknown option `%s'\n", str);
6665 early_param("pci", pci_setup);
6668 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6669 * in pci_setup(), above, to point to data in the __initdata section which
6670 * will be freed after the init sequence is complete. We can't allocate memory
6671 * in pci_setup() because some architectures do not have any memory allocation
6672 * service available during an early_param() call. So we allocate memory and
6673 * copy the variable here before the init section is freed.
6676 static int __init pci_realloc_setup_params(void)
6678 resource_alignment_param = kstrdup(resource_alignment_param,
6680 disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
6684 pure_initcall(pci_realloc_setup_params);