1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 * Copyright (C) 2016 Christoph Hellwig.
10 #include <linux/err.h>
12 #include <linux/irq.h>
13 #include <linux/interrupt.h>
14 #include <linux/export.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
19 #include <linux/smp.h>
20 #include <linux/errno.h>
22 #include <linux/acpi_iort.h>
23 #include <linux/slab.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_irq.h>
31 static int pci_msi_enable = 1;
32 int pci_msi_ignore_mask;
34 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
36 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
37 static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
39 struct irq_domain *domain;
41 domain = dev_get_msi_domain(&dev->dev);
42 if (domain && irq_domain_is_hierarchy(domain))
43 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
45 return arch_setup_msi_irqs(dev, nvec, type);
48 static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
50 struct irq_domain *domain;
52 domain = dev_get_msi_domain(&dev->dev);
53 if (domain && irq_domain_is_hierarchy(domain))
54 msi_domain_free_irqs(domain, &dev->dev);
56 arch_teardown_msi_irqs(dev);
59 #define pci_msi_setup_msi_irqs arch_setup_msi_irqs
60 #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
63 #ifdef CONFIG_PCI_MSI_ARCH_FALLBACKS
65 int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
70 void __weak arch_teardown_msi_irq(unsigned int irq)
74 int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
76 struct msi_desc *entry;
80 * If an architecture wants to support multiple MSI, it needs to
81 * override arch_setup_msi_irqs()
83 if (type == PCI_CAP_ID_MSI && nvec > 1)
86 for_each_pci_msi_entry(entry, dev) {
87 ret = arch_setup_msi_irq(dev, entry);
97 void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
100 struct msi_desc *entry;
102 for_each_pci_msi_entry(entry, dev)
104 for (i = 0; i < entry->nvec_used; i++)
105 arch_teardown_msi_irq(entry->irq + i);
107 #endif /* CONFIG_PCI_MSI_ARCH_FALLBACKS */
109 static void default_restore_msi_irq(struct pci_dev *dev, int irq)
111 struct msi_desc *entry;
114 if (dev->msix_enabled) {
115 for_each_pci_msi_entry(entry, dev) {
116 if (irq == entry->irq)
119 } else if (dev->msi_enabled) {
120 entry = irq_get_msi_desc(irq);
124 __pci_write_msi_msg(entry, &entry->msg);
127 void __weak arch_restore_msi_irqs(struct pci_dev *dev)
129 return default_restore_msi_irqs(dev);
132 static inline __attribute_const__ u32 msi_mask(unsigned x)
134 /* Don't shift by >= width of type */
137 return (1 << (1 << x)) - 1;
141 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
142 * mask all MSI interrupts by clearing the MSI enable bit does not work
143 * reliably as devices without an INTx disable bit will then generate a
144 * level IRQ which will never be cleared.
146 void __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
148 raw_spinlock_t *lock = &desc->dev->msi_lock;
151 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
154 raw_spin_lock_irqsave(lock, flags);
155 desc->masked &= ~mask;
156 desc->masked |= flag;
157 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
159 raw_spin_unlock_irqrestore(lock, flags);
162 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
164 __pci_msi_desc_mask_irq(desc, mask, flag);
167 static void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
169 if (desc->msi_attrib.is_virtual)
172 return desc->mask_base +
173 desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
177 * This internal function does not flush PCI writes to the device.
178 * All users must ensure that they read from the device before either
179 * assuming that the device state is up to date, or returning out of this
180 * file. This saves a few milliseconds when initialising devices with lots
181 * of MSI-X interrupts.
183 u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
185 u32 mask_bits = desc->masked;
186 void __iomem *desc_addr;
188 if (pci_msi_ignore_mask)
191 desc_addr = pci_msix_desc_addr(desc);
195 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
196 if (flag & PCI_MSIX_ENTRY_CTRL_MASKBIT)
197 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
199 writel(mask_bits, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
204 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
206 desc->masked = __pci_msix_desc_mask_irq(desc, flag);
209 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
211 struct msi_desc *desc = irq_data_get_msi_desc(data);
213 if (desc->msi_attrib.is_msix) {
214 msix_mask_irq(desc, flag);
215 readl(desc->mask_base); /* Flush write to device */
217 unsigned offset = data->irq - desc->irq;
218 msi_mask_irq(desc, 1 << offset, flag << offset);
223 * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts
224 * @data: pointer to irqdata associated to that interrupt
226 void pci_msi_mask_irq(struct irq_data *data)
228 msi_set_mask_bit(data, 1);
230 EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
233 * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts
234 * @data: pointer to irqdata associated to that interrupt
236 void pci_msi_unmask_irq(struct irq_data *data)
238 msi_set_mask_bit(data, 0);
240 EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
242 void default_restore_msi_irqs(struct pci_dev *dev)
244 struct msi_desc *entry;
246 for_each_pci_msi_entry(entry, dev)
247 default_restore_msi_irq(dev, entry->irq);
250 void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
252 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
254 BUG_ON(dev->current_state != PCI_D0);
256 if (entry->msi_attrib.is_msix) {
257 void __iomem *base = pci_msix_desc_addr(entry);
264 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
265 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
266 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
268 int pos = dev->msi_cap;
271 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
273 if (entry->msi_attrib.is_64) {
274 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
276 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
279 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
285 void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
287 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
289 if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) {
290 /* Don't touch the hardware now */
291 } else if (entry->msi_attrib.is_msix) {
292 void __iomem *base = pci_msix_desc_addr(entry);
293 bool unmasked = !(entry->masked & PCI_MSIX_ENTRY_CTRL_MASKBIT);
299 * The specification mandates that the entry is masked
300 * when the message is modified:
302 * "If software changes the Address or Data value of an
303 * entry while the entry is unmasked, the result is
307 __pci_msix_desc_mask_irq(entry, PCI_MSIX_ENTRY_CTRL_MASKBIT);
309 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
310 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
311 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
314 __pci_msix_desc_mask_irq(entry, 0);
316 /* Ensure that the writes are visible in the device */
317 readl(base + PCI_MSIX_ENTRY_DATA);
319 int pos = dev->msi_cap;
322 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
323 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
324 msgctl |= entry->msi_attrib.multiple << 4;
325 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
327 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
329 if (entry->msi_attrib.is_64) {
330 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
332 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
335 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
338 /* Ensure that the writes are visible in the device */
339 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
345 if (entry->write_msi_msg)
346 entry->write_msi_msg(entry, entry->write_msi_msg_data);
350 void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
352 struct msi_desc *entry = irq_get_msi_desc(irq);
354 __pci_write_msi_msg(entry, msg);
356 EXPORT_SYMBOL_GPL(pci_write_msi_msg);
358 static void free_msi_irqs(struct pci_dev *dev)
360 struct list_head *msi_list = dev_to_msi_list(&dev->dev);
361 struct msi_desc *entry, *tmp;
362 struct attribute **msi_attrs;
363 struct device_attribute *dev_attr;
366 for_each_pci_msi_entry(entry, dev)
368 for (i = 0; i < entry->nvec_used; i++)
369 BUG_ON(irq_has_action(entry->irq + i));
371 pci_msi_teardown_msi_irqs(dev);
373 list_for_each_entry_safe(entry, tmp, msi_list, list) {
374 if (entry->msi_attrib.is_msix) {
375 if (list_is_last(&entry->list, msi_list))
376 iounmap(entry->mask_base);
379 list_del(&entry->list);
380 free_msi_entry(entry);
383 if (dev->msi_irq_groups) {
384 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
385 msi_attrs = dev->msi_irq_groups[0]->attrs;
386 while (msi_attrs[count]) {
387 dev_attr = container_of(msi_attrs[count],
388 struct device_attribute, attr);
389 kfree(dev_attr->attr.name);
394 kfree(dev->msi_irq_groups[0]);
395 kfree(dev->msi_irq_groups);
396 dev->msi_irq_groups = NULL;
400 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
402 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
403 pci_intx(dev, enable);
406 static void pci_msi_set_enable(struct pci_dev *dev, int enable)
410 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
411 control &= ~PCI_MSI_FLAGS_ENABLE;
413 control |= PCI_MSI_FLAGS_ENABLE;
414 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
417 static void __pci_restore_msi_state(struct pci_dev *dev)
420 struct msi_desc *entry;
422 if (!dev->msi_enabled)
425 entry = irq_get_msi_desc(dev->irq);
427 pci_intx_for_msi(dev, 0);
428 pci_msi_set_enable(dev, 0);
429 arch_restore_msi_irqs(dev);
431 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
432 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
434 control &= ~PCI_MSI_FLAGS_QSIZE;
435 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
436 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
439 static void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
443 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
446 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
449 static void __pci_restore_msix_state(struct pci_dev *dev)
451 struct msi_desc *entry;
453 if (!dev->msix_enabled)
455 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
457 /* route the table */
458 pci_intx_for_msi(dev, 0);
459 pci_msix_clear_and_set_ctrl(dev, 0,
460 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
462 arch_restore_msi_irqs(dev);
463 for_each_pci_msi_entry(entry, dev)
464 msix_mask_irq(entry, entry->masked);
466 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
469 void pci_restore_msi_state(struct pci_dev *dev)
471 __pci_restore_msi_state(dev);
472 __pci_restore_msix_state(dev);
474 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
476 static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
479 struct msi_desc *entry;
483 retval = kstrtoul(attr->attr.name, 10, &irq);
487 entry = irq_get_msi_desc(irq);
491 return sysfs_emit(buf, "%s\n",
492 entry->msi_attrib.is_msix ? "msix" : "msi");
495 static int populate_msi_sysfs(struct pci_dev *pdev)
497 struct attribute **msi_attrs;
498 struct attribute *msi_attr;
499 struct device_attribute *msi_dev_attr;
500 struct attribute_group *msi_irq_group;
501 const struct attribute_group **msi_irq_groups;
502 struct msi_desc *entry;
508 /* Determine how many msi entries we have */
509 for_each_pci_msi_entry(entry, pdev)
510 num_msi += entry->nvec_used;
514 /* Dynamically create the MSI attributes for the PCI device */
515 msi_attrs = kcalloc(num_msi + 1, sizeof(void *), GFP_KERNEL);
518 for_each_pci_msi_entry(entry, pdev) {
519 for (i = 0; i < entry->nvec_used; i++) {
520 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
523 msi_attrs[count] = &msi_dev_attr->attr;
525 sysfs_attr_init(&msi_dev_attr->attr);
526 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
528 if (!msi_dev_attr->attr.name)
530 msi_dev_attr->attr.mode = S_IRUGO;
531 msi_dev_attr->show = msi_mode_show;
536 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
539 msi_irq_group->name = "msi_irqs";
540 msi_irq_group->attrs = msi_attrs;
542 msi_irq_groups = kcalloc(2, sizeof(void *), GFP_KERNEL);
544 goto error_irq_group;
545 msi_irq_groups[0] = msi_irq_group;
547 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
549 goto error_irq_groups;
550 pdev->msi_irq_groups = msi_irq_groups;
555 kfree(msi_irq_groups);
557 kfree(msi_irq_group);
560 msi_attr = msi_attrs[count];
562 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
563 kfree(msi_attr->name);
566 msi_attr = msi_attrs[count];
572 static struct msi_desc *
573 msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd)
575 struct irq_affinity_desc *masks = NULL;
576 struct msi_desc *entry;
580 masks = irq_create_affinity_masks(nvec, affd);
582 /* MSI Entry Initialization */
583 entry = alloc_msi_entry(&dev->dev, nvec, masks);
587 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
589 entry->msi_attrib.is_msix = 0;
590 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
591 entry->msi_attrib.is_virtual = 0;
592 entry->msi_attrib.entry_nr = 0;
593 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
594 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
595 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
596 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
598 if (control & PCI_MSI_FLAGS_64BIT)
599 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
601 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
603 /* Save the initial mask status */
604 if (entry->msi_attrib.maskbit)
605 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
612 static int msi_verify_entries(struct pci_dev *dev)
614 struct msi_desc *entry;
616 for_each_pci_msi_entry(entry, dev) {
617 if (entry->msg.address_hi && dev->no_64bit_msi) {
618 pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n",
619 entry->msg.address_hi, entry->msg.address_lo);
627 * msi_capability_init - configure device's MSI capability structure
628 * @dev: pointer to the pci_dev data structure of MSI device function
629 * @nvec: number of interrupts to allocate
630 * @affd: description of automatic IRQ affinity assignments (may be %NULL)
632 * Setup the MSI capability structure of the device with the requested
633 * number of interrupts. A return value of zero indicates the successful
634 * setup of an entry with the new MSI IRQ. A negative return value indicates
635 * an error, and a positive return value indicates the number of interrupts
636 * which could have been allocated.
638 static int msi_capability_init(struct pci_dev *dev, int nvec,
639 struct irq_affinity *affd)
641 struct msi_desc *entry;
645 pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
647 entry = msi_setup_entry(dev, nvec, affd);
651 /* All MSIs are unmasked by default; mask them all */
652 mask = msi_mask(entry->msi_attrib.multi_cap);
653 msi_mask_irq(entry, mask, mask);
655 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
657 /* Configure MSI capability structure */
658 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
660 msi_mask_irq(entry, mask, 0);
665 ret = msi_verify_entries(dev);
667 msi_mask_irq(entry, mask, 0);
672 ret = populate_msi_sysfs(dev);
674 msi_mask_irq(entry, mask, 0);
679 /* Set MSI enabled bits */
680 pci_intx_for_msi(dev, 0);
681 pci_msi_set_enable(dev, 1);
682 dev->msi_enabled = 1;
684 pcibios_free_irq(dev);
685 dev->irq = entry->irq;
689 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
691 resource_size_t phys_addr;
696 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
698 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
699 flags = pci_resource_flags(dev, bir);
700 if (!flags || (flags & IORESOURCE_UNSET))
703 table_offset &= PCI_MSIX_TABLE_OFFSET;
704 phys_addr = pci_resource_start(dev, bir) + table_offset;
706 return ioremap(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
709 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
710 struct msix_entry *entries, int nvec,
711 struct irq_affinity *affd)
713 struct irq_affinity_desc *curmsk, *masks = NULL;
714 struct msi_desc *entry;
717 int vec_count = pci_msix_vec_count(dev);
720 masks = irq_create_affinity_masks(nvec, affd);
722 for (i = 0, curmsk = masks; i < nvec; i++) {
723 entry = alloc_msi_entry(&dev->dev, 1, curmsk);
729 /* No enough memory. Don't try again */
734 entry->msi_attrib.is_msix = 1;
735 entry->msi_attrib.is_64 = 1;
738 entry->msi_attrib.entry_nr = entries[i].entry;
740 entry->msi_attrib.entry_nr = i;
742 entry->msi_attrib.is_virtual =
743 entry->msi_attrib.entry_nr >= vec_count;
745 entry->msi_attrib.default_irq = dev->irq;
746 entry->mask_base = base;
748 addr = pci_msix_desc_addr(entry);
750 entry->masked = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
752 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
762 static void msix_update_entries(struct pci_dev *dev, struct msix_entry *entries)
764 struct msi_desc *entry;
766 for_each_pci_msi_entry(entry, dev) {
768 entries->vector = entry->irq;
774 static void msix_mask_all(void __iomem *base, int tsize)
776 u32 ctrl = PCI_MSIX_ENTRY_CTRL_MASKBIT;
779 for (i = 0; i < tsize; i++, base += PCI_MSIX_ENTRY_SIZE)
780 writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL);
784 * msix_capability_init - configure device's MSI-X capability
785 * @dev: pointer to the pci_dev data structure of MSI-X device function
786 * @entries: pointer to an array of struct msix_entry entries
787 * @nvec: number of @entries
788 * @affd: Optional pointer to enable automatic affinity assignment
790 * Setup the MSI-X capability structure of device function with a
791 * single MSI-X IRQ. A return of zero indicates the successful setup of
792 * requested MSI-X entries with allocated IRQs or non-zero for otherwise.
794 static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
795 int nvec, struct irq_affinity *affd)
802 * Some devices require MSI-X to be enabled before the MSI-X
803 * registers can be accessed. Mask all the vectors to prevent
804 * interrupts coming in before they're fully set up.
806 pci_msix_clear_and_set_ctrl(dev, 0, PCI_MSIX_FLAGS_MASKALL |
807 PCI_MSIX_FLAGS_ENABLE);
809 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
810 /* Request & Map MSI-X table region */
811 tsize = msix_table_size(control);
812 base = msix_map_region(dev, tsize);
818 /* Ensure that all table entries are masked. */
819 msix_mask_all(base, tsize);
821 ret = msix_setup_entries(dev, base, entries, nvec, affd);
825 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
829 /* Check if all MSI entries honor device restrictions */
830 ret = msi_verify_entries(dev);
834 msix_update_entries(dev, entries);
836 ret = populate_msi_sysfs(dev);
840 /* Set MSI-X enabled bits and unmask the function */
841 pci_intx_for_msi(dev, 0);
842 dev->msix_enabled = 1;
843 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
845 pcibios_free_irq(dev);
851 * If we had some success, report the number of IRQs
852 * we succeeded in setting up.
854 struct msi_desc *entry;
857 for_each_pci_msi_entry(entry, dev) {
869 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
875 * pci_msi_supported - check whether MSI may be enabled on a device
876 * @dev: pointer to the pci_dev data structure of MSI device function
877 * @nvec: how many MSIs have been requested?
879 * Look at global flags, the device itself, and its parent buses
880 * to determine if MSI/-X are supported for the device. If MSI/-X is
881 * supported return 1, else return 0.
883 static int pci_msi_supported(struct pci_dev *dev, int nvec)
887 /* MSI must be globally enabled and supported by the device */
891 if (!dev || dev->no_msi)
895 * You can't ask to have 0 or less MSIs configured.
897 * b) the list manipulation code assumes nvec >= 1.
903 * Any bridge which does NOT route MSI transactions from its
904 * secondary bus to its primary bus must set NO_MSI flag on
905 * the secondary pci_bus.
907 * The NO_MSI flag can either be set directly by:
908 * - arch-specific PCI host bus controller drivers (deprecated)
909 * - quirks for specific PCI bridges
911 * or indirectly by platform-specific PCI host bridge drivers by
912 * advertising the 'msi_domain' property, which results in
913 * the NO_MSI flag when no MSI domain is found for this bridge
916 for (bus = dev->bus; bus; bus = bus->parent)
917 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
924 * pci_msi_vec_count - Return the number of MSI vectors a device can send
925 * @dev: device to report about
927 * This function returns the number of MSI vectors a device requested via
928 * Multiple Message Capable register. It returns a negative errno if the
929 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
930 * and returns a power of two, up to a maximum of 2^5 (32), according to the
933 int pci_msi_vec_count(struct pci_dev *dev)
941 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
942 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
946 EXPORT_SYMBOL(pci_msi_vec_count);
948 static void pci_msi_shutdown(struct pci_dev *dev)
950 struct msi_desc *desc;
953 if (!pci_msi_enable || !dev || !dev->msi_enabled)
956 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
957 desc = first_pci_msi_entry(dev);
959 pci_msi_set_enable(dev, 0);
960 pci_intx_for_msi(dev, 1);
961 dev->msi_enabled = 0;
963 /* Return the device with MSI unmasked as initial states */
964 mask = msi_mask(desc->msi_attrib.multi_cap);
965 msi_mask_irq(desc, mask, 0);
967 /* Restore dev->irq to its default pin-assertion IRQ */
968 dev->irq = desc->msi_attrib.default_irq;
969 pcibios_alloc_irq(dev);
972 void pci_disable_msi(struct pci_dev *dev)
974 if (!pci_msi_enable || !dev || !dev->msi_enabled)
977 pci_msi_shutdown(dev);
980 EXPORT_SYMBOL(pci_disable_msi);
983 * pci_msix_vec_count - return the number of device's MSI-X table entries
984 * @dev: pointer to the pci_dev data structure of MSI-X device function
985 * This function returns the number of device's MSI-X table entries and
986 * therefore the number of MSI-X vectors device is capable of sending.
987 * It returns a negative errno if the device is not capable of sending MSI-X
990 int pci_msix_vec_count(struct pci_dev *dev)
997 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
998 return msix_table_size(control);
1000 EXPORT_SYMBOL(pci_msix_vec_count);
1002 static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
1003 int nvec, struct irq_affinity *affd, int flags)
1008 if (!pci_msi_supported(dev, nvec) || dev->current_state != PCI_D0)
1011 nr_entries = pci_msix_vec_count(dev);
1014 if (nvec > nr_entries && !(flags & PCI_IRQ_VIRTUAL))
1018 /* Check for any invalid entries */
1019 for (i = 0; i < nvec; i++) {
1020 if (entries[i].entry >= nr_entries)
1021 return -EINVAL; /* invalid entry */
1022 for (j = i + 1; j < nvec; j++) {
1023 if (entries[i].entry == entries[j].entry)
1024 return -EINVAL; /* duplicate entry */
1029 /* Check whether driver already requested for MSI IRQ */
1030 if (dev->msi_enabled) {
1031 pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
1034 return msix_capability_init(dev, entries, nvec, affd);
1037 static void pci_msix_shutdown(struct pci_dev *dev)
1039 struct msi_desc *entry;
1041 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1044 if (pci_dev_is_disconnected(dev)) {
1045 dev->msix_enabled = 0;
1049 /* Return the device with MSI-X masked as initial states */
1050 for_each_pci_msi_entry(entry, dev)
1051 __pci_msix_desc_mask_irq(entry, 1);
1053 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1054 pci_intx_for_msi(dev, 1);
1055 dev->msix_enabled = 0;
1056 pcibios_alloc_irq(dev);
1059 void pci_disable_msix(struct pci_dev *dev)
1061 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1064 pci_msix_shutdown(dev);
1067 EXPORT_SYMBOL(pci_disable_msix);
1069 void pci_no_msi(void)
1075 * pci_msi_enabled - is MSI enabled?
1077 * Returns true if MSI has not been disabled by the command-line option
1080 int pci_msi_enabled(void)
1082 return pci_msi_enable;
1084 EXPORT_SYMBOL(pci_msi_enabled);
1086 static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
1087 struct irq_affinity *affd)
1092 if (!pci_msi_supported(dev, minvec) || dev->current_state != PCI_D0)
1095 /* Check whether driver already requested MSI-X IRQs */
1096 if (dev->msix_enabled) {
1097 pci_info(dev, "can't enable MSI (MSI-X already enabled)\n");
1101 if (maxvec < minvec)
1104 if (WARN_ON_ONCE(dev->msi_enabled))
1107 nvec = pci_msi_vec_count(dev);
1118 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
1123 rc = msi_capability_init(dev, nvec, affd);
1136 /* deprecated, don't use */
1137 int pci_enable_msi(struct pci_dev *dev)
1139 int rc = __pci_enable_msi_range(dev, 1, 1, NULL);
1144 EXPORT_SYMBOL(pci_enable_msi);
1146 static int __pci_enable_msix_range(struct pci_dev *dev,
1147 struct msix_entry *entries, int minvec,
1148 int maxvec, struct irq_affinity *affd,
1151 int rc, nvec = maxvec;
1153 if (maxvec < minvec)
1156 if (WARN_ON_ONCE(dev->msix_enabled))
1161 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
1166 rc = __pci_enable_msix(dev, entries, nvec, affd, flags);
1180 * pci_enable_msix_range - configure device's MSI-X capability structure
1181 * @dev: pointer to the pci_dev data structure of MSI-X device function
1182 * @entries: pointer to an array of MSI-X entries
1183 * @minvec: minimum number of MSI-X IRQs requested
1184 * @maxvec: maximum number of MSI-X IRQs requested
1186 * Setup the MSI-X capability structure of device function with a maximum
1187 * possible number of interrupts in the range between @minvec and @maxvec
1188 * upon its software driver call to request for MSI-X mode enabled on its
1189 * hardware device function. It returns a negative errno if an error occurs.
1190 * If it succeeds, it returns the actual number of interrupts allocated and
1191 * indicates the successful configuration of MSI-X capability structure
1192 * with new allocated MSI-X interrupts.
1194 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1195 int minvec, int maxvec)
1197 return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL, 0);
1199 EXPORT_SYMBOL(pci_enable_msix_range);
1202 * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device
1203 * @dev: PCI device to operate on
1204 * @min_vecs: minimum number of vectors required (must be >= 1)
1205 * @max_vecs: maximum (desired) number of vectors
1206 * @flags: flags or quirks for the allocation
1207 * @affd: optional description of the affinity requirements
1209 * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
1210 * vectors if available, and fall back to a single legacy vector
1211 * if neither is available. Return the number of vectors allocated,
1212 * (which might be smaller than @max_vecs) if successful, or a negative
1213 * error code on error. If less than @min_vecs interrupt vectors are
1214 * available for @dev the function will fail with -ENOSPC.
1216 * To get the Linux IRQ number used for a vector that can be passed to
1217 * request_irq() use the pci_irq_vector() helper.
1219 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1220 unsigned int max_vecs, unsigned int flags,
1221 struct irq_affinity *affd)
1223 struct irq_affinity msi_default_affd = {0};
1224 int nvecs = -ENOSPC;
1226 if (flags & PCI_IRQ_AFFINITY) {
1228 affd = &msi_default_affd;
1234 if (flags & PCI_IRQ_MSIX) {
1235 nvecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs,
1241 if (flags & PCI_IRQ_MSI) {
1242 nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd);
1247 /* use legacy IRQ if allowed */
1248 if (flags & PCI_IRQ_LEGACY) {
1249 if (min_vecs == 1 && dev->irq) {
1251 * Invoke the affinity spreading logic to ensure that
1252 * the device driver can adjust queue configuration
1253 * for the single interrupt case.
1256 irq_create_affinity_masks(1, affd);
1264 EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity);
1267 * pci_free_irq_vectors - free previously allocated IRQs for a device
1268 * @dev: PCI device to operate on
1270 * Undoes the allocations and enabling in pci_alloc_irq_vectors().
1272 void pci_free_irq_vectors(struct pci_dev *dev)
1274 pci_disable_msix(dev);
1275 pci_disable_msi(dev);
1277 EXPORT_SYMBOL(pci_free_irq_vectors);
1280 * pci_irq_vector - return Linux IRQ number of a device vector
1281 * @dev: PCI device to operate on
1282 * @nr: device-relative interrupt vector index (0-based).
1284 int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1286 if (dev->msix_enabled) {
1287 struct msi_desc *entry;
1290 for_each_pci_msi_entry(entry, dev) {
1299 if (dev->msi_enabled) {
1300 struct msi_desc *entry = first_pci_msi_entry(dev);
1302 if (WARN_ON_ONCE(nr >= entry->nvec_used))
1305 if (WARN_ON_ONCE(nr > 0))
1309 return dev->irq + nr;
1311 EXPORT_SYMBOL(pci_irq_vector);
1314 * pci_irq_get_affinity - return the affinity of a particular MSI vector
1315 * @dev: PCI device to operate on
1316 * @nr: device-relative interrupt vector index (0-based).
1318 const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
1320 if (dev->msix_enabled) {
1321 struct msi_desc *entry;
1324 for_each_pci_msi_entry(entry, dev) {
1326 return &entry->affinity->mask;
1331 } else if (dev->msi_enabled) {
1332 struct msi_desc *entry = first_pci_msi_entry(dev);
1334 if (WARN_ON_ONCE(!entry || !entry->affinity ||
1335 nr >= entry->nvec_used))
1338 return &entry->affinity[nr].mask;
1340 return cpu_possible_mask;
1343 EXPORT_SYMBOL(pci_irq_get_affinity);
1345 struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1347 return to_pci_dev(desc->dev);
1349 EXPORT_SYMBOL(msi_desc_to_pci_dev);
1351 void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
1353 struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1355 return dev->bus->sysdata;
1357 EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
1359 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1361 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1362 * @irq_data: Pointer to interrupt data of the MSI interrupt
1363 * @msg: Pointer to the message
1365 void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1367 struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
1370 * For MSI-X desc->irq is always equal to irq_data->irq. For
1371 * MSI only the first interrupt of MULTI MSI passes the test.
1373 if (desc->irq == irq_data->irq)
1374 __pci_write_msi_msg(desc, msg);
1378 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1379 * @desc: Pointer to the MSI descriptor
1381 * The ID number is only used within the irqdomain.
1383 static irq_hw_number_t pci_msi_domain_calc_hwirq(struct msi_desc *desc)
1385 struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1387 return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1388 pci_dev_id(dev) << 11 |
1389 (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
1392 static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1394 return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1398 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities
1400 * @domain: The interrupt domain to check
1401 * @info: The domain info for verification
1402 * @dev: The device to check
1405 * 0 if the functionality is supported
1406 * 1 if Multi MSI is requested, but the domain does not support it
1407 * -ENOTSUPP otherwise
1409 int pci_msi_domain_check_cap(struct irq_domain *domain,
1410 struct msi_domain_info *info, struct device *dev)
1412 struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1414 /* Special handling to support __pci_enable_msi_range() */
1415 if (pci_msi_desc_is_multi_msi(desc) &&
1416 !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1418 else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1424 static int pci_msi_domain_handle_error(struct irq_domain *domain,
1425 struct msi_desc *desc, int error)
1427 /* Special handling to support __pci_enable_msi_range() */
1428 if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1434 static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1435 struct msi_desc *desc)
1438 arg->hwirq = pci_msi_domain_calc_hwirq(desc);
1441 static struct msi_domain_ops pci_msi_domain_ops_default = {
1442 .set_desc = pci_msi_domain_set_desc,
1443 .msi_check = pci_msi_domain_check_cap,
1444 .handle_error = pci_msi_domain_handle_error,
1447 static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1449 struct msi_domain_ops *ops = info->ops;
1452 info->ops = &pci_msi_domain_ops_default;
1454 if (ops->set_desc == NULL)
1455 ops->set_desc = pci_msi_domain_set_desc;
1456 if (ops->msi_check == NULL)
1457 ops->msi_check = pci_msi_domain_check_cap;
1458 if (ops->handle_error == NULL)
1459 ops->handle_error = pci_msi_domain_handle_error;
1463 static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1465 struct irq_chip *chip = info->chip;
1468 if (!chip->irq_write_msi_msg)
1469 chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1470 if (!chip->irq_mask)
1471 chip->irq_mask = pci_msi_mask_irq;
1472 if (!chip->irq_unmask)
1473 chip->irq_unmask = pci_msi_unmask_irq;
1477 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1478 * @fwnode: Optional fwnode of the interrupt controller
1479 * @info: MSI domain info
1480 * @parent: Parent irq domain
1482 * Updates the domain and chip ops and creates a MSI interrupt domain.
1485 * A domain pointer or NULL in case of failure.
1487 struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
1488 struct msi_domain_info *info,
1489 struct irq_domain *parent)
1491 struct irq_domain *domain;
1493 if (WARN_ON(info->flags & MSI_FLAG_LEVEL_CAPABLE))
1494 info->flags &= ~MSI_FLAG_LEVEL_CAPABLE;
1496 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1497 pci_msi_domain_update_dom_ops(info);
1498 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1499 pci_msi_domain_update_chip_ops(info);
1501 info->flags |= MSI_FLAG_ACTIVATE_EARLY;
1502 if (IS_ENABLED(CONFIG_GENERIC_IRQ_RESERVATION_MODE))
1503 info->flags |= MSI_FLAG_MUST_REACTIVATE;
1505 /* PCI-MSI is oneshot-safe */
1506 info->chip->flags |= IRQCHIP_ONESHOT_SAFE;
1508 domain = msi_create_irq_domain(fwnode, info, parent);
1512 irq_domain_update_bus_token(domain, DOMAIN_BUS_PCI_MSI);
1515 EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain);
1518 * Users of the generic MSI infrastructure expect a device to have a single ID,
1519 * so with DMA aliases we have to pick the least-worst compromise. Devices with
1520 * DMA phantom functions tend to still emit MSIs from the real function number,
1521 * so we ignore those and only consider topological aliases where either the
1522 * alias device or RID appears on a different bus number. We also make the
1523 * reasonable assumption that bridges are walked in an upstream direction (so
1524 * the last one seen wins), and the much braver assumption that the most likely
1525 * case is that of PCI->PCIe so we should always use the alias RID. This echoes
1526 * the logic from intel_irq_remapping's set_msi_sid(), which presumably works
1527 * well enough in practice; in the face of the horrible PCIe<->PCI-X conditions
1528 * for taking ownership all we can really do is close our eyes and hope...
1530 static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
1533 u8 bus = PCI_BUS_NUM(*pa);
1535 if (pdev->bus->number != bus || PCI_BUS_NUM(alias) != bus)
1542 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1543 * @domain: The interrupt domain
1544 * @pdev: The PCI device.
1546 * The RID for a device is formed from the alias, with a firmware
1547 * supplied mapping applied
1551 u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
1553 struct device_node *of_node;
1554 u32 rid = pci_dev_id(pdev);
1556 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1558 of_node = irq_domain_get_of_node(domain);
1559 rid = of_node ? of_msi_map_id(&pdev->dev, of_node, rid) :
1560 iort_msi_map_id(&pdev->dev, rid);
1566 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1567 * @pdev: The PCI device
1569 * Use the firmware data to find a device-specific MSI domain
1570 * (i.e. not one that is set as a default).
1572 * Returns: The corresponding MSI domain or NULL if none has been found.
1574 struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
1576 struct irq_domain *dom;
1577 u32 rid = pci_dev_id(pdev);
1579 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1580 dom = of_msi_map_get_device_domain(&pdev->dev, rid, DOMAIN_BUS_PCI_MSI);
1582 dom = iort_get_device_domain(&pdev->dev, rid,
1583 DOMAIN_BUS_PCI_MSI);
1588 * pci_dev_has_special_msi_domain - Check whether the device is handled by
1589 * a non-standard PCI-MSI domain
1590 * @pdev: The PCI device to check.
1592 * Returns: True if the device irqdomain or the bus irqdomain is
1593 * non-standard PCI/MSI.
1595 bool pci_dev_has_special_msi_domain(struct pci_dev *pdev)
1597 struct irq_domain *dom = dev_get_msi_domain(&pdev->dev);
1600 dom = dev_get_msi_domain(&pdev->bus->dev);
1605 return dom->bus_token != DOMAIN_BUS_PCI_MSI;
1608 #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */
1609 #endif /* CONFIG_PCI_MSI */
1611 void pci_msi_init(struct pci_dev *dev)
1616 * Disable the MSI hardware to avoid screaming interrupts
1617 * during boot. This is the power on reset default so
1618 * usually this should be a noop.
1620 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1624 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl);
1625 if (ctrl & PCI_MSI_FLAGS_ENABLE)
1626 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS,
1627 ctrl & ~PCI_MSI_FLAGS_ENABLE);
1629 if (!(ctrl & PCI_MSI_FLAGS_64BIT))
1630 dev->no_64bit_msi = 1;
1633 void pci_msix_init(struct pci_dev *dev)
1637 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1641 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
1642 if (ctrl & PCI_MSIX_FLAGS_ENABLE)
1643 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS,
1644 ctrl & ~PCI_MSIX_FLAGS_ENABLE);