3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/export.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
19 #include <linux/errno.h>
21 #include <linux/slab.h>
22 #include <linux/irqdomain.h>
26 static int pci_msi_enable = 1;
27 int pci_msi_ignore_mask;
29 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
31 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
32 static struct irq_domain *pci_msi_default_domain;
33 static DEFINE_MUTEX(pci_msi_domain_lock);
35 struct irq_domain * __weak arch_get_pci_msi_domain(struct pci_dev *dev)
37 return pci_msi_default_domain;
40 static struct irq_domain *pci_msi_get_domain(struct pci_dev *dev)
42 struct irq_domain *domain = NULL;
45 domain = dev->bus->msi->domain;
47 domain = arch_get_pci_msi_domain(dev);
52 static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
54 struct irq_domain *domain;
56 domain = pci_msi_get_domain(dev);
58 return pci_msi_domain_alloc_irqs(domain, dev, nvec, type);
60 return arch_setup_msi_irqs(dev, nvec, type);
63 static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
65 struct irq_domain *domain;
67 domain = pci_msi_get_domain(dev);
69 pci_msi_domain_free_irqs(domain, dev);
71 arch_teardown_msi_irqs(dev);
74 #define pci_msi_setup_msi_irqs arch_setup_msi_irqs
75 #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
80 int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
82 struct msi_controller *chip = dev->bus->msi;
85 if (!chip || !chip->setup_irq)
88 err = chip->setup_irq(chip, dev, desc);
92 irq_set_chip_data(desc->irq, chip);
97 void __weak arch_teardown_msi_irq(unsigned int irq)
99 struct msi_controller *chip = irq_get_chip_data(irq);
101 if (!chip || !chip->teardown_irq)
104 chip->teardown_irq(chip, irq);
107 int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
109 struct msi_desc *entry;
113 * If an architecture wants to support multiple MSI, it needs to
114 * override arch_setup_msi_irqs()
116 if (type == PCI_CAP_ID_MSI && nvec > 1)
119 list_for_each_entry(entry, &dev->msi_list, list) {
120 ret = arch_setup_msi_irq(dev, entry);
131 * We have a default implementation available as a separate non-weak
132 * function, as it is used by the Xen x86 PCI code
134 void default_teardown_msi_irqs(struct pci_dev *dev)
137 struct msi_desc *entry;
139 list_for_each_entry(entry, &dev->msi_list, list)
141 for (i = 0; i < entry->nvec_used; i++)
142 arch_teardown_msi_irq(entry->irq + i);
145 void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
147 return default_teardown_msi_irqs(dev);
150 static void default_restore_msi_irq(struct pci_dev *dev, int irq)
152 struct msi_desc *entry;
155 if (dev->msix_enabled) {
156 list_for_each_entry(entry, &dev->msi_list, list) {
157 if (irq == entry->irq)
160 } else if (dev->msi_enabled) {
161 entry = irq_get_msi_desc(irq);
165 __pci_write_msi_msg(entry, &entry->msg);
168 void __weak arch_restore_msi_irqs(struct pci_dev *dev)
170 return default_restore_msi_irqs(dev);
173 static inline __attribute_const__ u32 msi_mask(unsigned x)
175 /* Don't shift by >= width of type */
178 return (1 << (1 << x)) - 1;
182 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
183 * mask all MSI interrupts by clearing the MSI enable bit does not work
184 * reliably as devices without an INTx disable bit will then generate a
185 * level IRQ which will never be cleared.
187 u32 __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
189 u32 mask_bits = desc->masked;
191 if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
196 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
201 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
203 desc->masked = __pci_msi_desc_mask_irq(desc, mask, flag);
207 * This internal function does not flush PCI writes to the device.
208 * All users must ensure that they read from the device before either
209 * assuming that the device state is up to date, or returning out of this
210 * file. This saves a few milliseconds when initialising devices with lots
211 * of MSI-X interrupts.
213 u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
215 u32 mask_bits = desc->masked;
216 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
217 PCI_MSIX_ENTRY_VECTOR_CTRL;
219 if (pci_msi_ignore_mask)
222 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
224 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
225 writel(mask_bits, desc->mask_base + offset);
230 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
232 desc->masked = __pci_msix_desc_mask_irq(desc, flag);
235 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
237 struct msi_desc *desc = irq_data_get_msi(data);
239 if (desc->msi_attrib.is_msix) {
240 msix_mask_irq(desc, flag);
241 readl(desc->mask_base); /* Flush write to device */
243 unsigned offset = data->irq - desc->irq;
244 msi_mask_irq(desc, 1 << offset, flag << offset);
249 * pci_msi_mask_irq - Generic irq chip callback to mask PCI/MSI interrupts
250 * @data: pointer to irqdata associated to that interrupt
252 void pci_msi_mask_irq(struct irq_data *data)
254 msi_set_mask_bit(data, 1);
258 * pci_msi_unmask_irq - Generic irq chip callback to unmask PCI/MSI interrupts
259 * @data: pointer to irqdata associated to that interrupt
261 void pci_msi_unmask_irq(struct irq_data *data)
263 msi_set_mask_bit(data, 0);
266 void default_restore_msi_irqs(struct pci_dev *dev)
268 struct msi_desc *entry;
270 list_for_each_entry(entry, &dev->msi_list, list)
271 default_restore_msi_irq(dev, entry->irq);
274 void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
276 BUG_ON(entry->dev->current_state != PCI_D0);
278 if (entry->msi_attrib.is_msix) {
279 void __iomem *base = entry->mask_base +
280 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
282 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
283 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
284 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
286 struct pci_dev *dev = entry->dev;
287 int pos = dev->msi_cap;
290 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
292 if (entry->msi_attrib.is_64) {
293 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
295 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
298 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
304 void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
306 if (entry->dev->current_state != PCI_D0) {
307 /* Don't touch the hardware now */
308 } else if (entry->msi_attrib.is_msix) {
310 base = entry->mask_base +
311 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
313 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
314 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
315 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
317 struct pci_dev *dev = entry->dev;
318 int pos = dev->msi_cap;
321 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
322 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
323 msgctl |= entry->msi_attrib.multiple << 4;
324 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
326 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
328 if (entry->msi_attrib.is_64) {
329 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
331 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
334 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
341 void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
343 struct msi_desc *entry = irq_get_msi_desc(irq);
345 __pci_write_msi_msg(entry, msg);
347 EXPORT_SYMBOL_GPL(pci_write_msi_msg);
349 static void free_msi_irqs(struct pci_dev *dev)
351 struct msi_desc *entry, *tmp;
352 struct attribute **msi_attrs;
353 struct device_attribute *dev_attr;
356 list_for_each_entry(entry, &dev->msi_list, list)
358 for (i = 0; i < entry->nvec_used; i++)
359 BUG_ON(irq_has_action(entry->irq + i));
361 pci_msi_teardown_msi_irqs(dev);
363 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
364 if (entry->msi_attrib.is_msix) {
365 if (list_is_last(&entry->list, &dev->msi_list))
366 iounmap(entry->mask_base);
369 list_del(&entry->list);
373 if (dev->msi_irq_groups) {
374 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
375 msi_attrs = dev->msi_irq_groups[0]->attrs;
376 while (msi_attrs[count]) {
377 dev_attr = container_of(msi_attrs[count],
378 struct device_attribute, attr);
379 kfree(dev_attr->attr.name);
384 kfree(dev->msi_irq_groups[0]);
385 kfree(dev->msi_irq_groups);
386 dev->msi_irq_groups = NULL;
390 static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
392 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
396 INIT_LIST_HEAD(&desc->list);
402 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
404 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
405 pci_intx(dev, enable);
408 static void __pci_restore_msi_state(struct pci_dev *dev)
411 struct msi_desc *entry;
413 if (!dev->msi_enabled)
416 entry = irq_get_msi_desc(dev->irq);
418 pci_intx_for_msi(dev, 0);
419 pci_msi_set_enable(dev, 0);
420 arch_restore_msi_irqs(dev);
422 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
423 msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
425 control &= ~PCI_MSI_FLAGS_QSIZE;
426 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
427 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
430 static void __pci_restore_msix_state(struct pci_dev *dev)
432 struct msi_desc *entry;
434 if (!dev->msix_enabled)
436 BUG_ON(list_empty(&dev->msi_list));
438 /* route the table */
439 pci_intx_for_msi(dev, 0);
440 pci_msix_clear_and_set_ctrl(dev, 0,
441 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
443 arch_restore_msi_irqs(dev);
444 list_for_each_entry(entry, &dev->msi_list, list)
445 msix_mask_irq(entry, entry->masked);
447 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
450 void pci_restore_msi_state(struct pci_dev *dev)
452 __pci_restore_msi_state(dev);
453 __pci_restore_msix_state(dev);
455 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
457 static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
460 struct msi_desc *entry;
464 retval = kstrtoul(attr->attr.name, 10, &irq);
468 entry = irq_get_msi_desc(irq);
470 return sprintf(buf, "%s\n",
471 entry->msi_attrib.is_msix ? "msix" : "msi");
476 static int populate_msi_sysfs(struct pci_dev *pdev)
478 struct attribute **msi_attrs;
479 struct attribute *msi_attr;
480 struct device_attribute *msi_dev_attr;
481 struct attribute_group *msi_irq_group;
482 const struct attribute_group **msi_irq_groups;
483 struct msi_desc *entry;
488 /* Determine how many msi entries we have */
489 list_for_each_entry(entry, &pdev->msi_list, list)
494 /* Dynamically create the MSI attributes for the PCI device */
495 msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL);
498 list_for_each_entry(entry, &pdev->msi_list, list) {
499 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
502 msi_attrs[count] = &msi_dev_attr->attr;
504 sysfs_attr_init(&msi_dev_attr->attr);
505 msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
507 if (!msi_dev_attr->attr.name)
509 msi_dev_attr->attr.mode = S_IRUGO;
510 msi_dev_attr->show = msi_mode_show;
514 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
517 msi_irq_group->name = "msi_irqs";
518 msi_irq_group->attrs = msi_attrs;
520 msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL);
522 goto error_irq_group;
523 msi_irq_groups[0] = msi_irq_group;
525 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
527 goto error_irq_groups;
528 pdev->msi_irq_groups = msi_irq_groups;
533 kfree(msi_irq_groups);
535 kfree(msi_irq_group);
538 msi_attr = msi_attrs[count];
540 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
541 kfree(msi_attr->name);
544 msi_attr = msi_attrs[count];
550 static struct msi_desc *msi_setup_entry(struct pci_dev *dev, int nvec)
553 struct msi_desc *entry;
555 /* MSI Entry Initialization */
556 entry = alloc_msi_entry(dev);
560 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
562 entry->msi_attrib.is_msix = 0;
563 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
564 entry->msi_attrib.entry_nr = 0;
565 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
566 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
567 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
568 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
569 entry->nvec_used = nvec;
571 if (control & PCI_MSI_FLAGS_64BIT)
572 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
574 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
576 /* Save the initial mask status */
577 if (entry->msi_attrib.maskbit)
578 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
583 static int msi_verify_entries(struct pci_dev *dev)
585 struct msi_desc *entry;
587 list_for_each_entry(entry, &dev->msi_list, list) {
588 if (!dev->no_64bit_msi || !entry->msg.address_hi)
590 dev_err(&dev->dev, "Device has broken 64-bit MSI but arch"
591 " tried to assign one above 4G\n");
598 * msi_capability_init - configure device's MSI capability structure
599 * @dev: pointer to the pci_dev data structure of MSI device function
600 * @nvec: number of interrupts to allocate
602 * Setup the MSI capability structure of the device with the requested
603 * number of interrupts. A return value of zero indicates the successful
604 * setup of an entry with the new MSI irq. A negative return value indicates
605 * an error, and a positive return value indicates the number of interrupts
606 * which could have been allocated.
608 static int msi_capability_init(struct pci_dev *dev, int nvec)
610 struct msi_desc *entry;
614 pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
616 entry = msi_setup_entry(dev, nvec);
620 /* All MSIs are unmasked by default, Mask them all */
621 mask = msi_mask(entry->msi_attrib.multi_cap);
622 msi_mask_irq(entry, mask, mask);
624 list_add_tail(&entry->list, &dev->msi_list);
626 /* Configure MSI capability structure */
627 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
629 msi_mask_irq(entry, mask, ~mask);
634 ret = msi_verify_entries(dev);
636 msi_mask_irq(entry, mask, ~mask);
641 ret = populate_msi_sysfs(dev);
643 msi_mask_irq(entry, mask, ~mask);
648 /* Set MSI enabled bits */
649 pci_intx_for_msi(dev, 0);
650 pci_msi_set_enable(dev, 1);
651 dev->msi_enabled = 1;
653 pcibios_free_irq(dev);
654 dev->irq = entry->irq;
658 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
660 resource_size_t phys_addr;
665 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
667 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
668 flags = pci_resource_flags(dev, bir);
669 if (!flags || (flags & IORESOURCE_UNSET))
672 table_offset &= PCI_MSIX_TABLE_OFFSET;
673 phys_addr = pci_resource_start(dev, bir) + table_offset;
675 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
678 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
679 struct msix_entry *entries, int nvec)
681 struct msi_desc *entry;
684 for (i = 0; i < nvec; i++) {
685 entry = alloc_msi_entry(dev);
691 /* No enough memory. Don't try again */
695 entry->msi_attrib.is_msix = 1;
696 entry->msi_attrib.is_64 = 1;
697 entry->msi_attrib.entry_nr = entries[i].entry;
698 entry->msi_attrib.default_irq = dev->irq;
699 entry->mask_base = base;
700 entry->nvec_used = 1;
702 list_add_tail(&entry->list, &dev->msi_list);
708 static void msix_program_entries(struct pci_dev *dev,
709 struct msix_entry *entries)
711 struct msi_desc *entry;
714 list_for_each_entry(entry, &dev->msi_list, list) {
715 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
716 PCI_MSIX_ENTRY_VECTOR_CTRL;
718 entries[i].vector = entry->irq;
719 entry->masked = readl(entry->mask_base + offset);
720 msix_mask_irq(entry, 1);
726 * msix_capability_init - configure device's MSI-X capability
727 * @dev: pointer to the pci_dev data structure of MSI-X device function
728 * @entries: pointer to an array of struct msix_entry entries
729 * @nvec: number of @entries
731 * Setup the MSI-X capability structure of device function with a
732 * single MSI-X irq. A return of zero indicates the successful setup of
733 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
735 static int msix_capability_init(struct pci_dev *dev,
736 struct msix_entry *entries, int nvec)
742 /* Ensure MSI-X is disabled while it is set up */
743 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
745 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
746 /* Request & Map MSI-X table region */
747 base = msix_map_region(dev, msix_table_size(control));
751 ret = msix_setup_entries(dev, base, entries, nvec);
755 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
759 /* Check if all MSI entries honor device restrictions */
760 ret = msi_verify_entries(dev);
765 * Some devices require MSI-X to be enabled before we can touch the
766 * MSI-X registers. We need to mask all the vectors to prevent
767 * interrupts coming in before they're fully set up.
769 pci_msix_clear_and_set_ctrl(dev, 0,
770 PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE);
772 msix_program_entries(dev, entries);
774 ret = populate_msi_sysfs(dev);
778 /* Set MSI-X enabled bits and unmask the function */
779 pci_intx_for_msi(dev, 0);
780 dev->msix_enabled = 1;
781 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
783 pcibios_free_irq(dev);
789 * If we had some success, report the number of irqs
790 * we succeeded in setting up.
792 struct msi_desc *entry;
795 list_for_each_entry(entry, &dev->msi_list, list) {
810 * pci_msi_supported - check whether MSI may be enabled on a device
811 * @dev: pointer to the pci_dev data structure of MSI device function
812 * @nvec: how many MSIs have been requested ?
814 * Look at global flags, the device itself, and its parent buses
815 * to determine if MSI/-X are supported for the device. If MSI/-X is
816 * supported return 1, else return 0.
818 static int pci_msi_supported(struct pci_dev *dev, int nvec)
822 /* MSI must be globally enabled and supported by the device */
826 if (!dev || dev->no_msi || dev->current_state != PCI_D0)
830 * You can't ask to have 0 or less MSIs configured.
832 * b) the list manipulation code assumes nvec >= 1.
838 * Any bridge which does NOT route MSI transactions from its
839 * secondary bus to its primary bus must set NO_MSI flag on
840 * the secondary pci_bus.
841 * We expect only arch-specific PCI host bus controller driver
842 * or quirks for specific PCI bridges to be setting NO_MSI.
844 for (bus = dev->bus; bus; bus = bus->parent)
845 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
852 * pci_msi_vec_count - Return the number of MSI vectors a device can send
853 * @dev: device to report about
855 * This function returns the number of MSI vectors a device requested via
856 * Multiple Message Capable register. It returns a negative errno if the
857 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
858 * and returns a power of two, up to a maximum of 2^5 (32), according to the
861 int pci_msi_vec_count(struct pci_dev *dev)
869 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
870 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
874 EXPORT_SYMBOL(pci_msi_vec_count);
876 void pci_msi_shutdown(struct pci_dev *dev)
878 struct msi_desc *desc;
881 if (!pci_msi_enable || !dev || !dev->msi_enabled)
884 BUG_ON(list_empty(&dev->msi_list));
885 desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
887 pci_msi_set_enable(dev, 0);
888 pci_intx_for_msi(dev, 1);
889 dev->msi_enabled = 0;
891 /* Return the device with MSI unmasked as initial states */
892 mask = msi_mask(desc->msi_attrib.multi_cap);
893 /* Keep cached state to be restored */
894 __pci_msi_desc_mask_irq(desc, mask, ~mask);
896 /* Restore dev->irq to its default pin-assertion irq */
897 dev->irq = desc->msi_attrib.default_irq;
898 pcibios_alloc_irq(dev);
901 void pci_disable_msi(struct pci_dev *dev)
903 if (!pci_msi_enable || !dev || !dev->msi_enabled)
906 pci_msi_shutdown(dev);
909 EXPORT_SYMBOL(pci_disable_msi);
912 * pci_msix_vec_count - return the number of device's MSI-X table entries
913 * @dev: pointer to the pci_dev data structure of MSI-X device function
914 * This function returns the number of device's MSI-X table entries and
915 * therefore the number of MSI-X vectors device is capable of sending.
916 * It returns a negative errno if the device is not capable of sending MSI-X
919 int pci_msix_vec_count(struct pci_dev *dev)
926 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
927 return msix_table_size(control);
929 EXPORT_SYMBOL(pci_msix_vec_count);
932 * pci_enable_msix - configure device's MSI-X capability structure
933 * @dev: pointer to the pci_dev data structure of MSI-X device function
934 * @entries: pointer to an array of MSI-X entries
935 * @nvec: number of MSI-X irqs requested for allocation by device driver
937 * Setup the MSI-X capability structure of device function with the number
938 * of requested irqs upon its software driver call to request for
939 * MSI-X mode enabled on its hardware device function. A return of zero
940 * indicates the successful configuration of MSI-X capability structure
941 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
942 * Or a return of > 0 indicates that driver request is exceeding the number
943 * of irqs or MSI-X vectors available. Driver should use the returned value to
944 * re-send its request.
946 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
951 if (!pci_msi_supported(dev, nvec))
957 nr_entries = pci_msix_vec_count(dev);
960 if (nvec > nr_entries)
963 /* Check for any invalid entries */
964 for (i = 0; i < nvec; i++) {
965 if (entries[i].entry >= nr_entries)
966 return -EINVAL; /* invalid entry */
967 for (j = i + 1; j < nvec; j++) {
968 if (entries[i].entry == entries[j].entry)
969 return -EINVAL; /* duplicate entry */
972 WARN_ON(!!dev->msix_enabled);
974 /* Check whether driver already requested for MSI irq */
975 if (dev->msi_enabled) {
976 dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
979 return msix_capability_init(dev, entries, nvec);
981 EXPORT_SYMBOL(pci_enable_msix);
983 void pci_msix_shutdown(struct pci_dev *dev)
985 struct msi_desc *entry;
987 if (!pci_msi_enable || !dev || !dev->msix_enabled)
990 /* Return the device with MSI-X masked as initial states */
991 list_for_each_entry(entry, &dev->msi_list, list) {
992 /* Keep cached states to be restored */
993 __pci_msix_desc_mask_irq(entry, 1);
996 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
997 pci_intx_for_msi(dev, 1);
998 dev->msix_enabled = 0;
999 pcibios_alloc_irq(dev);
1002 void pci_disable_msix(struct pci_dev *dev)
1004 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1007 pci_msix_shutdown(dev);
1010 EXPORT_SYMBOL(pci_disable_msix);
1012 void pci_no_msi(void)
1018 * pci_msi_enabled - is MSI enabled?
1020 * Returns true if MSI has not been disabled by the command-line option
1023 int pci_msi_enabled(void)
1025 return pci_msi_enable;
1027 EXPORT_SYMBOL(pci_msi_enabled);
1029 void pci_msi_init_pci_dev(struct pci_dev *dev)
1031 INIT_LIST_HEAD(&dev->msi_list);
1035 * pci_enable_msi_range - configure device's MSI capability structure
1036 * @dev: device to configure
1037 * @minvec: minimal number of interrupts to configure
1038 * @maxvec: maximum number of interrupts to configure
1040 * This function tries to allocate a maximum possible number of interrupts in a
1041 * range between @minvec and @maxvec. It returns a negative errno if an error
1042 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1043 * and updates the @dev's irq member to the lowest new interrupt number;
1044 * the other interrupt numbers allocated to this device are consecutive.
1046 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec)
1051 if (!pci_msi_supported(dev, minvec))
1054 WARN_ON(!!dev->msi_enabled);
1056 /* Check whether driver already requested MSI-X irqs */
1057 if (dev->msix_enabled) {
1059 "can't enable MSI (MSI-X already enabled)\n");
1063 if (maxvec < minvec)
1066 nvec = pci_msi_vec_count(dev);
1069 else if (nvec < minvec)
1071 else if (nvec > maxvec)
1075 rc = msi_capability_init(dev, nvec);
1078 } else if (rc > 0) {
1087 EXPORT_SYMBOL(pci_enable_msi_range);
1090 * pci_enable_msix_range - configure device's MSI-X capability structure
1091 * @dev: pointer to the pci_dev data structure of MSI-X device function
1092 * @entries: pointer to an array of MSI-X entries
1093 * @minvec: minimum number of MSI-X irqs requested
1094 * @maxvec: maximum number of MSI-X irqs requested
1096 * Setup the MSI-X capability structure of device function with a maximum
1097 * possible number of interrupts in the range between @minvec and @maxvec
1098 * upon its software driver call to request for MSI-X mode enabled on its
1099 * hardware device function. It returns a negative errno if an error occurs.
1100 * If it succeeds, it returns the actual number of interrupts allocated and
1101 * indicates the successful configuration of MSI-X capability structure
1102 * with new allocated MSI-X interrupts.
1104 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1105 int minvec, int maxvec)
1110 if (maxvec < minvec)
1114 rc = pci_enable_msix(dev, entries, nvec);
1117 } else if (rc > 0) {
1126 EXPORT_SYMBOL(pci_enable_msix_range);
1128 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1130 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1131 * @irq_data: Pointer to interrupt data of the MSI interrupt
1132 * @msg: Pointer to the message
1134 void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1136 struct msi_desc *desc = irq_data->msi_desc;
1139 * For MSI-X desc->irq is always equal to irq_data->irq. For
1140 * MSI only the first interrupt of MULTI MSI passes the test.
1142 if (desc->irq == irq_data->irq)
1143 __pci_write_msi_msg(desc, msg);
1147 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1148 * @dev: Pointer to the PCI device
1149 * @desc: Pointer to the msi descriptor
1151 * The ID number is only used within the irqdomain.
1153 irq_hw_number_t pci_msi_domain_calc_hwirq(struct pci_dev *dev,
1154 struct msi_desc *desc)
1156 return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1157 PCI_DEVID(dev->bus->number, dev->devfn) << 11 |
1158 (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
1161 static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1163 return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1167 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities for @dev
1168 * @domain: The interrupt domain to check
1169 * @info: The domain info for verification
1170 * @dev: The device to check
1173 * 0 if the functionality is supported
1174 * 1 if Multi MSI is requested, but the domain does not support it
1175 * -ENOTSUPP otherwise
1177 int pci_msi_domain_check_cap(struct irq_domain *domain,
1178 struct msi_domain_info *info, struct device *dev)
1180 struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1182 /* Special handling to support pci_enable_msi_range() */
1183 if (pci_msi_desc_is_multi_msi(desc) &&
1184 !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1186 else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1192 static int pci_msi_domain_handle_error(struct irq_domain *domain,
1193 struct msi_desc *desc, int error)
1195 /* Special handling to support pci_enable_msi_range() */
1196 if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1202 #ifdef GENERIC_MSI_DOMAIN_OPS
1203 static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1204 struct msi_desc *desc)
1207 arg->hwirq = pci_msi_domain_calc_hwirq(msi_desc_to_pci_dev(desc),
1211 #define pci_msi_domain_set_desc NULL
1214 static struct msi_domain_ops pci_msi_domain_ops_default = {
1215 .set_desc = pci_msi_domain_set_desc,
1216 .msi_check = pci_msi_domain_check_cap,
1217 .handle_error = pci_msi_domain_handle_error,
1220 static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1222 struct msi_domain_ops *ops = info->ops;
1225 info->ops = &pci_msi_domain_ops_default;
1227 if (ops->set_desc == NULL)
1228 ops->set_desc = pci_msi_domain_set_desc;
1229 if (ops->msi_check == NULL)
1230 ops->msi_check = pci_msi_domain_check_cap;
1231 if (ops->handle_error == NULL)
1232 ops->handle_error = pci_msi_domain_handle_error;
1236 static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1238 struct irq_chip *chip = info->chip;
1241 if (!chip->irq_write_msi_msg)
1242 chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1246 * pci_msi_create_irq_domain - Creat a MSI interrupt domain
1247 * @node: Optional device-tree node of the interrupt controller
1248 * @info: MSI domain info
1249 * @parent: Parent irq domain
1251 * Updates the domain and chip ops and creates a MSI interrupt domain.
1254 * A domain pointer or NULL in case of failure.
1256 struct irq_domain *pci_msi_create_irq_domain(struct device_node *node,
1257 struct msi_domain_info *info,
1258 struct irq_domain *parent)
1260 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1261 pci_msi_domain_update_dom_ops(info);
1262 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1263 pci_msi_domain_update_chip_ops(info);
1265 return msi_create_irq_domain(node, info, parent);
1269 * pci_msi_domain_alloc_irqs - Allocate interrupts for @dev in @domain
1270 * @domain: The interrupt domain to allocate from
1271 * @dev: The device for which to allocate
1272 * @nvec: The number of interrupts to allocate
1273 * @type: Unused to allow simpler migration from the arch_XXX interfaces
1276 * A virtual interrupt number or an error code in case of failure
1278 int pci_msi_domain_alloc_irqs(struct irq_domain *domain, struct pci_dev *dev,
1281 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
1285 * pci_msi_domain_free_irqs - Free interrupts for @dev in @domain
1286 * @domain: The interrupt domain
1287 * @dev: The device for which to free interrupts
1289 void pci_msi_domain_free_irqs(struct irq_domain *domain, struct pci_dev *dev)
1291 msi_domain_free_irqs(domain, &dev->dev);
1295 * pci_msi_create_default_irq_domain - Create a default MSI interrupt domain
1296 * @node: Optional device-tree node of the interrupt controller
1297 * @info: MSI domain info
1298 * @parent: Parent irq domain
1300 * Returns: A domain pointer or NULL in case of failure. If successful
1301 * the default PCI/MSI irqdomain pointer is updated.
1303 struct irq_domain *pci_msi_create_default_irq_domain(struct device_node *node,
1304 struct msi_domain_info *info, struct irq_domain *parent)
1306 struct irq_domain *domain;
1308 mutex_lock(&pci_msi_domain_lock);
1309 if (pci_msi_default_domain) {
1310 pr_err("PCI: default irq domain for PCI MSI has already been created.\n");
1313 domain = pci_msi_create_irq_domain(node, info, parent);
1314 pci_msi_default_domain = domain;
1316 mutex_unlock(&pci_msi_domain_lock);
1320 #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */