1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 * Copyright (C) 2016 Christoph Hellwig.
10 #include <linux/export.h>
11 #include <linux/irq.h>
16 static int pci_msi_enable = 1;
17 int pci_msi_ignore_mask;
19 static noinline void pci_msi_update_mask(struct msi_desc *desc, u32 clear, u32 set)
21 raw_spinlock_t *lock = &to_pci_dev(desc->dev)->msi_lock;
24 if (!desc->pci.msi_attrib.can_mask)
27 raw_spin_lock_irqsave(lock, flags);
28 desc->pci.msi_mask &= ~clear;
29 desc->pci.msi_mask |= set;
30 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->pci.mask_pos,
32 raw_spin_unlock_irqrestore(lock, flags);
35 static inline void pci_msi_mask(struct msi_desc *desc, u32 mask)
37 pci_msi_update_mask(desc, 0, mask);
40 static inline void pci_msi_unmask(struct msi_desc *desc, u32 mask)
42 pci_msi_update_mask(desc, mask, 0);
45 static inline void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
47 return desc->pci.mask_base + desc->msi_index * PCI_MSIX_ENTRY_SIZE;
51 * This internal function does not flush PCI writes to the device. All
52 * users must ensure that they read from the device before either assuming
53 * that the device state is up to date, or returning out of this file.
54 * It does not affect the msi_desc::msix_ctrl cache either. Use with care!
56 static void pci_msix_write_vector_ctrl(struct msi_desc *desc, u32 ctrl)
58 void __iomem *desc_addr = pci_msix_desc_addr(desc);
60 if (desc->pci.msi_attrib.can_mask)
61 writel(ctrl, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
64 static inline void pci_msix_mask(struct msi_desc *desc)
66 desc->pci.msix_ctrl |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
67 pci_msix_write_vector_ctrl(desc, desc->pci.msix_ctrl);
68 /* Flush write to device */
69 readl(desc->pci.mask_base);
72 static inline void pci_msix_unmask(struct msi_desc *desc)
74 desc->pci.msix_ctrl &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
75 pci_msix_write_vector_ctrl(desc, desc->pci.msix_ctrl);
78 static void __pci_msi_mask_desc(struct msi_desc *desc, u32 mask)
80 if (desc->pci.msi_attrib.is_msix)
83 pci_msi_mask(desc, mask);
86 static void __pci_msi_unmask_desc(struct msi_desc *desc, u32 mask)
88 if (desc->pci.msi_attrib.is_msix)
89 pci_msix_unmask(desc);
91 pci_msi_unmask(desc, mask);
95 * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts
96 * @data: pointer to irqdata associated to that interrupt
98 void pci_msi_mask_irq(struct irq_data *data)
100 struct msi_desc *desc = irq_data_get_msi_desc(data);
102 __pci_msi_mask_desc(desc, BIT(data->irq - desc->irq));
104 EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
107 * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts
108 * @data: pointer to irqdata associated to that interrupt
110 void pci_msi_unmask_irq(struct irq_data *data)
112 struct msi_desc *desc = irq_data_get_msi_desc(data);
114 __pci_msi_unmask_desc(desc, BIT(data->irq - desc->irq));
116 EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
118 void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
120 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
122 BUG_ON(dev->current_state != PCI_D0);
124 if (entry->pci.msi_attrib.is_msix) {
125 void __iomem *base = pci_msix_desc_addr(entry);
127 if (WARN_ON_ONCE(entry->pci.msi_attrib.is_virtual))
130 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
131 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
132 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
134 int pos = dev->msi_cap;
137 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
139 if (entry->pci.msi_attrib.is_64) {
140 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
142 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
145 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
151 void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
153 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
155 if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) {
156 /* Don't touch the hardware now */
157 } else if (entry->pci.msi_attrib.is_msix) {
158 void __iomem *base = pci_msix_desc_addr(entry);
159 u32 ctrl = entry->pci.msix_ctrl;
160 bool unmasked = !(ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT);
162 if (entry->pci.msi_attrib.is_virtual)
166 * The specification mandates that the entry is masked
167 * when the message is modified:
169 * "If software changes the Address or Data value of an
170 * entry while the entry is unmasked, the result is
174 pci_msix_write_vector_ctrl(entry, ctrl | PCI_MSIX_ENTRY_CTRL_MASKBIT);
176 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
177 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
178 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
181 pci_msix_write_vector_ctrl(entry, ctrl);
183 /* Ensure that the writes are visible in the device */
184 readl(base + PCI_MSIX_ENTRY_DATA);
186 int pos = dev->msi_cap;
189 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
190 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
191 msgctl |= entry->pci.msi_attrib.multiple << 4;
192 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
194 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
196 if (entry->pci.msi_attrib.is_64) {
197 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
199 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
202 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
205 /* Ensure that the writes are visible in the device */
206 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
212 if (entry->write_msi_msg)
213 entry->write_msi_msg(entry, entry->write_msi_msg_data);
217 void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
219 struct msi_desc *entry = irq_get_msi_desc(irq);
221 __pci_write_msi_msg(entry, msg);
223 EXPORT_SYMBOL_GPL(pci_write_msi_msg);
225 static void free_msi_irqs(struct pci_dev *dev)
227 pci_msi_teardown_msi_irqs(dev);
229 if (dev->msix_base) {
230 iounmap(dev->msix_base);
231 dev->msix_base = NULL;
235 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
237 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
238 pci_intx(dev, enable);
241 static void pci_msi_set_enable(struct pci_dev *dev, int enable)
245 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
246 control &= ~PCI_MSI_FLAGS_ENABLE;
248 control |= PCI_MSI_FLAGS_ENABLE;
249 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
253 * Architecture override returns true when the PCI MSI message should be
254 * written by the generic restore function.
256 bool __weak arch_restore_msi_irqs(struct pci_dev *dev)
261 static void __pci_restore_msi_state(struct pci_dev *dev)
263 struct msi_desc *entry;
266 if (!dev->msi_enabled)
269 entry = irq_get_msi_desc(dev->irq);
271 pci_intx_for_msi(dev, 0);
272 pci_msi_set_enable(dev, 0);
273 if (arch_restore_msi_irqs(dev))
274 __pci_write_msi_msg(entry, &entry->msg);
276 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
277 pci_msi_update_mask(entry, 0, 0);
278 control &= ~PCI_MSI_FLAGS_QSIZE;
279 control |= (entry->pci.msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
280 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
283 static void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
287 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
290 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
293 static void __pci_restore_msix_state(struct pci_dev *dev)
295 struct msi_desc *entry;
298 if (!dev->msix_enabled)
301 /* route the table */
302 pci_intx_for_msi(dev, 0);
303 pci_msix_clear_and_set_ctrl(dev, 0,
304 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
306 write_msg = arch_restore_msi_irqs(dev);
308 msi_lock_descs(&dev->dev);
309 msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) {
311 __pci_write_msi_msg(entry, &entry->msg);
312 pci_msix_write_vector_ctrl(entry, entry->pci.msix_ctrl);
314 msi_unlock_descs(&dev->dev);
316 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
319 void pci_restore_msi_state(struct pci_dev *dev)
321 __pci_restore_msi_state(dev);
322 __pci_restore_msix_state(dev);
324 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
326 static void pcim_msi_release(void *pcidev)
328 struct pci_dev *dev = pcidev;
330 dev->is_msi_managed = false;
331 pci_free_irq_vectors(dev);
335 * Needs to be separate from pcim_release to prevent an ordering problem
336 * vs. msi_device_data_release() in the MSI core code.
338 static int pcim_setup_msi_release(struct pci_dev *dev)
342 if (!pci_is_managed(dev) || dev->is_msi_managed)
345 ret = devm_add_action(&dev->dev, pcim_msi_release, dev);
347 dev->is_msi_managed = true;
352 * Ordering vs. devres: msi device data has to be installed first so that
353 * pcim_msi_release() is invoked before it on device release.
355 static int pci_setup_msi_context(struct pci_dev *dev)
357 int ret = msi_setup_device_data(&dev->dev);
360 ret = pcim_setup_msi_release(dev);
364 static int msi_setup_msi_desc(struct pci_dev *dev, int nvec,
365 struct irq_affinity_desc *masks)
367 struct msi_desc desc;
370 /* MSI Entry Initialization */
371 memset(&desc, 0, sizeof(desc));
373 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
374 /* Lies, damned lies, and MSIs */
375 if (dev->dev_flags & PCI_DEV_FLAGS_HAS_MSI_MASKING)
376 control |= PCI_MSI_FLAGS_MASKBIT;
377 /* Respect XEN's mask disabling */
378 if (pci_msi_ignore_mask)
379 control &= ~PCI_MSI_FLAGS_MASKBIT;
381 desc.nvec_used = nvec;
382 desc.pci.msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
383 desc.pci.msi_attrib.can_mask = !!(control & PCI_MSI_FLAGS_MASKBIT);
384 desc.pci.msi_attrib.default_irq = dev->irq;
385 desc.pci.msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
386 desc.pci.msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
387 desc.affinity = masks;
389 if (control & PCI_MSI_FLAGS_64BIT)
390 desc.pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
392 desc.pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
394 /* Save the initial mask status */
395 if (desc.pci.msi_attrib.can_mask)
396 pci_read_config_dword(dev, desc.pci.mask_pos, &desc.pci.msi_mask);
398 return msi_add_msi_desc(&dev->dev, &desc);
401 static int msi_verify_entries(struct pci_dev *dev)
403 struct msi_desc *entry;
405 if (!dev->no_64bit_msi)
408 msi_for_each_desc(entry, &dev->dev, MSI_DESC_ALL) {
409 if (entry->msg.address_hi) {
410 pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n",
411 entry->msg.address_hi, entry->msg.address_lo);
415 return !entry ? 0 : -EIO;
419 * msi_capability_init - configure device's MSI capability structure
420 * @dev: pointer to the pci_dev data structure of MSI device function
421 * @nvec: number of interrupts to allocate
422 * @affd: description of automatic IRQ affinity assignments (may be %NULL)
424 * Setup the MSI capability structure of the device with the requested
425 * number of interrupts. A return value of zero indicates the successful
426 * setup of an entry with the new MSI IRQ. A negative return value indicates
427 * an error, and a positive return value indicates the number of interrupts
428 * which could have been allocated.
430 static int msi_capability_init(struct pci_dev *dev, int nvec,
431 struct irq_affinity *affd)
433 struct irq_affinity_desc *masks = NULL;
434 struct msi_desc *entry;
438 * Disable MSI during setup in the hardware, but mark it enabled
439 * so that setup code can evaluate it.
441 pci_msi_set_enable(dev, 0);
442 dev->msi_enabled = 1;
445 masks = irq_create_affinity_masks(nvec, affd);
447 msi_lock_descs(&dev->dev);
448 ret = msi_setup_msi_desc(dev, nvec, masks);
452 /* All MSIs are unmasked by default; mask them all */
453 entry = msi_first_desc(&dev->dev, MSI_DESC_ALL);
454 pci_msi_mask(entry, msi_multi_mask(entry));
456 /* Configure MSI capability structure */
457 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
461 ret = msi_verify_entries(dev);
465 /* Set MSI enabled bits */
466 pci_intx_for_msi(dev, 0);
467 pci_msi_set_enable(dev, 1);
469 pcibios_free_irq(dev);
470 dev->irq = entry->irq;
474 pci_msi_unmask(entry, msi_multi_mask(entry));
477 dev->msi_enabled = 0;
479 msi_unlock_descs(&dev->dev);
484 static void __iomem *msix_map_region(struct pci_dev *dev,
485 unsigned int nr_entries)
487 resource_size_t phys_addr;
492 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
494 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
495 flags = pci_resource_flags(dev, bir);
496 if (!flags || (flags & IORESOURCE_UNSET))
499 table_offset &= PCI_MSIX_TABLE_OFFSET;
500 phys_addr = pci_resource_start(dev, bir) + table_offset;
502 return ioremap(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
505 static int msix_setup_msi_descs(struct pci_dev *dev, void __iomem *base,
506 struct msix_entry *entries, int nvec,
507 struct irq_affinity_desc *masks)
509 int ret = 0, i, vec_count = pci_msix_vec_count(dev);
510 struct irq_affinity_desc *curmsk;
511 struct msi_desc desc;
514 memset(&desc, 0, sizeof(desc));
517 desc.pci.msi_attrib.is_msix = 1;
518 desc.pci.msi_attrib.is_64 = 1;
519 desc.pci.msi_attrib.default_irq = dev->irq;
520 desc.pci.mask_base = base;
522 for (i = 0, curmsk = masks; i < nvec; i++, curmsk++) {
523 desc.msi_index = entries ? entries[i].entry : i;
524 desc.affinity = masks ? curmsk : NULL;
525 desc.pci.msi_attrib.is_virtual = desc.msi_index >= vec_count;
526 desc.pci.msi_attrib.can_mask = !pci_msi_ignore_mask &&
527 !desc.pci.msi_attrib.is_virtual;
529 if (!desc.pci.msi_attrib.can_mask) {
530 addr = pci_msix_desc_addr(&desc);
531 desc.pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
534 ret = msi_add_msi_desc(&dev->dev, &desc);
541 static void msix_update_entries(struct pci_dev *dev, struct msix_entry *entries)
543 struct msi_desc *desc;
546 msi_for_each_desc(desc, &dev->dev, MSI_DESC_ALL) {
547 entries->vector = desc->irq;
553 static void msix_mask_all(void __iomem *base, int tsize)
555 u32 ctrl = PCI_MSIX_ENTRY_CTRL_MASKBIT;
558 if (pci_msi_ignore_mask)
561 for (i = 0; i < tsize; i++, base += PCI_MSIX_ENTRY_SIZE)
562 writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL);
565 static int msix_setup_interrupts(struct pci_dev *dev, void __iomem *base,
566 struct msix_entry *entries, int nvec,
567 struct irq_affinity *affd)
569 struct irq_affinity_desc *masks = NULL;
573 masks = irq_create_affinity_masks(nvec, affd);
575 msi_lock_descs(&dev->dev);
576 ret = msix_setup_msi_descs(dev, base, entries, nvec, masks);
580 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
584 /* Check if all MSI entries honor device restrictions */
585 ret = msi_verify_entries(dev);
589 msix_update_entries(dev, entries);
595 msi_unlock_descs(&dev->dev);
601 * msix_capability_init - configure device's MSI-X capability
602 * @dev: pointer to the pci_dev data structure of MSI-X device function
603 * @entries: pointer to an array of struct msix_entry entries
604 * @nvec: number of @entries
605 * @affd: Optional pointer to enable automatic affinity assignment
607 * Setup the MSI-X capability structure of device function with a
608 * single MSI-X IRQ. A return of zero indicates the successful setup of
609 * requested MSI-X entries with allocated IRQs or non-zero for otherwise.
611 static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
612 int nvec, struct irq_affinity *affd)
619 * Some devices require MSI-X to be enabled before the MSI-X
620 * registers can be accessed. Mask all the vectors to prevent
621 * interrupts coming in before they're fully set up.
623 pci_msix_clear_and_set_ctrl(dev, 0, PCI_MSIX_FLAGS_MASKALL |
624 PCI_MSIX_FLAGS_ENABLE);
626 /* Mark it enabled so setup functions can query it */
627 dev->msix_enabled = 1;
629 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
630 /* Request & Map MSI-X table region */
631 tsize = msix_table_size(control);
632 base = msix_map_region(dev, tsize);
638 dev->msix_base = base;
640 ret = msix_setup_interrupts(dev, base, entries, nvec, affd);
645 pci_intx_for_msi(dev, 0);
648 * Ensure that all table entries are masked to prevent
649 * stale entries from firing in a crash kernel.
651 * Done late to deal with a broken Marvell NVME device
652 * which takes the MSI-X mask bits into account even
653 * when MSI-X is disabled, which prevents MSI delivery.
655 msix_mask_all(base, tsize);
656 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
658 pcibios_free_irq(dev);
662 dev->msix_enabled = 0;
663 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE, 0);
669 * pci_msi_supported - check whether MSI may be enabled on a device
670 * @dev: pointer to the pci_dev data structure of MSI device function
671 * @nvec: how many MSIs have been requested?
673 * Look at global flags, the device itself, and its parent buses
674 * to determine if MSI/-X are supported for the device. If MSI/-X is
675 * supported return 1, else return 0.
677 static int pci_msi_supported(struct pci_dev *dev, int nvec)
681 /* MSI must be globally enabled and supported by the device */
685 if (!dev || dev->no_msi)
689 * You can't ask to have 0 or less MSIs configured.
691 * b) the list manipulation code assumes nvec >= 1.
697 * Any bridge which does NOT route MSI transactions from its
698 * secondary bus to its primary bus must set NO_MSI flag on
699 * the secondary pci_bus.
701 * The NO_MSI flag can either be set directly by:
702 * - arch-specific PCI host bus controller drivers (deprecated)
703 * - quirks for specific PCI bridges
705 * or indirectly by platform-specific PCI host bridge drivers by
706 * advertising the 'msi_domain' property, which results in
707 * the NO_MSI flag when no MSI domain is found for this bridge
710 for (bus = dev->bus; bus; bus = bus->parent)
711 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
718 * pci_msi_vec_count - Return the number of MSI vectors a device can send
719 * @dev: device to report about
721 * This function returns the number of MSI vectors a device requested via
722 * Multiple Message Capable register. It returns a negative errno if the
723 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
724 * and returns a power of two, up to a maximum of 2^5 (32), according to the
727 int pci_msi_vec_count(struct pci_dev *dev)
735 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
736 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
740 EXPORT_SYMBOL(pci_msi_vec_count);
742 static void pci_msi_shutdown(struct pci_dev *dev)
744 struct msi_desc *desc;
746 if (!pci_msi_enable || !dev || !dev->msi_enabled)
749 pci_msi_set_enable(dev, 0);
750 pci_intx_for_msi(dev, 1);
751 dev->msi_enabled = 0;
753 /* Return the device with MSI unmasked as initial states */
754 desc = msi_first_desc(&dev->dev, MSI_DESC_ALL);
755 if (!WARN_ON_ONCE(!desc))
756 pci_msi_unmask(desc, msi_multi_mask(desc));
758 /* Restore dev->irq to its default pin-assertion IRQ */
759 dev->irq = desc->pci.msi_attrib.default_irq;
760 pcibios_alloc_irq(dev);
763 void pci_disable_msi(struct pci_dev *dev)
765 if (!pci_msi_enable || !dev || !dev->msi_enabled)
768 msi_lock_descs(&dev->dev);
769 pci_msi_shutdown(dev);
771 msi_unlock_descs(&dev->dev);
773 EXPORT_SYMBOL(pci_disable_msi);
776 * pci_msix_vec_count - return the number of device's MSI-X table entries
777 * @dev: pointer to the pci_dev data structure of MSI-X device function
778 * This function returns the number of device's MSI-X table entries and
779 * therefore the number of MSI-X vectors device is capable of sending.
780 * It returns a negative errno if the device is not capable of sending MSI-X
783 int pci_msix_vec_count(struct pci_dev *dev)
790 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
791 return msix_table_size(control);
793 EXPORT_SYMBOL(pci_msix_vec_count);
795 static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
796 int nvec, struct irq_affinity *affd, int flags)
801 if (!pci_msi_supported(dev, nvec) || dev->current_state != PCI_D0)
804 nr_entries = pci_msix_vec_count(dev);
807 if (nvec > nr_entries && !(flags & PCI_IRQ_VIRTUAL))
811 /* Check for any invalid entries */
812 for (i = 0; i < nvec; i++) {
813 if (entries[i].entry >= nr_entries)
814 return -EINVAL; /* invalid entry */
815 for (j = i + 1; j < nvec; j++) {
816 if (entries[i].entry == entries[j].entry)
817 return -EINVAL; /* duplicate entry */
822 /* Check whether driver already requested for MSI IRQ */
823 if (dev->msi_enabled) {
824 pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
827 return msix_capability_init(dev, entries, nvec, affd);
830 static void pci_msix_shutdown(struct pci_dev *dev)
832 struct msi_desc *desc;
834 if (!pci_msi_enable || !dev || !dev->msix_enabled)
837 if (pci_dev_is_disconnected(dev)) {
838 dev->msix_enabled = 0;
842 /* Return the device with MSI-X masked as initial states */
843 msi_for_each_desc(desc, &dev->dev, MSI_DESC_ALL)
846 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
847 pci_intx_for_msi(dev, 1);
848 dev->msix_enabled = 0;
849 pcibios_alloc_irq(dev);
852 void pci_disable_msix(struct pci_dev *dev)
854 if (!pci_msi_enable || !dev || !dev->msix_enabled)
857 msi_lock_descs(&dev->dev);
858 pci_msix_shutdown(dev);
860 msi_unlock_descs(&dev->dev);
862 EXPORT_SYMBOL(pci_disable_msix);
864 static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
865 struct irq_affinity *affd)
870 if (!pci_msi_supported(dev, minvec) || dev->current_state != PCI_D0)
873 /* Check whether driver already requested MSI-X IRQs */
874 if (dev->msix_enabled) {
875 pci_info(dev, "can't enable MSI (MSI-X already enabled)\n");
882 if (WARN_ON_ONCE(dev->msi_enabled))
885 nvec = pci_msi_vec_count(dev);
894 rc = pci_setup_msi_context(dev);
900 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
905 rc = msi_capability_init(dev, nvec, affd);
918 /* deprecated, don't use */
919 int pci_enable_msi(struct pci_dev *dev)
921 int rc = __pci_enable_msi_range(dev, 1, 1, NULL);
926 EXPORT_SYMBOL(pci_enable_msi);
928 static int __pci_enable_msix_range(struct pci_dev *dev,
929 struct msix_entry *entries, int minvec,
930 int maxvec, struct irq_affinity *affd,
933 int rc, nvec = maxvec;
938 if (WARN_ON_ONCE(dev->msix_enabled))
941 rc = pci_setup_msi_context(dev);
947 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
952 rc = __pci_enable_msix(dev, entries, nvec, affd, flags);
966 * pci_enable_msix_range - configure device's MSI-X capability structure
967 * @dev: pointer to the pci_dev data structure of MSI-X device function
968 * @entries: pointer to an array of MSI-X entries
969 * @minvec: minimum number of MSI-X IRQs requested
970 * @maxvec: maximum number of MSI-X IRQs requested
972 * Setup the MSI-X capability structure of device function with a maximum
973 * possible number of interrupts in the range between @minvec and @maxvec
974 * upon its software driver call to request for MSI-X mode enabled on its
975 * hardware device function. It returns a negative errno if an error occurs.
976 * If it succeeds, it returns the actual number of interrupts allocated and
977 * indicates the successful configuration of MSI-X capability structure
978 * with new allocated MSI-X interrupts.
980 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
981 int minvec, int maxvec)
983 return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL, 0);
985 EXPORT_SYMBOL(pci_enable_msix_range);
988 * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device
989 * @dev: PCI device to operate on
990 * @min_vecs: minimum number of vectors required (must be >= 1)
991 * @max_vecs: maximum (desired) number of vectors
992 * @flags: flags or quirks for the allocation
993 * @affd: optional description of the affinity requirements
995 * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
996 * vectors if available, and fall back to a single legacy vector
997 * if neither is available. Return the number of vectors allocated,
998 * (which might be smaller than @max_vecs) if successful, or a negative
999 * error code on error. If less than @min_vecs interrupt vectors are
1000 * available for @dev the function will fail with -ENOSPC.
1002 * To get the Linux IRQ number used for a vector that can be passed to
1003 * request_irq() use the pci_irq_vector() helper.
1005 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1006 unsigned int max_vecs, unsigned int flags,
1007 struct irq_affinity *affd)
1009 struct irq_affinity msi_default_affd = {0};
1010 int nvecs = -ENOSPC;
1012 if (flags & PCI_IRQ_AFFINITY) {
1014 affd = &msi_default_affd;
1020 if (flags & PCI_IRQ_MSIX) {
1021 nvecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs,
1027 if (flags & PCI_IRQ_MSI) {
1028 nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd);
1033 /* use legacy IRQ if allowed */
1034 if (flags & PCI_IRQ_LEGACY) {
1035 if (min_vecs == 1 && dev->irq) {
1037 * Invoke the affinity spreading logic to ensure that
1038 * the device driver can adjust queue configuration
1039 * for the single interrupt case.
1042 irq_create_affinity_masks(1, affd);
1050 EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity);
1053 * pci_free_irq_vectors - free previously allocated IRQs for a device
1054 * @dev: PCI device to operate on
1056 * Undoes the allocations and enabling in pci_alloc_irq_vectors().
1058 void pci_free_irq_vectors(struct pci_dev *dev)
1060 pci_disable_msix(dev);
1061 pci_disable_msi(dev);
1063 EXPORT_SYMBOL(pci_free_irq_vectors);
1066 * pci_irq_vector - return Linux IRQ number of a device vector
1067 * @dev: PCI device to operate on
1068 * @nr: Interrupt vector index (0-based)
1070 * @nr has the following meanings depending on the interrupt mode:
1071 * MSI-X: The index in the MSI-X vector table
1072 * MSI: The index of the enabled MSI vectors
1075 * Return: The Linux interrupt number or -EINVAl if @nr is out of range.
1077 int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1081 if (!dev->msi_enabled && !dev->msix_enabled)
1082 return !nr ? dev->irq : -EINVAL;
1084 irq = msi_get_virq(&dev->dev, nr);
1085 return irq ? irq : -EINVAL;
1087 EXPORT_SYMBOL(pci_irq_vector);
1090 * pci_irq_get_affinity - return the affinity of a particular MSI vector
1091 * @dev: PCI device to operate on
1092 * @nr: device-relative interrupt vector index (0-based).
1094 * @nr has the following meanings depending on the interrupt mode:
1095 * MSI-X: The index in the MSI-X vector table
1096 * MSI: The index of the enabled MSI vectors
1099 * Return: A cpumask pointer or NULL if @nr is out of range
1101 const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
1103 int idx, irq = pci_irq_vector(dev, nr);
1104 struct msi_desc *desc;
1106 if (WARN_ON_ONCE(irq <= 0))
1109 desc = irq_get_msi_desc(irq);
1110 /* Non-MSI does not have the information handy */
1112 return cpu_possible_mask;
1114 if (WARN_ON_ONCE(!desc->affinity))
1118 * MSI has a mask array in the descriptor.
1119 * MSI-X has a single mask.
1121 idx = dev->msi_enabled ? nr : 0;
1122 return &desc->affinity[idx].mask;
1124 EXPORT_SYMBOL(pci_irq_get_affinity);
1126 struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1128 return to_pci_dev(desc->dev);
1130 EXPORT_SYMBOL(msi_desc_to_pci_dev);
1132 void pci_no_msi(void)
1138 * pci_msi_enabled - is MSI enabled?
1140 * Returns true if MSI has not been disabled by the command-line option
1143 int pci_msi_enabled(void)
1145 return pci_msi_enable;
1147 EXPORT_SYMBOL(pci_msi_enabled);