1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 * Copyright (C) 2016 Christoph Hellwig.
10 #include <linux/export.h>
11 #include <linux/irq.h>
16 static int pci_msi_enable = 1;
17 int pci_msi_ignore_mask;
19 static noinline void pci_msi_update_mask(struct msi_desc *desc, u32 clear, u32 set)
21 raw_spinlock_t *lock = &to_pci_dev(desc->dev)->msi_lock;
24 if (!desc->pci.msi_attrib.can_mask)
27 raw_spin_lock_irqsave(lock, flags);
28 desc->pci.msi_mask &= ~clear;
29 desc->pci.msi_mask |= set;
30 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->pci.mask_pos,
32 raw_spin_unlock_irqrestore(lock, flags);
35 static inline void pci_msi_mask(struct msi_desc *desc, u32 mask)
37 pci_msi_update_mask(desc, 0, mask);
40 static inline void pci_msi_unmask(struct msi_desc *desc, u32 mask)
42 pci_msi_update_mask(desc, mask, 0);
45 static inline void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
47 return desc->pci.mask_base + desc->pci.msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
51 * This internal function does not flush PCI writes to the device. All
52 * users must ensure that they read from the device before either assuming
53 * that the device state is up to date, or returning out of this file.
54 * It does not affect the msi_desc::msix_ctrl cache either. Use with care!
56 static void pci_msix_write_vector_ctrl(struct msi_desc *desc, u32 ctrl)
58 void __iomem *desc_addr = pci_msix_desc_addr(desc);
60 if (desc->pci.msi_attrib.can_mask)
61 writel(ctrl, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
64 static inline void pci_msix_mask(struct msi_desc *desc)
66 desc->pci.msix_ctrl |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
67 pci_msix_write_vector_ctrl(desc, desc->pci.msix_ctrl);
68 /* Flush write to device */
69 readl(desc->pci.mask_base);
72 static inline void pci_msix_unmask(struct msi_desc *desc)
74 desc->pci.msix_ctrl &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
75 pci_msix_write_vector_ctrl(desc, desc->pci.msix_ctrl);
78 static void __pci_msi_mask_desc(struct msi_desc *desc, u32 mask)
80 if (desc->pci.msi_attrib.is_msix)
83 pci_msi_mask(desc, mask);
86 static void __pci_msi_unmask_desc(struct msi_desc *desc, u32 mask)
88 if (desc->pci.msi_attrib.is_msix)
89 pci_msix_unmask(desc);
91 pci_msi_unmask(desc, mask);
95 * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts
96 * @data: pointer to irqdata associated to that interrupt
98 void pci_msi_mask_irq(struct irq_data *data)
100 struct msi_desc *desc = irq_data_get_msi_desc(data);
102 __pci_msi_mask_desc(desc, BIT(data->irq - desc->irq));
104 EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
107 * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts
108 * @data: pointer to irqdata associated to that interrupt
110 void pci_msi_unmask_irq(struct irq_data *data)
112 struct msi_desc *desc = irq_data_get_msi_desc(data);
114 __pci_msi_unmask_desc(desc, BIT(data->irq - desc->irq));
116 EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
118 void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
120 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
122 BUG_ON(dev->current_state != PCI_D0);
124 if (entry->pci.msi_attrib.is_msix) {
125 void __iomem *base = pci_msix_desc_addr(entry);
127 if (WARN_ON_ONCE(entry->pci.msi_attrib.is_virtual))
130 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
131 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
132 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
134 int pos = dev->msi_cap;
137 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
139 if (entry->pci.msi_attrib.is_64) {
140 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
142 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
145 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
151 void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
153 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
155 if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) {
156 /* Don't touch the hardware now */
157 } else if (entry->pci.msi_attrib.is_msix) {
158 void __iomem *base = pci_msix_desc_addr(entry);
159 u32 ctrl = entry->pci.msix_ctrl;
160 bool unmasked = !(ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT);
162 if (entry->pci.msi_attrib.is_virtual)
166 * The specification mandates that the entry is masked
167 * when the message is modified:
169 * "If software changes the Address or Data value of an
170 * entry while the entry is unmasked, the result is
174 pci_msix_write_vector_ctrl(entry, ctrl | PCI_MSIX_ENTRY_CTRL_MASKBIT);
176 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
177 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
178 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
181 pci_msix_write_vector_ctrl(entry, ctrl);
183 /* Ensure that the writes are visible in the device */
184 readl(base + PCI_MSIX_ENTRY_DATA);
186 int pos = dev->msi_cap;
189 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
190 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
191 msgctl |= entry->pci.msi_attrib.multiple << 4;
192 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
194 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
196 if (entry->pci.msi_attrib.is_64) {
197 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
199 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
202 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
205 /* Ensure that the writes are visible in the device */
206 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
212 if (entry->write_msi_msg)
213 entry->write_msi_msg(entry, entry->write_msi_msg_data);
217 void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
219 struct msi_desc *entry = irq_get_msi_desc(irq);
221 __pci_write_msi_msg(entry, msg);
223 EXPORT_SYMBOL_GPL(pci_write_msi_msg);
225 static void free_msi_irqs(struct pci_dev *dev)
227 struct list_head *msi_list = dev_to_msi_list(&dev->dev);
228 struct msi_desc *entry, *tmp;
231 for_each_pci_msi_entry(entry, dev)
233 for (i = 0; i < entry->nvec_used; i++)
234 BUG_ON(irq_has_action(entry->irq + i));
236 if (dev->msi_irq_groups) {
237 msi_destroy_sysfs(&dev->dev, dev->msi_irq_groups);
238 dev->msi_irq_groups = NULL;
241 pci_msi_teardown_msi_irqs(dev);
243 list_for_each_entry_safe(entry, tmp, msi_list, list) {
244 list_del(&entry->list);
245 free_msi_entry(entry);
248 if (dev->msix_base) {
249 iounmap(dev->msix_base);
250 dev->msix_base = NULL;
254 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
256 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
257 pci_intx(dev, enable);
260 static void pci_msi_set_enable(struct pci_dev *dev, int enable)
264 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
265 control &= ~PCI_MSI_FLAGS_ENABLE;
267 control |= PCI_MSI_FLAGS_ENABLE;
268 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
272 * Architecture override returns true when the PCI MSI message should be
273 * written by the generic restore function.
275 bool __weak arch_restore_msi_irqs(struct pci_dev *dev)
280 static void __pci_restore_msi_state(struct pci_dev *dev)
282 struct msi_desc *entry;
285 if (!dev->msi_enabled)
288 entry = irq_get_msi_desc(dev->irq);
290 pci_intx_for_msi(dev, 0);
291 pci_msi_set_enable(dev, 0);
292 if (arch_restore_msi_irqs(dev))
293 __pci_write_msi_msg(entry, &entry->msg);
295 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
296 pci_msi_update_mask(entry, 0, 0);
297 control &= ~PCI_MSI_FLAGS_QSIZE;
298 control |= (entry->pci.msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
299 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
302 static void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
306 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
309 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
312 static void __pci_restore_msix_state(struct pci_dev *dev)
314 struct msi_desc *entry;
317 if (!dev->msix_enabled)
319 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
321 /* route the table */
322 pci_intx_for_msi(dev, 0);
323 pci_msix_clear_and_set_ctrl(dev, 0,
324 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
326 write_msg = arch_restore_msi_irqs(dev);
328 for_each_pci_msi_entry(entry, dev) {
330 __pci_write_msi_msg(entry, &entry->msg);
331 pci_msix_write_vector_ctrl(entry, entry->pci.msix_ctrl);
334 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
337 void pci_restore_msi_state(struct pci_dev *dev)
339 __pci_restore_msi_state(dev);
340 __pci_restore_msix_state(dev);
342 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
344 static struct msi_desc *
345 msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd)
347 struct irq_affinity_desc *masks = NULL;
348 struct msi_desc *entry;
352 masks = irq_create_affinity_masks(nvec, affd);
354 /* MSI Entry Initialization */
355 entry = alloc_msi_entry(&dev->dev, nvec, masks);
359 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
360 /* Lies, damned lies, and MSIs */
361 if (dev->dev_flags & PCI_DEV_FLAGS_HAS_MSI_MASKING)
362 control |= PCI_MSI_FLAGS_MASKBIT;
364 entry->pci.msi_attrib.is_msix = 0;
365 entry->pci.msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
366 entry->pci.msi_attrib.is_virtual = 0;
367 entry->pci.msi_attrib.entry_nr = 0;
368 entry->pci.msi_attrib.can_mask = !pci_msi_ignore_mask &&
369 !!(control & PCI_MSI_FLAGS_MASKBIT);
370 entry->pci.msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
371 entry->pci.msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
372 entry->pci.msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
374 if (control & PCI_MSI_FLAGS_64BIT)
375 entry->pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
377 entry->pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
379 /* Save the initial mask status */
380 if (entry->pci.msi_attrib.can_mask)
381 pci_read_config_dword(dev, entry->pci.mask_pos, &entry->pci.msi_mask);
388 static int msi_verify_entries(struct pci_dev *dev)
390 struct msi_desc *entry;
392 if (!dev->no_64bit_msi)
395 for_each_pci_msi_entry(entry, dev) {
396 if (entry->msg.address_hi) {
397 pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n",
398 entry->msg.address_hi, entry->msg.address_lo);
406 * msi_capability_init - configure device's MSI capability structure
407 * @dev: pointer to the pci_dev data structure of MSI device function
408 * @nvec: number of interrupts to allocate
409 * @affd: description of automatic IRQ affinity assignments (may be %NULL)
411 * Setup the MSI capability structure of the device with the requested
412 * number of interrupts. A return value of zero indicates the successful
413 * setup of an entry with the new MSI IRQ. A negative return value indicates
414 * an error, and a positive return value indicates the number of interrupts
415 * which could have been allocated.
417 static int msi_capability_init(struct pci_dev *dev, int nvec,
418 struct irq_affinity *affd)
420 const struct attribute_group **groups;
421 struct msi_desc *entry;
424 pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
426 entry = msi_setup_entry(dev, nvec, affd);
430 /* All MSIs are unmasked by default; mask them all */
431 pci_msi_mask(entry, msi_multi_mask(entry));
433 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
435 /* Configure MSI capability structure */
436 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
440 ret = msi_verify_entries(dev);
444 groups = msi_populate_sysfs(&dev->dev);
445 if (IS_ERR(groups)) {
446 ret = PTR_ERR(groups);
450 dev->msi_irq_groups = groups;
452 /* Set MSI enabled bits */
453 pci_intx_for_msi(dev, 0);
454 pci_msi_set_enable(dev, 1);
455 dev->msi_enabled = 1;
457 pcibios_free_irq(dev);
458 dev->irq = entry->irq;
462 pci_msi_unmask(entry, msi_multi_mask(entry));
467 static void __iomem *msix_map_region(struct pci_dev *dev,
468 unsigned int nr_entries)
470 resource_size_t phys_addr;
475 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
477 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
478 flags = pci_resource_flags(dev, bir);
479 if (!flags || (flags & IORESOURCE_UNSET))
482 table_offset &= PCI_MSIX_TABLE_OFFSET;
483 phys_addr = pci_resource_start(dev, bir) + table_offset;
485 return ioremap(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
488 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
489 struct msix_entry *entries, int nvec,
490 struct irq_affinity *affd)
492 struct irq_affinity_desc *curmsk, *masks = NULL;
493 struct msi_desc *entry;
496 int vec_count = pci_msix_vec_count(dev);
499 masks = irq_create_affinity_masks(nvec, affd);
501 for (i = 0, curmsk = masks; i < nvec; i++) {
502 entry = alloc_msi_entry(&dev->dev, 1, curmsk);
504 /* No enough memory. Don't try again */
509 entry->pci.msi_attrib.is_msix = 1;
510 entry->pci.msi_attrib.is_64 = 1;
513 entry->pci.msi_attrib.entry_nr = entries[i].entry;
515 entry->pci.msi_attrib.entry_nr = i;
517 entry->pci.msi_attrib.is_virtual =
518 entry->pci.msi_attrib.entry_nr >= vec_count;
520 entry->pci.msi_attrib.can_mask = !pci_msi_ignore_mask &&
521 !entry->pci.msi_attrib.is_virtual;
523 entry->pci.msi_attrib.default_irq = dev->irq;
524 entry->pci.mask_base = base;
526 if (entry->pci.msi_attrib.can_mask) {
527 addr = pci_msix_desc_addr(entry);
528 entry->pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
531 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
541 static void msix_update_entries(struct pci_dev *dev, struct msix_entry *entries)
543 struct msi_desc *entry;
546 for_each_pci_msi_entry(entry, dev) {
547 entries->vector = entry->irq;
553 static void msix_mask_all(void __iomem *base, int tsize)
555 u32 ctrl = PCI_MSIX_ENTRY_CTRL_MASKBIT;
558 if (pci_msi_ignore_mask)
561 for (i = 0; i < tsize; i++, base += PCI_MSIX_ENTRY_SIZE)
562 writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL);
566 * msix_capability_init - configure device's MSI-X capability
567 * @dev: pointer to the pci_dev data structure of MSI-X device function
568 * @entries: pointer to an array of struct msix_entry entries
569 * @nvec: number of @entries
570 * @affd: Optional pointer to enable automatic affinity assignment
572 * Setup the MSI-X capability structure of device function with a
573 * single MSI-X IRQ. A return of zero indicates the successful setup of
574 * requested MSI-X entries with allocated IRQs or non-zero for otherwise.
576 static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
577 int nvec, struct irq_affinity *affd)
579 const struct attribute_group **groups;
585 * Some devices require MSI-X to be enabled before the MSI-X
586 * registers can be accessed. Mask all the vectors to prevent
587 * interrupts coming in before they're fully set up.
589 pci_msix_clear_and_set_ctrl(dev, 0, PCI_MSIX_FLAGS_MASKALL |
590 PCI_MSIX_FLAGS_ENABLE);
592 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
593 /* Request & Map MSI-X table region */
594 tsize = msix_table_size(control);
595 base = msix_map_region(dev, tsize);
601 dev->msix_base = base;
603 ret = msix_setup_entries(dev, base, entries, nvec, affd);
607 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
611 /* Check if all MSI entries honor device restrictions */
612 ret = msi_verify_entries(dev);
616 msix_update_entries(dev, entries);
618 groups = msi_populate_sysfs(&dev->dev);
619 if (IS_ERR(groups)) {
620 ret = PTR_ERR(groups);
624 dev->msi_irq_groups = groups;
626 /* Set MSI-X enabled bits and unmask the function */
627 pci_intx_for_msi(dev, 0);
628 dev->msix_enabled = 1;
631 * Ensure that all table entries are masked to prevent
632 * stale entries from firing in a crash kernel.
634 * Done late to deal with a broken Marvell NVME device
635 * which takes the MSI-X mask bits into account even
636 * when MSI-X is disabled, which prevents MSI delivery.
638 msix_mask_all(base, tsize);
639 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
641 pcibios_free_irq(dev);
648 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE, 0);
654 * pci_msi_supported - check whether MSI may be enabled on a device
655 * @dev: pointer to the pci_dev data structure of MSI device function
656 * @nvec: how many MSIs have been requested?
658 * Look at global flags, the device itself, and its parent buses
659 * to determine if MSI/-X are supported for the device. If MSI/-X is
660 * supported return 1, else return 0.
662 static int pci_msi_supported(struct pci_dev *dev, int nvec)
666 /* MSI must be globally enabled and supported by the device */
670 if (!dev || dev->no_msi)
674 * You can't ask to have 0 or less MSIs configured.
676 * b) the list manipulation code assumes nvec >= 1.
682 * Any bridge which does NOT route MSI transactions from its
683 * secondary bus to its primary bus must set NO_MSI flag on
684 * the secondary pci_bus.
686 * The NO_MSI flag can either be set directly by:
687 * - arch-specific PCI host bus controller drivers (deprecated)
688 * - quirks for specific PCI bridges
690 * or indirectly by platform-specific PCI host bridge drivers by
691 * advertising the 'msi_domain' property, which results in
692 * the NO_MSI flag when no MSI domain is found for this bridge
695 for (bus = dev->bus; bus; bus = bus->parent)
696 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
703 * pci_msi_vec_count - Return the number of MSI vectors a device can send
704 * @dev: device to report about
706 * This function returns the number of MSI vectors a device requested via
707 * Multiple Message Capable register. It returns a negative errno if the
708 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
709 * and returns a power of two, up to a maximum of 2^5 (32), according to the
712 int pci_msi_vec_count(struct pci_dev *dev)
720 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
721 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
725 EXPORT_SYMBOL(pci_msi_vec_count);
727 static void pci_msi_shutdown(struct pci_dev *dev)
729 struct msi_desc *desc;
731 if (!pci_msi_enable || !dev || !dev->msi_enabled)
734 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
735 desc = first_pci_msi_entry(dev);
737 pci_msi_set_enable(dev, 0);
738 pci_intx_for_msi(dev, 1);
739 dev->msi_enabled = 0;
741 /* Return the device with MSI unmasked as initial states */
742 pci_msi_unmask(desc, msi_multi_mask(desc));
744 /* Restore dev->irq to its default pin-assertion IRQ */
745 dev->irq = desc->pci.msi_attrib.default_irq;
746 pcibios_alloc_irq(dev);
749 void pci_disable_msi(struct pci_dev *dev)
751 if (!pci_msi_enable || !dev || !dev->msi_enabled)
754 pci_msi_shutdown(dev);
757 EXPORT_SYMBOL(pci_disable_msi);
760 * pci_msix_vec_count - return the number of device's MSI-X table entries
761 * @dev: pointer to the pci_dev data structure of MSI-X device function
762 * This function returns the number of device's MSI-X table entries and
763 * therefore the number of MSI-X vectors device is capable of sending.
764 * It returns a negative errno if the device is not capable of sending MSI-X
767 int pci_msix_vec_count(struct pci_dev *dev)
774 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
775 return msix_table_size(control);
777 EXPORT_SYMBOL(pci_msix_vec_count);
779 static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
780 int nvec, struct irq_affinity *affd, int flags)
785 if (!pci_msi_supported(dev, nvec) || dev->current_state != PCI_D0)
788 nr_entries = pci_msix_vec_count(dev);
791 if (nvec > nr_entries && !(flags & PCI_IRQ_VIRTUAL))
795 /* Check for any invalid entries */
796 for (i = 0; i < nvec; i++) {
797 if (entries[i].entry >= nr_entries)
798 return -EINVAL; /* invalid entry */
799 for (j = i + 1; j < nvec; j++) {
800 if (entries[i].entry == entries[j].entry)
801 return -EINVAL; /* duplicate entry */
806 /* Check whether driver already requested for MSI IRQ */
807 if (dev->msi_enabled) {
808 pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
811 return msix_capability_init(dev, entries, nvec, affd);
814 static void pci_msix_shutdown(struct pci_dev *dev)
816 struct msi_desc *entry;
818 if (!pci_msi_enable || !dev || !dev->msix_enabled)
821 if (pci_dev_is_disconnected(dev)) {
822 dev->msix_enabled = 0;
826 /* Return the device with MSI-X masked as initial states */
827 for_each_pci_msi_entry(entry, dev)
828 pci_msix_mask(entry);
830 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
831 pci_intx_for_msi(dev, 1);
832 dev->msix_enabled = 0;
833 pcibios_alloc_irq(dev);
836 void pci_disable_msix(struct pci_dev *dev)
838 if (!pci_msi_enable || !dev || !dev->msix_enabled)
841 pci_msix_shutdown(dev);
844 EXPORT_SYMBOL(pci_disable_msix);
846 static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
847 struct irq_affinity *affd)
852 if (!pci_msi_supported(dev, minvec) || dev->current_state != PCI_D0)
855 /* Check whether driver already requested MSI-X IRQs */
856 if (dev->msix_enabled) {
857 pci_info(dev, "can't enable MSI (MSI-X already enabled)\n");
864 if (WARN_ON_ONCE(dev->msi_enabled))
867 nvec = pci_msi_vec_count(dev);
878 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
883 rc = msi_capability_init(dev, nvec, affd);
896 /* deprecated, don't use */
897 int pci_enable_msi(struct pci_dev *dev)
899 int rc = __pci_enable_msi_range(dev, 1, 1, NULL);
904 EXPORT_SYMBOL(pci_enable_msi);
906 static int __pci_enable_msix_range(struct pci_dev *dev,
907 struct msix_entry *entries, int minvec,
908 int maxvec, struct irq_affinity *affd,
911 int rc, nvec = maxvec;
916 if (WARN_ON_ONCE(dev->msix_enabled))
921 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
926 rc = __pci_enable_msix(dev, entries, nvec, affd, flags);
940 * pci_enable_msix_range - configure device's MSI-X capability structure
941 * @dev: pointer to the pci_dev data structure of MSI-X device function
942 * @entries: pointer to an array of MSI-X entries
943 * @minvec: minimum number of MSI-X IRQs requested
944 * @maxvec: maximum number of MSI-X IRQs requested
946 * Setup the MSI-X capability structure of device function with a maximum
947 * possible number of interrupts in the range between @minvec and @maxvec
948 * upon its software driver call to request for MSI-X mode enabled on its
949 * hardware device function. It returns a negative errno if an error occurs.
950 * If it succeeds, it returns the actual number of interrupts allocated and
951 * indicates the successful configuration of MSI-X capability structure
952 * with new allocated MSI-X interrupts.
954 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
955 int minvec, int maxvec)
957 return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL, 0);
959 EXPORT_SYMBOL(pci_enable_msix_range);
962 * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device
963 * @dev: PCI device to operate on
964 * @min_vecs: minimum number of vectors required (must be >= 1)
965 * @max_vecs: maximum (desired) number of vectors
966 * @flags: flags or quirks for the allocation
967 * @affd: optional description of the affinity requirements
969 * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
970 * vectors if available, and fall back to a single legacy vector
971 * if neither is available. Return the number of vectors allocated,
972 * (which might be smaller than @max_vecs) if successful, or a negative
973 * error code on error. If less than @min_vecs interrupt vectors are
974 * available for @dev the function will fail with -ENOSPC.
976 * To get the Linux IRQ number used for a vector that can be passed to
977 * request_irq() use the pci_irq_vector() helper.
979 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
980 unsigned int max_vecs, unsigned int flags,
981 struct irq_affinity *affd)
983 struct irq_affinity msi_default_affd = {0};
986 if (flags & PCI_IRQ_AFFINITY) {
988 affd = &msi_default_affd;
994 if (flags & PCI_IRQ_MSIX) {
995 nvecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs,
1001 if (flags & PCI_IRQ_MSI) {
1002 nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd);
1007 /* use legacy IRQ if allowed */
1008 if (flags & PCI_IRQ_LEGACY) {
1009 if (min_vecs == 1 && dev->irq) {
1011 * Invoke the affinity spreading logic to ensure that
1012 * the device driver can adjust queue configuration
1013 * for the single interrupt case.
1016 irq_create_affinity_masks(1, affd);
1024 EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity);
1027 * pci_free_irq_vectors - free previously allocated IRQs for a device
1028 * @dev: PCI device to operate on
1030 * Undoes the allocations and enabling in pci_alloc_irq_vectors().
1032 void pci_free_irq_vectors(struct pci_dev *dev)
1034 pci_disable_msix(dev);
1035 pci_disable_msi(dev);
1037 EXPORT_SYMBOL(pci_free_irq_vectors);
1040 * pci_irq_vector - return Linux IRQ number of a device vector
1041 * @dev: PCI device to operate on
1042 * @nr: Interrupt vector index (0-based)
1044 * @nr has the following meanings depending on the interrupt mode:
1045 * MSI-X: The index in the MSI-X vector table
1046 * MSI: The index of the enabled MSI vectors
1049 * Return: The Linux interrupt number or -EINVAl if @nr is out of range.
1051 int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1053 if (dev->msix_enabled) {
1054 struct msi_desc *entry;
1056 for_each_pci_msi_entry(entry, dev) {
1057 if (entry->pci.msi_attrib.entry_nr == nr)
1064 if (dev->msi_enabled) {
1065 struct msi_desc *entry = first_pci_msi_entry(dev);
1067 if (WARN_ON_ONCE(nr >= entry->nvec_used))
1070 if (WARN_ON_ONCE(nr > 0))
1074 return dev->irq + nr;
1076 EXPORT_SYMBOL(pci_irq_vector);
1079 * pci_irq_get_affinity - return the affinity of a particular MSI vector
1080 * @dev: PCI device to operate on
1081 * @nr: device-relative interrupt vector index (0-based).
1083 * @nr has the following meanings depending on the interrupt mode:
1084 * MSI-X: The index in the MSI-X vector table
1085 * MSI: The index of the enabled MSI vectors
1088 * Return: A cpumask pointer or NULL if @nr is out of range
1090 const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
1092 if (dev->msix_enabled) {
1093 struct msi_desc *entry;
1095 for_each_pci_msi_entry(entry, dev) {
1096 if (entry->pci.msi_attrib.entry_nr == nr)
1097 return &entry->affinity->mask;
1101 } else if (dev->msi_enabled) {
1102 struct msi_desc *entry = first_pci_msi_entry(dev);
1104 if (WARN_ON_ONCE(!entry || !entry->affinity ||
1105 nr >= entry->nvec_used))
1108 return &entry->affinity[nr].mask;
1110 return cpu_possible_mask;
1113 EXPORT_SYMBOL(pci_irq_get_affinity);
1115 struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1117 return to_pci_dev(desc->dev);
1119 EXPORT_SYMBOL(msi_desc_to_pci_dev);
1121 void pci_no_msi(void)
1127 * pci_msi_enabled - is MSI enabled?
1129 * Returns true if MSI has not been disabled by the command-line option
1132 int pci_msi_enabled(void)
1134 return pci_msi_enable;
1136 EXPORT_SYMBOL(pci_msi_enabled);