1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 * Copyright (C) 2016 Christoph Hellwig.
10 #include <linux/export.h>
11 #include <linux/irq.h>
16 static int pci_msi_enable = 1;
17 int pci_msi_ignore_mask;
19 static noinline void pci_msi_update_mask(struct msi_desc *desc, u32 clear, u32 set)
21 raw_spinlock_t *lock = &to_pci_dev(desc->dev)->msi_lock;
24 if (!desc->pci.msi_attrib.can_mask)
27 raw_spin_lock_irqsave(lock, flags);
28 desc->pci.msi_mask &= ~clear;
29 desc->pci.msi_mask |= set;
30 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->pci.mask_pos,
32 raw_spin_unlock_irqrestore(lock, flags);
35 static inline void pci_msi_mask(struct msi_desc *desc, u32 mask)
37 pci_msi_update_mask(desc, 0, mask);
40 static inline void pci_msi_unmask(struct msi_desc *desc, u32 mask)
42 pci_msi_update_mask(desc, mask, 0);
45 static inline void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
47 return desc->pci.mask_base + desc->msi_index * PCI_MSIX_ENTRY_SIZE;
51 * This internal function does not flush PCI writes to the device. All
52 * users must ensure that they read from the device before either assuming
53 * that the device state is up to date, or returning out of this file.
54 * It does not affect the msi_desc::msix_ctrl cache either. Use with care!
56 static void pci_msix_write_vector_ctrl(struct msi_desc *desc, u32 ctrl)
58 void __iomem *desc_addr = pci_msix_desc_addr(desc);
60 if (desc->pci.msi_attrib.can_mask)
61 writel(ctrl, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
64 static inline void pci_msix_mask(struct msi_desc *desc)
66 desc->pci.msix_ctrl |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
67 pci_msix_write_vector_ctrl(desc, desc->pci.msix_ctrl);
68 /* Flush write to device */
69 readl(desc->pci.mask_base);
72 static inline void pci_msix_unmask(struct msi_desc *desc)
74 desc->pci.msix_ctrl &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
75 pci_msix_write_vector_ctrl(desc, desc->pci.msix_ctrl);
78 static void __pci_msi_mask_desc(struct msi_desc *desc, u32 mask)
80 if (desc->pci.msi_attrib.is_msix)
83 pci_msi_mask(desc, mask);
86 static void __pci_msi_unmask_desc(struct msi_desc *desc, u32 mask)
88 if (desc->pci.msi_attrib.is_msix)
89 pci_msix_unmask(desc);
91 pci_msi_unmask(desc, mask);
95 * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts
96 * @data: pointer to irqdata associated to that interrupt
98 void pci_msi_mask_irq(struct irq_data *data)
100 struct msi_desc *desc = irq_data_get_msi_desc(data);
102 __pci_msi_mask_desc(desc, BIT(data->irq - desc->irq));
104 EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
107 * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts
108 * @data: pointer to irqdata associated to that interrupt
110 void pci_msi_unmask_irq(struct irq_data *data)
112 struct msi_desc *desc = irq_data_get_msi_desc(data);
114 __pci_msi_unmask_desc(desc, BIT(data->irq - desc->irq));
116 EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
118 void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
120 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
122 BUG_ON(dev->current_state != PCI_D0);
124 if (entry->pci.msi_attrib.is_msix) {
125 void __iomem *base = pci_msix_desc_addr(entry);
127 if (WARN_ON_ONCE(entry->pci.msi_attrib.is_virtual))
130 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
131 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
132 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
134 int pos = dev->msi_cap;
137 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
139 if (entry->pci.msi_attrib.is_64) {
140 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
142 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
145 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
151 void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
153 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
155 if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) {
156 /* Don't touch the hardware now */
157 } else if (entry->pci.msi_attrib.is_msix) {
158 void __iomem *base = pci_msix_desc_addr(entry);
159 u32 ctrl = entry->pci.msix_ctrl;
160 bool unmasked = !(ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT);
162 if (entry->pci.msi_attrib.is_virtual)
166 * The specification mandates that the entry is masked
167 * when the message is modified:
169 * "If software changes the Address or Data value of an
170 * entry while the entry is unmasked, the result is
174 pci_msix_write_vector_ctrl(entry, ctrl | PCI_MSIX_ENTRY_CTRL_MASKBIT);
176 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
177 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
178 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
181 pci_msix_write_vector_ctrl(entry, ctrl);
183 /* Ensure that the writes are visible in the device */
184 readl(base + PCI_MSIX_ENTRY_DATA);
186 int pos = dev->msi_cap;
189 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
190 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
191 msgctl |= entry->pci.msi_attrib.multiple << 4;
192 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
194 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
196 if (entry->pci.msi_attrib.is_64) {
197 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
199 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
202 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
205 /* Ensure that the writes are visible in the device */
206 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
212 if (entry->write_msi_msg)
213 entry->write_msi_msg(entry, entry->write_msi_msg_data);
217 void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
219 struct msi_desc *entry = irq_get_msi_desc(irq);
221 __pci_write_msi_msg(entry, msg);
223 EXPORT_SYMBOL_GPL(pci_write_msi_msg);
225 static void free_msi_irqs(struct pci_dev *dev)
227 struct list_head *msi_list = dev_to_msi_list(&dev->dev);
228 struct msi_desc *entry, *tmp;
231 for_each_pci_msi_entry(entry, dev)
233 for (i = 0; i < entry->nvec_used; i++)
234 BUG_ON(irq_has_action(entry->irq + i));
236 pci_msi_teardown_msi_irqs(dev);
238 list_for_each_entry_safe(entry, tmp, msi_list, list) {
239 list_del(&entry->list);
240 free_msi_entry(entry);
243 if (dev->msix_base) {
244 iounmap(dev->msix_base);
245 dev->msix_base = NULL;
249 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
251 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
252 pci_intx(dev, enable);
255 static void pci_msi_set_enable(struct pci_dev *dev, int enable)
259 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
260 control &= ~PCI_MSI_FLAGS_ENABLE;
262 control |= PCI_MSI_FLAGS_ENABLE;
263 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
267 * Architecture override returns true when the PCI MSI message should be
268 * written by the generic restore function.
270 bool __weak arch_restore_msi_irqs(struct pci_dev *dev)
275 static void __pci_restore_msi_state(struct pci_dev *dev)
277 struct msi_desc *entry;
280 if (!dev->msi_enabled)
283 entry = irq_get_msi_desc(dev->irq);
285 pci_intx_for_msi(dev, 0);
286 pci_msi_set_enable(dev, 0);
287 if (arch_restore_msi_irqs(dev))
288 __pci_write_msi_msg(entry, &entry->msg);
290 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
291 pci_msi_update_mask(entry, 0, 0);
292 control &= ~PCI_MSI_FLAGS_QSIZE;
293 control |= (entry->pci.msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
294 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
297 static void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
301 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
304 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
307 static void __pci_restore_msix_state(struct pci_dev *dev)
309 struct msi_desc *entry;
312 if (!dev->msix_enabled)
314 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
316 /* route the table */
317 pci_intx_for_msi(dev, 0);
318 pci_msix_clear_and_set_ctrl(dev, 0,
319 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
321 write_msg = arch_restore_msi_irqs(dev);
323 for_each_pci_msi_entry(entry, dev) {
325 __pci_write_msi_msg(entry, &entry->msg);
326 pci_msix_write_vector_ctrl(entry, entry->pci.msix_ctrl);
329 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
332 void pci_restore_msi_state(struct pci_dev *dev)
334 __pci_restore_msi_state(dev);
335 __pci_restore_msix_state(dev);
337 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
339 static void pcim_msi_release(void *pcidev)
341 struct pci_dev *dev = pcidev;
343 dev->is_msi_managed = false;
344 pci_free_irq_vectors(dev);
348 * Needs to be separate from pcim_release to prevent an ordering problem
349 * vs. msi_device_data_release() in the MSI core code.
351 static int pcim_setup_msi_release(struct pci_dev *dev)
355 if (!pci_is_managed(dev) || dev->is_msi_managed)
358 ret = devm_add_action(&dev->dev, pcim_msi_release, dev);
360 dev->is_msi_managed = true;
365 * Ordering vs. devres: msi device data has to be installed first so that
366 * pcim_msi_release() is invoked before it on device release.
368 static int pci_setup_msi_context(struct pci_dev *dev)
370 int ret = msi_setup_device_data(&dev->dev);
373 ret = pcim_setup_msi_release(dev);
377 static struct msi_desc *
378 msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd)
380 struct irq_affinity_desc *masks = NULL;
381 struct msi_desc *entry;
385 masks = irq_create_affinity_masks(nvec, affd);
387 /* MSI Entry Initialization */
388 entry = alloc_msi_entry(&dev->dev, nvec, masks);
392 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
393 /* Lies, damned lies, and MSIs */
394 if (dev->dev_flags & PCI_DEV_FLAGS_HAS_MSI_MASKING)
395 control |= PCI_MSI_FLAGS_MASKBIT;
397 entry->pci.msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
398 entry->pci.msi_attrib.can_mask = !pci_msi_ignore_mask &&
399 !!(control & PCI_MSI_FLAGS_MASKBIT);
400 entry->pci.msi_attrib.default_irq = dev->irq;
401 entry->pci.msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
402 entry->pci.msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
404 if (control & PCI_MSI_FLAGS_64BIT)
405 entry->pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
407 entry->pci.mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
409 /* Save the initial mask status */
410 if (entry->pci.msi_attrib.can_mask)
411 pci_read_config_dword(dev, entry->pci.mask_pos, &entry->pci.msi_mask);
418 static int msi_verify_entries(struct pci_dev *dev)
420 struct msi_desc *entry;
422 if (!dev->no_64bit_msi)
425 for_each_pci_msi_entry(entry, dev) {
426 if (entry->msg.address_hi) {
427 pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n",
428 entry->msg.address_hi, entry->msg.address_lo);
436 * msi_capability_init - configure device's MSI capability structure
437 * @dev: pointer to the pci_dev data structure of MSI device function
438 * @nvec: number of interrupts to allocate
439 * @affd: description of automatic IRQ affinity assignments (may be %NULL)
441 * Setup the MSI capability structure of the device with the requested
442 * number of interrupts. A return value of zero indicates the successful
443 * setup of an entry with the new MSI IRQ. A negative return value indicates
444 * an error, and a positive return value indicates the number of interrupts
445 * which could have been allocated.
447 static int msi_capability_init(struct pci_dev *dev, int nvec,
448 struct irq_affinity *affd)
450 struct msi_desc *entry;
454 * Disable MSI during setup in the hardware, but mark it enabled
455 * so that setup code can evaluate it.
457 pci_msi_set_enable(dev, 0);
458 dev->msi_enabled = 1;
460 entry = msi_setup_entry(dev, nvec, affd);
466 /* All MSIs are unmasked by default; mask them all */
467 pci_msi_mask(entry, msi_multi_mask(entry));
469 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
471 /* Configure MSI capability structure */
472 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
476 ret = msi_verify_entries(dev);
480 /* Set MSI enabled bits */
481 pci_intx_for_msi(dev, 0);
482 pci_msi_set_enable(dev, 1);
484 pcibios_free_irq(dev);
485 dev->irq = entry->irq;
489 pci_msi_unmask(entry, msi_multi_mask(entry));
492 dev->msi_enabled = 0;
496 static void __iomem *msix_map_region(struct pci_dev *dev,
497 unsigned int nr_entries)
499 resource_size_t phys_addr;
504 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
506 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
507 flags = pci_resource_flags(dev, bir);
508 if (!flags || (flags & IORESOURCE_UNSET))
511 table_offset &= PCI_MSIX_TABLE_OFFSET;
512 phys_addr = pci_resource_start(dev, bir) + table_offset;
514 return ioremap(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
517 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
518 struct msix_entry *entries, int nvec,
519 struct irq_affinity *affd)
521 struct irq_affinity_desc *curmsk, *masks = NULL;
522 struct msi_desc *entry;
525 int vec_count = pci_msix_vec_count(dev);
528 masks = irq_create_affinity_masks(nvec, affd);
530 for (i = 0, curmsk = masks; i < nvec; i++) {
531 entry = alloc_msi_entry(&dev->dev, 1, curmsk);
533 /* No enough memory. Don't try again */
538 entry->pci.msi_attrib.is_msix = 1;
539 entry->pci.msi_attrib.is_64 = 1;
542 entry->msi_index = entries[i].entry;
544 entry->msi_index = i;
546 entry->pci.msi_attrib.is_virtual = entry->msi_index >= vec_count;
548 entry->pci.msi_attrib.can_mask = !pci_msi_ignore_mask &&
549 !entry->pci.msi_attrib.is_virtual;
551 entry->pci.msi_attrib.default_irq = dev->irq;
552 entry->pci.mask_base = base;
554 if (entry->pci.msi_attrib.can_mask) {
555 addr = pci_msix_desc_addr(entry);
556 entry->pci.msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
559 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
569 static void msix_update_entries(struct pci_dev *dev, struct msix_entry *entries)
571 struct msi_desc *entry;
574 for_each_pci_msi_entry(entry, dev) {
575 entries->vector = entry->irq;
581 static void msix_mask_all(void __iomem *base, int tsize)
583 u32 ctrl = PCI_MSIX_ENTRY_CTRL_MASKBIT;
586 if (pci_msi_ignore_mask)
589 for (i = 0; i < tsize; i++, base += PCI_MSIX_ENTRY_SIZE)
590 writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL);
594 * msix_capability_init - configure device's MSI-X capability
595 * @dev: pointer to the pci_dev data structure of MSI-X device function
596 * @entries: pointer to an array of struct msix_entry entries
597 * @nvec: number of @entries
598 * @affd: Optional pointer to enable automatic affinity assignment
600 * Setup the MSI-X capability structure of device function with a
601 * single MSI-X IRQ. A return of zero indicates the successful setup of
602 * requested MSI-X entries with allocated IRQs or non-zero for otherwise.
604 static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
605 int nvec, struct irq_affinity *affd)
612 * Some devices require MSI-X to be enabled before the MSI-X
613 * registers can be accessed. Mask all the vectors to prevent
614 * interrupts coming in before they're fully set up.
616 pci_msix_clear_and_set_ctrl(dev, 0, PCI_MSIX_FLAGS_MASKALL |
617 PCI_MSIX_FLAGS_ENABLE);
619 /* Mark it enabled so setup functions can query it */
620 dev->msix_enabled = 1;
622 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
623 /* Request & Map MSI-X table region */
624 tsize = msix_table_size(control);
625 base = msix_map_region(dev, tsize);
631 dev->msix_base = base;
633 ret = msix_setup_entries(dev, base, entries, nvec, affd);
637 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
641 /* Check if all MSI entries honor device restrictions */
642 ret = msi_verify_entries(dev);
646 msix_update_entries(dev, entries);
649 pci_intx_for_msi(dev, 0);
652 * Ensure that all table entries are masked to prevent
653 * stale entries from firing in a crash kernel.
655 * Done late to deal with a broken Marvell NVME device
656 * which takes the MSI-X mask bits into account even
657 * when MSI-X is disabled, which prevents MSI delivery.
659 msix_mask_all(base, tsize);
660 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
662 pcibios_free_irq(dev);
669 dev->msix_enabled = 0;
670 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE, 0);
676 * pci_msi_supported - check whether MSI may be enabled on a device
677 * @dev: pointer to the pci_dev data structure of MSI device function
678 * @nvec: how many MSIs have been requested?
680 * Look at global flags, the device itself, and its parent buses
681 * to determine if MSI/-X are supported for the device. If MSI/-X is
682 * supported return 1, else return 0.
684 static int pci_msi_supported(struct pci_dev *dev, int nvec)
688 /* MSI must be globally enabled and supported by the device */
692 if (!dev || dev->no_msi)
696 * You can't ask to have 0 or less MSIs configured.
698 * b) the list manipulation code assumes nvec >= 1.
704 * Any bridge which does NOT route MSI transactions from its
705 * secondary bus to its primary bus must set NO_MSI flag on
706 * the secondary pci_bus.
708 * The NO_MSI flag can either be set directly by:
709 * - arch-specific PCI host bus controller drivers (deprecated)
710 * - quirks for specific PCI bridges
712 * or indirectly by platform-specific PCI host bridge drivers by
713 * advertising the 'msi_domain' property, which results in
714 * the NO_MSI flag when no MSI domain is found for this bridge
717 for (bus = dev->bus; bus; bus = bus->parent)
718 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
725 * pci_msi_vec_count - Return the number of MSI vectors a device can send
726 * @dev: device to report about
728 * This function returns the number of MSI vectors a device requested via
729 * Multiple Message Capable register. It returns a negative errno if the
730 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
731 * and returns a power of two, up to a maximum of 2^5 (32), according to the
734 int pci_msi_vec_count(struct pci_dev *dev)
742 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
743 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
747 EXPORT_SYMBOL(pci_msi_vec_count);
749 static void pci_msi_shutdown(struct pci_dev *dev)
751 struct msi_desc *desc;
753 if (!pci_msi_enable || !dev || !dev->msi_enabled)
756 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
757 desc = first_pci_msi_entry(dev);
759 pci_msi_set_enable(dev, 0);
760 pci_intx_for_msi(dev, 1);
761 dev->msi_enabled = 0;
763 /* Return the device with MSI unmasked as initial states */
764 pci_msi_unmask(desc, msi_multi_mask(desc));
766 /* Restore dev->irq to its default pin-assertion IRQ */
767 dev->irq = desc->pci.msi_attrib.default_irq;
768 pcibios_alloc_irq(dev);
771 void pci_disable_msi(struct pci_dev *dev)
773 if (!pci_msi_enable || !dev || !dev->msi_enabled)
776 pci_msi_shutdown(dev);
779 EXPORT_SYMBOL(pci_disable_msi);
782 * pci_msix_vec_count - return the number of device's MSI-X table entries
783 * @dev: pointer to the pci_dev data structure of MSI-X device function
784 * This function returns the number of device's MSI-X table entries and
785 * therefore the number of MSI-X vectors device is capable of sending.
786 * It returns a negative errno if the device is not capable of sending MSI-X
789 int pci_msix_vec_count(struct pci_dev *dev)
796 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
797 return msix_table_size(control);
799 EXPORT_SYMBOL(pci_msix_vec_count);
801 static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
802 int nvec, struct irq_affinity *affd, int flags)
807 if (!pci_msi_supported(dev, nvec) || dev->current_state != PCI_D0)
810 nr_entries = pci_msix_vec_count(dev);
813 if (nvec > nr_entries && !(flags & PCI_IRQ_VIRTUAL))
817 /* Check for any invalid entries */
818 for (i = 0; i < nvec; i++) {
819 if (entries[i].entry >= nr_entries)
820 return -EINVAL; /* invalid entry */
821 for (j = i + 1; j < nvec; j++) {
822 if (entries[i].entry == entries[j].entry)
823 return -EINVAL; /* duplicate entry */
828 /* Check whether driver already requested for MSI IRQ */
829 if (dev->msi_enabled) {
830 pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
833 return msix_capability_init(dev, entries, nvec, affd);
836 static void pci_msix_shutdown(struct pci_dev *dev)
838 struct msi_desc *entry;
840 if (!pci_msi_enable || !dev || !dev->msix_enabled)
843 if (pci_dev_is_disconnected(dev)) {
844 dev->msix_enabled = 0;
848 /* Return the device with MSI-X masked as initial states */
849 for_each_pci_msi_entry(entry, dev)
850 pci_msix_mask(entry);
852 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
853 pci_intx_for_msi(dev, 1);
854 dev->msix_enabled = 0;
855 pcibios_alloc_irq(dev);
858 void pci_disable_msix(struct pci_dev *dev)
860 if (!pci_msi_enable || !dev || !dev->msix_enabled)
863 pci_msix_shutdown(dev);
866 EXPORT_SYMBOL(pci_disable_msix);
868 static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
869 struct irq_affinity *affd)
874 if (!pci_msi_supported(dev, minvec) || dev->current_state != PCI_D0)
877 /* Check whether driver already requested MSI-X IRQs */
878 if (dev->msix_enabled) {
879 pci_info(dev, "can't enable MSI (MSI-X already enabled)\n");
886 if (WARN_ON_ONCE(dev->msi_enabled))
889 nvec = pci_msi_vec_count(dev);
898 rc = pci_setup_msi_context(dev);
904 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
909 rc = msi_capability_init(dev, nvec, affd);
922 /* deprecated, don't use */
923 int pci_enable_msi(struct pci_dev *dev)
925 int rc = __pci_enable_msi_range(dev, 1, 1, NULL);
930 EXPORT_SYMBOL(pci_enable_msi);
932 static int __pci_enable_msix_range(struct pci_dev *dev,
933 struct msix_entry *entries, int minvec,
934 int maxvec, struct irq_affinity *affd,
937 int rc, nvec = maxvec;
942 if (WARN_ON_ONCE(dev->msix_enabled))
945 rc = pci_setup_msi_context(dev);
951 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
956 rc = __pci_enable_msix(dev, entries, nvec, affd, flags);
970 * pci_enable_msix_range - configure device's MSI-X capability structure
971 * @dev: pointer to the pci_dev data structure of MSI-X device function
972 * @entries: pointer to an array of MSI-X entries
973 * @minvec: minimum number of MSI-X IRQs requested
974 * @maxvec: maximum number of MSI-X IRQs requested
976 * Setup the MSI-X capability structure of device function with a maximum
977 * possible number of interrupts in the range between @minvec and @maxvec
978 * upon its software driver call to request for MSI-X mode enabled on its
979 * hardware device function. It returns a negative errno if an error occurs.
980 * If it succeeds, it returns the actual number of interrupts allocated and
981 * indicates the successful configuration of MSI-X capability structure
982 * with new allocated MSI-X interrupts.
984 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
985 int minvec, int maxvec)
987 return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL, 0);
989 EXPORT_SYMBOL(pci_enable_msix_range);
992 * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device
993 * @dev: PCI device to operate on
994 * @min_vecs: minimum number of vectors required (must be >= 1)
995 * @max_vecs: maximum (desired) number of vectors
996 * @flags: flags or quirks for the allocation
997 * @affd: optional description of the affinity requirements
999 * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
1000 * vectors if available, and fall back to a single legacy vector
1001 * if neither is available. Return the number of vectors allocated,
1002 * (which might be smaller than @max_vecs) if successful, or a negative
1003 * error code on error. If less than @min_vecs interrupt vectors are
1004 * available for @dev the function will fail with -ENOSPC.
1006 * To get the Linux IRQ number used for a vector that can be passed to
1007 * request_irq() use the pci_irq_vector() helper.
1009 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1010 unsigned int max_vecs, unsigned int flags,
1011 struct irq_affinity *affd)
1013 struct irq_affinity msi_default_affd = {0};
1014 int nvecs = -ENOSPC;
1016 if (flags & PCI_IRQ_AFFINITY) {
1018 affd = &msi_default_affd;
1024 if (flags & PCI_IRQ_MSIX) {
1025 nvecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs,
1031 if (flags & PCI_IRQ_MSI) {
1032 nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd);
1037 /* use legacy IRQ if allowed */
1038 if (flags & PCI_IRQ_LEGACY) {
1039 if (min_vecs == 1 && dev->irq) {
1041 * Invoke the affinity spreading logic to ensure that
1042 * the device driver can adjust queue configuration
1043 * for the single interrupt case.
1046 irq_create_affinity_masks(1, affd);
1054 EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity);
1057 * pci_free_irq_vectors - free previously allocated IRQs for a device
1058 * @dev: PCI device to operate on
1060 * Undoes the allocations and enabling in pci_alloc_irq_vectors().
1062 void pci_free_irq_vectors(struct pci_dev *dev)
1064 pci_disable_msix(dev);
1065 pci_disable_msi(dev);
1067 EXPORT_SYMBOL(pci_free_irq_vectors);
1070 * pci_irq_vector - return Linux IRQ number of a device vector
1071 * @dev: PCI device to operate on
1072 * @nr: Interrupt vector index (0-based)
1074 * @nr has the following meanings depending on the interrupt mode:
1075 * MSI-X: The index in the MSI-X vector table
1076 * MSI: The index of the enabled MSI vectors
1079 * Return: The Linux interrupt number or -EINVAl if @nr is out of range.
1081 int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1083 if (dev->msix_enabled) {
1084 struct msi_desc *entry;
1086 for_each_pci_msi_entry(entry, dev) {
1087 if (entry->msi_index == nr)
1094 if (dev->msi_enabled) {
1095 struct msi_desc *entry = first_pci_msi_entry(dev);
1097 if (WARN_ON_ONCE(nr >= entry->nvec_used))
1100 if (WARN_ON_ONCE(nr > 0))
1104 return dev->irq + nr;
1106 EXPORT_SYMBOL(pci_irq_vector);
1109 * pci_irq_get_affinity - return the affinity of a particular MSI vector
1110 * @dev: PCI device to operate on
1111 * @nr: device-relative interrupt vector index (0-based).
1113 * @nr has the following meanings depending on the interrupt mode:
1114 * MSI-X: The index in the MSI-X vector table
1115 * MSI: The index of the enabled MSI vectors
1118 * Return: A cpumask pointer or NULL if @nr is out of range
1120 const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
1122 if (dev->msix_enabled) {
1123 struct msi_desc *entry;
1125 for_each_pci_msi_entry(entry, dev) {
1126 if (entry->msi_index == nr)
1127 return &entry->affinity->mask;
1131 } else if (dev->msi_enabled) {
1132 struct msi_desc *entry = first_pci_msi_entry(dev);
1134 if (WARN_ON_ONCE(!entry || !entry->affinity ||
1135 nr >= entry->nvec_used))
1138 return &entry->affinity[nr].mask;
1140 return cpu_possible_mask;
1143 EXPORT_SYMBOL(pci_irq_get_affinity);
1145 struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1147 return to_pci_dev(desc->dev);
1149 EXPORT_SYMBOL(msi_desc_to_pci_dev);
1151 void pci_no_msi(void)
1157 * pci_msi_enabled - is MSI enabled?
1159 * Returns true if MSI has not been disabled by the command-line option
1162 int pci_msi_enabled(void)
1164 return pci_msi_enable;
1166 EXPORT_SYMBOL(pci_msi_enabled);