1 // SPDX-License-Identifier: GPL-2.0+
3 * PCI Express PCI Hot Plug Driver
5 * Copyright (C) 1995,2001 Compaq Computer Corporation
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7 * Copyright (C) 2001 IBM Corp.
8 * Copyright (C) 2003-2004 Intel Corporation
10 * All rights reserved.
12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/types.h>
18 #include <linux/signal.h>
19 #include <linux/jiffies.h>
20 #include <linux/kthread.h>
21 #include <linux/pci.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/interrupt.h>
24 #include <linux/time.h>
25 #include <linux/slab.h>
30 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
32 return ctrl->pcie->port;
35 static irqreturn_t pciehp_isr(int irq, void *dev_id);
36 static irqreturn_t pciehp_ist(int irq, void *dev_id);
37 static int pciehp_poll(void *data);
39 static inline int pciehp_request_irq(struct controller *ctrl)
41 int retval, irq = ctrl->pcie->irq;
43 if (pciehp_poll_mode) {
44 ctrl->poll_thread = kthread_run(&pciehp_poll, ctrl,
46 slot_name(ctrl->slot));
47 return PTR_ERR_OR_ZERO(ctrl->poll_thread);
50 /* Installs the interrupt handler */
51 retval = request_threaded_irq(irq, pciehp_isr, pciehp_ist,
52 IRQF_SHARED, MY_NAME, ctrl);
54 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
59 static inline void pciehp_free_irq(struct controller *ctrl)
62 kthread_stop(ctrl->poll_thread);
64 free_irq(ctrl->pcie->irq, ctrl);
67 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
69 struct pci_dev *pdev = ctrl_dev(ctrl);
73 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
74 if (slot_status == (u16) ~0) {
75 ctrl_info(ctrl, "%s: no response from device\n",
80 if (slot_status & PCI_EXP_SLTSTA_CC) {
81 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
90 return 0; /* timeout */
93 static void pcie_wait_cmd(struct controller *ctrl)
95 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
96 unsigned long duration = msecs_to_jiffies(msecs);
97 unsigned long cmd_timeout = ctrl->cmd_started + duration;
98 unsigned long now, timeout;
102 * If the controller does not generate notifications for command
103 * completions, we never need to wait between writes.
105 if (NO_CMD_CMPL(ctrl))
112 * Even if the command has already timed out, we want to call
113 * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
116 if (time_before_eq(cmd_timeout, now))
119 timeout = cmd_timeout - now;
121 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
122 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
123 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
125 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
128 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
130 jiffies_to_msecs(jiffies - ctrl->cmd_started));
133 #define CC_ERRATUM_MASK (PCI_EXP_SLTCTL_PCC | \
134 PCI_EXP_SLTCTL_PIC | \
135 PCI_EXP_SLTCTL_AIC | \
138 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
141 struct pci_dev *pdev = ctrl_dev(ctrl);
142 u16 slot_ctrl_orig, slot_ctrl;
144 mutex_lock(&ctrl->ctrl_lock);
147 * Always wait for any previous command that might still be in progress
151 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
152 if (slot_ctrl == (u16) ~0) {
153 ctrl_info(ctrl, "%s: no response from device\n", __func__);
157 slot_ctrl_orig = slot_ctrl;
159 slot_ctrl |= (cmd & mask);
162 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
163 ctrl->cmd_started = jiffies;
164 ctrl->slot_ctrl = slot_ctrl;
167 * Controllers with the Intel CF118 and similar errata advertise
168 * Command Completed support, but they only set Command Completed
169 * if we change the "Control" bits for power, power indicator,
170 * attention indicator, or interlock. If we only change the
171 * "Enable" bits, they never set the Command Completed bit.
173 if (pdev->broken_cmd_compl &&
174 (slot_ctrl_orig & CC_ERRATUM_MASK) == (slot_ctrl & CC_ERRATUM_MASK))
178 * Optionally wait for the hardware to be ready for a new command,
179 * indicating completion of the above issued command.
185 mutex_unlock(&ctrl->ctrl_lock);
189 * pcie_write_cmd - Issue controller command
190 * @ctrl: controller to which the command is issued
191 * @cmd: command value written to slot control register
192 * @mask: bitmask of slot control register to be modified
194 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
196 pcie_do_write_cmd(ctrl, cmd, mask, true);
199 /* Same as above without waiting for the hardware to latch */
200 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
202 pcie_do_write_cmd(ctrl, cmd, mask, false);
205 bool pciehp_check_link_active(struct controller *ctrl)
207 struct pci_dev *pdev = ctrl_dev(ctrl);
211 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
212 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
215 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
220 static void pcie_wait_link_active(struct controller *ctrl)
222 struct pci_dev *pdev = ctrl_dev(ctrl);
224 pcie_wait_for_link(pdev, true);
227 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
231 int delay = 1000, step = 20;
235 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
245 if (count > 1 && pciehp_debug)
246 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
247 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
248 PCI_FUNC(devfn), count, step, l);
253 int pciehp_check_link_status(struct controller *ctrl)
255 struct pci_dev *pdev = ctrl_dev(ctrl);
260 * Data Link Layer Link Active Reporting must be capable for
261 * hot-plug capable downstream port. But old controller might
262 * not implement it. In this case, we wait for 1000 ms.
264 if (ctrl->link_active_reporting)
265 pcie_wait_link_active(ctrl);
269 /* wait 100ms before read pci conf, and try in 1s */
271 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
274 /* ignore link or presence changes up to this point */
276 atomic_and(~(PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC),
277 &ctrl->pending_events);
279 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
280 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
281 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
282 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
283 ctrl_err(ctrl, "link training error: status %#06x\n",
288 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
296 static int __pciehp_link_set(struct controller *ctrl, bool enable)
298 struct pci_dev *pdev = ctrl_dev(ctrl);
301 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
304 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
306 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
308 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
309 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
313 static int pciehp_link_enable(struct controller *ctrl)
315 return __pciehp_link_set(ctrl, true);
318 int pciehp_get_raw_indicator_status(struct hotplug_slot *hotplug_slot,
321 struct slot *slot = hotplug_slot->private;
322 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
325 pci_config_pm_runtime_get(pdev);
326 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
327 pci_config_pm_runtime_put(pdev);
328 *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
332 void pciehp_get_attention_status(struct slot *slot, u8 *status)
334 struct controller *ctrl = slot->ctrl;
335 struct pci_dev *pdev = ctrl_dev(ctrl);
338 pci_config_pm_runtime_get(pdev);
339 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
340 pci_config_pm_runtime_put(pdev);
341 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
342 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
344 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
345 case PCI_EXP_SLTCTL_ATTN_IND_ON:
346 *status = 1; /* On */
348 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
349 *status = 2; /* Blink */
351 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
352 *status = 0; /* Off */
360 void pciehp_get_power_status(struct slot *slot, u8 *status)
362 struct controller *ctrl = slot->ctrl;
363 struct pci_dev *pdev = ctrl_dev(ctrl);
366 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
367 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
368 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
370 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
371 case PCI_EXP_SLTCTL_PWR_ON:
372 *status = 1; /* On */
374 case PCI_EXP_SLTCTL_PWR_OFF:
375 *status = 0; /* Off */
383 void pciehp_get_latch_status(struct slot *slot, u8 *status)
385 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
388 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
389 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
392 void pciehp_get_adapter_status(struct slot *slot, u8 *status)
394 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
397 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
398 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
401 int pciehp_query_power_fault(struct slot *slot)
403 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
406 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
407 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
410 int pciehp_set_raw_indicator_status(struct hotplug_slot *hotplug_slot,
413 struct slot *slot = hotplug_slot->private;
414 struct controller *ctrl = slot->ctrl;
415 struct pci_dev *pdev = ctrl_dev(ctrl);
417 pci_config_pm_runtime_get(pdev);
418 pcie_write_cmd_nowait(ctrl, status << 6,
419 PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
420 pci_config_pm_runtime_put(pdev);
424 void pciehp_set_attention_status(struct slot *slot, u8 value)
426 struct controller *ctrl = slot->ctrl;
433 case 0: /* turn off */
434 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
436 case 1: /* turn on */
437 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
439 case 2: /* turn blink */
440 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
445 pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
446 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
447 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
450 void pciehp_green_led_on(struct slot *slot)
452 struct controller *ctrl = slot->ctrl;
457 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
459 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
460 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
461 PCI_EXP_SLTCTL_PWR_IND_ON);
464 void pciehp_green_led_off(struct slot *slot)
466 struct controller *ctrl = slot->ctrl;
471 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
473 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
474 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
475 PCI_EXP_SLTCTL_PWR_IND_OFF);
478 void pciehp_green_led_blink(struct slot *slot)
480 struct controller *ctrl = slot->ctrl;
485 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
487 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
488 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
489 PCI_EXP_SLTCTL_PWR_IND_BLINK);
492 int pciehp_power_on_slot(struct slot *slot)
494 struct controller *ctrl = slot->ctrl;
495 struct pci_dev *pdev = ctrl_dev(ctrl);
499 /* Clear power-fault bit from previous power failures */
500 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
501 if (slot_status & PCI_EXP_SLTSTA_PFD)
502 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
504 ctrl->power_fault_detected = 0;
506 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
507 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
508 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
509 PCI_EXP_SLTCTL_PWR_ON);
511 retval = pciehp_link_enable(ctrl);
513 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
518 void pciehp_power_off_slot(struct slot *slot)
520 struct controller *ctrl = slot->ctrl;
522 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
523 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
524 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
525 PCI_EXP_SLTCTL_PWR_OFF);
528 static irqreturn_t pciehp_isr(int irq, void *dev_id)
530 struct controller *ctrl = (struct controller *)dev_id;
531 struct pci_dev *pdev = ctrl_dev(ctrl);
532 struct device *parent = pdev->dev.parent;
536 * Interrupts only occur in D3hot or shallower (PCIe r4.0, sec 6.7.3.4).
538 if (pdev->current_state == PCI_D3cold)
542 * Keep the port accessible by holding a runtime PM ref on its parent.
543 * Defer resume of the parent to the IRQ thread if it's suspended.
544 * Mask the interrupt until then.
547 pm_runtime_get_noresume(parent);
548 if (!pm_runtime_active(parent)) {
549 pm_runtime_put(parent);
550 disable_irq_nosync(irq);
551 atomic_or(RERUN_ISR, &ctrl->pending_events);
552 return IRQ_WAKE_THREAD;
556 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
557 if (status == (u16) ~0) {
558 ctrl_info(ctrl, "%s: no response from device\n", __func__);
560 pm_runtime_put(parent);
565 * Slot Status contains plain status bits as well as event
566 * notification bits; right now we only want the event bits.
568 events = status & (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
569 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
570 PCI_EXP_SLTSTA_DLLSC);
573 * If we've already reported a power fault, don't report it again
574 * until we've done something to handle it.
576 if (ctrl->power_fault_detected)
577 events &= ~PCI_EXP_SLTSTA_PFD;
581 pm_runtime_put(parent);
585 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events);
586 ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
588 pm_runtime_put(parent);
591 * Command Completed notifications are not deferred to the
592 * IRQ thread because it may be waiting for their arrival.
594 if (events & PCI_EXP_SLTSTA_CC) {
597 wake_up(&ctrl->queue);
599 if (events == PCI_EXP_SLTSTA_CC)
602 events &= ~PCI_EXP_SLTSTA_CC;
605 if (pdev->ignore_hotplug) {
606 ctrl_dbg(ctrl, "ignoring hotplug event %#06x\n", events);
610 /* Save pending events for consumption by IRQ thread. */
611 atomic_or(events, &ctrl->pending_events);
612 return IRQ_WAKE_THREAD;
615 static irqreturn_t pciehp_ist(int irq, void *dev_id)
617 struct controller *ctrl = (struct controller *)dev_id;
618 struct pci_dev *pdev = ctrl_dev(ctrl);
619 struct slot *slot = ctrl->slot;
623 pci_config_pm_runtime_get(pdev);
625 /* rerun pciehp_isr() if the port was inaccessible on interrupt */
626 if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) {
627 ret = pciehp_isr(irq, dev_id);
629 if (ret != IRQ_WAKE_THREAD) {
630 pci_config_pm_runtime_put(pdev);
635 synchronize_hardirq(irq);
636 events = atomic_xchg(&ctrl->pending_events, 0);
638 pci_config_pm_runtime_put(pdev);
642 /* Check Attention Button Pressed */
643 if (events & PCI_EXP_SLTSTA_ABP) {
644 ctrl_info(ctrl, "Slot(%s): Attention button pressed\n",
646 pciehp_handle_button_press(slot);
649 /* Check Power Fault Detected */
650 if ((events & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
651 ctrl->power_fault_detected = 1;
652 ctrl_err(ctrl, "Slot(%s): Power fault\n", slot_name(slot));
653 pciehp_set_attention_status(slot, 1);
654 pciehp_green_led_off(slot);
658 * Disable requests have higher priority than Presence Detect Changed
659 * or Data Link Layer State Changed events.
661 down_read(&ctrl->reset_lock);
662 if (events & DISABLE_SLOT)
663 pciehp_handle_disable_request(slot);
664 else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC))
665 pciehp_handle_presence_or_link_change(slot, events);
666 up_read(&ctrl->reset_lock);
668 pci_config_pm_runtime_put(pdev);
669 wake_up(&ctrl->requester);
673 static int pciehp_poll(void *data)
675 struct controller *ctrl = data;
677 schedule_timeout_idle(10 * HZ); /* start with 10 sec delay */
679 while (!kthread_should_stop()) {
680 /* poll for interrupt events or user requests */
681 while (pciehp_isr(IRQ_NOTCONNECTED, ctrl) == IRQ_WAKE_THREAD ||
682 atomic_read(&ctrl->pending_events))
683 pciehp_ist(IRQ_NOTCONNECTED, ctrl);
685 if (pciehp_poll_time <= 0 || pciehp_poll_time > 60)
686 pciehp_poll_time = 2; /* clamp to sane value */
688 schedule_timeout_idle(pciehp_poll_time * HZ);
694 static void pcie_enable_notification(struct controller *ctrl)
699 * TBD: Power fault detected software notification support.
701 * Power fault detected software notification is not enabled
702 * now, because it caused power fault detected interrupt storm
703 * on some machines. On those machines, power fault detected
704 * bit in the slot status register was set again immediately
705 * when it is cleared in the interrupt service routine, and
706 * next power fault detected interrupt was notified again.
710 * Always enable link events: thus link-up and link-down shall
711 * always be treated as hotplug and unplug respectively. Enable
712 * presence detect only if Attention Button is not present.
714 cmd = PCI_EXP_SLTCTL_DLLSCE;
715 if (ATTN_BUTTN(ctrl))
716 cmd |= PCI_EXP_SLTCTL_ABPE;
718 cmd |= PCI_EXP_SLTCTL_PDCE;
719 if (!pciehp_poll_mode)
720 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
722 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
723 PCI_EXP_SLTCTL_PFDE |
724 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
725 PCI_EXP_SLTCTL_DLLSCE);
727 pcie_write_cmd_nowait(ctrl, cmd, mask);
728 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
729 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
732 static void pcie_disable_notification(struct controller *ctrl)
736 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
737 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
738 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
739 PCI_EXP_SLTCTL_DLLSCE);
740 pcie_write_cmd(ctrl, 0, mask);
741 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
742 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
745 void pcie_clear_hotplug_events(struct controller *ctrl)
747 pcie_capability_write_word(ctrl_dev(ctrl), PCI_EXP_SLTSTA,
748 PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC);
752 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
753 * bus reset of the bridge, but at the same time we want to ensure that it is
754 * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
755 * disable link state notification and presence detection change notification
756 * momentarily, if we see that they could interfere. Also, clear any spurious
759 int pciehp_reset_slot(struct slot *slot, int probe)
761 struct controller *ctrl = slot->ctrl;
762 struct pci_dev *pdev = ctrl_dev(ctrl);
763 u16 stat_mask = 0, ctrl_mask = 0;
769 down_write(&ctrl->reset_lock);
771 if (!ATTN_BUTTN(ctrl)) {
772 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
773 stat_mask |= PCI_EXP_SLTSTA_PDC;
775 ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
776 stat_mask |= PCI_EXP_SLTSTA_DLLSC;
778 pcie_write_cmd(ctrl, 0, ctrl_mask);
779 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
780 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
782 rc = pci_bridge_secondary_bus_reset(ctrl->pcie->port);
784 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
785 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
786 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
787 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
789 up_write(&ctrl->reset_lock);
793 int pcie_init_notification(struct controller *ctrl)
795 if (pciehp_request_irq(ctrl))
797 pcie_enable_notification(ctrl);
798 ctrl->notification_enabled = 1;
802 void pcie_shutdown_notification(struct controller *ctrl)
804 if (ctrl->notification_enabled) {
805 pcie_disable_notification(ctrl);
806 pciehp_free_irq(ctrl);
807 ctrl->notification_enabled = 0;
811 static int pcie_init_slot(struct controller *ctrl)
813 struct pci_bus *subordinate = ctrl_dev(ctrl)->subordinate;
816 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
820 down_read(&pci_bus_sem);
821 slot->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE;
822 up_read(&pci_bus_sem);
825 mutex_init(&slot->lock);
826 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
831 static void pcie_cleanup_slot(struct controller *ctrl)
833 struct slot *slot = ctrl->slot;
835 cancel_delayed_work_sync(&slot->work);
839 static inline void dbg_ctrl(struct controller *ctrl)
841 struct pci_dev *pdev = ctrl->pcie->port;
847 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
848 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
849 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
850 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
851 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
854 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
856 struct controller *pcie_init(struct pcie_device *dev)
858 struct controller *ctrl;
859 u32 slot_cap, link_cap;
860 u8 occupied, poweron;
861 struct pci_dev *pdev = dev->port;
863 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
868 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
870 if (pdev->hotplug_user_indicators)
871 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
874 * We assume no Thunderbolt controllers support Command Complete events,
875 * but some controllers falsely claim they do.
877 if (pdev->is_thunderbolt)
878 slot_cap |= PCI_EXP_SLTCAP_NCCS;
880 ctrl->slot_cap = slot_cap;
881 mutex_init(&ctrl->ctrl_lock);
882 init_rwsem(&ctrl->reset_lock);
883 init_waitqueue_head(&ctrl->requester);
884 init_waitqueue_head(&ctrl->queue);
887 /* Check if Data Link Layer Link Active Reporting is implemented */
888 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
889 if (link_cap & PCI_EXP_LNKCAP_DLLLARC)
890 ctrl->link_active_reporting = 1;
892 /* Clear all remaining event bits in Slot Status register. */
893 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
894 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
895 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
896 PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC);
898 ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c%s\n",
899 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
900 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
901 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
902 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
903 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
904 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
905 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
906 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
907 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
908 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
909 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC),
910 pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : "");
912 if (pcie_init_slot(ctrl))
916 * If empty slot's power status is on, turn power off. The IRQ isn't
917 * requested yet, so avoid triggering a notification with this command.
919 if (POWER_CTRL(ctrl)) {
920 pciehp_get_adapter_status(ctrl->slot, &occupied);
921 pciehp_get_power_status(ctrl->slot, &poweron);
922 if (!occupied && poweron) {
923 pcie_disable_notification(ctrl);
924 pciehp_power_off_slot(ctrl->slot);
936 void pciehp_release_ctrl(struct controller *ctrl)
938 pcie_cleanup_slot(ctrl);
942 static void quirk_cmd_compl(struct pci_dev *pdev)
946 if (pci_is_pcie(pdev)) {
947 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
948 if (slot_cap & PCI_EXP_SLTCAP_HPC &&
949 !(slot_cap & PCI_EXP_SLTCAP_NCCS))
950 pdev->broken_cmd_compl = 1;
953 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
954 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
955 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0400,
956 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);
957 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_QCOM, 0x0401,
958 PCI_CLASS_BRIDGE_PCI, 8, quirk_cmd_compl);